Methods for patterning process modeling

Abstract

A method for patterning process modeling is described. The method includes: determining, using a front end of a process model, a function associated with process physics and / or process chemistry of operations within a patterning process flow; and determining, using a back end of the process model, the predicted wafer geometry. The back end includes a volume representation of a target area on the wafer. The predicted wafer geometry is determined by applying the function from the front end to manipulate the volume representation of the wafer. The volume representation of the wafer can be generated using a volume dynamic B-tree. The volume representation of the wafer can be manipulated using a level set method. The function associated with process physics and / or process chemistry of the operations within the patterning process flow can be a velocity / rate function. Ray tracing can be used to determine an incident flux on a modeled surface of the wafer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application 62 / 864,322, filed on June 20, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The description herein generally relates to mask making and patterning processes. More particularly, the specification relates to an apparatus and method for modeling a patterning process. Background Art

[0004] Lithographic projection apparatus may be used, for example, in the manufacture of integrated circuits (ICs). In such cases, a patterning device (e.g., a mask) may provide a pattern corresponding to a single layer of the IC (a "design layout"), and such a pattern may be transferred to a target portion of the substrate by methods such as irradiating a target portion (e.g., comprising one or more dies) on a (e.g., silicon wafer) coated with a layer of radiation-sensitive material ("resist") through the pattern on the patterning device. Typically, a single substrate comprises a plurality of adjacent target portions to which the pattern is transferred successively, one target portion at a time, by the lithographic projection apparatus. In one type of lithographic projection apparatus, in one operation, the pattern on the entire patterning device is transferred to one target portion. Such an apparatus is typically referred to as a stepper. In an alternative apparatus, typically referred to as a step-and-scan apparatus, a projection beam is scanned over the patterning device in a given reference direction (the "scanning" direction) while synchronously moving the substrate in a direction parallel or antiparallel to the reference direction. Different portions of the pattern on the patterning device are gradually transferred to one target portion. Since typically the lithographic projection apparatus will have a reduction ratio M (e.g. 4), the rate F at which the substrate is moved will be 1 / M times the rate at which the projection beam scans the patterning device. Further information on lithographic apparatus as described herein can be gleaned, for example, from US 6,046,792, which is incorporated herein by reference.

[0005] Before the pattern is transferred from the pattern forming device to the substrate, the substrate may undergo various processes, such as primer coating, resist coating and soft baking. After exposure, the substrate may undergo other processes ("post-exposure processes"), such as post-exposure baking (PEB), development, hard baking and measurement / inspection of the transferred pattern. This series of processes is used as the basis for manufacturing a single layer of a device (e.g., IC). The substrate may then undergo various processes, such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, etc., all of which are intended to ultimately complete a single layer of the device. If the device requires multiple layers, the entire process or its variation is repeated for each layer. Ultimately, the device will be set in each target portion on the substrate. These devices are then separated from each other by techniques such as slicing or cutting, whereby individual devices can be mounted on a carrier, connected to pins, etc.

[0006] Thus, manufacturing devices (such as semiconductor devices) typically involves using multiple manufacturing processes to process a substrate (e.g., a semiconductor wafer) to form various features and multiple layers of the device. These layers and features are typically manufactured and processed using, for example, deposition, lithography, etching, chemical mechanical polishing, and ion implantation. Multiple devices can be manufactured on multiple dies on a substrate and then separated into separate devices. This device manufacturing process can be considered a patterning process. The patterning process involves a patterning step, such as optical and / or nanoimprint lithography using a patterning device in a lithographic apparatus to transfer the pattern on the patterning device to the substrate, and typically but optionally involves one or more related pattern processing steps, such as resist development by a developing apparatus, substrate baking using a baking tool, etching using a pattern using an etching apparatus, etc. In addition, one or more measurement processes are typically involved in the patterning process.

[0007] As mentioned, photolithography is a core step in the manufacture of devices such as ICs, where patterns formed on a substrate define the functional elements of the device, such as microprocessors, memory chips, etc. Similar photolithography techniques are also used to form flat panel displays, microelectromechanical systems (MEMS), and other devices.

[0008] As semiconductor manufacturing processes continue to advance, the size of functional elements has been continuously reduced over the decades while the number of functional elements (such as transistors) per device has been steadily increasing, following a trend commonly referred to as "Moore's Law." In the current state of the art, multiple layers of a device are fabricated using a lithographic projection apparatus that projects a design layout onto a substrate using illumination from a deep ultraviolet illumination source, thereby forming a single functional element having a size well below 100 nm (i.e., less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source)).

[0009] This process in which features with dimensions smaller than the classical resolution limit of the lithographic projection apparatus are printed is generally referred to as low-k1 lithography, and is based on the resolution formula CD=k1×λ / NA, where λ is the wavelength of the radiation employed (currently 248 nm or 193 nm in most cases), NA is the numerical aperture of the projection optics in the lithographic projection apparatus, CD is the "critical dimension" (usually the smallest feature size printed), and k1 is an empirical resolution factor. In general, the smaller k1 is, the more difficult it becomes to reproduce on a substrate a pattern that resembles the shape and dimensions planned by the designer in order to achieve specific electrical functionality and performance. To overcome these difficulties, complex fine-tuning steps are applied to the lithographic projection apparatus, the design layout, or the patterning device. These steps include, for example, but are not limited to: optimization of NA and optical coherence settings, customized illumination schemes, use of phase-shifting patterning devices, optical proximity correction (OPC, sometimes also called "optical and process correction") in the design layout, or other methods generally defined as "resolution enhancement techniques" (RET). The term "projection optics" as used herein should be broadly interpreted to cover various types of optical systems, including, for example, refractive optics, reflective optics, apertures, and reflective-refractive optics. The term "projection optics" may also include components that operate according to any of these design types for guiding, shaping or controlling a projection radiation beam, either collectively or individually. The term "projection optics" may include any optical component in a lithographic projection apparatus, regardless of where the optical component is located on the optical path of the lithographic projection apparatus. Projection optics may include optical components for shaping, adjusting and / or projecting radiation from a source before the radiation passes through a pattern forming device, or optical components for shaping, adjusting and / or projecting the radiation after the radiation passes through a pattern forming device. Projection optics typically do not include a source and a pattern forming device. Summary of the invention

[0010] According to an embodiment, a patterning process modeling method is provided. The method includes: determining, using a front end of a process model, a function associated with process physics and / or process chemistry of operations within a patterning process flow; and determining, using a back end of the process model, a predicted wafer geometry. The back end of the process model includes a volume representation of a target area on the wafer. The predicted wafer geometry is determined by the back end by applying the function associated with the process physics and / or process chemistry from the front end to manipulate the volume representation of the target area on the wafer.

[0011] In an embodiment, the method comprises: determining a second function associated with process physics and / or process chemistry of a second operation within the patterning process flow using a second front end of the process model; and determining a second predicted wafer geometry using the same back end of the process model. The back end of the process model comprises the same volume representation of the target area on the wafer. The second predicted wafer geometry is determined by the back end by applying the second function associated with process physics and / or process chemistry of the second operation within the patterning process flow to manipulate the volume representation of the target area on the wafer.

[0012] In an embodiment, the operation within the patterning process flow includes etching, and the second operation within the patterning process flow includes deposition.

[0013] In an embodiment, the method includes implementing, by the process model, time-based iterative flow control of switching from front-end logic to back-end logic.

[0014] In an embodiment, the front end and the back end communicate via (1) a set of configurable surface point parameters defined by the front end. The surface point parameters are obtained by the back end from the front end before applying a function from the front end. The front end and the back end also communicate via (2) a velocity field determined by the front end based on the surface point parameters.

[0015] In an embodiment, the method includes generating, with the back end of the process model, the volumetric representation of the target area on the wafer using a volumetric dynamic B-tree.

[0016] In an embodiment, the method includes manipulating the volume representation of the target area on the wafer using a level set method with the back end of the process model.

[0017] In an embodiment, the function associated with the process physics and / or process chemistry of the operations within the patterning process flow is a speed / rate function. In an embodiment, the speed / rate function describes the motion of the surface of the wafer at the interface between the wafer and the environment surrounding the wafer. In an embodiment, the speed / rate function is configured to generate different speed values ​​for different points on the surface. The different speed values ​​vary with the process physics and / or process chemistry of the operations within the patterning process flow for different points on the surface of the wafer.

[0018] In an embodiment, the function associated with process physics and / or process chemistry of the operation within the patterning process flow comprises qualitative parameters and numerical constants associated with the qualitative parameters. The numerical constants are determined by the front end using a machine learning model configured to enhance consistency between measurements made on a physical wafer and the predicted wafer geometry from the back end.

[0019] In an embodiment, the method comprises determining, using ray tracing with the front end of the process model, incident flux at a plurality of individual points on a modeled surface of the wafer at an interface between the wafer and an environment surrounding the wafer. In an embodiment, the function associated with process physics and / or process chemistry of the operations within the patterning process flow is a level aggregate velocity function, and incident flux determination is performed directly from the level aggregate function with a graphics processing unit.

[0020] In an embodiment, the method comprises determining the incident flux using ray tracing based on a representation of the target area on the wafer generated using a volumetric dynamic B-tree.

[0021] In an embodiment, the operations within the patterning process flow include etching, deposition, chemical mechanical polishing, or other operations.

[0022] According to another embodiment, a method for patterning process modeling is provided. The method includes determining, using a front end of a process model, a function associated with process physics and / or process chemistry of operations within a patterning process flow. The method includes determining, using a back end of the process model, the predicted wafer geometry. The back end of the process model includes a volume representation of a target area on the wafer. The predicted wafer geometry is determined by the back end by applying the function associated with the process physics and / or process chemistry from the front end to manipulate the volume representation of the target area on the wafer. The method includes determining one or more process parameters based on the prediction from the process model; and determining adjustments to wafer manufacturing equipment based on the one or more process parameters determined.

[0023] In an embodiment, the method comprises: determining a second function associated with process physics and / or process chemistry of a second operation within the patterning process flow using a second front end of the process model; and determining a second predicted wafer geometry using the same back end of the process model. The back end of the process model comprises the same volume representation of the target area on the wafer. The second predicted wafer geometry is determined by the back end by applying the second function associated with process physics and / or process chemistry of the second operation within the patterning process flow to manipulate the volume representation of the target area on the wafer.

[0024] In an embodiment, the operation within the patterning process flow includes etching, and the second operation within the patterning process flow includes deposition. In an embodiment, the operation within the patterning process flow and / or the second operation within the patterning process flow may include etching, deposition, chemical mechanical polishing, an intermediate data set from an external simulation that can be converted into a velocity field by the front end (e.g., a pressure field), and / or other operations. In an embodiment, the one or more process parameters determined include one or more of a mask design, a pupil shape, a dose, or a focal length. In an embodiment, the one or more process parameters determined include the mask design, and adjusting the wafer manufacturing equipment based on the mask design includes changing the mask design from a first mask design to a second mask design.

[0025] In an embodiment, the one or more process parameters determined are associated with one or both of particle properties and surface reaction rates.

[0026] In an embodiment, the method includes adjusting the wafer fabrication equipment based on the determined adjustment.

[0027] According to another embodiment, a computer program product is provided, including a non-transitory computer-readable medium having instructions recorded thereon, the instructions implementing any one of the methods described above when executed by a computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments and, together with the specification, explain these embodiments. Embodiments of the present invention will now be described by way of example only with reference to the accompanying schematic drawings, in which corresponding reference numerals indicate corresponding components, and in which:

[0029] Figure 1 A lithographic apparatus according to an embodiment is schematically depicted.

[0030] Figure 2 Embodiments of a lithography cell or lithography cluster according to embodiments are schematically depicted.

[0031] Figure 3A is a flow chart illustrating various stages of a design for controlling a process flow according to an embodiment.

[0032] Figure 3B is a block diagram illustrating various stages for visualization according to an embodiment.

[0033] Figure 3C is a flow chart illustrating how a design for controlling a process determines a measurement target design that is robust against process disturbances according to an embodiment.

[0034] Figure 4 An example use of the present software architecture for etch simulation in the context of a design for controlling a process flow is illustrated according to an embodiment.

[0035] Figure 5 An example of a software architecture of the present system and method according to an embodiment is illustrated.

[0036] Figure 6 An illustration of a region where a multi-resolution grid is applied to a wafer surface profile in accordance with an embodiment.

[0037] Figure 7 The tracking of the temporal evolution of a surface is illustrated according to an embodiment.

[0038] Figure 8 The training, application, evaluation, and updating of a model (eg, the present software architecture) including a velocity function according to an embodiment is schematically illustrated.

[0039] Fig. 9 Illustrated is an example of ray marching ray tracer functionality according to an embodiment.

[0040] Fig.10 is a block diagram of an example computer system according to an embodiment.

[0041] Fig.11 is similar to Figure 1 Schematic diagram of a lithography projection apparatus.

[0042] Fig.12 According to the embodiment Fig.11 A more detailed view of the device in FIG.

[0043] Fig.13 According to the embodiment Fig.11 and Fig.12 A more detailed view of the source collector module SO of the device. DETAILED DESCRIPTION

[0044] The description herein relates to an apparatus and method for semiconductor device processing and / or process modeling. The apparatus or method may include or be associated with a simulation system configured to predict or otherwise determine the wafer layer (e.g., after etching, deposition, chemical mechanical polishing, etc.) profile based on modeled process physics and / or process chemistry. Semiconductor process modeling can be performed in different ways, which have advantages and disadvantages that may or may not be relevant depending on the application area. One way to deal with the problem is to implement a simplified geometric model that implements a priori semantics for process steps that need to be modeled, such as etching, deposition (including physical vapor deposition, chemical vapor deposition, electrochemical deposition, atomic layer deposition), chemical mechanical polishing (CMP), etc. This approach is implemented by current modeling tools (e.g., ASML's Design 4Control (D4C, i.e., "Design for Control"), which uses B-rep (i.e., boundary representation) geometry representation and B-rep CAD architecture for geometric transformations that enable the semantics of process models to be implemented).

[0045] The present system and method facilitates modeling of semiconductor process operations without a priori semantics. The present system and method include a model of a physical wafer (e.g., stack, layer, etc.) that is parameterized using a set of quantities and simulation start states that are directly related to the physics and / or chemistry involved in a given manufacturing operation (e.g., etching, deposition, etc.). In contrast, typical process simulators typically use several volume modeling methods to model only specific process operations such as etching or deposition.

[0046] A disadvantage of existing process simulators is that they have a narrow focus on (a subset of) process operations. For example, an etch simulator may only implement a limited / constrained etch model for a subset of etch operations (only for a limited set of starting configurations, etc.). A deposition model may only implement conformal deposition, not planar deposition. A CMP model may be able to use the input of some other deposition model, but its output may not be available to a subsequent etch simulator.

[0047] The present system and method include a software architecture that separates volume representation and manipulation from domain-specific simulation logic that implements the physics and / or chemistry of a specific process model for simulation. The software architecture is split into a backend that uses a volume dynamic B-tree (VDB) to store simulation states and a level set method (LSM) to manipulate the simulation states, and a frontend that implements process physics and / or process chemistry. The backend representation can be reused by different (e.g., second, third, fourth, etc.) front ends. For example, a conformal deposition front end can use the results of a process simulation implemented by an etching front end, and treat the backend VDB representation after the etching simulation as its input. The front end is configured to describe the behavior of (separate and interchangeable) semiconductor manufacturing operations and the results of such behavior, which can be used to monitor and control process changes, to discover root causes of defects, to improve productivity, and / or for other purposes.

[0048] By allowing the combination and interchange of analog front ends, the present simulation architecture facilitates easier and more efficient simulation of an entire semiconductor production flow including different process operations than combining different simulators from different vendors and / or using different input / output representations (e.g., as may be required with a typical system). The present architecture also allows for easier comparisons between different solid models that approximate / simulate the same process operation. For example, the effect of a dry etch front end on a plasma etch front end can be directly compared since they share the same input / simulation / output representation (e.g., VDB). Another advantage is that any improvements and / or changes that are typically implemented on the back end can be available to any of a plurality of front ends (e.g., different front ends associated with different processing operations, or associated with the same operation with different processing variables).

[0049] Although specific reference may be made herein to the manufacture of integrated circuits (ICs), it should be understood that the description herein has many other possible applications. For example, the description herein may be used to manufacture integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal display panels, thin film magnetic heads, etc. Those skilled in the art will appreciate that in the context of such alternative applications, any use of the terms "reticle", "wafer" or "die" herein should be considered interchangeable with the more general terms "mask", "substrate" and "target portion", respectively.

[0050] As an introduction, Figure 1 An embodiment of a lithographic apparatus LA which may be included in and / or associated with the present system and / or method is schematically depicted. The apparatus comprises:

[0051] - an illumination system (illuminator) IL configured to condition a radiation beam B (e.g. UV radiation, DUV radiation or EUV radiation);

[0052] a support structure (e.g. mask table) MT configured to support a patterning device (e.g. mask) MA and connected to a first positioning device PM configured to accurately position the patterning device according to certain parameters;

[0053] a substrate table (e.g. wafer stage) WT (e.g. WTa, WTb or both) configured to hold a substrate (e.g. a resist-coated wafer) W and connected to a second positioning device PW configured to accurately position the substrate according to certain parameters; and

[0054] - a projection system (e.g., a refractive projection lens system) PS, which is configured to project the pattern imparted to the radiation beam B by the pattern forming device MA onto a target portion C (e.g., comprising one or more dies and often referred to as a field) of the substrate W, the projection system being supported on a reference frame (RF).

[0055] As depicted, the device is of the transmissive type (eg, using a transmissive mask). Alternatively, the device may be of the reflective type (eg, using a programmable mirror array of the type mentioned above, or using a reflective mask).

[0056] The illuminator IL receives a radiation beam from a radiation source SO. For example, when the source is an excimer laser, the source and the lithographic apparatus may be separate entities. In such a case, the source is not considered to form part of the lithographic apparatus, and the radiation beam is transferred from the source SO to the illuminator IL by means of a beam delivery system BD comprising, for example, suitable directional mirrors and / or a beam expander. In other cases, for example, when the source is a mercury lamp, the source may be an integral part of the apparatus. The source SO and the illuminator IL together with the beam delivery system BD (where necessary) may be referred to as a radiation system.

[0057] The illuminator IL may vary the intensity distribution of the beam. The illuminator may be arranged to limit the radial extent of the radiation beam so that the intensity distribution within an annular region in a pupil plane of the illuminator IL is non-zero. Additionally or alternatively, the illuminator IL may be operable to limit the distribution of the beam in the pupil plane so that the intensity distribution in a plurality of equally spaced segments in the pupil plane is non-zero. The intensity distribution of the radiation beam in the pupil plane of the illuminator IL may be referred to as an illumination pattern.

[0058] The illuminator IL may comprise an adjuster AM configured to adjust the (angular / spatial) intensity distribution of the beam. Typically, at least the outer radial extent and / or the inner radial extent (typically referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. The illuminator IL may be operable to change the angular distribution of the beam. For example, the illuminator may be operable to change the number and angular extent of the segments in the pupil plane in which the intensity distribution is non-zero. By adjusting the intensity distribution of the beam in the pupil plane of the illuminator, different illumination modes may be achieved. For example, by limiting the radial extent and the angular extent of the intensity distribution in the pupil plane of the illuminator IL, the intensity distribution may have a multipolar distribution, such as a dipole, quadrupole or hexapole distribution. The illumination mode may be obtained, for example, by inserting an optical device providing the desired illumination mode into the illuminator IL or by using a spatial light modulator.

[0059] The illuminator IL may be operable to change the polarization of the beam and may be operable to adjust the polarization using an adjuster AM. The polarization state of the radiation beam across the pupil plane of the illuminator IL may be referred to as a polarization mode. Using different polarization modes may allow a greater contrast to be achieved in the image formed on the substrate W. The radiation beam may be unpolarized. Alternatively, the illuminator may be arranged to polarize the radiation beam linearly. The polarization direction of the radiation beam may vary across the pupil plane of the illuminator IL. The polarization direction of the radiation may be different in different zones in the pupil plane of the illuminator IL. The polarization state of the radiation may be selected depending on the illumination mode. For a multipolar illumination mode, the polarization of each pole of the radiation beam may generally be perpendicular to the position vector of the pole in the pupil plane of the illuminator IL. For example, for a dipole illumination mode, the radiation may be linearly polarized in a direction substantially perpendicular to a line of two opposing segments bisecting a dipole. The radiation beam may be polarized in one of two different orthogonal directions, which may be referred to as an X polarization state and a Y polarization state. For a quadrupole illumination mode, the radiation in the segments of each pole may be linearly polarized in a direction substantially perpendicular to a line bisecting the segments. This polarization mode may be referred to as XY polarization. Similarly, for a hexapole illumination mode, the radiation in the segments of each pole may be linearly polarized in a direction substantially perpendicular to a line bisecting the segments. This polarization mode may be referred to as TE polarization.

[0060] In addition, the illuminator IL typically includes various other components, such as an integrator IN and a condenser CO. The illumination system may include various types of optical components for directing, shaping or controlling the radiation, such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof. Thus, the illuminator provides a conditioned radiation beam B having a desired uniformity and intensity distribution in cross-section.

[0061] The support structure MT supports the pattern forming device in a manner that depends on the orientation of the pattern forming device, the design of the lithographic apparatus, and other conditions such as whether the pattern forming device is maintained in a vacuum environment. The support structure can use mechanical, vacuum, electrostatic or other clamping techniques to hold the pattern forming device. The support structure can be, for example, a frame or a table, which can be fixed or movable as required. The support structure can ensure that the pattern forming device is in a desired position, for example relative to a projection system. Any use of the term "reticle" or "mask" in the present invention can be regarded as synonymous with the more general term "pattern forming device".

[0062] The term "patterning device" as used in the present invention should be broadly interpreted as referring to any device that can be used to impart a pattern in a target portion of a substrate. In an embodiment, the patterning device is any device that can be used to impart a pattern to a radiation beam in its cross-section so as to produce a pattern in a target portion of a substrate. It should be noted that, for example, if the pattern imparted to the radiation beam includes phase-shifting features or so-called assist features, the pattern may not exactly correspond to the desired pattern in the target portion of the substrate. Typically, the pattern imparted to the radiation beam will correspond to a specific functional layer in a device (such as an integrated circuit) produced in the target portion.

[0063] The patterning device may be transmissive or reflective. Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels. Masks are well known in lithography and include mask types such as binary, alternating phase shift, and attenuated phase shift, as well as various hybrid mask types. An example of a programmable mirror array uses a matrix arrangement of small mirrors, each of which can be individually tilted so as to reflect an incident radiation beam in different directions. The tilted mirrors impart a pattern in the radiation beam reflected by the mirror matrix.

[0064] The term "projection system" as used herein should be interpreted broadly to cover any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof, as appropriate to the exposure radiation used or to other factors such as the use of an immersion liquid or the use of a vacuum. Any use of the term "projection lens" in this disclosure may be considered synonymous with the more general term "projection system".

[0065] The projection system PS has an optical transfer function that may be non-uniform and may affect the pattern imaged onto the substrate W. For unpolarized radiation, such effects can be fairly well described by two scalar maps that describe the transmission (apodization) and relative phase (aberration) of the radiation exiting the projection system PS as a function of the position in the pupil plane of the radiation. These scalar maps, which can be referred to as transmission maps and relative phase maps, can be expressed as linear combinations of a full set of basis functions. A particularly suitable set is the Zernike polynomials, which form a set of orthogonal polynomials defined on the unit circle. The determination of each scalar map may involve determining coefficients in such an expansion. Since the Zernike polynomials are orthogonal on the unit circle, the Zernike coefficients may be determined by calculating the inner product of the measured scalar map with each Zernike polynomial in turn and dividing this inner product by the square of the norm of the Zernike polynomial.

[0066] Transmission mapping and relative phase mapping are field and system dependent. That is, typically, each projection system PS will have a different Zernike expansion for each field point (i.e., for each spatial location in the image plane of the projection system). The relative phase of the projection system PS in its pupil plane can be determined by projecting, for example, radiation from a point-like source in the object plane of the projection system PS (i.e., the plane of the pattern forming device MA) through the projection system PS and measuring the wavefront (i.e., the trajectory of points with the same phase) using a shearing interferometer. The shearing interferometer is a common path interferometer, and therefore advantageously, no secondary reference beam is required to measure the wavefront. The shearing interferometer may include a diffraction grating (e.g., a two-dimensional grid) in the image plane of the projection system (i.e., the substrate table WT), and a detector arranged to detect an interference pattern in a plane conjugate to the pupil plane of the projection system PS. The interference pattern is related to the derivative of the phase of the radiation and the coordinates in the pupil plane in the shear direction. The detector may include an array of sensing elements such as, for example, a charge coupled device (CCD).

[0067] The projection system PS of the lithographic apparatus may not produce visible fringes, and therefore a phase stepping technique (such as moving a diffraction grating) may be used to enhance the accuracy of the wavefront determination. Stepping may be performed in the plane of the diffraction grating and in a direction perpendicular to the scanning direction of the measurement. The stepping range may be one grating period, and at least three (uniformly distributed) phase steps may be used. Thus, for example, three scanning measurements may be performed in the y direction, each scanning measurement being performed for a different position in the x direction. Such stepping of the diffraction grating effectively converts phase changes into intensity changes, thereby allowing the phase information to be determined. The grating may be stepped in a direction perpendicular to the diffraction grating (z direction) to calibrate the detector.

[0068] The diffraction grating may be scanned sequentially in two perpendicular directions, which may coincide with the axes (x and y) of the coordinate system of the projection system PS or may be at an angle (such as 45 degrees) to these axes. The scan may be performed over an integer number of grating periods (e.g., one grating period). The scan averages the phase change in one direction, allowing reconstruction of the phase change in the other direction. This allows the wavefront to be determined as a function of the two directions.

[0069] The transmission (apodization) of the projection system PS in its pupil plane may be determined by projecting radiation, e.g. from a point-like source in the object plane of the projection system PS (i.e. the plane of the patterning device MA) through the projection system PS and measuring the intensity of the radiation in a plane conjugate to the pupil plane of the projection system PS using a detector. The same detector may be used as the one used to measure the wavefront to determine the aberrations.

[0070] The projection system PS may include a plurality of optical (e.g., lens) elements, and may further include an adjustment mechanism AM configured to adjust one or more of the optical elements so as to correct aberrations (phase variations in the pupil plane across the entire field). To achieve such adjustment, the adjustment mechanism may be operable to manipulate one or more optical (e.g., lens) elements within the projection system PS in one or more different ways. The projection system may have a coordinate system in which the optical axis of the projection system extends in the z-direction. The adjustment mechanism may be operable to perform any combination of the following: displacing one or more optical elements; tilting one or more optical elements; and / or deforming one or more optical elements. Displacing of optical elements may be performed in any direction (x, y, z, or a combination thereof). Tilt of an optical element is typically performed out of a plane perpendicular to the optical axis by rotating about an axis in the x and / or y directions, but rotation about the z-axis may be used for non-rotationally symmetric aspheric optical elements. Deformation of an optical element may include low-frequency shapes (e.g., astigmatism) and / or high-frequency shapes (e.g., free-form aspheric surfaces). Deformation of the optical element may be performed, for example, by using one or more actuators to apply forces to one or more sides of the optical element and / or by using one or more heating elements to heat one or more selected regions of the optical element. Typically, it is not possible to adjust the projection system PS to correct for apodization (variation of transmission across the pupil plane). A transmission map of the projection system PS may be used when designing a patterning device (e.g., mask) MA for the lithographic apparatus LA. Using computational lithography techniques, the patterning device MA may be designed to at least partially correct for apodization.

[0071] The lithographic apparatus may be of a type having two (dual-stage) or more tables (e.g. two or more substrate tables WTa, WTb, two or more patterning device tables, a substrate table WTa and a table WTb below the projection system in the absence of a dedicated substrate for, for example, facilitating measurement and / or cleaning, etc.). In these "multi-stage" machines, the additional tables may be used in parallel, or preparatory steps may be performed on one or more tables while one or more other tables are being used for exposure. For example, alignment measurements may be performed using an alignment sensor AS and / or level (height, inclination, etc.) measurements may be performed using a level sensor (or leveling sensor) LS.

[0072] The lithographic apparatus may also be of a type in which at least a portion of the substrate may be covered by a liquid having a relatively high refractive index, such as water, so as to fill the space between the projection system and the substrate. Immersion liquid may also be applied to other spaces in the lithographic apparatus, such as the space between the patterning device and the projection system. Immersion techniques are well known in the art and are used to increase the numerical aperture of the projection system. The term "immersion" as used in the present invention does not mean that structures such as the substrate must be immersed in the liquid, but only means that the liquid is located between the projection system and the substrate during exposure.

[0073] In operation of the lithographic apparatus, a radiation beam is conditioned and provided by an illumination system IL. The radiation beam B is incident on a patterning device (e.g. a mask) MA held on a support structure (e.g. a mask table) MT and is patterned by the patterning device. Having traversed the patterning device MA, the radiation beam B passes through a projection system PS which focuses the beam onto a target portion C of a substrate W. With the aid of a second positioning device PW and a position sensor IF (e.g. an interferometric device, a linear encoder, a 2-D encoder or a capacitive sensor), the substrate table WT can be accurately moved, for example in order to position different target portions C in the path of the radiation beam B. Similarly, the first positioning device PM and a further position sensor (in Figure 1The support structure MT may be used to accurately position the patterning device MA relative to the path of the radiation beam B, for example after mechanical retrieval from a mask library or during scanning. Typically, movement of the support structure MT may be achieved with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) forming part of the first positioning device PM. Similarly, movement of the substrate table WT may be achieved using a long-stroke module and a short-stroke module forming part of the second positioning device PW. In the case of a stepper (as opposed to a scanner), the support structure MT may be connected only to the short-stroke actuator, or may be fixed. The patterning device MA and the substrate W may be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2. Although the substrate alignment marks as illustrated occupy dedicated target portions, the marks may be located in the spaces between the target portions (these marks are referred to as scribe alignment marks). Similarly, in the case where more than one die is provided on the patterning device MA, the patterning device alignment marks may be located between the dies.

[0074] The depicted device may be used in at least one of the following modes:

[0075] 1. In step mode, a pattern imparted to the radiation beam is projected once onto a target portion C while the support structure MT and the substrate table WT are kept substantially stationary (i.e. a single static exposure). Subsequently, the substrate table WT is shifted in the X and / or Y direction so that a different target portion C can be exposed. In step mode, the maximum size of the exposure field limits the size of the target portion C imaged in a single static exposure.

[0076] 2. In scan mode, the support structure MT and substrate table WT are scanned synchronously while a pattern imparted to the radiation beam is projected onto a target portion C (i.e. a single dynamic exposure). The speed and direction of the substrate table WT relative to the support structure MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS. In scan mode, the maximum size of the exposure field limits the width of the target portion in a single dynamic exposure (in the non-scanning direction), while the length of the scanning movement determines the height of the target portion (in the scanning direction).

[0077] 3. In another mode, the support structure MT is held substantially stationary, thereby holding the programmable patterning device, and the substrate table WT is moved or scanned while a pattern imparted to the radiation beam is projected onto a target portion C. In this mode, a pulsed radiation source is typically used, and the programmable patterning device is updated as required after each movement of the substrate table WT, or between successive radiation pulses during a scan. This mode of operation can be readily applied to maskless lithography utilizing a programmable patterning device, such as a programmable mirror array of the type mentioned above.

[0078] Combinations and / or variations on the above-described modes of use or entirely different modes of use may also be used.

[0079] The substrates referred to in the present invention may be processed before or after exposure in, for example, a coating and developing system or track (a tool that typically applies a resist layer to a substrate and develops the exposed resist), or a metrology or inspection tool. Where applicable, the disclosure of the present invention may be applied to these and other substrate processing tools. In addition, a substrate may be processed more than once, for example to produce a multi-layer IC, so that the term substrate used in the present invention may also refer to a substrate that has included multiple processed layers.

[0080] The terms "radiation" and "beam" as used in the present invention encompass all types of electromagnetic radiation, including ultraviolet (UV) or deep ultraviolet (DUV) radiation (e.g., having a wavelength of 365, 248, 193, 157 or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having a wavelength in the range of 5 to 20 nm), as well as particle beams, such as ion beams or electron beams.

[0081] Various patterns on or provided by a pattern forming device may have different process windows, i.e., the space of process variables in which patterns within specifications will be produced. Examples of pattern specifications related to potential systematic defects include checking for necking, line pullback, line thinning, CD, edge placement, overlap, resist top loss, resist undercut and / or bridging. The process windows of all patterns on a pattern forming device or a region thereof may be obtained by merging the process windows of each individual pattern (e.g., overlapping the process windows). The boundaries of the process windows of all patterns contain the boundaries of the process windows of some of the individual patterns. In other words, these individual patterns limit the process windows of all patterns. These patterns may be referred to as "hot spots" or "process window limiting patterns (PWLP)", and "hot spots" or "process window limiting patterns (PWLP)" are used interchangeably in the present invention. When controlling a portion of a patterning process, it is possible and economical to focus on hot spots. When hot spots are defect-free, it is most likely that all patterns are defect-free.

[0082] like Figure 2As shown in , the lithography equipment LA can form part of a lithography unit LC (sometimes also referred to as a lithography cell or lithography cluster), which also includes equipment for performing pre-exposure and post-exposure processes on a substrate. Conventionally, these devices include one or more spin coaters SC for depositing one or more resist layers, one or more developers for developing the exposed resist, one or more chill plates CH and / or one or more baking plates BK. The substrate handling device or robot RO picks up one or more substrates from the input / output ports I / O1, I / O2, moves these substrates between different process equipment and transfers these substrates to the feed station LB of the lithography equipment. These devices, which are often collectively referred to as coating and developing systems or tracks, are controlled by a coating and developing system control unit or a track control unit TCU, which is itself controlled by a management control system SCS, and the management control system also controls the lithography equipment via a lithography control unit LACU. Thus, different devices can be operated to maximize throughput and processing efficiency.

[0083] In order to correctly and consistently expose a substrate exposed by a lithographic apparatus and / or to monitor a portion of a patterning process (e.g., a device manufacturing process) that includes at least one pattern transfer step (e.g., an optical lithography step), it is desirable to inspect a substrate or other object to measure or determine one or more properties, such as alignment, overlay (the overlay may be, for example, between structures in overlapping layers or between structures in the same layer that have been provided separately from the layer by, for example, a double patterning process), line thickness, critical dimension (CD), focus offset, material properties, etc. Therefore, a manufacturing facility in which a lithography cell LC is located typically also includes a metrology system that measures the substrate W ( Figure 1 ) or other objects in the lithography cell. The measurement system may be part of the lithography cell LC, for example it may be part of the lithography apparatus LA (such as an alignment sensor AS ( Figure 1 )).

[0084] For example, one or more measured parameters may include: alignment between successive layers formed in or on a patterned substrate, overlay, critical dimensions (CD) of features formed in or on a patterned substrate (e.g., critical line width), focus or focus error of an optical lithography step, dose or dose error of an optical lithography step, optical aberration of an optical lithography step, etc. Such measurements may be performed on a target of the product substrate itself and / or on a dedicated metrology target provided on the substrate. The measurements may be performed after resist development but before etching, after etching, after deposition, and / or at other times.

[0085] There are various techniques for measuring structures formed during the patterning process, including the use of scanning electron microscopes, image-based metrology tools, and / or various special tools. As discussed above, a fast and non-invasive form of a special metrology tool is a measurement tool in which a radiation beam is directed to a target on the surface of a substrate and measures the properties of the scattered (diffracted / reflected) beam. By evaluating one or more properties of the radiation scattered by the substrate, one or more properties of the substrate can be determined. This can be referred to as diffraction-based metrology. One such application of such diffraction-based metrology is in the measurement of feature asymmetry within a target. This can be used as a measure of overlap, for example, but other applications are also known. For example, asymmetry can be measured by comparing relative portions of the diffraction spectrum (e.g., comparing -1 order with +1 order in the diffraction spectrum of a periodic grating). This can be performed as described above and as described in, for example, U.S. Patent Application Publication No. US2006-066855, which is incorporated herein by reference in its entirety. Another application of diffraction-based metrology is in the measurement of feature width (CD) within a target.

[0086] Thus, in a device fabrication process (e.g., a patterning process or a lithography process), a substrate or other object may be subjected to various types of measurements during or after the process. The measurements may determine whether a particular substrate is defective, may adjust the process and equipment used in the process (e.g., aligning two layers on a substrate or aligning a pattern forming device with a substrate), may measure the performance of the process and equipment, or may be used for other purposes. Examples of measurements include optical imaging (e.g., optical microscopy), non-imaging optical measurements (e.g., diffraction-based measurements, such as ASML YieldStar metrology tools, ASML SMASH metrology systems), mechanical measurements (e.g., profile probing using a stylus, atomic force microscopy (AFM)), and / or non-optical imaging (e.g., scanning electron microscopy (SEM)). The Smart Alignment Sensor Hybrid (SMASH) system as described in U.S. Patent No. 6,961,116, which is incorporated herein by reference in its entirety, uses a self-referencing interferometer that produces two overlapping and relatively rotated images of an alignment mark, detects intensity in a pupil plane where Fourier transforms of the images cause interference, and extracts position information from the phase difference between the diffraction orders of the two images, which is expressed as intensity variations in the interference orders.

[0087] The measurement results may be provided directly or indirectly to the supervisory control system SCS. If an error is detected, the exposure of subsequent substrates (especially if the inspection can be completed quickly and quickly enough that one or more other substrates of the batch are still to be exposed) and / or the subsequent exposure of the exposed substrate may be adjusted. In addition, the exposed substrate may be stripped and reworked to improve yield, or discarded, thereby avoiding further processing of substrates known to be defective. In the case where only some target portions of the substrate are defective, further exposure may be performed only on those target portions that meet the specifications.

[0088] Within the metrology system MET, the metrology equipment is used to determine one or more properties of a substrate, and in particular, to determine how one or more properties of different substrates vary or how different layers of the same substrate vary from layer to layer. As mentioned above, the metrology equipment may be integrated into the lithographic apparatus LA or the lithography cell LC, or may be a separate device.

[0089] In order to achieve the measurement, one or more targets may be provided on the substrate. In an embodiment, the target is specially designed and may include a periodic structure. In an embodiment, the target is a part of a device pattern, for example, a periodic structure of the device pattern. In an embodiment, the device pattern is a periodic structure of a memory device (e.g., a bipolar transistor (BPT), a bit line contact (BLC), etc.).

[0090] In an embodiment, the target on the substrate may include one or more one-dimensional periodic structures (e.g., gratings) that are printed such that after development, the periodic structural features are formed by solid resist lines. In an embodiment, the target may include one or more two-dimensional periodic structures (e.g., gratings) that are printed such that after development, the one or more periodic structures are formed by solid resist guide posts or vias in the resist. The bars, guide posts or vias may alternatively be etched into the substrate (e.g., etched into one or more layers on the substrate).

[0091] In an embodiment, one of the parameters of interest in the patterning process is overlap. Overlap can be measured using dark field scatterometry, in which the zeroth order of diffraction (corresponding to specular reflection) is blocked and only higher orders are processed. Examples of dark field measurements can be found in PCT patent application publications WO 2009 / 078708 and WO 2009 / 106279, which are hereby incorporated by reference in their entirety. Further developments of the technology have been described in U.S. patent application publications US2011-0027704, US2011-0043791, and US2012-0242970, which are hereby incorporated by reference in their entirety. Diffraction-based overlap using dark field detection of diffraction orders enables overlap measurement of smaller targets. These targets can be smaller than the irradiation spot and can be surrounded by device product structures on the substrate. In an embodiment, multiple targets can be measured in one radiation capture.

[0092] As lithography nodes keep shrinking, more and more complex wafer designs can be implemented. Various tools and / or techniques can be used by the designer to ensure that the complex design is accurately transferred to the physical wafer. These tools and techniques can include mask optimization, source mask optimization (SMO), OPC, design for control, and / or other tools and / or techniques. For example, the source mask optimization process is described in U.S. Patent No. 9,588,438, entitled "Optimization Flows of Source, Mask and Projection Optics," which is incorporated by reference in its entirety.

[0093] Figure 3A A flow chart listing the main stages of the "Design for Control" (D4C) method is shown. In stage 310, materials to be used in the lithography process are selected. The materials can be selected from a material library that interfaces with D4C via an appropriate GUI. In stage 320, the lithography process is defined by entering each of the process steps and building a computer simulation model for the entire process sequence.

[0094] For example, the simulation may be used to configure one or more features of the patterned device pattern (e.g., to perform optical proximity effect correction), one or more features of the illumination (e.g., to change one or more properties of the spatial / angular intensity distribution of the illumination, such as to change shape), one or more features of the projection optics (e.g., numerical aperture, etc.), one or more features of multiple individual lithography operations such as etching, deposition, CMP, etc., and / or other aspects of a process sequence. In some embodiments, the simulation may include multiple individual models for multiple individual aspects of a process sequence (e.g., etching, deposition, CMP, etc.), where outputs from models of previous process steps are used as inputs for models of subsequent process steps.

[0095] In some embodiments, the model can be used to optimize (the steps (operations) in) the wafer manufacturing process. The optimization process of the manufacturing process can be expressed as a cost function. The optimization process can include finding a set of parameters (design variables, process variables, etc.) of the system that minimizes the cost function. The cost function can have any suitable form depending on the goal of the optimization. For example, the cost function can be the weighted root mean square (RMS) of the deviations of certain characteristics (evaluation points) of the system relative to the expected values ​​(e.g., ideal values) of these characteristics. The cost function can also be the maximum value (i.e., the worst deviation) of these deviations. The term "evaluation point" should be broadly interpreted to include any characteristic of the system or manufacturing method. Due to the practicality of the implementation of the above-mentioned system and / or method, the design and / or process variables of the system can be limited to a limited range and / or be interdependent. In the case of a lithographic projection device, the constraints are often associated with the physical properties and characteristics of the hardware (such as the tunable range and / or the manufacturability design rules of the pattern forming device). The evaluation points can include physical points on the image on the substrate, as well as non-physical characteristics.

[0096] In some embodiments, a given model associated with and / or included in an integrated circuit manufacturing process may be an empirical model that models the operation of a corresponding processing method. The empirical model may predict outputs based on correlations between various inputs (e.g., one or more characteristics of a mask or wafer image, one or more characteristics of a design layout, one or more characteristics of the pattern forming device, one or more characteristics of the lithography process (e.g., etching, deposition, CMP, etc.)).

[0097] As an example, the empirical model can be a machine learning model and / or any other parameterized model. In some embodiments, the machine learning model (for example) can be and / or include a mathematical equation, an algorithm, a plotted graph, a chart, a network (e.g., a neural network), and / or other tools and machine learning model parts or components. For example, the machine learning model can be and / or include one or more neural networks having an input layer, an output layer, and one or more intermediate or hidden layers. In some embodiments, the one or more neural networks can be and / or include a deep neural network (e.g., a neural network having one or more intermediate or hidden layers between the input layer and the output layer).

[0098] As an example, the one or more neural networks may be based on a large collection of neuron units (or artificial neurons). The one or more neural networks may not strictly imitate the way biological brains work (e.g., via multiple large clusters of multiple biological neurons connected by axons). Each neuron unit of the neural network may be connected to many other neuron units of the neural network. Such connections may strengthen or inhibit their influence on the activation state of the connected neuron units. In some embodiments, each individual neuron unit may have a summation function that combines the values ​​of all its inputs. In some embodiments, each connection (or neuron unit itself) may have a threshold function so that the signal must exceed the threshold before it is allowed to propagate to other neuron units. These neural network systems may be self-learning and trained, rather than being explicitly programmed, and may perform significantly better in certain problem-solving areas compared to traditional computer programs. In some embodiments, the one or more neural networks may include multiple layers (e.g., where the signal path traverses from the front-end layer to the back-end layer). In some embodiments, the neural network may utilize backpropagation techniques, where forward stimulation is used to reset weights for the "front-end" neuron units. In some embodiments, stimulation and inhibition of the one or more neural networks may flow more freely, where connections interact in a more chaotic and complex manner. In some embodiments, the one or more intermediate layers of the neural network include one or more convolutional layers, one or more recurrent layers, and / or other layers.

[0099] The one or more neural networks may be trained (i.e., parameters of the neural networks are determined) using a set of training data. The training data may include a set of training samples. Each sample may be a pair including an input object (usually a vector, which may be referred to as a feature vector) and a desired output value (also referred to as a management signal). A training algorithm analyzes the training data and adjusts the behavior of the neural network by adjusting the parameters of the neural network (e.g., the weights of one or more layers) based on the training data. For example, given a model of {(x1, y1), (x2, y2), ..., (x N ,y N )) is a set of N training samples such that x i is the eigenvector of the ith example and y i is its governing signal, then the training algorithm seeks a neural network g:X→Y, where X is the input space and Y is the output space. A feature vector is an n-dimensional vector that represents the numerical features of an object (e.g., a wafer design, a fragment, etc. as in the above example). The vector space associated with these vectors is often called the feature space. After training, the neural network can be used to make predictions using new samples.

[0100] In stage 330, the measurement target is defined, that is, the dimensions and other characteristics of the various features included in the target are entered into the D4C program. For example, if a grating is included in the structure, the number of grating elements, the width of a single grating element, the spacing between two grating elements, etc. must be defined. In stage 340, a 3D geometry is generated. This step also takes into account whether there is any information related to the multi-layer target design, such as the relative displacement between different layers. This feature enables multi-layer target design. In stage 350, the final geometry of the designed target is visualized. As will be explained in more detail below, not only is the final design visualized, but as the designer applies the various steps of the lithography process, the designer can visualize how the 3D geometry is formed and changes due to process-induced effects. For example, the 3D geometry after resist patterning is different from the 3D geometry after resist removal and etching.

[0101] An important aspect of the present disclosure is to enable the target designer to visualize the stages of the method to facilitate their perception and control during modeling and simulation. Different visualization tools called "viewers" are built into the D4C software. For example, Figure 3B, the designer can view the material plot 360 (and can also obtain a run time estimate plot) based on the defined lithography process and objectives. Once the lithography model is generated, the designer can view the model parameters through the model viewer tool 375. The design layout viewer tool 380 can be used to view the design layout (e.g., a visual presentation / rendering of a GDS file). The resist profile viewer tool 385 can be used to view the pattern profile in the resist. The geometry viewer tool 390 can be used to view the 3D structure on the substrate. The pupil viewer tool 395 can be used to view the simulated response to the measurement tool. Those skilled in the art will understand that these viewing tools can be used to enhance the designer's understanding during design and simulation. In some embodiments of the D4C software, one or more of these tools may not be present, and in some other embodiments, additional viewing tools may be present.

[0102] Figure 3C A flow chart illustrating how the D4C process increases efficiency in the overall simulation process by reducing the number of measurement targets selected for actual simulation of the lithography process. As mentioned previously, D4C enables designers to design thousands or even millions of designs. Not all of these designs may be robust with respect to changes in the process steps. In order to select a subset of target designs that can tolerate process changes, the lithography personnel can intentionally perturb one or more steps of the defined lithography process, as shown in block 352. The introduction of the perturbation changes the entire process sequence in terms of how it was originally defined. Therefore, applying the perturbed process sequence (block 354) also changes the 3D geometry of the designed target. The lithography personnel only selects perturbations that show non-zero changes in the original design targets, and creates a subset of the selected process perturbations (block 356). This subset of process perturbations is then used to simulate the lithography process (block 358).

[0103] The use of the lithography process (or generally, the patterning process) to manufacture or produce a substrate generally involves process variations. The process variations are not uniform across the entire substrate. For example, during deposition, the film tends to be thicker at the center of the substrate and thinner when close to the edge. These systematic variations are generally reflected in the measurement data as a "fingerprint", which is a characteristic of the substrate based on known process conditions. In other words, there is a stack on the substrate, and the stack has a spatial variation as a function of the substrate coordinates. The stack includes a plurality of layers formed on the substrate during the patterning process to form a selected pattern (e.g., a design pattern) on the substrate. Each layer of the stack can be associated with thickness, material properties, and features and related parameters of the patterning process (e.g., CD, pitch, overlap, etc.).

[0104] The present system, and / or method can be used as a stand-alone tool and / or technique, in conjunction with a D4C process, and / or in conjunction with other semiconductor manufacturing processes modeled using the process to enhance the accurate transfer of complex designs to physical wafers. As described above, the present system and method include a software architecture that separates volume representation and manipulation from domain-specific simulation logic that implements the physics and / or chemistry of a specific process model for simulation. The software architecture is split into a back end that uses a volume dynamic B-tree (VDB) to store the simulation state and a level set method (LSM) to manipulate the simulation state, and a front end that implements process physics and / or process chemistry. The back end representation can be reused by different (e.g., second, third, fourth, etc.) front ends.

[0105] As a non-limiting example, Figure 4 An example use of the present software architecture for an etch simulation 400 (using the Level Set Method (LSM) described herein) is illustrated in the context of a D4C process flow 402. Note that even though the etch simulation is presented in the context of Figure 4 , but the etching simulation can be replaced by any other lithography process simulation. Figure 4 , simulation 400 is based on simulation (e.g., etching in this example) parameters 404, geometry to LSM conversion 406, and / or other information. Conversion 406 is based on material 408, polygon-based geometry (e.g., from a.gds file) 410, BRep geometry 412, and / or other information. Geometry 412 is based on next generation geometry (NGG) rendering operations 414, NGG matching schemes (e.g., XML) 416, and / or other information. Output from simulation 400 can be used by cross-section extractor 420, LSM slicer 422 for LSM to mesh conversion 424, and / or for other purposes. Cross-section extractor 420 can generate cross-sections 430 (e.g., images, contour data, etc.) and / or other information. Slicer 422 can generate sliced ​​geometry (e.g., stored in an XML-based format) 440, sliced ​​etched volumes 444, and / or other information for RCWA solution process 442. The transformation 424 may be used to generate an etch volume mesh 426 and / or other information. The transformation 424, the sliced ​​etch volume 444, and / or other information may be applied to a D4C etch simulation session 450. The session 450 may also receive as input a pre-etch BRep geometry 452, a pre-etch NGG matching scheme 454, and / or other information. The session 450 may generate as output a post-etch BRep geometry 456, a post-etch NGG matching scheme 458, and / or other information.

[0106] Figure 5 An example of a software architecture 500 of the present system and method is shown. Figure 5 5 , the architecture 500 includes a front end 502, a back end 504, a front end preparation portion 506, and / or other components. In some embodiments, the front end preparation portion 506 may form a part of the front end 502 or be included in the front end 502. In some embodiments, the front end preparation portion 506 may be configured to determine process and / or wafer properties at a plurality of separate points on a wafer surface. The front end 502 may be configured to use the process and / or wafer properties to perform a process physics and / or process chemistry simulation on the wafer surface.

[0107] The architecture 500 can be configured to perform one or more patterning process flow operation modeling methods. In some embodiments, the method includes: determining, using the front end 502, a function associated with process physics and / or process chemistry of a given operation within the patterning process flow; and determining, using the back end 504, a predicted wafer geometry. The back end 504 includes a volume representation of a target area of ​​the wafer. The predicted wafer geometry is determined by the back end 504 by applying the function associated with the process physics and / or process chemistry from the front end 502 to manipulate the volume representation of the target area on the wafer.

[0108] In some embodiments, the method includes: determining different (e.g., second, third, fourth, etc.) functions associated with process physics and / or process chemistry of different (e.g., second, third, fourth, etc.) operations within the patterning process flow using different (e.g., second, third, fourth, etc.) front ends; and determining different (e.g., second, third, fourth, etc.) predicted wafer geometries using the same back end (e.g., back end 504) of the process model. In these embodiments, back end 504 includes the same volume representation of the target area of ​​the wafer. The different (e.g., second, third, fourth, etc.) predicted wafer geometries are determined by back end 504 by applying different functions associated with process physics and / or process chemistry of different (e.g., second, third, fourth, etc.) operations within the patterning process flow to manipulate the volume representation of the target area on the wafer. For example, in some embodiments, the different (e.g., second, third, fourth, etc.) operations within the patterning process flow include etching and deposition (and / or chemical mechanical polishing, and / or any other process). The back end 504 may be configured to be coupled to the front end (e.g., 502a, 502b, which are connected to different etching and deposition (or other) operations. Figure 5 (not shown) are used interchangeably.

[0109] In some embodiments, the architecture 500 is configured to implement time-based iterative flow control switching from front-end logic to back-end logic. In some embodiments, the front-end 502 and the back-end 504 communicate via (1) a set of configurable surface point parameters 510 (e.g., per-integration point parameters) defined by a front-end preparation portion 506 of the front-end 502. The surface point parameters can be obtained from the front-end 502 by the back-end 504, for example, before applying a function from the front-end 502. The front-end and the back-end also communicate via (2) a velocity field 512 determined by the front-end 502 based on the surface point parameters 510.

[0110] like Figure 5As shown in , the backend 504 may be configured to receive 513 information about the input stack related to per-integration point parameters 516 (which may alternatively be included in the frontend preparation portion 506 - at 516, the configuration of the per-integration point parameters is determined (i.e., a subset thereof is calculated and how it is configured by the frontend 502), and 506 about the values ​​of the per-integration point parameters (as calculated by the backend 504 according to the configuration set by the frontend 502 prior to the simulation)), global modeling parameters 518, material parameters 520, and / or other information. The backend 504 may be configured to perform optional LSM downsampling (downsampling). The front-end preparation portion 506 may extract gradients 530, perform visibility calculations 532, map material etch (in this example) rates 534, and / or perform other operations. The front-end may perform velocity function determination operations 540, velocity field determination operations 512, and / or other operations. In some embodiments, the back-end 504 is configured to perform advection operations 542, unit cell clipping operations 544, and / or other operations. In some embodiments, the architecture 500 is configured such that one or more of these operations are iteratively performed 550 until the etch (in this example) structure is extracted 552. In some embodiments, determining the function associated with process physics and / or process chemistry of a given operation (e.g., etching in this example) within the patterning process flow using the front end 502 includes one or both of operations 540 and 512. In some embodiments, determining the function associated with process physics and / or process chemistry of a given operation within the patterning process flow using the front end 502 includes one or more of operations 540, 512, 510, 532, and / or 534. In some embodiments, determining the predicted wafer geometry using the back end 504 (e.g., by applying the function associated with process physics and / or process chemistry) includes one or both of operations 542 and 544. In some embodiments, determining the predicted wafer geometry using the back end 504 includes one or more of operations 542, 544, 522, 524, 526, 528, and / or 513.

[0111] In some embodiments, the back end 504 is configured to generate the volume representation of the target area of ​​the wafer using a volume dynamic B-tree. In some embodiments, for example, generating the volume representation of the target area of ​​the wafer using a volume dynamic B-tree includes one or more operations in operations 513, 524, 526, or 528. Generating the volume representation of the target area on the wafer using a volume dynamic B-tree may include applying a dynamic multi-resolution grid to multiple regions of the wafer surface profile. In regions where the grid covers more features, denser features, and / or key or critical features, the back end 504 may be configured to increase the resolution of the grid and store more geometric information and / or other information about the surface profile. For example, such regions may include the edges of features on the surface. In regions where the grid covers fewer, sparser, and / or less important features, the back end 504 may be configured to reduce the resolution of the grid and store less geometric information and / or other information about the surface profile. Such regions may include planar regions and / or plateaus where the size and / or material properties of the surface of the wafer do not change. The grid can be dynamic in the sense that the grid resolution can change across the layers of the wafer as features change through the thickness of the wafer (e.g., in the z-direction), between layers, for the same surface point that changes at various iteration times during simulation, and so on. Storing geometric information and / or other information about the surface profile can include sampling information at different points on the wafer surface, extracting local surface properties, determining dimensions, and so on (such that more information is stored for more points where the grid resolution is high, and less information is stored for fewer points where the grid resolution is low). In some embodiments, using a volumetric dynamic B-tree to generate the volumetric representation of the target area on the wafer reduces the amount of computational and storage resources required by architecture 500 (e.g., because information is stored and / or computations are performed only for areas of the wafer surface where there are more features, denser features, and / or key or critical features).

[0112] As a non-limiting example, Figure 6 The multi-resolution grid 600 is illustrated as being applied to a region 602 of the wafer surface profile. The grid 600 includes resolution boxes 604, 606, 607, 608 having different sizes (e.g., listed from largest to smallest). In regions of the grid 600 that cover more features, denser features, and / or key or critical features (e.g., along the rounded edge 620 of feature 622 in region 602), the back end 504 ( Figure 5) can be configured to increase the resolution of the grid (e.g., using smaller boxes 607 and 608) and store more geometric information and / or other information about the surface profile. For example, such areas may include the edges of features on the surface, such as edge 620. In multiple areas of the grid 600 that cover areas with fewer, sparser, and / or less important features, the back end 504 can be configured to reduce the resolution of the grid (e.g., using larger boxes 604 and 606) and store less geometric information and / or other information about the surface profile. Such areas may include flat areas and / or flat line areas 650, or areas beyond features 652 where the size and / or material properties of the surface of the wafer are not changed.

[0113] Back to Figure 5 In some embodiments, the back end 504 is configured to manipulate the volume representation of the target region of the wafer using a level set method (LSM). In some embodiments, manipulating the volume representation of the target region of the wafer includes operations 542, 544, and / or other operations. LSM is a conceptual framework suitable for tracking the time evolution of a surface. Manipulating the volume representation of the target region of the wafer includes embedding a propagation interface as a zero level set of a higher dimensional level set function φ. Figure 6 Such a function of the characteristics shown in can be, for example,

[0114]

[0115] For example, where φ(x,y)>0 for the region outside the circle and φ(x,y)>0 for the region inside the circle. The motion of the interface is then described by manipulating the level set function φ. Given the location of the interface (e.g., between a layer of the wafer stack and air), a new location of the front end (e.g., the surface of the wafer at the interface) can be predicted based on the velocities at multiple individual points on the surface at the interface itself (determined based on φ). The velocities, in turn, depend on the solutions (described below) associated with various systems of equations for plasma physics, particle transport, surface chemical reactions, etc. determined by the front end 502.

[0116] For example, Figure 7 Tracking the time evolution 700 of a surface 702 is illustrated. In some embodiments, the equation of motion for the surface 702 (used to track the location of the surface 702 at multiple individual time points t) may be:

[0117]

[0118] where v is a velocity function (e.g., as described below). (speed in the normal direction), then:

[0119]

[0120] F can be the normal component of the velocity function. For example, there can be different values ​​of F at each individual point across the entire surface 702. The value of F can depend, for example, on wafer characteristics, such as the density or size of features in the region (e.g., the size of the open space in the design), the process being performed (e.g., etching, deposition, etc.), and / or other characteristics. Thus, the motion of the surface 702 (e.g., the interface between the wafer layer and the surrounding environment) can be modeled based on the velocity function.

[0121] Figure 7 Also illustrated is a cross-sectional view 704 of the time evolution 700 of a surface 702. The surface 702 is located at the interface of a wafer 708 (including portions 710, 712, 714, and 716) and air 720. An initial boundary 703 of the surface 702 may be set to zero (level set) and a signed distance field (SDF) may be determined 750. An SDF is a scalar field whose each value indicates a distance to an implied surface, where the sign of the value indicates (by convention) inside or outside. Level set functions are often, or start out as, SDFs, but manipulating the level sets may "destroy" the signed distance property because the values ​​are no longer exact distances, necessitating the need to periodically reinitialize / renormalize the level sets to SDFs again. The SDF property is (especially) useful for ray tracing (described herein) for visibility / flux computations, since it allows efficient traversal along surface normals, with the step size (distance) being read directly from the level set function (this is often referred to as "ray stepping"). Figure 7 As shown in , the boundary 703 evolves over time by means of advection of the level set function (described herein).

[0122] Back to Figure 5There are some simulators that can numerically model complex operations in patterning process flows such as etching. However, rigorous process (e.g., plasma etching) modeling is computationally expensive, at least due to the multi-scale nature of the phenomena involved, ranging from plasma physics to fluid transport and surface chemical reactions. From the perspective of numerical modeling, it is complex to combine mathematical equations associated with such phenomena at different spatial scales (and therefore time scales), because the discretization scheme must follow the multi-scale nature of the problem. In the patterning process flow (e.g., etching), rigorous modeling of operations usually requires solving very different physical equations (plasma physics in reactors, particle transport, surface chemical reactions, electromagnetic equations, surface time evolution, etc.) at the same time. These often require different discretization schemes. Therefore, there is no unified architecture that can adapt to the entire modeling process. This may result in the need to be modeled and / or consider a large number of parameters, which results in surprisingly long simulation times. In addition, the specific parameters of the simulation are usually a priori unknown, and many experiments may be required to tune the model parameters. For example, the ion set that may be present in a specific plasma gas experiment is unknown, and can be guessed until the result matches the observed value. Typically, developed gas phase chemistry methods include dozens of species and hundreds of chemical reactions. Current academic plasma and chemical models are based on a large number of assumptions and there is no such thing as a true ab initio model, i.e., a model from scratch. Data-driven methods alone often produce complex erroneous trends with artificial effects, rely on weighting to compromise among patterns (e.g., due to insufficient predictive power), lack a physical basis, and / or have other shortcomings.

[0123] In contrast, the present systems and methods utilize velocity (or rate) functions to model complex plasma physics, particle transport, surface chemical reactions, etc. In some embodiments, determining the velocity function includes one or more of operations 540, 512, and / or Figure 5 . In some embodiments, the front end 502 can be configured such that the function associated with the process physics and / or process chemistry of the operations within the patterning process flow is a velocity function. In some embodiments, the velocity function describes the motion of the surface of the wafer at the interface between the wafer and the environment surrounding the wafer (e.g., as described above with respect to LSM). In an embodiment, the velocity function is configured to produce different velocity values ​​for different points on the surface. The different velocity values ​​vary with the process physics and / or process chemistry of the operations within the patterning process flow for different points on the surface of the wafer.

[0124] For example, the combined effects of complex plasma physics, particle transport, surface chemical reactions, and the like can be approximated by a simplified velocity function that depends only on a very restricted set of parameters. These parameters do not necessarily correspond to the mathematical parameters that appear in the physical equations associated with the phenomena. The architecture 500 does not solve such physical equations. Instead, the architecture 500 (the front end 502 and / or the front end preparation portion 506) determines their combined effects to produce a velocity function v. The velocity function is formulated in a manner that accurately represents the behavior of the manufacturing operation. For example, in the case of etching, it is known that open areas tend to etch faster. The velocity function is configured to take this into account because it depends on the fraction of energy collected from the plasma source (e.g., estimated by means of ray tracing techniques described below). The velocity function is configurable and can be designed to reproduce the expected (observed) evolution of the surface profile of the wafer during processing in a quantitative manner, with parameters calibrated for quantitative matching.

[0125] In some embodiments, a function associated with process physics and / or process chemistry of operations within a patterning process flow, such as the speed function described above, includes qualitative parameters and numerical constants associated with the qualitative parameters. The numerical constants are determined by the front end 502 using a machine learning model configured to enhance consistency between measurements made on a physical wafer and the predicted wafer geometry from the back end 504.

[0126] For example, the front end 502 and / or the front end preparation portion 506 may use machine learning to calibrate the velocity function. Calibration may include determining parameters of the velocity function (e.g., parameters of a partial differential equation governing the evolution of the surface during the wafer fabrication (etching) process). These parameters may be determined as follows: (1) The velocity function v may be configured to qualitatively reproduce the expected behavior according to the following equation

[0127] v=v(x)

[0128] where x is a general vector representing the parameters of the function. For example, the function v can be configured to account for the angular energy spectrum of the plasma source, dependence on the material being etched, and / or other features such as charging effects and / or microgrooving. (2) The numerical constants of the function can be calibrated according to the following equation using machine learning (e.g., minimizing the error generated by the function relative to a large set of critical dimension scanning electron microscopy measurements made on physical wafers):

[0129] exist Under the conditions

[0130] where f(x) is a measure of the error, and I and J are sets (possibly empty sets) of indices defining the constraints. This calibration consists of exploring the parameter space X (x∈X) to find a point x0∈X that best approximates the mapping from the developed (AD) profile to the etched (AE) profile (for this etch example).

[0131] As a non-limiting example, Figure 8 Schematically illustrates training 800, applying 802, evaluating 804, and updating 806 the model including the speed function (e.g. Figure 5 ). In this example, training 800 can be based on known AD / AE pair profile information. Information 810 related to AD stacks, processes and / or model parameters, and / or other information can be input into the model and the model can be applied 802. Model outputs 820 (e.g., AE stacks 822 and / or other outputs) can be evaluated 804 based on, for example, SEM images 830 of corresponding physical wafers and / or other information. Evaluation 804 can include, for example, determining the difference between the predicted AD stack and the actual image of the corresponding stack. Update 806 can be based on evaluation 804 and / or other information. For example, update 806 can include updating the speed function and / or other updates.

[0132] Back to Figure 5 , after calibration, the speed function generated by the front end 502 (and / or the front end portion 506) in conjunction with the back end 504 can provide a simplified and configurable model of a process operation (e.g., etching) that does not require modeling and solving physical equations associated with the complex physical phenomena that occur during processing. Due to this, the user of the architecture 500 does not need to be an expert who can set up complex physical simulations or have in-depth knowledge about a specific wafer manufacturing (e.g., etching) process. In addition, simulation times can be measured in hours, compared to days or weeks of simulation times for previous systems.

[0133] In some embodiments, the front end 502 (and / or the front end preparation portion 506) is configured to determine, using ray tracing, incident flux at a plurality of separate points on a modeled surface of the wafer at an interface between the wafer and an environment surrounding the wafer (e.g., for a moving surface associated with the LSM described above). In some embodiments, this may include, for example, Figure 5 In some embodiments, the function associated with the process physics and / or process chemistry of the operation within the patterning process flow is a level set function and is processed using a graphics processing unit (e.g., as described below). Fig. 9) directly performs the incident flux determination based on a level set function. (As a simplified illustration, the level set function is a scalar field describing the geometry and the velocity function is a vector field used to convect the level set function.) In some embodiments, the front end 502 is configured to use ray tracing to determine the incident flux based on a representation of the wafer generated using a volumetric dynamic B-tree (such as described above).

[0134] For example, there are different methods for simulating the trajectory of particles (e.g., ions, neutral particles, and electrons) near the surface of a wafer during a semiconductor manufacturing process. For example, these methods include Monte Carlo simulations. In order to increase the simulation rate while retaining simulation accuracy, flux simulations can be used. A general method for performing flux calculations for topography simulations uses ray tracing. This helps to determine the visibility (e.g., the area of ​​the particle source visible / exposed at the surface site) at the sampling point on the simulated surface by tracking some angular distributions of rays from each surface sample point and integrating those rays that can (directly, or after one or more reflections) reach the source plane (e.g., at the particle source).

[0135] Ray tracing may be performed on a mesh representation of the simulated wafer layer surface that does not always match the representation that is best suited for topography manipulation (e.g., as described above). For topography simulations performed as a moving surface problem (e.g., as described herein), where the surface velocity may be determined based on the particle flux of particles reaching the simulated surface (e.g., etching, deposition, and / or other simulations), the representation of the simulated topography may be, for example, a (discretization of) a level set function.

[0136] However, using a traditional (explicit) grid ray tracer requires extracting such a grid at each iteration, after which the ray tracer will have to build acceleration structures (e.g., a bounding volume hierarchy, i.e., a bounding box hierarchy) to be able to efficiently trace rays on the grid. Finally, the ray tracing results need to be mapped back onto the (implicit) level set function. Such grid extraction and bounding volume hierarchy or bounding box hierarchy (BVH) not only construct computationally expensive operations, but they also introduce often unwanted smoothing and precision loss due to numerical dissipation. Projecting the ray tracing results back onto the level set function requires some form of interpolation of visibility samples to the discretized points of the level set function, which is not trivial and may also affect, for example, simulation accuracy. In addition, the requirement to switch representations between those parts of the simulator that determine the surface velocity (via ray tracing) and those parts that transform the simulated morphology (level set convection) can complicate the implementation of an integrated solution that allows information and logic to be shared between these parts.

[0137] Architecture 500 may be implemented as a flux computation directly on the level set function (described above) by means of a ray-walking ray tracer running on a graphics processing unit (GPU) and using the same volume dynamic B-tree (VDB) representation used throughout architecture 500 (e.g., for sampling the surface, extracting local surface properties, convection, etc.). Architecture 500 is an improvement over prior art systems due to at least the combination of: a) using the same representation for both flux computation (ray tracing) and the rest of the simulation; and b) running the ray-walking level set ray tracer on the GPU. This a) saves computation time by not requiring mesh extraction, BVH construction, and projecting the ray tracer results back onto the level set function; b) allows significantly higher ray tracer throughput (in rays / second); and c) prevents and / or otherwise reduces accuracy loss due to numerical dissipation and interpolation. With at least these and other advantages, architecture 500 facilitates simulation of more advanced physical effects that would otherwise result in impractical simulation runtimes.

[0138] Fig. 9 An example of ray-stepping ray tracer functionality is shown. Fig. 9 , a single circle 900 indicates that the ray stepper can advance towards a surface 902 in one step without "overrunning / outgrowing" it. In this way, the ray tracer can find ray-surface intersection points 904 without requiring some explicit representation such as triangles, which is how a "normal" grid-based ray tracer works. Advantageously, where ray-stepping level sets are utilized (as described herein), the closest distance to the surface (e.g., the radius of each circle 900) is the value stored for the level set at that point (e.g., as long as it remains a function of distance and the value is not too perturbed by, for example, convection, thereby requiring the periodic renormalization described above).

[0139] Back to Figure 5In some embodiments, the architecture 500 is configured to determine one or more manufacturing operation process parameters based on the prediction from the back end 504. The architecture 500 can determine adjustments for wafer manufacturing equipment based on the determined one or more process parameters. In some embodiments, the manufacturing operation process includes etching, deposition, chemical mechanical polishing, and / or other wafer manufacturing processes. In some embodiments, the one or more process parameters determined include one or more of mask design, pupil shape, dose, or focus. In some embodiments, the one or more process parameters determined include mask design, and adjusting the wafer manufacturing equipment based on the mask design includes changing the mask design from a first mask design to a second mask design. In some embodiments, the one or more process parameters determined are associated with one or both of particle properties and surface reaction rates. In some embodiments, the method includes adjusting the wafer manufacturing equipment based on the determined adjustments.

[0140] Fig.10 1 is a block diagram illustrating a computer system 100 that can assist in implementing the methods, processes, or systems disclosed herein. The computer system 100 includes a bus 102 or other communication mechanism for communicating information, and a processor 104 (or multiple processors 104 and 105) coupled to the bus 102 for processing information. The computer system 100 also includes a main memory 106, such as a random access memory (RAM) or other dynamic storage device, coupled to the bus 102 for storing information and instructions to be executed by the processor 104. The main memory 106 can also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 104. The computer system 100 also includes a read-only memory (ROM) 108 or other static storage device coupled to the bus 102 for storing static information and instructions for the processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to the bus 102 for storing information and instructions.

[0141] The computer system 100 can be connected to a display 112 via the bus 102, such as a cathode ray tube (CRT) or a flat panel or touch panel display for displaying information to a computer user. An input device 114 including alphanumeric keys and other keys is connected to the bus 102 for communicating information and command selections to the processor 104. Another type of user input device is a cursor control 116, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to the processor 104 and for controlling the movement of a cursor on the display 112. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), which allows the device to specify a position in a plane. A touch panel (screen) display can also be used as an input device.

[0142] According to one embodiment, a portion of one or more methods described herein may be performed by computer system 100 in response to processor 104 executing one or more sequences of one or more instructions contained in main memory 106. Such instructions may be read into main memory 106 from another computer-readable medium such as storage device 110. Executing the sequence of instructions contained in main memory 106 causes processor 104 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequence of instructions contained in main memory 106. In alternative embodiments, hard-wired circuitry may be used in place of, or in combination with, software instructions. Thus, the description herein is not limited to any specific combination of hardware circuitry and software.

[0143] As used herein, the term "computer-readable medium" refers to any medium that participates in providing instructions to the processor 104 for execution. Such media can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 110. Volatile media include dynamic memory, such as main memory 106. Transmission media include coaxial cables, copper wires, and optical fibers, including cables that constitute bus 102. Transmission media can also take the form of sound waves or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, DVDs, any other optical media, punch cards, paper tapes, any other physical media with hole patterns, RAM, PROMs and EPROMs, FLASH-EPROMs, any other memory chips or cartridges, and carrier waves described below, or any other media from which a computer can read.

[0144] Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to the processor 104 for execution. For example, the instructions may be initially carried on a disk of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to the computer system 100 may receive data on the telephone line and convert the data into an infrared signal using an infrared transmitter. An infrared detector connected to the bus 102 may receive the data carried in the infrared signal and place the data on the bus 102. The bus 102 carries the data to the main memory 106, from which the processor 104 retrieves and executes the instructions. The instructions received by the main memory 106 may optionally be stored on the storage device 110 before or after being executed by the processor 104.

[0145] The computer system 100 may also include a communication interface 118 coupled to the bus 102. The communication interface 118 provides bidirectional data communication coupled to a network link 120 connected to a local network 122. For example, the communication interface 118 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, the communication interface 118 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link may also be implemented. In any such implementation, the communication interface 118 sends and receives electrical, electromagnetic, or optical signals carrying digital data streams representing various types of information.

[0146] The network link 120 typically provides data communications to other data devices through one or more networks. For example, the network link 120 can provide a connection to a host computer through a local area network 122 or to a data device operated by an Internet Service Provider (ISP) 126. The ISP 126 in turn provides data communication services through a global packet data communication network, now commonly referred to as the "Internet" 128. Both the local area network 122 and the Internet 128 use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on the network link 120 and through the communication interface 118, which carry the digital data to and from the computer system 100, are example forms of carrier waves that transport the information.

[0147] The computer system 100 can send messages and receive data, including program code, through the network, network link 120, and communication interface 118. In the example of the Internet, the server 130 can transmit the requested code for the application program through the Internet 128, ISP 126, local area network 122, and communication interface 118. For example, one such downloaded application can provide all or part of the methods described herein. The received code can be executed by the processor 104 when it is received, and / or stored in the storage device 110 or other non-volatile storage device for later execution. In this way, the computer system 100 can obtain application code in the form of a carrier wave.

[0148] Fig.11 Schematically depicts a device that can be used in conjunction with the techniques described herein. Figure 1 An exemplary lithographic projection apparatus similar and / or identical to the apparatus shown in . The apparatus comprises:

[0149] - an illumination system IL for conditioning the radiation beam B. In this particular case, the illumination system further comprises a radiation source SO;

[0150] a first object table (e.g. patterning device table) MT having a patterning device holder for holding a patterning device MA (e.g. mask table) and connected to a first positioner for accurately positioning the patterning device relative to the item PS;

[0151] a second object table (substrate table) WT having a substrate holder for holding a substrate W (e.g. a silicon wafer coated with resist) and connected to a second positioner for accurately positioning the substrate relative to item PS;

[0152] - a projection system ("lens") PS (eg a refractive, reflective or catadioptric optical system) for imaging the irradiated portion of the patterning device MA onto a target portion C of the substrate W (eg comprising one or more dies).

[0153] As described herein, the apparatus is of the transmissive type (e.g., employing a transmissive patterning device). However, in general, it may be of the reflective type (e.g., employing a reflective patterning device). The apparatus may employ a different kind of patterning device than a classical mask; examples include a programmable mirror array or an LCD matrix.

[0154] A source SO (e.g. a mercury lamp or an excimer laser, laser produced plasma (LPP) EUV source) generates a radiation beam. This beam is fed into an illumination system (illuminator) IL, for example directly or after having traversed a conditioning device such as a beam expander Ex. The illuminator IL may comprise an adjustment device AD ​​for setting the outer radial extent and / or the inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the beam. In addition, the illuminator IL will typically comprise various other components, such as an integrator IN and a condenser CO. In this way, the beam B impinging on the patterning device MA has a desired uniformity and intensity distribution in its cross section.

[0155] about Fig.11 It should be noted that, although the source SO may be within the housing of the lithographic projection apparatus (this is often the case when the source SO is, for example, a mercury lamp), it may also be remote from the lithographic projection apparatus, the radiation beam it generates being directed into the apparatus (for example, with the aid of appropriate directional mirrors); the latter situation is often the case when the source SO is an excimer laser (for example, based on KrF, ArF or F2 laser action).

[0156] The beam PB is then intercepted at the patterning device MA which is held on the patterning device table MT. Having traversed the patterning device MA, the beam PB passes through a lens PL which focuses the beam B onto a target portion C of the substrate W. With the aid of the second positioning device (and the interferometric measurement device IF), the substrate table WT can be accurately moved, for example, in order to position different target portions C in the path of the beam PB. Similarly, the first positioning device can be used to accurately position the patterning device MA relative to the path of the beam B, for example after mechanically acquiring the patterning device MA from a patterning device library or during scanning. Typically, movement of the object tables MT, WT will be achieved with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) which are not explicitly depicted. However, in the case of a stepper (as opposed to a step-and-scan tool), the patterning device table MT may be connected only to a short-stroke actuator, or may be fixed.

[0157] The depicted tool can be used in two different modes:

[0158] - in step mode, the patterning device table MT is kept substantially stationary and the entire patterning device image is projected at once (i.e. a single "flash") onto a target portion C. The substrate table WT is then shifted in the x and / or y direction so that a different target portion C can be irradiated by the beam PB;

[0159] - In scan mode, essentially the same applies, except that a given target portion C is not exposed in a single "flash". Alternatively, the patterning device table MT can be moved in a given direction (the so-called "scanning direction", e.g. the y-direction) at a velocity v, so that the projection beam B is scanned over the patterning device image; while the substrate table WT is simultaneously moved in the same or opposite direction at a velocity V=Mv, where M is the magnification of the lens PL (typically M=1 / 4 or 1 / 5). In this way, a relatively large target portion C can be exposed without having to compromise on resolution.

[0160] Fig.12 The apparatus 1000 is shown in more detail, including a source collector module SO, an illumination system IL, and a projection system PS. The source collector module SO is constructed and arranged to maintain a vacuum environment in an enclosure 220 of the source collector module SO. A plasma 210 emitting EUV radiation can be formed by a discharge-generated plasma source. EUV radiation can be generated by a gas or vapor, such as xenon, lithium vapor, or tin vapor, in which a very hot plasma 210 is generated to emit radiation in the EUV range of the electromagnetic spectrum. For example, a hot plasma 210 is generated by causing a discharge of an at least partially ionized plasma. In order to effectively generate radiation, it may be necessary to have, for example, a partial pressure of 10Pa of Xe, Li, Sn vapor, or any other suitable gas or vapor. In an embodiment, an excited tin (Sn) plasma is provided to generate EUV radiation.

[0161] The radiation emitted by the hot plasma 210 is transferred from the source chamber 211 to the collector chamber 212 via an optional gas barrier or contaminant trap 230 (also referred to as a contaminant barrier or foil trap in some cases) positioned in or behind an opening in the source chamber 211. The contaminant trap 230 may include a channel structure. The contaminant trap 230 may also include a gas barrier, or a combination of a gas barrier and a channel structure. As is known in the art, the contaminant trap or contaminant barrier 230 further shown herein includes at least a channel structure.

[0162] The collector chamber 211 may include a radiation collector CO which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation traversing the collector CO may be reflected by the grating spectral filter 240 and then focused at a virtual source point IF along the optical axis indicated by the dash-dot line "O". The virtual source point IF is often referred to as an intermediate focus, and the source collector module is arranged so that the intermediate focus IF is located at or near an opening 221 in the enclosure structure 220. The virtual source point IF is an image of the radiation emitting plasma 210.

[0163] The radiation then traverses an illumination system IL which may include a faceted field mirror arrangement 22 and a faceted pupil mirror arrangement 24 arranged to provide a radiation beam 21 having a desired angular distribution at the patterning device MA, and a radiation intensity having a desired uniformity at the patterning device MA. After reflection of the radiation beam 21 at the patterning device MA held by the support structure MT, a patterned beam 26 is formed and the patterned beam 26 is imaged by the projection system PS via reflective elements 28, 30 onto a substrate W held by a substrate table WT.

[0164] There may typically be more elements than shown in the illumination optics unit IL and the projection system PS. Depending on the type of lithographic apparatus, a grating spectral filter 240 may optionally be present. Furthermore, there may be more mirrors than shown in the figures, for example there may be more than 200 in the projection system PS. Fig.12 1 to 6 additional reflective elements beyond the elements shown.

[0165] like Fig.10 The collector optics CO illustrated in FIG. 1 is depicted as a nested collector with grazing incidence reflectors 253, 254 and 255, merely as an example of a collector (or collector mirror). The grazing incidence reflectors 253, 254 and 255 are arranged axially symmetrically around the optical axis O, and this type of collector optics CO can be used in combination with a discharge produced plasma source, often referred to as a DPP source.

[0166] Alternatively, the source collector module SO may be as follows Fig.13 A portion of the LPP radiation system shown. The laser LA is arranged to deposit laser energy into a fuel such as xenon (Xe), tin (Sn) or lithium (Li), thereby producing a highly ionized plasma 210 with an electron temperature of several tens of electron volts. The high-energy radiation produced during the deexcitation and recombination or recombination of these ions is emitted from the plasma, collected by the near normal incidence collector optics CO, and focused onto an opening 221 in the enclosure structure 220.

[0167] The concepts disclosed herein can simulate or mathematically model any general imaging system for imaging sub-wavelength features, and may be particularly useful in emerging imaging technologies that are capable of producing wavelengths with increasingly smaller sizes. Emerging technologies already in use include extreme ultraviolet (EUV) lithography that can produce 193 nm wavelengths by using ArF lasers and even 157 nm wavelengths by using fluorine lasers. In addition, EUV lithography can produce wavelengths in the range of 20 to 5 nm by using a synchrotron or by using high energy electrons to impinge on a material (solid or plasma) in order to produce photons in this range.

[0168] The embodiments of the present disclosure may be further described in the following aspects.

[0169] 1. A method comprising:

[0170] determining, using a front end of a process model, functions associated with process physics and / or process chemistry of operations within a patterned process flow;

[0171] determining the predicted wafer geometry using a back end of the process model, the back end of the process model including a volumetric representation of a target region on the wafer, the predicted wafer geometry being determined by the back end by applying the function associated with the process physics and / or process chemistry from the front end to manipulate the volumetric representation of the target region on the wafer;

[0172] determining one or more process parameters based on the predictions from the process model; and

[0173] Adjustments to wafer fabrication equipment are determined based on the determined one or more process parameters.

[0174] 2. The method according to aspect 1 further comprises:

[0175] determining, using a second front end of the process model, a second function associated with process physics and / or process chemistry of a second operation within the patterned process flow; and

[0176] A second predicted wafer geometry is determined using the same back end of the process model, the back end of the process model including the same volumetric representation of the target area on the wafer, the second predicted wafer geometry being determined by the back end by applying a second function associated with process physics and / or process chemistry of a second operation within the patterning process flow to manipulate the volumetric representation of the target area on the wafer.

[0177] 3. The method of clause 2, wherein the operation within the patterning process flow comprises etching, and wherein the second operation comprises deposition or chemical mechanical polishing.

[0178] 4. The method of any one of aspects 1 to 3, wherein the one or more process parameters determined include one or more of mask design, pupil shape, dose, or focal length.

[0179] 5. The method of clause 4, wherein the one or more process parameters determined include the mask design, and adjusting the wafer fabrication equipment based on the mask design includes changing the mask design from a first mask design to a second mask design.

[0180] 6. A method according to any one of aspects 1 to 3, wherein the one or more process parameters determined are associated with one or both of particle properties and surface reaction rates.

[0181] 7. The method of clause 1, further comprising adjusting the wafer fabrication equipment based on the determined adjustment.

[0182] 8. A method comprising:

[0183] determining, using a front end of a process model, functions associated with process physics and / or process chemistry of operations within a patterned process flow; and

[0184] The predicted wafer geometry is determined using a back end of the process model, the back end of the process model comprising a volumetric representation of a target area on the wafer, the predicted wafer geometry being determined by the back end by applying the function associated with the process physics and / or process chemistry from the front end to manipulate the volumetric representation of the target area on the wafer.

[0185] 9. The method of clause 8, further comprising determining, using a second front end of the process model, a second function associated with process physics and / or process chemistry of a second operation within the patterned process flow; and

[0186] A second predicted wafer geometry is determined using the same back end of the process model, the back end of the process model including the same volumetric representation of the target area on the wafer, the second predicted wafer geometry being determined by the back end by applying a second function associated with process physics and / or process chemistry of a second operation within the patterning process flow to manipulate the volumetric representation of the target area on the wafer.

[0187] 10. The method of clause 9, wherein the operation within the patterning process flow comprises etching, and wherein the second operation within the patterning process flow comprises deposition or chemical mechanical polishing.

[0188] 11. The method according to any one of aspects 8 to 10, further comprising implementing, by the process model, a time-based iterative flow control of switching from the front-end logic to the back-end logic.

[0189] 12. A method according to any one of aspects 8 to 11, wherein the front end and the back end communicate via: (1) a set of configurable surface point parameters defined by the front end, the surface point parameters being obtained by the back end from the front end before applying a function from the front end, and (2) a velocity field determined by the front end based on the surface point parameters.

[0190] 13. The method of any one of clauses 8 to 12, further comprising generating the volume representation of the target area on the wafer using a volumetric dynamic B-tree with the back end of the process model.

[0191] 14. The method of any one of clauses 8 to 13, further comprising manipulating the volume representation of the target region on the wafer using a level set method with the back end of the process model.

[0192] 15. The method of any one of aspects 8 to 14, wherein the function associated with process physics and / or process chemistry of the operations within the patterning process flow is a speed / rate function.

[0193] 16. The method of clause 15, wherein the velocity / speed function describes the motion of the surface of the wafer at an interface between the wafer and an environment surrounding the wafer.

[0194] 17. A method according to aspect 16, wherein the speed / rate function is configured to generate different speed values ​​for different points on the surface, and the different speed values ​​vary with the process physics and / or process chemistry of the operation within the patterning process flow for different points on the surface of the wafer.

[0195] 18. A method according to any one of Aspects 8 to 17, wherein the function associated with the process physics and / or process chemistry of the operation within the patterning process flow includes qualitative parameters and numerical constants associated with the qualitative parameters, and the numerical constants are determined by the front end using a machine learning model, and the machine learning model is configured to enhance the consistency between measurements made on the physical wafer and the predicted wafer geometry from the back end.

[0196] 19. The method of any one of aspects 8 to 18, further comprising using ray tracing with the front end of the process model to determine incident flux at multiple individual points on the modeled surface of the wafer at the interface between the wafer and the environment surrounding the wafer.

[0197] 20. A method according to aspect 19, wherein the function associated with the process physics and / or process chemistry of the operations within the patterning process flow is a level aggregate velocity function, and wherein the incident flux determination is performed directly from the level aggregate function using a graphics processing unit.

[0198] 21. The method of clause 20, further comprising utilizing the graphics processing unit to perform ray tracing based on the level set function to increase a rate of modeling.

[0199] 22. The method of clause 20, further comprising determining the incident flux using ray tracing based on a representation of the target area on the wafer generated using a volumetric dynamic B-tree.

[0200] 23. The method of clause 8, wherein the operations within the patterning process flow include etching, deposition, or chemical mechanical polishing.

[0201] 24. A computer program product, comprising a non-transitory computer-readable medium having recorded thereon instructions, the instructions implementing the method according to any one of aspects 1 to 23 when executed by a computer.

[0202] Although the concepts disclosed herein can be used for wafer fabrication on substrates such as silicon wafers, it should be understood that the disclosed concepts can be used with any type of manufacturing system, for example, a manufacturing system for fabrication on substrates other than silicon wafers. In addition, combinations and sub-combinations of the disclosed elements can include multiple separate embodiments. For example, the front end and the back end of the software architecture can include multiple separate embodiments, and / or these features can be used together in the same embodiment.

[0203] The above description is intended to be illustrative rather than limiting. Accordingly, those skilled in the art will appreciate that modifications may be made to the described invention without departing from the scope of the claims set forth below.

Claims

1. A method for patterning process modeling, comprising: determining, using a front end of a process model, functions associated with process physics and / or process chemistry of operations within a patterned process flow; and A predicted wafer geometry is determined using a back end of the process model, wherein the back end of the process model includes a volumetric representation of a target area on the wafer, wherein the predicted wafer geometry is determined by the back end by applying the function associated with the process physics and / or process chemistry from the front end to manipulate the volumetric representation of the target area on the wafer.

2. The method according to claim 1, further comprising: determining, using a second front end of the process model, a second function associated with process physics and / or process chemistry of a second operation within the patterned process flow; and A second predicted wafer geometry is determined using the same back end of the process model, the back end of the process model including the same volumetric representation of the target area on the wafer, the second predicted wafer geometry being determined by the back end by applying a second function associated with process physics and / or process chemistry of a second operation within the patterning process flow to manipulate the volumetric representation of the target area on the wafer. 3 . The method of claim 2 , wherein the operation within the patterning process flow comprises etching, and wherein the second operation within the patterning process flow comprises deposition or chemical mechanical polishing. 4 . The method of claim 1 , further comprising implementing, by the process model, time-based iterative flow control of switching from front-end logic to back-end logic.

5. The method of claim 1 , wherein the front end and the back end communicate via: (1) a set of configurable surface point parameters defined by the front end, and (2) a velocity field determined by the front end based on the surface point parameters, the surface point parameters being obtained by the back end from the front end before applying a function from the front end.

6. The method of claim 1 further comprising generating the volume representation of the target area on the wafer using a volumetric dynamic B-tree with the back end of the process model.

7. The method of claim 1 further comprising manipulating the volume representation of the target region on the wafer using a level set method with the back end of the process model.

8. The method of claim 1, wherein the function associated with process physics and / or process chemistry of the operations within the patterning process flow is a speed / rate function.

9. The method of claim 8, wherein the speed / velocity function describes the motion of the surface of the wafer at an interface between the wafer and an environment surrounding the wafer.

10. The method of claim 9, wherein the speed / rate function is configured to produce different speed values ​​for different points on the surface, the different speed values ​​varying with process physics and / or process chemistry of the operations within the patterning process flow for different points on the surface of the wafer.

11. A method according to claim 1, wherein the function associated with the process physics and / or process chemistry of the operation within the patterning process flow includes qualitative parameters and numerical constants associated with the qualitative parameters, and the numerical constants are determined by the front end using a machine learning model, and the machine learning model is configured to enhance the consistency between measurements made on the physical wafer and the predicted wafer geometry from the back end.

12. The method of claim 1 further comprising determining, with the front end of the process model, using ray tracing, incident flux at a plurality of separate points on a modeled surface of the wafer at an interface between the wafer and an environment surrounding the wafer.

13. The method of claim 12, wherein the function associated with the process physics and / or process chemistry of the operations within the patterning process flow is a level aggregate velocity function, and wherein incident flux determination is performed directly from the level aggregate function using a graphics processing unit.

14. The method of claim 13, further comprising determining the incident flux using ray tracing based on a representation of the target area on the wafer generated using a volumetric dynamic B-tree.

15. The method of claim 1, wherein the operations within the patterning process flow include etching, deposition, or chemical mechanical polishing.

16. The method of claim 1 , wherein the front end of the process model is a domain specific simulation logic that implements the physics and / or chemistry methods of a specific process model for simulation, and the back end of the process model is a volumetric representation that uses a volume dynamic B-tree (VDB) to store simulation states and a level set method (LSM) for manipulating the simulation states.

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