An Inter-instruction Variable Dependency Analysis Method for Predicate Execution Vector Processors

Abstract

The present invention discloses a method for analyzing variable dependencies between instructions of a vector processor, the method comprising: top-level processing of variable dependencies between instructions in a basic block and their predecessor instructions; category analysis of dependencies between conventional variables and shared combination variables between instructions; accurate analysis and judgment of variable dependencies under predicate execution; accurate analysis and judgment of variable dependencies under predicate execution. The present invention can accurately analyze variable dependencies between instructions for codes that use conventional variables and shared combination variables in a processor that supports predicate execution, effectively avoid redundant dependency edges formed by dependency transfer, and provide more opportunities for improving instruction parallelism.

Description

Technical Field

[0001] The present invention relates to the technical field of code optimization compilation, and in particular to a method for analyzing the dependency relationship between instructions in a basic block caused by using variables, targeting codes of a high-performance vector processor with a predicate execution function. Background Art

[0002] During the compilation process, many processing links need to be based on the dependency information between instructions to proceed normally. In particular, in the current high-performance architecture, technologies such as predicate execution and vector processing are widely used, so correct and effective dependency information between instructions is the basis for ensuring the correctness and effectiveness of many important compilation optimization processes such as register allocation and instruction scheduling. Among them, the dependency between instructions caused by the use of variables is one of the key information. In order to obtain this relationship, it is often necessary to process it through the process of variable dependency analysis between instructions, which is the process of determining the sequential relationship that must be followed by instructions in a basic block due to the use of variables.

[0003] The dependency relationship between instructions in a basic block is generally described by a directed acyclic graph (DAG). In the process of constructing the dependency DAG of a basic block, the prior art method for determining other instructions that a certain instruction depends on is as follows: process all instructions of the basic block in sequence, and for each instruction Ia, analyze its conflict relationship with each instruction Ib before it. If there is a conflict between the two, add an edge between the two instructions to indicate the dependency relationship between them. If it is necessary to adapt to the hardware's capabilities in terms of resource configuration, predicate execution, etc., corresponding processing can be added in certain links.

[0004] However, modern high-performance processors may also have the following characteristics: (1) Scalar processing units and vector (SIMD) processing units coexist, so that scalar instructions and vector instructions exist in the code at the same time; (2) There is a dedicated register group (hereinafter referred to as the channel register group) that acts as a high-speed channel between the scalar processing unit and the vector processing unit to provide data exchange at the register speed level.

[0005] For processors with such characteristics, existing methods have the following problems:

[0006] 1) The identity of the symbolic variables corresponding to the channel register group from the perspective of the scalar processing unit and the vector processing unit is not considered. The channel register group is accessed as a whole in the vector processing unit, but is accessed by its members in the scalar processing unit. Although they are different from the perspective of the two instructions, they physically correspond to the same entity.

[0007] 2) In the mixed instruction sequence of scalar instructions and vector instructions, the order relationship between scalar and vector instructions cannot be correctly analyzed. Since the physical identity of the channel register group and its link in the data processing flow are not considered, the existing method can only consider the two types of instructions as two unrelated aspects in isolation and consider their internal dependencies separately, and the result is bound to be incorrect.

[0008] The above problems cause the existing methods to be unable to obtain the correct dependencies within mixed scalar and vector instruction sequences, and even more unable to support considering predicate characteristics to eliminate redundant dependency edges, thus failing to adapt to the inter-instruction dependency analysis needs of predicate-executed vector processors. Summary of the invention

[0009] The technical problem solved by the present invention is: in view of the shortcomings of the existing inter-instruction dependency analysis method, a method for analyzing the variable dependency between instructions of a vector processor is provided. When analyzing the data dependency caused by the use of variables between instructions in a basic block mixed with scalar processing instructions and vector processing instructions, the influence of the variables corresponding to the channel register group and the predicate execution characteristics of the hardware are fully considered, so that an accurate description of the variable dependency between instructions in the corresponding code can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 : is a schematic diagram of the overall method of the present invention for accurately analyzing the variable dependent instructions of an instruction.

[0011] Figure 2 : It is a logic diagram of the accurate variable dependency analysis method under the predicate execution feature of the method of the present invention.

[0012] Figure 3 : It is a processing logic diagram of the method of the present invention for confirming the variable dependency relationship and attempting to eliminate the instruction variable dependency analysis requirements.

[0013] Figure 4 : is a summary of the specification of the method of the present invention. DETAILED DESCRIPTION

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] The implementation method of the variable dependency analysis method between instructions based on the predicate execution vector processor of the present invention includes: constructing a data model, top-level processing of the variable dependency between instructions and predecessor instructions, category analysis of the regular variables and shared combination class variables between instructions, accurate variable dependency analysis and judgment under predicate execution, variable dependency confirmation and variable dependency analysis demand processing. The implementation content involved in the method of the present invention can be encapsulated in a variable dependency analysis class.

[0016] Since the present invention only involves the problem of analyzing the dependency relationship between variables between instructions in a basic block, it is assumed that the method of the present invention is implemented on the following basic information or modules:

[0017] 1) Basic code information such as basic block information of the code, instruction sequence information, information of each field in the instruction, predicate execution information of the instruction (including execution condition variable name and condition mode), and a collection of various variable names in the instruction (including regular source variable name, regular destination variable name, shared combination source variable name, shared combination destination variable name, etc.), which have been stored in objects of related classes (such as basic block class objects, instruction class objects, etc.);

[0018] 2) Information about the complementary conditional execution instruction pairs in the basic block has been stored in the complementary conditional execution instruction pair set;

[0019] 3) For instruction template information, they are stored in the object of instruction template class;

[0020] 4) For the basic information of the processor's predicate execution vector architecture, they have been saved in the architecture class object.

[0021] In the following description of the specific implementation manner, only the contents directly related to the present invention are involved.

[0022] The method of the present invention needs to construct the following special data models:

[0023] 1) Classification and definition of variable dependency types between instructions: read-after-write, write-after-read, and write-after-write for regular variables; read-after-write, write-after-read, and write-after-write for shared combinational variables.

[0024] 2) SCombVars, a set of shared composite variable names corresponding to basic blocks: The content of this set is gradually added as the instructions in the basic block are traversed. When the variable dependency analysis process reaches an instruction, it contains the names of all shared composite symbolic variables used in the sequence from the beginning of the basic block to the instruction.

[0025] 3) The instnPairInfos set corresponding to the basic block: This set records the variable pseudo-dependency types between instructions found during the variable dependency analysis process and the instruction pair complementary conditional execution information they constitute.

[0026] 4) The set corresponding to the current instruction I:

[0027] a) The source variable set and the target variable set contained in I: their contents are the names of the variables to be read and modified by I respectively;

[0028] b) A collection of shared combination class variables of I: its content is the name of the variable in I that needs to be ultimately mapped to the channel register as a whole or a channel register member;

[0029] c) I's dependent variable set Sdv: It is the variable set to be processed during variable dependency analysis.

[0030] d) The dependent instruction condition variable name set SNC that is no longer considered corresponding to each variable of I:

[0031] The elements in this set will be used to determine whether I has a dependency on the conditionally executed predecessor instruction X. Each variable of the instruction corresponds to an SNC;

[0032] e) I may release some variable dependency analysis requirements involving a set Sa of variable names;

[0033] f) a set varDepTypeSet consisting of I and various variable dependency types of a predecessor instruction;

[0034] g) the set SADICV consisting of the execution condition variable names of all known variable-dependent instructions of I;

[0035] h) I's dependent instruction set and dependent instruction set: the elements in the two sets are other instructions that I depends on and other instructions that depend on I;

[0036] 5) Related flag data of current instruction I:

[0037] a) needAnalyzeFlag: a flag indicating whether the instruction has a variable dependency analysis requirement. This data is only related to the instruction itself. Initially, as long as the variable storing data is used in the instruction, the value is true, otherwise it is false. During the analysis process, once the value is set to false, the process of searching for new variable dependency instructions for the instruction can be stopped.

[0038] b) bDep: A flag indicating that I depends on a predecessor instruction X. True indicates dependency, and false indicates no dependency;

[0039] c) bCanParalExec: A flag indicating that I can be executed in parallel with a predecessor instruction X. True means that it can be executed in parallel, and false means that it cannot be executed in parallel;

[0040] d) bGoOn: Indicates whether to continue the analysis and processing of I related to a predecessor instruction X. Its main function is to determine whether to perform the following processing: analyze the dependency analysis requirements of some dependent variables released by the predecessor instruction. True means that the analysis should continue, false means that it should not continue and switch to the next predecessor instruction.

[0041] The specific steps of the method for analyzing the inter-instruction variable dependency relationship for the predicate execution vector processor in this embodiment are as follows:

[0042] S1. Top-level processing of analyzing variable dependencies between instructions and predecessor instructions;

[0043] S2. Analyze the possible variable dependency types between the instruction and a predecessor instruction;

[0044] S3. Accurate analysis and judgment of variable dependencies in the case of predicate execution;

[0045] S4. Variable dependency confirmation and variable dependency analysis requirements processing.

[0046] In this embodiment, the overall method of analyzing the variable dependency relationship between instruction I and its predecessor instruction in step S1 is as follows: Figure 1 As shown, the specific steps are:

[0047] S11. Perform pre-processing before analysis; this is to prepare some data belonging to I itself that is needed in the analysis process;

[0048] S12. If the variable dependency analysis requirement of I has been released, go to step S18 to end the processing. Otherwise, continue to use the following steps to analyze the variable dependency relationship with I one by one from the first instruction before I to the beginning of the basic block in reverse order.

[0049] S13. Determine whether there is a next predecessor instruction. If there is no next predecessor instruction, go to step S18 to end the process.

[0050] Otherwise, proceed to the following steps;

[0051] S14. Switch to the new predecessor instruction X and analyze whether there is a variable dependency relationship between X and I. If there is no variable dependency relationship, go to step S13. Otherwise, proceed to the following steps;

[0052] S15. Consider the predicate execution characteristics of the hardware to perform accurate variable dependency analysis. This step considers whether I and X are complementary conditional execution instructions, and the impact of the conditional execution between I's predecessor instruction and X or I on the relationship between X and I. In addition, the value of bGoOn is determined depending on the situation;

[0053] S16. If the value of bGoOn is false, go to step S13. Otherwise, proceed to the following steps;

[0054] S17. Perform processing after confirming the variable dependency relationship between I and X, and try to remove the variable dependency analysis requirement of I;

[0055] S18. End the process.

[0056] In this embodiment, the specific steps in step S11 are:

[0057] S111. Initialize the comprehensive variable dependency analysis requirement flag needAnalyzeFlag to true;

[0058] S112. Add the shared composite variable names used by I to the set SCombVars. Here, if the dependency analysis currently being performed is before register allocation is completed, and some of the source or destination variables of I are shared composite class variables, then add these variable names to SCombVars;

[0059] S113. Create a copy of the source variable name set srcVarsCopyI and a copy of the target variable name set aimVarsCopyX. The reason for creating the copy here is to ensure that the subsequent addition and deletion of shared combination class variables does not affect the content of the original set, so that the demand for related information in other compilation processing links except variable dependency analysis is not affected;

[0060] S114. If I is a predicate execution instruction, the execution condition variable name and conditional execution mode information of I are read for use in subsequent links;

[0061] S115. Convert the implicit SVR data dependency of I to explicit variable dependency. If any one of srcVarsCopyI is a shared physical register group name, all shared physical register names and the contents of SCombVars are added to srcVarsCopyI. If any one of aimVarsCopyI is a shared physical register group name, all shared physical register names and the contents of SCombVars are added to aimVarsCopyI.

[0062] S116. Create a dependent variable set Sdv of I, which includes regular variables and shared combination class variables involved in I.

[0063] In this embodiment, the specific steps of step S2 are:

[0064] The method for analyzing whether instruction I may be variable dependent on a predecessor instruction X thereof is implemented by the following steps:

[0065] S21. Assume that there is no variable dependency relationship between I and X, and let the set varDepTypeSet be empty;

[0066] S22. If the regular source variable of X has the same name as the regular destination variable of I, then add the regular variable read-after-write dependency type to varDepTypeSet;

[0067] S23. If the regular destination variable of X has the same name as the regular source variable of I, then the regular variable read-after-write dependency type is added to varDepTypeSet;

[0068] S24. If the regular purpose variable of X has the same name as the regular purpose variable of I, then add the regular variable write-after-write dependency type to varDepTypeSet;

[0069] S25. If one of I and X is a scalar instruction and the other is a vector instruction, and X has a shared composite source variable, and I has a shared composite destination variable, then add the shared composite variable read-after-write dependency type to varDepTypeSet;

[0070] S26. If one of I and X is a scalar instruction and the other is a vector instruction, and X has a shared composite destination variable, and I has a shared composite source variable, then add the shared composite variable read-after-write dependency type to varDepTypeSet;

[0071] S27. If one of I and X is a scalar instruction and the other is a vector instruction, and both X and I have a shared composite destination variable, then the shared composite variable write-after-write dependency type is added to varDepTypeSet; if varDepTypeSet is empty, there is no variable dependency relationship between X and I, otherwise, there may be a variable dependency relationship.

[0072] In this embodiment, the specific logic of step S3 is as follows: Figure 2 As shown, the specific steps are:

[0073] S31. Create a copy of the source variable name set srcVarsCopyX of X and a copy of the target variable name set aimVarsCopyX respectively;

[0074] S32. If there is a shared composite variable read-after-write dependency between I and X, all shared composite physical register names and the contents of SCombVars are added to srcVarsCopyX. If there is a shared composite variable write-after-read dependency or a shared composite variable write-after-write dependency between I and X, all shared composite physical register names and the contents of SCombVars are added to aimVarsCopyX.

[0075] S33. Find the difference set: srcVarsCopyX = srcVarsCopyX – aimVarsCopyX. Find the three intersections related to the shared composite variables and the regular variables:

[0076] 1)RWforCVs=srcVarsCopyX∩aimVarsCopyI;

[0077] 2) WRforCVs=aimVarsCopyX∩srcVarsCopyI;

[0078] 3)WWforCVs=aimVarsCopyX∩aimVarsCopyI;

[0079] S34. Analyze or read the conditional mode and conditional quantity of Ipre. If X and I do not meet the characteristics of complementary conditional execution, set bCanParalExec to false, and then go to step S38. Otherwise, execute the next step;

[0080] S35. Set bCanParalExec to true. If the conditional variable of X is already in the variable dependency SADICV set of I, go to step S38. Otherwise, go to the next step;

[0081] S36. Based on the known complementary instruction pair information, analyze whether X has formed a complementary conditional execution instruction pair with an instruction before X. If yes, go to step S38. Otherwise, go to the next step;

[0082] S37. Add the variable pseudo-dependency type between X and I and the instruction pair complementary conditional execution information they constitute to the instnPairInfos set of the basic block. Set bGoOn to false. Go to step S39;

[0083] S38. Set bDep to false and bGoOn to true;

[0084] S39. End of analysis.

[0085] In this embodiment, the specific logic of step S4 is as follows: Figure 3 As shown, the specific steps are:

[0086] S401. Calculate the pure read-after-write variable name set Srw = Sdv∩RWforCVs;

[0087] S402. Calculate the set of dependent variable names that may be eliminated Sa = WRforCVs∪WWforCVs;

[0088] S403. If Sa is not empty, go to the next step. Otherwise, go to step S418;

[0089] S404. If X is an unconditional execution instruction, go to the next step. Otherwise, go to step S416;

[0090] S405. Let x be the first element of Sa;

[0091] S406. Check whether the traversal of each element x in Sa is complete. If yes, go to step S417. Otherwise, go to the next step;

[0092] S407. If the execution condition of X is in the SNC corresponding to x, go to step S412. Otherwise, go to the next step;

[0093] S408. If the conditional quantity of X is not in the known conditional dependency information of X, go to the next step. Otherwise, go to step S413;

[0094] S409. Add a dependency instruction and its conditional amount and conditional mode information for the dependent variable name x;

[0095] S410. Add the conditional quantity of X to the SADICV set corresponding to x;

[0096] S411. Set bDep to true;

[0097] S412. Let x be the next element of Sa. Go to step S46;

[0098] S413. If X is the same as the conditional variable of the dependent instruction Ia that has been found, and the conditional mode is opposite, and the conditional variable A of X has not been newly set in the interval [X, Ia), then the variable dependency analysis of x is canceled and the process goes to step S411. Otherwise, it can be determined that I does not depend on X due to accessing variable x, and the process goes to the next step;

[0099] S414. Analyze whether the following conditions are met: X has the same conditional variable and conditional mode as the already discovered I-dependent instruction Ia (i.e., has the same execution condition), and the conditional variable A of X has not been newly set in the interval [X, Ia). If yes, go to step S412, otherwise, go to the next step;

[0100] S415. Delete the conditional dependency information of x related to the conditional variable A of X from the dependency information of x. Add A to the dependent instruction of x and no longer consider the conditional variable set SNC. Go to step S412;

[0101] S416. Set bDep to true. Remove the need for variable dependency analysis for all elements in Sa;

[0102] S417. If Sdv is not empty, go to step S418. Otherwise, set needAnalyzeFlag to false, clear the relevant data obtained by variable dependency analysis, and go to step S419;

[0103] S418. If Srw is not empty, set bDep to true;

[0104] S419. If the dependency flag bDep of X and I is true, and bCanParalExec is false, the variable dependency relationship between them is recorded in their respective dependent instruction sets and dependent instruction sets;

[0105] S420. End analysis.

Claims

1. A method for analyzing inter-instruction variable dependencies for a predicate execution vector processor, characterized in that: The method includes: S1. Top-level processing of analyzing variable dependencies between instructions and predecessor instructions; S2. Analyze the possible variable dependency types between the instruction and a predecessor instruction; S3. Accurate analysis and judgment of variable dependencies in the case of predicate execution; S4. Variable dependency confirmation and variable dependency analysis requirements processing; The specific steps in step S1 are: S11. Perform pre-processing before analysis; this is to prepare some data belonging to I itself that is needed in the analysis process; S12. If the variable dependency analysis requirement of I has been released, go to step S18 to end the processing. Otherwise, continue to use the following steps to analyze the variable dependency relationship with I one by one from the first instruction before I to the beginning of the basic block in reverse order. S13 determines whether there is a next predecessor instruction; if there is no more, go to step S18 to end the process; otherwise, proceed to the following steps; S14. Switch to the new predecessor instruction X, and analyze whether there may be a variable dependency relationship between X and I; if there is no variable dependency relationship, go to step S13; otherwise, proceed to the following steps; S15. Consider the predicate execution characteristics of the hardware to perform accurate variable dependency analysis; this step considers whether I and X are complementary conditional execution instructions, and the impact of the conditional execution between the predecessor instruction of I and X or I on the relationship between X and I; in addition, the value of bGoOn is determined according to the situation; S16. If the value of bGoOn is false, go to step S13; otherwise, proceed to the following steps; S17. Perform processing after confirming the variable dependency relationship between I and X, and try to remove the variable dependency analysis requirement of I; S18. End the process; The specific steps in step S11 are: S111. Initialize the comprehensive variable dependency analysis requirement flag needAnalyzeFlag to true; S112. Add the shared composite variable names used by I to the set SCombVars; here, if the dependency analysis currently being performed is before register allocation is completed, and some of the source or destination variables of I are shared composite class variables, then add these variable names to SCombVars; S113. Create a copy of the source variable name set srcVarsCopyI of I, and a copy of the target variable name set aimVarsCopyX; the reason for creating the copy here is to ensure that the subsequent addition and deletion of shared combination class variables does not affect the content of the original set, so that the demand for related information in other compilation processing links except variable dependency analysis is not affected; S114. If I is a predicate execution instruction, the execution condition variable name and conditional execution mode information of I are read for use in subsequent links; S115. Convert the implicit SVR data dependency of I into explicit variable dependency; if any one of srcVarsCopyI is a shared physical register group name, then all shared physical register names and the contents of SCombVars are added to srcVarsCopyI; if any one of aimVarsCopyI is a shared physical register group name, then all shared physical register names and the contents of SCombVars are added to aimVarsCopyI; S116. Create a dependent variable set Sdv of I, which includes regular variables and shared combination class variables involved in I; The specific steps in step S2 are: S21. Assume that there is no variable dependency relationship between I and X, and let the set varDepTypeSet be empty; S22. If the regular source variable of X has the same name as the regular destination variable of I, then add the regular variable read-after-write dependency type to varDepTypeSet; S23. If the regular destination variable of X has the same name as the regular source variable of I, then the regular variable read-after-write dependency type is added to varDepTypeSet; S24. If the regular purpose variable of X has the same name as the regular purpose variable of I, then add the regular variable write-after-write dependency type to varDepTypeSet; S25. If one of I and X is a scalar instruction and the other is a vector instruction, and X has a shared composite source variable, and I has a shared composite destination variable, then add the shared composite variable read-after-write dependency type to varDepTypeSet; S26. If one of I and X is a scalar instruction and the other is a vector instruction, and X has a shared composite destination variable, and I has a shared composite source variable, then add the shared composite variable read-after-write dependency type to varDepTypeSet; S27. If one of I and X is a scalar instruction and the other is a vector instruction, and both X and I have a shared composite destination variable, then add the shared composite variable write-after-write dependency type to varDepTypeSet; if varDepTypeSet is empty, there is no variable dependency relationship between X and I, otherwise, there may be a variable dependency relationship; The specific steps in step S3 are: S31. Create a copy of the source variable name set srcVarsCopyX of X and a copy of the target variable name set aimVarsCopyX respectively; S32. If there is a shared composite variable read-after-write dependency between I and X, all shared composite physical register names and the contents of SCombVars are added to srcVarsCopyX; if there is a shared composite variable write-after-read dependency or a shared composite variable write-after-write dependency between I and X, all shared composite physical register names and the contents of SCombVars are added to aimVarsCopyX; S33. Find the difference set: srcVarsCopyX = srcVarsCopyX – aimVarsCopyX; Find the three intersections related to the shared combination variables and the regular variables: 1)RWforCVs=srcVarsCopyX∩aimVarsCopyI; 2) WRforCVs=aimVarsCopyX∩srcVarsCopyI; 3)WWforCVs=aimVarsCopyX∩aimVarsCopyI; S34. Analyze or read the conditional mode and conditional amount of Ipre; if X and I do not satisfy the characteristics of complementary conditional execution, set bCanParalExec to false, and then go to step S38; otherwise, execute the next step; S35. Set bCanParalExec to true; if the conditional variable of X is already in the variable dependency SADICV set of I, go to step S38; otherwise, go to the next step; S36. According to the known complementary instruction pair information, analyze whether X has formed a complementary conditional execution instruction pair with an instruction before X; if so, go to step S38; otherwise, execute the next step; S37. Add the variable pseudo dependency type between X and I and the instruction pair complementary conditional execution information they constitute to the instnPairInfos set of the basic block; set bGoOn to false; go to step S39; S38. Set bDep to false and bGoOn to true; S39. End of analysis; The specific steps in step S4 are: S401. Calculate the pure read-after-write variable name set Srw = Sdv∩RWforCVs; S402. Calculate the set of dependent variable names that may be eliminated Sa = WRforCVs∪WWforCVs; S403. If Sa is not empty, go to the next step; otherwise go to step S418; S404. If X is an unconditional execution instruction, go to the next step; otherwise, go to step S416; S405. Let x be the first element of Sa; S406. Whether the traversal of each element x in Sa is completed, if yes, go to step S417; otherwise, go to the next step; S407. If the execution condition of X is in the SNC corresponding to x, go to step S412; otherwise, go to the next step; S408. If the conditional quantity of X is not in the known conditional dependency information of x, go to the next step; otherwise, go to step S413; S409. Add a dependency instruction and its conditional amount and conditional mode information for the dependent variable name x; S410. Add the conditional quantity of X to the SADICV set corresponding to x; S411. Set bDep to true; S412. Let x be the next element of Sa; go to step S46; S413. If X is the same as the conditional variable of the dependent instruction Ia that has been found, and the conditional mode is opposite, and the conditional variable A of X has not been newly set in the interval [X, Ia), then the variable dependency analysis of x is released and the process goes to step S411; otherwise, it can be determined that I does not depend on X due to accessing variable x, and the process goes to the next step; S414. Analyze whether the following conditions are met: X has the same conditional variable and conditional mode as the already discovered I-dependent instruction Ia (i.e., has the same execution condition), and the conditional variable A of X has not been newly set in the interval [X, Ia); if so, go to step S412, otherwise, go to the next step; S415. Delete the conditional dependency information of x related to the condition variable A of X from the dependency information of x; add A to the dependent instruction of x and no longer consider the conditional variable set SNC; go to step S412; S416. Set bDep to true; remove the requirement for variable dependency analysis for all elements in Sa; S417. If Sdv is not empty, go to step S418; otherwise, set needAnalyzeFlag to false, clear the relevant data obtained by the variable dependency analysis, and go to step S419; S418. If Srw is not empty, set bDep to true; S419. If the dependency flag bDep of X and I is true, and bCanParalExec is false, the variable dependency relationship between them is recorded in their respective dependent instruction sets and dependent instruction sets; S420. End analysis.

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