Method of forming an integrated circuit (IC) device and integrated circuit device

Abstract

An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed above the first substrate; and a second substrate disposed above the dielectric layer. The second substrate includes an anchoring region including silicon extending upward from the dielectric layer; and a series of mutually intersecting fingers extending from an inner sidewall of the anchoring region. The mutually intersecting fingers generally extend parallel to each other in a first direction and have respective finger lengths generally extending in the first direction. A plurality of silicon-containing peaks are disposed on the dielectric layer directly below the respective fingers. A series of mutually intersecting fingers are suspended above the plurality of peaks. A first peak is disposed below the base of the finger and has a first height, and a second peak is disposed below the tip of the finger and has a second height less than the first height. Embodiments of the present application also relate to a method of forming an integrated circuit (IC) device.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming integrated circuit (IC) devices and integrated circuit devices. Background Art

[0002] Microelectromechanical systems (MEMS) devices are becoming increasingly prevalent in modern devices (e.g., accelerometers, gyroscopes, microphones, smart speakers, hearing aids, camera devices). Many MEMS devices can be classified as sensors or actuators. Some MEMS sensors sense the presence of an external condition (e.g., acceleration, sound waves, light, magnetic signals) and communicate the presence of that condition as an electrical signal (e.g., voltage, current). Some MEMS sensors (such as accelerometers or gyroscopes) can use a comb structure that utilizes the electrostatic principle to detect changes in motion or pressure. Summary of the Invention

[0003] Some embodiments of the present application provide a method of forming an integrated circuit (IC) device, the method comprising: forming a dielectric layer over a first wafer; providing a second wafer over the dielectric layer; forming a plurality of trenches in an upper surface of the second wafer opposite the dielectric layer; forming a dielectric liner along lower portions and sidewalls of the plurality of trenches and filling remaining portions of the plurality of trenches with a conductive material to establish a series of intersecting fingers, the finger lengths of the intersecting fingers generally extending parallel to each other in a first direction; forming a mask over the upper surface of the second wafer, wherein the mask includes a series of openings disposed between outer sidewalls of adjacent fingers and wherein a first area of a first opening near a base of a finger is greater than a second area of a second opening near a tip of the finger; and performing an etch with the mask in place to form cavities between sidewalls of the intersecting fingers and between a bottom surface of the intersecting fingers and an upper surface of the dielectric layer.

[0004] Some other embodiments of the present application provide an integrated circuit (IC) device, comprising: a first substrate; a dielectric layer disposed above the first substrate; a second substrate disposed above the dielectric layer, wherein the second substrate includes an anchoring region including silicon extending upward from the dielectric layer; a series of mutually intersecting fingers extending from an inner sidewall of the anchoring region, wherein the mutually intersecting fingers generally extend parallel to each other in a first direction and have corresponding finger lengths generally extending in the first direction; and a plurality of silicon-containing peaks respectively disposed on the dielectric layer directly below the series of mutually intersecting fingers, wherein the series of mutually intersecting fingers are suspended above the plurality of peaks, and wherein a first peak disposed below a base of a finger has a first height, and a second peak disposed below a tip of the finger has a second height less than the first height.

[0005] Some further embodiments of the present application provide an integrated circuit (IC) device, comprising: a complementary metal oxide semiconductor (CMOS) substrate including a plurality of semiconductor devices disposed in the complementary metal oxide semiconductor substrate; an interconnect structure disposed above the complementary metal oxide semiconductor substrate; a dielectric layer disposed above the interconnect structure; a microelectromechanical system (MEMS) substrate disposed above the dielectric layer, wherein the MEMS substrate includes an anchoring region including silicon extending upward from the dielectric layer, and a plurality of conductive fingers intersect each other and are suspended above the dielectric layer; a cover substrate disposed above the MEMS substrate and establishing a cavity in which the conductive fingers are disposed, wherein a lower surface of the cavity is defined by an upper surface of the dielectric layer; and a plurality of silicon-containing peaks respectively disposed on the dielectric layer directly below the plurality of fingers, wherein a first peak of the plurality of peaks is disposed below a base of a finger and has a first height, and a second peak of the plurality of peaks is disposed below a tip of the finger and has a second height less than the first height. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A flowchart corresponding to some embodiments of a method of forming a MEMS structure is shown.

[0008] Figures 2A to 2D to Figures 8A to 8F Provided is a diagram showing for manufacturing with Figure 1A series of top views, cross-sectional views, and perspective views of some embodiments of a method for a consistent IC device.

[0009] Figure 9 A cross-sectional view of another IC device according to some embodiments is shown. Detailed Description

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0012] Microelectromechanical system (MEMS) structures can be used in devices such as cameras in mobile phones, such as, for example, accelerometers, gyroscopes, and / or optical image stabilizer systems. The MEMS structure can include a first comb structure and a second comb structure that are arranged such that the fingers of the first comb cross the fingers of the second comb, and the fingers of both the first and second combs are in a plane. During operation, the first comb can be held fixed in the plane while the second comb can slide relative to the first comb in the plane, for example, due to the acceleration experienced by the MEMS structure, such that the distance between the fingers of the first and second combs moves. This movement in the distance between the fingers of the first and second combs can correspond to the acceleration experienced by the MEMS structure and can be detected by capacitive sensing techniques, thereby allowing the detection of acceleration. Sound or other conditions can also be detected in a similar manner.

[0013] During the fabrication of MEMS structures, the fingers of the first comb and the second comb are formed to be initially attached to other (e.g., underlying) structures of the substrate and then released from those other structures by using a release etch. In some cases, even after the release etch, due to minor variations in the etch process above the wafer during fabrication, some fingers may still remain attached (i.e., "stuck") to the substrate. To "tear" or "pry" any such stuck fingers from the substrate, a finger release process can be used to apply a force to an individual finger (or to the entire comb structure). For example, the force can be applied by mechanical techniques or electrostatic techniques. Regardless of the exact technique used to apply such a force, some aspects of the present invention lie in realizing that if the tip of the finger is still attached to the underlying substrate when the finger release process is applied, the force is likely to cause the finger to break. In some cases, this may still allow the MEMS structure to function, but with reduced sensitivity, while in other cases, this may render the MEMS structure inoperable.

[0014] Accordingly, various embodiments of the present invention relate to methods of forming MEMS structures, wherein the release etch is configured such that the tips of the fingers are released from the substrate cleaner / more completely than the bases of such fingers, such that if any part of a finger "sticks" to the substrate, it will be the base of the finger rather than the tip. Thus, when the finger release process is applied to the MEMS structure, the chance of the finger breaking is much smaller than if the tip of the finger were still attached. In some embodiments, this is achieved by patterning a mask over the MEMS structure. The mask generally covers the fingers but has openings spaced above the gaps between the fingers, where the openings closer to the base of the finger are smaller than the openings closer to the tip of the finger. The release etch is performed with the mask in place such that the larger openings closer to the tip of the finger facilitate more etching closer to the tip of the finger to help ensure that the tips of the fingers are released from the substrate cleaner / more completely. Again, this can help reduce the chance of the fingers breaking and enhance better functionality for the final MEMS structure.

[0015] Reference Figure 1 , it can be seen a method 100 of forming an integrated circuit according to some embodiments. The method will now be briefly described and then some more specific embodiments will be further described with respect to Figures 2A to 2D to Figures 8A to 8E Each of Figures 2A to 2D to Figures 8A to 8E shows a top view and a series of cross-sectional views consistent with the various operations of method 100. More specifically, FIG. A of each figure shows the top view of each stage, FIGS. B to D of each figure show the respective cross-sectional views of each stage, and FIG. E (where applicable) shows a perspective cross-sectional view. It should be understood that although with respect toFigures 2A to 2D to Figures 8A to 8E The examples of Figure 1 describe a method, but Figure 1 the method of

[0016] is not limited by these examples. Figure 1 Now referring to

[0017] and Figures 2A to 2D to Figures 8A to 8E , various views of some embodiments of a semiconductor structure at various manufacturing stages are provided to illustrate Figure 1 the method of Figure 1 . Although described with respect to Figures 2A to 2D to Figures 8A to 8E the method 100 of Figures 2A to 2D to Figures 8A to 8E , it should be understood that Figures 2A to 2D to Figures 8A to 8E the structures disclosed in Figure 1 are not limited to method 100, but can exist independently as structures independent of method 100. Similarly, although described with respect to Figures 2A to 2D to Figures 8A to 8E the method 100 of Figures 2A to 2D to Figures 8A to 8E , it should be understood that method 100 is not limited to

[0018] Consistent with some embodiments of Figure 1 102 Figures 2A to 2D illustrates a dielectric layer 204 formed over a first wafer 202. In some embodiments, the first wafer is a first single-crystalline silicon wafer or a semiconductor-on-insulator (SOI) wafer. In some embodiments, the dielectric layer 204 is a silicon dioxide layer, a silicon nitride layer, a silicon oxynitride layer, or another dielectric layer. In some embodiments, the dielectric layer 204 is formed by a thermal oxidation process, such as a wet thermal oxidation process or a dry thermal oxidation process. During such an oxidation process, the first wafer 202 is placed in a furnace and heated in the presence of oxygen to a temperature typically in the range between 800 degrees Celsius and 1200 degrees Celsius to form the dielectric layer. In other embodiments, the dielectric layer 204 may be formed by a spin coating process or by plasma vapor deposition, chemical vapor deposition, atomic layer deposition, or other techniques.

[0019] Consistent with some examples of Figure 1 104 Figures 3A to 3D illustrates a second wafer 302, such as a single-crystalline silicon wafer, that has been bonded to the dielectric layer 204. In some embodiments, the second wafer 302 is bonded to the top surface of the dielectric layer 204 by a fusion bonding process. In other embodiments, steps 102 and 104 may be implemented by receiving an SOI wafer instead of bonding the first wafer and the second wafer to each other, where the first wafer 202 corresponds to the processed portion of the SOI wafer, the dielectric layer 204 corresponds to the insulating layer of the SOI wafer, and the second wafer 302 corresponds to the device layer of the SOI wafer.

[0020] Consistent with some examples of Figure 1 106 Figures 4A to 4DShown are a plurality of trenches 402 formed in a surface of the second wafer 302 opposite the dielectric layer 204. To form the trenches 402, a first mask may be formed over the upper surface of the second wafer 302, and with the first mask in place, etching may be performed. After etching, the trenches 402 have a length l in a first direction along the surface of the second wafer 302 and a width w in a second direction perpendicular to the first direction. The trenches 402 generally extend parallel to each other in the first direction. The central regions 408 of the trenches overlap each other in the first direction, and the ends of every other trench extend outwardly in opposite directions from the central region, such that the trenches cross each other. In some embodiments, the structure has a total length t of about 50 microns to 1000 microns in the first direction, and the overlapping central regions 408 have an overlap distance o in the range of about 5% to about 99% of the total length or in the range of about 30% to about 99% of the total length or in the range of 50% to 99% of the total length. In some embodiments, the width w of the trenches 402 is in the range of about 0.5 microns to about 10 microns. In some embodiments, the trenches may also have a depth d in the range of about 50 microns to about 300 microns.

[0021] Consistent with Figure 1 some examples of 108 Figures 5A to 5E Shown are some embodiments in which a dielectric liner 502 is formed along the lower surface and sidewalls of the trenches 402. The dielectric liner 502 leaves an unfilled remainder of the trenches, and then the remainder of the trenches is filled with a conductive material to establish a series of intersecting fingers 504, the finger lengths of which generally extend parallel to each other in the first direction. The fingers 504 include: a base region 504b located at the outermost ends of the total length of the structure; and a tip region 504t located in the central region where the fingers 504 overlap. In some embodiments, the dielectric liner 502 laterally surrounds the fingers 504 on all sides. Typically, after forming the conductive material, a chemical mechanical planarization (CMP) process is performed to remove excess dielectric liner and conductive material from above the trenches, and to planarize the upper surface of the dielectric liner 502 with the upper surface of the conductive material of the intersecting fingers 504 and with the upper surface of the second wafer 302. In some embodiments, the dielectric liner 502 is formed by plasma vapor deposition and / or thermal oxidation and includes the same material as the dielectric layer 204. In some embodiments, the dielectric liner 502 includes silicon dioxide, silicon nitride, silicon oxynitride, or another dielectric layer, and the conductive material of the fingers 504 includes polysilicon or metal.

[0022] Consistent with Figure 1 some examples of 110 Figures 6A to 6ESome embodiments are shown in which a mask 602 is formed above the upper surface of a second wafer 302. The mask 602 includes a series of openings 604 disposed above the second wafer 302 and between the outer sidewalls of adjacent fingers. A first area of a first opening 604a near the base of the finger is greater than a second area of a second opening 604b near the tip of the finger. In some embodiments, this variation in the area of the openings 604 helps ensure that the tips of the fingers are released from the second wafer 302 cleaner / more completely than the bases of such fingers, such that if any part of a finger “sticks” to the second wafer 302, it will be the base of the finger rather than the tip. This is because the larger openings near the tips of the fingers promote more etching near the tips of the fingers and under the tips of the fingers to help ensure that the tips of the fingers are released from the second wafer 302 cleaner / more completely. Also, this can help reduce the chance of a finger breaking and enhance better functionality for the final MEMS structure. In some embodiments, the ratio of the first area of the first opening 604a to the second area of the second opening is in the range of about 0.9999 to 0.01. In some embodiments, the first opening 604a may have a first length L1 in the range of 0.501 microns to 100 microns, the second opening 604b may have a second length L2 in the range of 0.5005 microns to 50 microns, and the third opening 604c may have a third length L3 in the range of 0.5 microns to 10 microns. Thus, in some embodiments, L1 is greater than L2, and L2 is greater than L3. Additionally, the spacing (e.g., “pitch”) between the centers of the openings may vary along line B-B. Thus, as shown, as measured from the centerline 615 of the device, the first opening having length L1 may have a first central axis 617 spaced from the centerline 615 by a distance d1, the second opening having length L2 may have a second central axis 619 spaced from the centerline 615 by a distance d2, and the third opening having length L3 may have a third central axis 621 spaced from the centerline 615 by a distance d3. In some embodiments, the central axes of these openings get closer together as the openings get closer to the outer edge of the trench. Thus, for example, d1 is greater than half of d2 (or d2 - d1 < d1), and d3 - d2 < d2 - d1 < d1. In some embodiments, the openings may be symmetric about the centerline 615 and / or mirror images of each other, although the openings move along line D-D on opposite sides of the centerline due to the intersecting nature of the fingers.

[0023] Figures 6F to 6I A top view shows some examples of alternative embodiments for the mask 602. Figure 6FAn example is shown where the mask openings closer to the tip of the finger "merge" such that the smaller outer openings are closer to the base of the finger and the larger inner openings are closer to the tip of the finger, and having an upper fan-shaped piece and a lower fan-shaped piece along the outer sidewall of the finger when viewed from above. Figure 6G Another example is shown where a plurality of narrow mask openings (e.g., "slits") having equal dimensions and areas with respect to each other are arranged such that the effective mask opening area closer to the tip of the finger is larger than the effective mask opening area closer to the base of the finger. In Figure 6G the mask openings are oriented perpendicular to the finger. Although Figure 6G the example of shows four slits closely spaced closer to the tip of the finger, two slits closer to the base of the finger, and three slits closer to the middle portion of the finger, any number of slits may be present and this is merely an example. Figure 6H Another example is shown where the slits are oriented parallel to the finger and where the slits have equal widths with respect to each other but different lengths. In Figure 6H the length of the slits is longer closer to the tip of the finger and shorter closer to the base of the finger. Figure 6I Another example is shown where an array of mask openings, each mask opening having a unit area, is arranged such that the effective mask opening area closer to the tip of the finger is larger than the effective mask opening area closer to the base of the finger.

[0024] Figures 7A to 7E and Figures 8A to 8E are consistent with some examples of which performs the release etch. Figure 1 of . Figures 7A to 7E An intermediate stage in some embodiments of the release etch is shown, and Figures 8A to 8E the structure at the completion of the release etch is shown. In some embodiments, the release etch is a hydrofluoric acid (HF) etch and can be an aqueous HF etch or a vapor phase HF etch. The release etch is selective in that it preferentially etches the second wafer 302 at a first etch rate while etching the dielectric layer 204 and the dielectric pad 502 at a second etch rate less than the first etch rate. In Figures 7A to 7E with the mask 602 in place, an early portion of the release etch removes the portion of the second wafer 302 under the openings in the mask 602 to form a cavity 702 between the sidewalls of the interdigitated fingers 504. As the etch proceeds, the etch extends the cavity to continue beneath the bottom surface of the interdigitated fingers 504 and exposes the upper surface of the dielectric layer 204. As Figures 7A to 7EAs shown, the release etch leaves the semiconductor material of the second wafer as a series of peaks 704 directly below the bottom surface of the intersecting fingers 504. However, because the mask opening near the base of the finger is smaller than the mask opening near the tip of the finger and / or the pitch of the mask opening near the base of the finger is smaller than the pitch of the mask opening near the base of the finger, the peaks in the near-base region are larger and can remain attached to the bottom surface of the intersecting fingers, while the peaks near the tip of the finger are completely released from the tip of the finger. As Figure 7E shown, the peaks 704 are offset from the openings and are approximately located in the middle between adjacent openings, although due to the way the etching is carried out, a given opening can be slightly closer to the larger of two adjacent openings. For example, in Figure 7E , the peak 704a is approximately located in the middle between the mask opening 604' and the mask opening 604" in the first direction, and the peak 704b is approximately located in the middle between the mask opening 604' and the mask opening 604''' in the first direction.

[0025] Figures 8A to 8E shows the structure after the release etch is completed. In these examples, the anchoring regions 808 including silicon extend upward from the dielectric layer 204. The conductive fingers 504 that cross each other extend inward from the inner sidewalls of the anchoring regions 808 and are suspended above the dielectric layer 204. The dielectric pads 502 cover the sidewalls and the bottom surface of the conductive fingers 504, and the peaks made of semiconductor material are provided on the dielectric layer 204. The peaks are spaced apart from each other but still remain below the conductive fingers 504. As Figure 8B , Figure 8C and Figure 8E can be seen, in the first direction (e.g., the x direction), the peak groups are located directly below the fingers, and the peaks in each group have different heights from each other along this direction. Therefore, the first peak 802 below the base of the finger has a first height greater than the second height of the second peak 804 below the tip of the finger, and the third peak 806 below the middle part of the finger has a third height between the first height and the second height. Viewed from above (see, for example Figure 8A ), the peaks can be square, rectangular or polygonal, and can have rounded corners (e.g., circular or elliptical). In some embodiments, the first peak 802 can have a height in the range of 0.1 micrometer to 100 micrometers; and the second peak 804 can have a height in the range of 0.0999 micrometer to 99.9 micrometers. In some embodiments, the ratio of the height of the first peak to the height of the second peak can be in the range of 0.999 to 100. In addition, as Figure 8D can be seen, in the second direction (e.g., the y direction), other groups of peaks have the same height as each other. Therefore, as Figure 8DAs shown, the peaks located directly beneath the bases of the different fingers each have substantially the same height. It should be understood that "substantially the same height" takes into account minor variations in height due to small fluctuations in the etching process, but the resulting heights are typically still within 1% of each other.

[0026] In some embodiments, such as Figure 8B and Figure 8C as shown, the peak beneath a single finger 504 has a monotonically decreasing height along the length of the finger from a first peak (e.g., 802) beneath the base of the finger to a second peak (e.g., 804) beneath the tip of the finger. Additionally, due to variations in the manufacturing process, after the release etch is performed, a small number of fingers in the MEMS device may still be attached to the underlying peaks. However, when attached, the peaks attach at the base of the finger rather than the tip. Thus, when a finger release process is applied to the finger to release any fingers not fully released by the release etch from the underlying peaks (e.g., Figure 1 114 in), the finger 504 is more likely to remain intact compared to previous methods. Accordingly, the manufacturing yield and device sensitivity are improved.

[0027] In other embodiments, such as Figure 8F as shown, the peak beneath a single finger 504 has a decreasing height from a first peak (e.g., 802) beneath the base of the finger to a third peak (e.g., 806) beneath the middle portion of the finger along the length of the finger, and then the height of the second peak 804 at the tip of the finger increases again. The height of the second peak 804 is still less than the height of the first peak 802.

[0028] It should be understood that Figures 2A to 8F is described with respect to a first wafer and a second wafer. Typically, at some stage of manufacturing, the first wafer and the second wafer are cut along a scribe line separating the die on the first wafer and the second wafer, thereby forming separate integrated circuits. Thus, while the first wafer and the second wafer are referred to as "wafers" during the manufacturing process prior to cutting, after cutting, the cut portions can be referred to as "substrates". These terms are interchangeable in some respects because a wafer, which can be implied to be a circular or disk-shaped structure, can also assume other shapes and thus can include many types of substrates.

[0029] In some embodiments, such as Figure 9 as shown, a third wafer / substrate 902 (which can be referred to as a cover wafer / substrate) is bonded to the face of the second wafer / substrate 302 opposite the dielectric layer 204. In Figure 9In [the figure], the capping wafer / substrate 902 includes a third semiconductor substrate joined to a second wafer / substrate by one or more seal rings 904. In some embodiments, the one or more seal rings 904 are or otherwise include, for example, aluminum copper and / or germanium. In some embodiments, the seal ring is a eutectic seal ring and may include: a first ring including aluminum copper; and a second ring stacked above or below the first ring and including germanium. Additionally, one or more first bonding pads 906 (such as copper or copper-aluminum bonding pads) may electrically and physically couple the second wafer / substrate 302 to the third wafer / substrate 902. Through-silicon vias (TSVs) 908 may pass through the third wafer / substrate 902 and couple the first bonding pads 906 to second bonding pads 910. Conductive bumps 912, which may include solder, may be disposed on the second bonding pads 910. It can be seen that the capping wafer / substrate 902, the second wafer / substrate 302, and the dielectric layer 204 together establish an enclosed cavity 914 in which the conductive fingers 504 are located. The cavity 914 may be filled with a gas such as air or nitrogen or a vacuum. In some embodiments, the first wafer 202, which may be referred to as a CMOS substrate in some cases, may include transistor devices 916 disposed on a semiconductor substrate 918, and the interconnect structure includes metal lines 920 and vias 922 in a dielectric structure 924 disposed above the semiconductor substrate 918. The semiconductor substrate 918 may include single-crystalline silicon, the metal lines 920 and vias 922 may include copper and / or aluminum, and the dielectric structure 924 may include a low-k dielectric or silicon dioxide. The illustrated transistor devices 916 may include a conductive gate electrode 930 disposed between doped source / drain regions 932, 934, but other devices such as diodes, bipolar junction transistors (BJTs), or other active or passive devices may be disposed in the semiconductor substrate.

[0030] Some embodiments relate to a method of forming an integrated circuit (IC) device. In the method, a dielectric layer is formed over a first wafer. A second wafer is provided over the dielectric layer, and a plurality of trenches are formed in an upper surface of the second wafer that is opposite the dielectric layer. Dielectric liners are formed along lower portions and sidewalls of the plurality of trenches, and the remaining portions of the plurality of trenches are filled with a conductive material to establish a series of intersecting fingers whose finger lengths generally extend parallel to each other in a first direction. A mask is formed over the upper surface of the second wafer. The mask includes a series of openings disposed between outer sidewalls of adjacent fingers, wherein a first area of a first opening near a base of the finger is greater than a second area of a second opening near a tip of the finger. Etching is performed with the mask in place to form cavities between sidewalls of the intersecting fingers and between a bottom surface of the intersecting fingers and an upper surface of the dielectric layer.

[0031] In some embodiments, the etching leaves the material of the first wafer as a series of peaks on the upper surface of the dielectric layer, wherein the peaks in the series of peaks are located directly below the fingers. In some embodiments, a first set of peaks is located directly below the fingers, the first set of peaks having different heights from each other, and wherein a first height of a first peak below the base of the finger is greater than a second height of a second peak below the tip of the finger. In some embodiments, the first set of peaks has a monotonically decreasing height from the first peak below the base of the finger to the second peak below the tip of the finger. In some embodiments, a second set of peaks is located directly below the bases of adjacent fingers and is generally arranged in a second direction perpendicular to the first direction, wherein each of the second set of peaks has the first height. In some embodiments, the conductive material comprises polysilicon, and the dielectric liner and the dielectric layer comprise silicon dioxide. In some embodiments, the method further comprises: bonding a third wafer to the face of the first wafer opposite the dielectric layer.

[0032] An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed above the first substrate; and a second substrate disposed above the dielectric layer. The second substrate includes an anchoring region including silicon extending upward from the dielectric layer, and a series of mutually intersecting fingers extending from an inner sidewall of the anchoring region. The mutually intersecting fingers generally extend parallel to each other in a first direction and have respective finger lengths generally extending in the first direction. A plurality of silicon-containing peaks are disposed on the dielectric layer directly below the respective mutually intersecting fingers. A series of mutually intersecting fingers is suspended above the plurality of peaks. A first peak is disposed below the base of the finger and has a first height, and a second peak is disposed below the tip of the finger and has a second height less than the first height.

[0033] In some embodiments, the series of interdigitated members includes a polysilicon core, and sidewalls and a lower surface of the polysilicon core are covered by a dielectric liner. In some embodiments, the plurality of peaks along a first line directly under a base of a plurality of fingers have the same height as each other. In some embodiments, all of the plurality of peaks are directly disposed under the interdigitated members, and there are no peaks directly under an opening between the interdigitated members. In some embodiments, more than two peaks are disposed directly under the fingers such that a first peak under a base of the finger has a first height and a second peak under a tip of the finger has a second height less than the first height. In some embodiments, additional peaks between the first peak and the second peak have respective heights such that heights of the more than two peaks decrease monotonically from the first peak to the second peak. In some embodiments, the peaks directly under a base of a finger are generally arranged in a second direction perpendicular to the first direction, wherein each of the peaks directly under the base of the finger has the first height.

[0034] Other embodiments also relate to an integrated circuit (IC) device. The IC device includes: a complementary metal oxide semiconductor (CMOS) substrate including a plurality of semiconductor devices disposed in the CMOS substrate. An interconnect structure is disposed over the CMOS substrate, and a dielectric layer is disposed over the interconnect structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric layer. The MEMS substrate includes an anchoring region including silicon extending upward from the dielectric layer, and a plurality of conductive fingers cross each other and are suspended over the dielectric layer. A cover substrate is disposed over the MEMS substrate and defines a cavity in which the conductive fingers are disposed. A lower surface of the cavity is defined by an upper surface of the dielectric layer, and a plurality of silicon-containing peaks are respectively disposed on the dielectric layer directly under the plurality of fingers. A first peak of the plurality of peaks is disposed under a base of the finger and has a first height, and a second peak of the plurality of peaks is disposed under a tip of the finger and has a second height less than the first height.

[0035] In some embodiments, the integrated circuit device further includes: a dielectric liner surrounding sidewalls and a lower surface of the conductive finger, wherein the dielectric liner has a first component and the dielectric layer has a second component, and the second component is the same as the first component. In some embodiments, the first set of peaks has a monotonically decreasing height from the first peak below the base of the finger to the second peak below the tip of the finger. In some embodiments, the second set of peaks is located directly below the base of the finger and is generally arranged in a second direction perpendicular to the first direction, wherein each of the second set of peaks has the first height. In some embodiments, the conductive material includes polysilicon, and the dielectric liner and the dielectric layer include silicon dioxide. In some embodiments, there are no peaks on the dielectric layer directly below the opening between the outer sidewalls of the intersecting fingers.

[0036] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming an integrated circuit device, the method comprising: forming a dielectric layer over a first wafer; providing a second wafer over the dielectric layer; forming a plurality of trenches in an upper surface of the second wafer that faces the dielectric layer; forming a dielectric liner along lower portions and sidewalls of the plurality of trenches and filling remaining portions of the plurality of trenches with a conductive material to establish a series of intersecting fingers, the fingers of the intersecting fingers extending parallel to each other in a first direction; forming a mask over the upper surface of the second wafer, wherein the mask includes a series of openings disposed between outer sidewalls of adjacent fingers, and wherein a first area of a first opening near a base of a finger is greater than a second area of a second opening near a tip of the finger; and performing an etch with the mask in place to form cavities between sidewalls of the intersecting fingers and between a bottom surface of the intersecting fingers and an upper surface of the dielectric layer, wherein the etch leaves material of the first wafer as a series of peaks on the upper surface of the dielectric layer, wherein peaks in the series of peaks are located directly below the fingers, wherein a first set of peaks is located directly below the fingers, the first set of peaks having different heights from each other, and wherein a first height of a first peak below the base of the finger is greater than a second height of a second peak below the tip of the finger.

2. The method according to claim 1, wherein, the first peak has a height in a range of 0.1 micrometer to 100 micrometers.

3. The method according to claim 1, wherein, the second peak has a height in a range of 0.0999 micrometer to 99.9 micrometers.

4. The method according to claim 1, wherein, the first set of peaks has a monotonically decreasing height from the first peak below the base of the finger to the second peak below the tip of the finger.

5. The method according to claim 1, wherein, a second set of peaks is located directly below bases of adjacent fingers and is arranged in a second direction perpendicular to the first direction, wherein each of the second set of peaks has the first height.

6. The method according to claim 1, wherein, the conductive material includes polysilicon, and the dielectric liner and the dielectric layer include silicon dioxide.

7. The method according to claim 1, further comprising: bonding a third wafer to a face of the first wafer that faces away from the dielectric layer.

8. An integrated circuit device, comprising: a first substrate; a dielectric layer disposed over the first substrate; a second substrate disposed over the dielectric layer, wherein the second substrate includes an anchoring region including silicon that extends upward from the dielectric layer; a series of intersecting fingers extending from inner sidewalls of the anchoring region, wherein the intersecting fingers extend parallel to each other in a first direction and have respective finger lengths extending in the first direction; and Multiple silicon-containing peaks are respectively disposed on the dielectric layer directly below the series of intersecting fingers, wherein the series of intersecting fingers are suspended above the multiple silicon-containing peaks, and wherein a first peak disposed below the base of the finger has a first height, and a second peak disposed below the tip of the finger has a second height less than the first height.

9. The integrated circuit device according to claim 8, wherein, the series of intersecting fingers includes a polysilicon core, and the sidewalls and the lower surface of the polysilicon core are covered by a dielectric pad.

10. The integrated circuit device according to claim 8, wherein, the multiple silicon-containing peaks along a first line directly below the bases of the multiple fingers have the same height as each other.

11. The integrated circuit device according to claim 9, wherein, all of the multiple silicon-containing peaks are directly disposed below the intersecting fingers, and there are no peaks directly below the openings between the intersecting fingers.

12. The integrated circuit device according to claim 9, wherein, more than two peaks are disposed directly below the fingers such that a first peak below the base of the finger has a first height, and a second peak below the tip of the finger has a second height less than the first height.

13. The integrated circuit device according to claim 12, wherein, the additional peaks between the first peak and the second peak have corresponding heights such that the heights of the more than two peaks decrease monotonically from the first peak to the second peak.

14. The integrated circuit device according to claim 9, wherein, the peaks disposed directly below the bases of the fingers are arranged in a second direction perpendicular to the first direction, wherein each of the peaks directly below the bases of the fingers has the first height.

15. An integrated circuit device, comprising: a complementary metal oxide semiconductor substrate including a plurality of semiconductor devices disposed in the complementary metal oxide semiconductor substrate; an interconnect structure disposed above the complementary metal oxide semiconductor substrate; a dielectric layer disposed above the interconnect structure; a microelectromechanical system substrate disposed above the dielectric layer, wherein the microelectromechanical system substrate includes an anchoring region including silicon extending upward from the dielectric layer, and a plurality of conductive fingers intersect each other and are suspended above the dielectric layer, wherein the finger lengths of the intersecting conductive fingers extend parallel to each other in a first direction; a cover substrate disposed above the microelectromechanical system substrate and establishing a cavity in which the conductive fingers are disposed, wherein the lower surface of the cavity is defined by the upper surface of the dielectric layer; and a plurality of silicon-containing peaks respectively disposed on the dielectric layer directly below the plurality of conductive fingers, wherein a first peak of the plurality of silicon-containing peaks is disposed below the base of the conductive finger and has a first height, and a second peak of the plurality of silicon-containing peaks is disposed below the tip of the conductive finger and has a second height less than the first height.

16. The integrated circuit device according to claim 15, further Comprising: A dielectric pad surrounding sidewalls and a lower surface of the conductive finger, wherein the dielectric pad has a first component and the dielectric layer has a second component, and the second component is the same as the first component.

17. The integrated circuit device according to claim 16, wherein, The first set of peaks has a monotonically decreasing height from the first peak below the base of the conductive finger to the second peak below the tip of the conductive finger.

18. The integrated circuit device according to claim 15, wherein, The second set of peaks is located directly below the base of the conductive finger and is arranged in a second direction perpendicular to the first direction, wherein each of the second set of peaks has the first height.

19. The integrated circuit device according to claim 16, wherein, The dielectric pad and the dielectric layer comprise silicon dioxide.

20. The integrated circuit device according to claim 15, wherein, There are no peaks on the dielectric layer directly below the opening between the outer sidewalls of the intersecting conductive fingers.

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