FinFET parasitic capacitance test structure and method

Abstract

The present invention discloses a parasitic capacitance test structure of a FinFET, wherein the FinFET includes a gate structure, a lightly doped source region and a lightly doped drain region composed of a first conductive type lightly doped region, a sidewall, a source region and a drain region composed of a first conductive type heavily doped region, a second conductive type well region, and a body lead-out region composed of a second conductive type heavily doped region. The parasitic capacitance test structure of the FinFET includes multiple parasitic capacitance test structures, and the first conductive type well region is formed in the fin body of the formation area of ​​the multiple parasitic capacitance test structures. The first test structure in the parasitic capacitance test structure is formed by replacing the second conductive type well region of the FinFET with the first conductive type well region and removing the lightly doped source region and the lightly doped drain region at the same time. The present invention also discloses a parasitic capacitance test method of the FinFET. The present invention can prevent the generation of butterfly defects and thus facilitate mass production, and can conveniently realize the calculation of the parasitic capacitance of the zero-layer metal layer, the zero-layer through hole, and the electrical thickness of the gate dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a parasitic capacitance testing structure of FinFET. The present invention also relates to a parasitic capacitance testing method of FinFET. Background Art

[0002] The gate structure of FinFET usually adopts metal gate (MG), and the gate dielectric layer usually includes a high dielectric constant layer (HK). The electrical thickness of the gate dielectric layer usually needs to be tested and extracted by the capacitance of the gate. Figure 1 As shown, it is a schematic diagram of the structure of an existing FinFET; the existing FinFET includes: the FinFET includes a gate structure, a lightly doped source region and a lightly doped drain region composed of a first conductive type lightly doped region, a side wall 110, a source region 105 and a drain region 106 composed of a first conductive type heavily doped region, a second conductive type well region 103 and a body lead-out region 107 composed of a second conductive type heavily doped region.

[0003] The gate structure is formed by stacking a gate dielectric layer 108 and a gate conductive material layer such as a metal gate 109 .

[0004] The second conductivity type well region 103 is formed in the fin body 102. In the prior art, the fin body 102 is formed by patterning and etching a semiconductor substrate such as a silicon substrate 101.

[0005] The gate structure covers the top surface and side surfaces of the fin body 102, a second conductive type well region 103 is formed in the fin body 102, and the surface of the second conductive type well region 103 covered by the gate structure is used to form a conductive channel; the shallowly doped source region and the shallowly doped drain region are self-alignedly formed in the fin body 102 on both sides of the gate structure, and the shallowly doped source region and the shallowly doped drain region extend below the bottom surface of the gate structure; the sidewalls 110 are self-alignedly formed on both sides of the gate structure, and the source region 105 and the drain region 106 are self-aligned In the fin body 102 formed on both sides of the sidewall 110 on both sides of the gate structure, the second conductive type well region 103 covers the source region 105, the drain region 106 and the body lead-out region 107; a zero-layer metal layer (M0) 111 is formed on the top of the source region 105, the drain region 106, the gate structure and the body lead-out region 107, and a zero-layer via (V0) 112 is formed on the top of the zero-layer metal layer 111. The zero-layer metal layer 111 and the zero-layer via 112 both pass through the interlayer film 113. A metal interconnection structure composed of metal layers (omitted) and vias (omitted) above the first metal layer is formed on the top of the zero-layer via 112. A first shallow trench isolation structure 104a is spaced between the drain region 106 and the body lead-out region 107.

[0006] for Figure 1 The capacitor structure shown in the figure is designed to extract the electrical thickness of the capacitor structure in actual production. Figure 1 As shown, a structure with a longer gate length is usually selected for testing, in which the main parasitic capacitances are:

[0007] Cgtm represents the parasitic capacitance between the gate structure and the metal interconnection lines above the zeroth metal layer 111 .

[0008] Cof represents the parasitic capacitance between the embedded epitaxial layer where the source region 105 or the drain region 106 is formed and the gate structure.

[0009] Cov represents the parasitic capacitance of the overlapping region between the shallowly doped source region or the shallowly doped drain region and the gate structure.

[0010] Since the area of ​​the FINFET process platform M0 is larger, the capacitance between the gate and M0 is larger than that of the planar process. In order to calculate the capacitance between the gate and M0, it is usually necessary to set up a test structure, such as Figure 2A , which is a schematic diagram of a first test structure in an existing parasitic capacitance test structure of FinFET; Figure 2A The corresponding first test structure and Figure 1The difference from the existing FinFET shown is that the first test structure is directly formed on the shallow trench isolation structure 104b, that is, the removed active area (AA). Thus, the first test capacitance obtained by testing the first test structure is the capacitance between the gate structure and the metal connection in the first test structure, where the metal connection includes the zero-layer metal layer 111 and the zero-layer through hole 112, and both the zero-layer metal layer 111 and the zero-layer through hole 112 pass through the interlayer film 113.

[0011] like Figure 2B , which is a schematic diagram of a second test structure in the existing parasitic capacitance test structure of FinFET; Figure 2B The corresponding second test structure and Figure 1 The difference from the existing FinFET shown is that the second test structure removes the zero-layer metal layer 111, i.e., M0, and the zero-layer via 112, i.e., V0, on the top of the source region 105, the drain region 106, and the body lead-out region 107. The second test structure is tested to obtain a second test capacitor. The capacitance between the gate structure and the zero-layer metal layer 111 and the capacitance between the gate structure and the zero-layer via 112 is obtained by subtracting the second test capacitor from the first test capacitor.

[0012] However, in actual production, the second test structure only removes M0 and V0, and passes through the dielectric layer during testing to directly connect to the source region or drain region, namely S / D. Therefore, the parasitic capacitance value of M0 or V0 cannot be measured. Therefore, it is necessary to combine the test structure of the first test structure to obtain the parasitic capacitance of M0 and V0.

[0013] but Figure 2A A large piece of metal gate is grown on a large area of ​​shallow trench isolation structure 104b, and a dishing phenomenon is likely to occur between the shallow trench isolation structure 104b and the metal gate, thereby causing defects and being unfavorable for mass production. Summary of the invention

[0014] The technical problem to be solved by the present invention is to provide a parasitic capacitance test structure of FinFET, in which the gate structure does not need to be arranged on a large-area shallow trench isolation structure, thereby preventing butterfly defects and facilitating mass production, and conveniently realizing the calculation of the parasitic capacitance of the zero-layer metal layer, the zero-layer through hole, and the electrical thickness of the gate dielectric layer. To this end, the present invention also provides a parasitic capacitance test method of FinFET.

[0015] In order to solve the above technical problems, in the parasitic capacitance test structure of FinFET provided by the present invention, FinFET includes a gate structure, a lightly doped source region and a lightly doped drain region composed of a first conductive type lightly doped region, a side wall, a source region and a drain region composed of a first conductive type heavily doped region, a second conductive type well region and a body lead-out region composed of a second conductive type heavily doped region.

[0016] The gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer.

[0017] The second conductive type well region is formed in the fin body, the gate structure covers the top surface and side of the fin body, the second conductive type well region is formed in the fin body, and the surface of the second conductive type well region covered by the gate structure is used to form a conductive channel; the shallowly doped source region and the shallowly doped drain region are self-alignedly formed in the fin body on both sides of the gate structure, and the shallowly doped source region and the shallowly doped drain region extend below the bottom surface of the gate structure; the sidewalls are self-alignedly formed on both sides of the gate structure, the source region and the drain region are self-alignedly formed in the fin body on both sides of the sidewalls on both sides of the gate structure, and the second conductive type well region covers the source region, the drain region and the body lead-out region; a zeroth metal layer is formed on the top of the source region, the drain region, the gate structure and the body lead-out region, a zeroth through hole is formed on the top of the metal zero layer, and a metal interconnection structure composed of metal layers and through holes above the first metal layer is formed on the top of the zeroth through hole.

[0018] The parasitic capacitance test structure of the FinFET includes a plurality of parasitic capacitance test structures, and a first conductive type well region is formed in the fin body in a formation region of the plurality of parasitic capacitance test structures.

[0019] The first test structure in the parasitic capacitance test structure is formed by replacing the second conductive type well region of the FinFET with the first conductive type well region and simultaneously removing the shallowly doped source region and the shallowly doped drain region. The test capacitor of the first test structure is a first test capacitor, and the first test capacitor includes a first parasitic capacitor and a second parasitic capacitor. The first parasitic capacitor is a parasitic capacitor between the source region or the drain region and the gate structure, and the second parasitic capacitor is a parasitic capacitor between the gate structure and the metal interconnect line above the zeroth metal layer.

[0020] A further improvement is that the parasitic capacitance test structure also includes a second test structure, which is obtained by removing the zeroth metal layer and the zeroth through hole on the top of the source region and the drain region in the first test structure, and the test capacitance of the second test structure is a second test capacitance.

[0021] A further improvement is that the parasitic capacitance test structure also includes a third test structure, which is obtained by removing the zeroth layer through-holes at the top of the source region and the drain region in the first test structure, and the test capacitance of the third test structure is a third test capacitance.

[0022] A third parasitic capacitance formed between the gate structure and the zeroth layer through hole is obtained by subtracting the third test capacitance from the first test capacitance.

[0023] A fourth parasitic capacitance formed between the gate structure and the zeroth metal layer is obtained by subtracting the second test capacitance from the third test capacitance.

[0024] A further improvement is that the FinFET further includes an embedded epitaxial layer, the embedded epitaxial layer is formed in the fin body on both sides of the gate structure, and the source region and the drain region are formed in the embedded epitaxial layer.

[0025] The parasitic capacitance test structure further includes a fourth test structure, and the fourth test structure is obtained by removing the embedded epitaxial layer in the first test structure, and the test capacitance of the fourth test structure is a fourth test capacitance.

[0026] A fifth parasitic capacitance formed between the gate structure and the embedded epitaxial layer is obtained by subtracting the fourth test capacitance from the first test capacitance.

[0027] A further improvement is that the parasitic capacitance test structure also includes a fifth test structure, which is obtained by removing the zero-layer through-hole at the top of the source region, the drain region and the body lead-out region in the FinFET, and the test capacitance of the fifth test structure is the fifth test capacitance.

[0028] A further improvement is that the material of the gate dielectric layer includes silicon dioxide or a high dielectric constant layer.

[0029] The gate conductive material layer is a polysilicon gate or a metal gate.

[0030] The sixth parasitic capacitance is a parasitic capacitance used to calculate the electrical thickness of the gate dielectric layer, and the sixth parasitic capacitance is obtained by subtracting the fifth test capacitance, the third parasitic capacitance, the fourth parasitic capacitance and the fifth parasitic capacitance from the first test capacitance.

[0031] A further improvement is that the sixth parasitic capacitance is directly obtained by adding the fourth test capacitance to the second test capacitance and subtracting the first test capacitance and the fifth test capacitance.

[0032] A further improvement is that the FinFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the FinFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0033] A further improvement is that when the FinFET is an N-type device, the material of the embedded epitaxial layer includes SiP.

[0034] A further improvement is that when the FinFET is a P-type device, the material of the embedded epitaxial layer includes SiGe.

[0035] A further improvement is that a first shallow trench isolation structure is provided between the drain region and the body lead-out region of the FinFET.

[0036] A further improvement is that the electrical thickness of the gate dielectric layer is the thickness of a gate oxide layer that is equivalent to the gate dielectric layer and is completely composed of silicon dioxide.

[0037] In order to solve the above technical problems, the present invention provides a FinFET parasitic capacitance testing method, comprising the following steps:

[0038] Step 1: Perform a capacitance test, including:

[0039] The first test structure is tested to obtain a first test capacitor.

[0040] The second test structure is tested to obtain a second test capacitance.

[0041] The third test structure is tested to obtain a third test capacitor.

[0042] The fourth test structure is tested to obtain a fourth test capacitor.

[0043] The fifth test structure is tested to obtain a fifth test capacitor.

[0044] Step 2: Calculate capacitance, including:

[0045] The third parasitic capacitance is obtained by subtracting the third test capacitance from the first test capacitance.

[0046] The fourth parasitic capacitance is obtained by subtracting the second test capacitance from the third test capacitance.

[0047] The fifth parasitic capacitance is obtained by subtracting the fourth test capacitance from the first test capacitance.

[0048] The seventh parasitic capacitance is obtained by subtracting the fifth test capacitance from the first test capacitance; the seventh parasitic capacitance is the parasitic capacitance between the gate structure and the metal interconnection line above the first metal layer.

[0049] Step three, obtaining the sixth parasitic capacitance, comprising: obtaining the sixth parasitic capacitance by subtracting the fifth test capacitance, the third parasitic capacitance, the fourth parasitic capacitance and the fifth parasitic capacitance from the first test capacitance.

[0050] A further improvement is that the method further comprises the steps of:

[0051] Step 4: Calculate the electrical thickness of the gate dielectric layer using the sixth parasitic capacitance.

[0052] A further improvement is that in step three, the sixth parasitic capacitance is directly obtained by adding the fourth test capacitance to the second test capacitance and subtracting the first test capacitance and the fifth test capacitance.

[0053] The fin body in the formation area of ​​the parasitic capacitance test structure of the FinFET of the present invention includes a first conductive type well region switched to the opposite of the FinFET, thereby avoiding the defect of the parasitic capacitance test structure in the prior art being formed on a large shallow trench isolation structure and thus preventing the generation of butterfly defects, thereby facilitating mass production.

[0054] The first test structure of the present invention can be achieved by switching the second conductive type well region of the FinFET to the first conductive type well region. The first test structure can well simulate the first parasitic capacitance Cof and the second parasitic capacitance Cgtm of the FinFET, so that the parasitic capacitance of the FinFET can be tested using the first test structure.

[0055] At the same time, since the various parasitic capacitance test structures of the present invention can be realized by making corresponding changes on the basis of the first test structure and by making changes through FinFET, and can realize the test of the parasitic capacitance between the gate structure and the zero-layer metal layer, the parasitic capacitance between the gate structure and the zero-layer through hole, the parasitic capacitance between the gate structure and the embedded epitaxial layer, and the parasitic capacitance between the gate structure and the metal interconnection line above the first metal layer, the parasitic capacitance of the electrical thickness of the gate dielectric layer can be calculated through the operation of multiple test resistors, and thus the electrical thickness of the gate dielectric layer can be calculated, so the calculation of the electrical thickness of the gate dielectric layer can be conveniently realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0057] Figure 1 It is a schematic diagram of the structure of the existing FinFET;

[0058] Figure 2A is a schematic diagram of a first test structure in an existing parasitic capacitance test structure of FinFET;

[0059] Figure 2B is a schematic diagram of a second test structure in an existing parasitic capacitance test structure of FinFET;

[0060] Figure 3 is a schematic diagram of the structure of a FinFET in an embodiment of the present invention;

[0061] Figure 4A is a schematic diagram of a first test structure in a parasitic capacitance test structure of a FinFET according to an embodiment of the present invention;

[0062] Figure 4B is a schematic diagram of a second test structure in a parasitic capacitance test structure of a FinFET according to an embodiment of the present invention;

[0063] Figure 4C is a schematic diagram of a third test structure in the parasitic capacitance test structure of FinFET according to an embodiment of the present invention;

[0064] Figure 4D is a schematic diagram of a fourth test structure in the parasitic capacitance test structure of FinFET according to an embodiment of the present invention;

[0065] Figure 4E 4 is a schematic diagram of a fifth test structure in the parasitic capacitance test structure of FinFET according to an embodiment of the present invention. DETAILED DESCRIPTION

[0066] like Figure 3 As shown, it is a schematic diagram of the structure of the FinFET in the embodiment of the present invention; in the parasitic capacitance test structure of the FinFET in the embodiment of the present invention, the FinFET301 includes a gate structure, a lightly doped source region and a lightly doped drain region composed of a first conductive type lightly doped region, a side wall 210, a source region 205 and a drain region 206 composed of a first conductive type heavily doped region, a second conductive type well region 203 and a body lead-out region 207 composed of a second conductive type heavily doped region.

[0067] The gate structure is formed by stacking a gate dielectric layer 208 and a gate conductive material layer 209 .

[0068] The second conductivity type well region 203 is formed in the fin body 202. In the embodiment of the present invention, the fin body 202 is formed by patterning and etching a semiconductor substrate such as a silicon substrate 201.

[0069] The gate structure covers the top surface and side surfaces of the fin body 202, a second conductive type well region 203 is formed in the fin body 202, and the surface of the second conductive type well region 203 covered by the gate structure is used to form a conductive channel; the shallowly doped source region and the shallowly doped drain region are self-alignedly formed in the fin body 202 on both sides of the gate structure, and the shallowly doped source region and the shallowly doped drain region extend below the bottom surface of the gate structure; the sidewalls 210 are self-alignedly formed on both sides of the gate structure, the source region 205 and the drain region are The region 206 is self-alignedly formed in the fin body 202 on both sides of the sidewall 210 on both sides of the gate structure, and the second conductive type well region 203 covers the source region 205, the drain region 206 and the body lead-out region 207; a zero-layer metal layer 211 is formed on the top of the source region 205, the drain region 206, the gate structure, and the body lead-out region 207, and a zero-layer through hole 212 is formed on the top of the metal zero layer, and the zero-layer metal layer 211 and the zero-layer through hole 212 both pass through the interlayer film 213. A metal interconnection structure composed of metal layers (omitted) and through holes (omitted) above the first metal layer is formed on the top of the zero-layer through hole 212. The parasitic capacitance test structure of the FinFET 301 includes multiple, and a first conductive type well region 214 is formed in the fin body 202 in the formation area of ​​the multiple parasitic capacitance test structures.

[0070] In the embodiment of the present invention, the source region 205 and the drain region 206 are formed in an embedded epitaxial layer, and the embedded epitaxial layer is formed in the fin body 202 on both sides of the gate structure. Figure 3 As shown, the parasitic capacitance of the FinFET includes Cgtm, Cof and Cov, where:

[0071] Cgtm represents the parasitic capacitance between the gate structure and the metal interconnection lines above the zeroth metal layer 211 .

[0072] Cof represents the parasitic capacitance between the embedded epitaxial layer where the source region 205 or the drain region 206 is formed and the gate structure.

[0073] Cov represents the parasitic capacitance of the overlapping region between the shallowly doped source region or the shallowly doped drain region and the gate structure.

[0074] like Figure 4AAs shown, it is a schematic diagram of the first test structure in the parasitic capacitance test structure of the FinFET in an embodiment of the present invention; the first test structure 302a in the parasitic capacitance test structure is formed by replacing the second conductive type well region 203 of the FinFET 301 with the first conductive type well region 214 and simultaneously removing the shallowly doped source region and the shallowly doped drain region, the test capacitance of the first test structure 302a is the first test capacitance, and the first test capacitance includes the first parasitic capacitance and the second parasitic capacitance.

[0075] The first parasitic capacitance is a parasitic capacitance between the source region 205 or the drain region 206 and the gate structure, that is, the first parasitic capacitance is Cof.

[0076] The second parasitic capacitance is the parasitic capacitance between the gate structure and the metal interconnection lines above the zeroth metal layer 211 , that is, the second parasitic capacitance is Cgtm.

[0077] The first test structure 302 a no longer has Cov.

[0078] like Figure 4B As shown, it is a schematic diagram of the second test structure in the parasitic capacitance test structure of the FinFET in an embodiment of the present invention; the parasitic capacitance test structure also includes a second test structure 302b, and the second test structure 302b is obtained by removing the zero-layer metal layer 211 and the zero-layer through hole 212 on the top of the source region 205 and the drain region 206 in the first test structure 302a, and the test capacitance of the second test structure 302b is the second test capacitance.

[0079] like Figure 4C As shown, it is a schematic diagram of the third test structure in the parasitic capacitance test structure of the FinFET in an embodiment of the present invention; the parasitic capacitance test structure also includes a third test structure 302c, and the third test structure 302c is obtained by removing the zero-layer through hole 212 at the top of the source region 205 and the drain region 206 in the first test structure 302a, and the test capacitance of the third test structure 302c is the third test capacitance.

[0080] The third parasitic capacitance formed between the gate structure and the zeroth layer via 212 is obtained by subtracting the third test capacitance from the first test capacitance. The third parasitic capacitance can also be represented by Cgv0, where v0 represents the zeroth layer via 212.

[0081] The fourth parasitic capacitance formed between the gate structure and the zeroth metal layer 211 is obtained by subtracting the second test capacitance from the third test capacitance. The fourth parasitic capacitance can also be represented by Cgm0, where m0 represents the zeroth metal layer 211.

[0082] like Figure 4D , is a schematic diagram of a fourth test structure in the parasitic capacitance test structure of FinFET according to an embodiment of the present invention; the parasitic capacitance test structure also includes a fourth test structure 302d, the fourth test structure 302d is obtained by removing the embedded epitaxial layer in the first test structure 302a, and the test capacitance of the third test structure 302c is the fourth test capacitance. Generally, the surface of the embedded epitaxial layer is higher than the surface of the fin body 202; Figure 4D In the embodiment, after the embedded epitaxial layer is removed, the source region 205 and the drain region 206 are directly formed in the fin body 202 .

[0083] A fifth parasitic capacitance formed between the gate structure and the embedded epitaxial layer is obtained by subtracting the fourth test capacitance from the first test capacitance.

[0084] like Figure 4E As shown, it is a schematic diagram of the fifth test structure 302e in the parasitic capacitance test structure of the FinFET in an embodiment of the present invention. The parasitic capacitance test structure also includes a fifth test structure 302e. The fifth test structure 302e is obtained by removing the zero-layer through hole 212 at the top of the source region 205, the drain region 206 and the body lead-out region 207 in the FinFET. The test capacitance of the fifth test structure 302e is the fifth test capacitance.

[0085] The material of the gate dielectric layer 208 includes silicon dioxide or a high dielectric constant layer;

[0086] The gate conductive material layer 209 is a polysilicon gate or a metal gate;

[0087] The sixth parasitic capacitance is a parasitic capacitance used to calculate the electrical thickness of the gate dielectric layer 208 , and the sixth parasitic capacitance is obtained by subtracting the fifth test capacitance, the third parasitic capacitance, the fourth parasitic capacitance, and the fifth parasitic capacitance from the first test capacitance.

[0088] The calculation formula of the sixth parasitic capacitance is:

[0089] C6=C structure1 -C structure5 -(C structure3 -C structure2 )-(C structure1 -C structure3 )-(C structure1 -C structure4 )

[0090] =C structure2 +C structure4 -Cstructure1 -C structure5 (1);

[0091] Wherein, C6 represents the sixth parasitic capacitance,

[0092] C structure1 represents the first test capacitor;

[0093] C structure2 represents the second test capacitor;

[0094] C structure3 represents the third test capacitor;

[0095] C structure4 represents the fourth test capacitor;

[0096] C structure5 represents the fifth test capacitor;

[0097] (C structure1 -C structure2 ) represents the third parasitic capacitance, (C structure3 -C structure2 ) represents the fourth parasitic capacitance, (C structure1 -C structure4 ) represents the fifth parasitic capacitance.

[0098] It can be seen from the equation after the second equal sign of formula (1) that the sixth parasitic capacitance is directly obtained by adding the second test capacitance to the fourth test capacitance and subtracting the first test capacitance and the fifth test capacitance.

[0099] The seventh parasitic capacitance is obtained by subtracting the fifth test capacitance from the first test capacitance; the seventh parasitic capacitance is the parasitic capacitance between the gate structure and the metal interconnection line above the first metal layer.

[0100] The FinFET 301 is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; the material of the embedded epitaxial layer includes SiP. In other embodiments, the FinFET 301 is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type; the material of the embedded epitaxial layer includes SiGe.

[0101] A first shallow trench isolation structure 204 is provided between the drain region 206 and the body lead-out region 207 of the FinFET 301 .

[0102] The electrical thickness of the gate dielectric layer 208 is the thickness of a gate oxide layer that is completely composed of silicon dioxide.

[0103] In the embodiment of the present invention, the fin body 202 in the formation area of ​​the parasitic capacitance test structure of FinFET301 is switched to a first conductive type well region 214 opposite to FinFET301, so that the formation areas of each parasitic capacitance test structure can be unified, thereby avoiding the defect in the prior art that the parasitic capacitance test structure will be formed on a large shallow trench isolation structure and thus preventing the generation of butterfly defects.

[0104] The first test structure 302a of the embodiment of the present invention can be realized by switching the second conductive type well region 203 of FinFET301 to the first conductive type well region 214. The first test structure 302a can well simulate the first parasitic capacitance Cof and the second parasitic capacitance Cgtm of FinFET301, so that the parasitic capacitance of FinFET301 can be tested using the first test structure 302a.

[0105] At the same time, since the well region structure of the fin body 202 in the formation area of ​​each parasitic capacitance test structure in the embodiment of the present invention is unified, the parasitic capacitance of the zero-layer metal layer 211 and the parasitic capacitance of the zero-layer through hole 212 can be tested by making corresponding changes on the basis of the first test structure 302a. By deducting the parasitic capacitance of the zero-layer metal layer 211 and the parasitic capacitance of the zero-layer through hole 212, the parasitic capacitance of the electrical thickness of the gate dielectric layer 208 can be calculated and the electrical thickness of the gate dielectric layer 208 can be calculated. Therefore, the calculation of the parasitic capacitance of the zero-layer metal layer 211, the zero-layer through hole 212 and the electrical thickness of the gate dielectric layer 208 can be conveniently realized.

[0106] In addition, in the embodiment of the present invention, the overlapping area between the shallowly doped source region, the shallowly doped drain region and the top gate structure is eliminated, so Cov is eliminated, so that the electrical thickness of the gate dielectric layer 208 can be calculated more accurately.

[0107] The parasitic capacitance testing method of FinFET according to the embodiment of the present invention comprises the following steps:

[0108] Step 1: Perform a capacitance test, including:

[0109] The first test structure 302a is tested to obtain a first test capacitor.

[0110] The second test structure 302b is tested to obtain a second test capacitor.

[0111] The third test structure 302c is tested to obtain a third test capacitor.

[0112] The fourth test structure 302d is tested to obtain a fourth test capacitor.

[0113] The fifth test structure 302d is tested to obtain a fifth test capacitor.

[0114] Step 2: Calculate capacitance, including:

[0115] The third parasitic capacitance is obtained by subtracting the third test capacitance from the first test capacitance.

[0116] The fourth parasitic capacitance is obtained by subtracting the second test capacitance from the third test capacitance.

[0117] The fifth parasitic capacitance is obtained by subtracting the fourth test capacitance from the first test capacitance.

[0118] The seventh parasitic capacitance is obtained by subtracting the fifth test capacitance from the first test capacitance; the seventh parasitic capacitance is the parasitic capacitance between the gate structure and the metal interconnection line above the first metal layer.

[0119] Step three, obtaining the sixth parasitic capacitance, comprising: obtaining the sixth parasitic capacitance by subtracting the fifth test capacitance, the third parasitic capacitance, the fourth parasitic capacitance and the fifth parasitic capacitance from the first test capacitance.

[0120] After that, the steps include:

[0121] Step 4: Use the sixth parasitic capacitor to calculate the electrical thickness of the gate dielectric layer 208. For capacitors with a planar structure, the dielectric constant between capacitors, the capacitor area, and the capacitance thickness of the dielectric layer between capacitors are related. By knowing the dielectric constant of the capacitor, the dielectric layer between capacitors, and the capacitor area, the electrical thickness of the dielectric layer between capacitors can be calculated.

[0122] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A parasitic capacitance test structure of FinFET, characterized in that: The FinFET includes a gate structure, a lightly doped source region and a lightly doped drain region composed of a first conductivity type lightly doped region, a sidewall, a source region and a drain region composed of a first conductivity type heavily doped region, a second conductivity type well region, and a body lead region composed of a second conductivity type heavily doped region; The gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer; The second conductive type well region is formed in the fin body, the gate structure covers the top surface and side surfaces of the fin body, the second conductive type well region is formed in the fin body, and the surface of the second conductive type well region covered by the gate structure is used to form a conductive channel; The shallowly doped source region and the shallowly doped drain region are self-alignedly formed in the fin body on both sides of the gate structure, and the shallowly doped source region and the shallowly doped drain region extend below the bottom surface of the gate structure; the sidewalls are self-alignedly formed on both sides of the gate structure, and the source region and the drain region are self-alignedly formed in the fin body on both sides of the sidewalls on both sides of the gate structure, and the second conductive type well region covers the source region, the drain region and the body lead-out region; a zero-layer metal layer is formed on the top of the source region, the drain region, the gate structure and the body lead-out region, a zero-layer through hole is formed on the top of the metal zero layer, and a metal interconnection structure composed of metal layers and through holes above the first metal layer is formed on the top of the zero-layer through hole; The parasitic capacitance test structure of the FinFET includes a plurality of structures, and a first conductive type well region is formed in the fin body in a formation area of ​​the plurality of parasitic capacitance test structures; The first test structure in the parasitic capacitance test structure is formed by replacing the second conductive type well region of the FinFET with the first conductive type well region and simultaneously removing the shallowly doped source region and the shallowly doped drain region. The test capacitor of the first test structure is a first test capacitor, and the first test capacitor includes a first parasitic capacitor and a second parasitic capacitor. The first parasitic capacitor is a parasitic capacitor between the source region or the drain region and the gate structure, and the second parasitic capacitor is a parasitic capacitor between the gate structure and the metal interconnect line above the zeroth metal layer.

2. The parasitic capacitance test structure of FinFET according to claim 1, characterized in that: The parasitic capacitance test structure also includes a second test structure, which is obtained by removing the zeroth metal layer and the zeroth through hole on the top of the source region and the drain region in the first test structure, and the test capacitance of the second test structure is a second test capacitance.

3. The parasitic capacitance test structure of FinFET according to claim 2, characterized in that: The parasitic capacitance test structure further includes a third test structure, the third test structure is obtained by removing the zeroth layer through hole at the top of the source region and the drain region in the first test structure, and the test capacitance of the third test structure is a third test capacitance; A third parasitic capacitance formed between the gate structure and the zeroth layer through hole is obtained by subtracting the third test capacitance from the first test capacitance; A fourth parasitic capacitance formed between the gate structure and the zeroth metal layer is obtained by subtracting the second test capacitance from the third test capacitance.

4. The parasitic capacitance test structure of FinFET according to claim 3, characterized in that: The FinFET further includes an embedded epitaxial layer, wherein the embedded epitaxial layer is formed in the fin body on both sides of the gate structure, and the source region and the drain region are formed in the embedded epitaxial layer; The parasitic capacitance test structure further includes a fourth test structure, the fourth test structure is obtained by removing the embedded epitaxial layer in the first test structure, and the test capacitance of the fourth test structure is a fourth test capacitance; A fifth parasitic capacitance formed between the gate structure and the embedded epitaxial layer is obtained by subtracting the fourth test capacitance from the first test capacitance.

5. The parasitic capacitance test structure of FinFET according to claim 4, characterized in that: The parasitic capacitance test structure also includes a fifth test structure, which is obtained by removing the zero-layer through-hole at the top of the source region, the drain region and the body lead-out region in the FinFET, and the test capacitance of the fifth test structure is a fifth test capacitance.

6. The parasitic capacitance test structure of FinFET according to claim 5, characterized in that: The material of the gate dielectric layer includes silicon dioxide or a high dielectric constant layer; The gate conductive material layer is a polysilicon gate or a metal gate; The sixth parasitic capacitance is a parasitic capacitance used to calculate the electrical thickness of the gate dielectric layer, and the sixth parasitic capacitance is obtained by subtracting the fifth test capacitance, the third parasitic capacitance, the fourth parasitic capacitance and the fifth parasitic capacitance from the first test capacitance.

7. The parasitic capacitance test structure of FinFET according to claim 6, characterized in that: The sixth parasitic capacitance is directly obtained by adding the fourth test capacitance to the second test capacitance and subtracting the first test capacitance and the fifth test capacitance.

8. The parasitic capacitance test structure of FinFET according to claim 7, characterized in that: The FinFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the FinFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

9. The parasitic capacitance test structure of FinFET according to claim 8, characterized in that: When the FinFET is an N-type device, the material of the embedded epitaxial layer includes SiP.

10. The parasitic capacitance test structure of FinFET according to claim 8, characterized in that: When the FinFET is a P-type device, the material of the embedded epitaxial layer includes SiGe.

11. The parasitic capacitance test structure of FinFET according to claim 1, characterized in that: A first shallow trench isolation structure is provided between the drain region and the body lead-out region of the FinFET.

12. The parasitic capacitance test structure of FinFET according to claim 6, characterized in that: The electrical thickness of the gate dielectric layer is the thickness of a gate oxide layer that is equivalent to the gate dielectric layer and is completely composed of silicon dioxide.

13. A method for performing parasitic capacitance testing using the parasitic capacitance testing structure of FinFET according to claim 6, characterized in that: The steps include: Step 1: Perform a capacitance test, including: Testing the first test structure to obtain a first test capacitor; Testing the second test structure to obtain a second test capacitance; Testing the third test structure to obtain a third test capacitance; Testing the fourth test structure to obtain a fourth test capacitor; Testing the fifth test structure to obtain a fifth test capacitor; Step 2: Calculate capacitance, including: Subtracting the third test capacitance from the first test capacitance to obtain the third parasitic capacitance; Subtracting the second test capacitance from the third test capacitance to obtain the fourth parasitic capacitance; The fifth parasitic capacitance is obtained by subtracting the fourth test capacitance from the first test capacitance; The seventh parasitic capacitance is obtained by subtracting the fifth test capacitance from the first test capacitance; the seventh parasitic capacitance is the parasitic capacitance between the gate structure and the metal interconnection line above the first metal layer; Step three, obtaining the sixth parasitic capacitance, comprising: obtaining the sixth parasitic capacitance by subtracting the fifth test capacitance, the third parasitic capacitance, the fourth parasitic capacitance and the fifth parasitic capacitance from the first test capacitance.

14. The parasitic capacitance testing method of FinFET according to claim 13, characterized in that: Also includes the steps: Step 4: Calculate the electrical thickness of the gate dielectric layer using the sixth parasitic capacitance.

15. The parasitic capacitance testing method of FinFET according to claim 13, characterized in that: In step three, the sixth parasitic capacitance is directly obtained by adding the fourth test capacitance to the second test capacitance and subtracting the first test capacitance and the fifth test capacitance.

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