A driving circuit for a semiconductor circuit

Abstract

The present invention relates to a driving circuit of a semiconductor circuit, comprising a low-voltage working circuit, a high-voltage working circuit, a bootstrap circuit and a pre-charge control circuit, wherein the input end of the low-voltage working circuit is the input end of the driving circuit, the output end of the low-voltage working circuit is connected to the input end of the high-voltage working circuit, the output end of the high-voltage working circuit is the output end of the driving circuit, the bootstrap circuit supplies power to the high-voltage working circuit, the control output end of the pre-charge control circuit is connected to the control input end of the bootstrap electric control, the voltage detection end of the pre-charge control circuit is connected to the low-voltage power supply of the driving circuit, and the pre-charge control circuit controls the bootstrap circuit to work to complete the charging process when detecting a power-on state. By setting the pre-charge control circuit, an MCU can effectively control an upper arm switch tube to be normally turned on when in a power-on state, thereby ensuring the normal operation of the semiconductor circuit.

Description

Technical Field

[0001] The invention relates to a driving circuit based on a semiconductor circuit, belonging to the technical field of semiconductor circuit applications. Background Art

[0002] Semiconductor circuits are power-driven products that combine power electronics and integrated circuit technology. Their internal driver circuit converts the control signals input by the MCU into signals that drive switching transistors, such as IGBTs. The driver circuit includes a bootstrap circuit, which contains a capacitor charging circuit. This circuit charges the capacitor when the lower-arm switch is on. When the upper-arm switch is on, the voltage in the bootstrap circuit's charging circuit is applied to the driver terminal of the upper-arm switch to maintain its on-state. The voltage then discharges while maintaining the on-state, and then recharges the capacitor the next time the lower-arm switch is turned on. This cycle repeats, ensuring the proper operation of both upper- and lower-arm switches. Current driver circuits prevent charging of the lower-arm switch during power-up because the lower-arm switch is turned off. The bootstrap circuit only charges when the MCU outputs a control signal to turn on the lower-arm switch. Therefore, if the MCU's control software is not designed to pre-charge the bootstrap circuit during power-up, the upper-arm switch can become unstable, leading to malfunctions in the entire semiconductor circuit. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to solve the problem in the existing semiconductor circuit driving circuit that the upper bridge arm switch tube does not work properly due to the lack of a pre-charge control signal when powered on.

[0004] Specifically, the present invention discloses a driving circuit for a semiconductor circuit, the driving circuit including a low-voltage operating circuit, a high-voltage operating circuit, a bootstrap circuit, and a pre-charge control circuit;

[0005] The input end of the low-voltage working circuit is the input end of the driving circuit, and the output end of the low-voltage working circuit is connected to the input end of the high-voltage working circuit;

[0006] The output end of the high-voltage working circuit is the output end of the driving circuit, and the bootstrap circuit supplies power to the high-voltage working circuit;

[0007] The control output end of the pre-charge control circuit is connected to the control input end of the bootstrap circuit, and the voltage detection end of the pre-charge control circuit is connected to the low-voltage power supply of the drive circuit. When the pre-charge control circuit detects the power-on state, it controls the bootstrap circuit to complete the charging process.

[0008] Optionally, the pre-charge control circuit includes a voltage rise detection circuit, a charge timing circuit and a control logic circuit;

[0009] The input end of the voltage rise detection circuit is the voltage detection end of the pre-charge control circuit, the first output end and the second output end of the voltage rise detection circuit are respectively connected to the charge start control end of the control logic circuit and the timing start control end of the charge timing circuit, the output end of the charge timing circuit is connected to the charge end control end of the control logic circuit, and the control output end of the control logic circuit is the control output end of the pre-charge control circuit;

[0010] The voltage rise detection circuit detects the rising edge signal of the low-voltage power supply when it is powered on, and outputs a charging start signal to the control logic circuit at the first output terminal, so that the control logic circuit outputs a bootstrap operation signal to control the bootstrap circuit to start working. At the same time, the second output terminal outputs a timing start signal to the charging timing circuit to start timing. When the timing time is up, the charging timing circuit outputs a charging end signal to the charging end control terminal to control the control logic circuit to control the bootstrap circuit to end working.

[0011] Optionally, the voltage rise detection circuit includes a voltage comparison unit and a detection logic unit;

[0012] The input end of the voltage comparison unit is the input end of the voltage rise detection circuit, the first output end and the second output end of the voltage comparison unit are respectively connected to the detection logic unit, the charging start signal output end of the detection logic unit is the first output end of the voltage rise detection circuit, and the timing start signal output end of the detection logic unit is the second output end of the voltage rise detection circuit; the voltage comparison unit detects the first level and the second level higher than the first level of the voltage of the low-voltage power supply input to the input end of the voltage comparison unit, and outputs detection signals corresponding to the first level and the second level to the detection logic unit at the first output end and the second output end of the voltage comparison unit respectively. When the detection logic unit determines that the interval time between the two detection signals is lower than the preset time, the charging start signal and the timing start signal are output from the charging start signal output end and the timing start signal output end respectively.

[0013] Optionally, the control logic circuit also includes a protection logic input terminal, and the protection signal output terminal of the low-voltage working circuit or the high-voltage working circuit is connected to the protection logic input terminal. When a protection action occurs in the low-voltage working circuit or the high-voltage working circuit, the signal input to the protection logic input terminal is valid to cause the bootstrap circuit to stop working.

[0014] Optionally, the control logic circuit includes a sixth inverter, a seventh NAND gate, an eighth inverter, a ninth NAND gate and a tenth inverter;

[0015] The input end of the sixth inverter is the charging end control end of the control logic circuit, and the output end of the sixth inverter is connected to the second input end of the seventh NAND gate;

[0016] The first input terminal of the seventh NAND gate is the charging start control terminal of the control logic circuit, and the output terminal of the seventh NAND gate is connected to the input terminal of the eighth inverter;

[0017] The output terminal of the eighth inverter is connected to the first input terminal of the ninth NAND gate;

[0018] The output end of the ninth NAND gate is connected to the input end of the tenth inverter, and the output end of the tenth inverter is the control output end of the control logic circuit.

[0019] Optionally, the control logic circuit also includes an enable signal output terminal, which is connected to the enable control terminal of the low-voltage working circuit. When the pre-charge control circuit controls the bootstrap circuit to work and charge, the enable control terminal outputs a valid control signal to stop the low-voltage working circuit from working.

[0020] Optionally, the output terminal of the ninth NAND gate is also commonly connected to the enable signal output terminal of the control logic circuit.

[0021] Optionally, the control logic circuit includes a sixth inverter, a seventh NAND gate, an eighth inverter, a ninth NAND gate, a tenth inverter, and an eleventh inverter;

[0022] The input end of the sixth inverter is the charging end control end of the control logic circuit, and the output end of the sixth inverter is connected to the second input end of the seventh NAND gate;

[0023] The first input terminal of the seventh NAND gate is the charging start control terminal of the control logic circuit, and the output terminal of the seventh NAND gate is connected to the input terminal of the eighth inverter;

[0024] The output terminal of the eighth inverter is connected to the first input terminal of the ninth NAND gate;

[0025] The output end of the ninth NAND gate is connected to the input end of the tenth inverter, and the output end of the tenth inverter is the control output end of the control logic circuit.

[0026] The input terminal of the eleventh inverter is the protection logic input terminal of the control logic circuit, and the output terminal of the eleventh inverter is connected to the second input terminal of the ninth NAND gate;

[0027] Optionally, the charging timing circuit includes an input logic circuit, a timing comparison circuit, and an output logic circuit connected in sequence;

[0028] The input end of the input logic circuit is the timing start control end of the charging timing circuit, and the output end of the output logic circuit is the output end of the charging timing circuit;

[0029] When the input logic circuit detects that the timing start signal is valid, it controls the timing comparison circuit to start charging. When the timing comparison circuit detects that the charging voltage is greater than the preset voltage threshold, it outputs a valid level signal to the output logic circuit to control the output logic circuit to output a charging end signal.

[0030] Optionally, the timing comparison circuit includes a third resistor, a first capacitor, a reference voltage source and a fifth comparator;

[0031] One end of the third resistor is the input end of the timing comparator circuit, the other end of the third resistor and one end of the first capacitor are connected to the non-inverting input end of the fifth comparator, the other end of the first capacitor is grounded, the output end of the reference voltage source is connected to the inverting input end of the fifth comparator, and the output end of the fifth comparator is the output end of the timing comparator circuit.

[0032] The driving circuit of the semiconductor circuit of the present invention includes a low-voltage working circuit, a high-voltage working circuit, a bootstrap circuit and a pre-charge control circuit, wherein the input end of the low-voltage working circuit is the input end of the driving circuit, the output end of the low-voltage working circuit is connected to the input end of the high-voltage working circuit, the output end of the high-voltage working circuit is the output end of the driving circuit, the bootstrap circuit is powered by the high-voltage working circuit, the control output end of the pre-charge control circuit is connected to the control input end of the bootstrap circuit, the voltage detection end of the pre-charge control circuit is connected to the low-voltage power supply of the driving circuit, and the pre-charge control circuit controls the bootstrap circuit to work to complete the charging process when the power-on state is detected. By setting the pre-charge control circuit, the MCU can effectively control the upper arm switch tube to be normally turned on when the power-on state is set, thereby ensuring the normal operation of the semiconductor circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a block diagram of a driving circuit of a semiconductor circuit according to an embodiment of the present invention;

[0034] Figure 2 is a block diagram of a pre-charge control circuit of a driving circuit according to an embodiment of the present invention;

[0035] Figure 3 A simplified schematic diagram of a voltage rise detection circuit of a pre-charge control circuit according to an embodiment of the present invention;

[0036] Figure 4 A simplified schematic diagram of a charging timing circuit of a pre-charging control circuit according to an embodiment of the present invention;

[0037] Figure 5 This is a simplified schematic diagram of a control logic circuit of a pre-charge control circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] It should be noted that, in the absence of structural or functional conflicts, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below based on examples.

[0039] The semiconductor circuit referred to in this invention is a circuit module that integrates power switching devices and high-voltage drive circuits in a sealed package. It has a wide range of applications in power electronics, such as motor drive inverters, various voltage inverters, variable frequency speed regulation, metallurgical machinery, electric traction, and variable frequency home appliances. The semiconductor circuit here is also known by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), hybrid integrated circuit, power semiconductor module, power module, etc.

[0040] The present invention first proposes a driving circuit for a semiconductor circuit, wherein the driving circuit includes a low-voltage operating circuit 300, a high-voltage operating circuit 400, a bootstrap circuit 200, and a pre-charge control circuit 100. The low-voltage operating circuit 300 operates in a low-voltage region, i.e., a low voltage such as 15V power supply, while the high-voltage operating region operates at a high voltage such as 300V power supply. The input end of the low-voltage operating circuit 300 serves as the input end of the driving circuit, the output end of the low-voltage operating circuit 300 is connected to the input end of the high-voltage operating circuit 400, the output end of the high-voltage operating circuit 400 serves as the output end of the driving circuit, the bootstrap circuit 200 supplies power to the high-voltage operating circuit 400, the control output end of the pre-charge control circuit 100 is connected to the control input end of the bootstrap circuit 200, and the voltage detection end of the pre-charge control circuit 100 is connected to the low-voltage power supply VCC of the driving circuit. When the pre-charge control circuit 100 detects a power-on state, it controls the bootstrap circuit 200 to complete the charging process. The input end of the low voltage working circuit 300 is connected to the low voltage control signal output by the MCU (not shown in the figure), specifically the upper arm switch control signal HIN and the lower arm switch control signal LIN, and passes through a series of module circuits such as Figure 1The Schmitt trigger in the circuit filters horizontal noise, and the filter filters high-frequency noise. The low-voltage signal is then boosted by the voltage regulator to increase the lower voltage, such as 5V, to a higher voltage, such as 15V. The circuit is interlocked to prevent the upper and lower arm switch tubes from being simultaneously turned on due to the high level of the upper and lower arm switch tube control signal HIN and the lower bridge arm switch tube control signal LIN. The interlock circuit outputs two paths. One path is delayed by the delay circuit and output to one input of the NAND gate. At the same time, the first voltage protection circuit detects the low-voltage direct current and outputs the detection signal to the other input of the NAND gate. Voltage protection is achieved through the NAND gate. The signal is output to the first output driver circuit composed of two MOS transistors through the NAND gate to output the lower bridge arm drive signal. The input signal of the first driver circuit is consistent with the lower bridge arm switch tube control signal LIN. At the same time, the interlock circuit outputs two pulse signals through the pulse generating circuit. The two pulse signals correspond to the rising edge and falling edge of the upper bridge arm switch tube control signal HIN, respectively. The two pulse signals are input to the high-voltage working circuit 400.

[0041] The high-voltage working circuit 400 includes a low-high voltage transition circuit, a filter, a second voltage protection circuit, a signal processing circuit, and a second drive circuit, wherein the low-high voltage transition circuit realizes the transition between the low-voltage area and the high-voltage area. The two input low-voltage pulse signals are converted into high-voltage pulse signals such as 300V by the low-high voltage transition circuit, and then filtered by the filter. The second voltage protection circuit prevents the voltage from being too low, causing the second drive circuit to stop working. Then, the signal processing circuit performs logical processing on the two high-voltage pulse signals, thereby converting the two pulse signals into drive signals corresponding to the control signal HIN of the upper bridge arm switch tube to drive the second output drive circuit of the subsequent stage to work. Finally, the second output drive circuit outputs the drive signal to drive the upper bridge arm switch tube to work.

[0042] The above-mentioned low-voltage working circuit 300 and high-voltage working circuit 400 are prior art, and the specific working principles of the internal module circuits are not described in detail. The input end of the bootstrap circuit 200 is connected to a low-voltage power supply VCC such as 15V, and the output end is connected to a floating high-voltage power supply VB such as 300V. The bootstrap circuit 200 contains a charging circuit with a capacitor, which is charged when the lower bridge arm switch tube is turned on. When the upper bridge arm switch tube is turned on, the voltage on the charging circuit of the bootstrap circuit 200 is loaded on the driving end of the upper bridge arm switch tube to maintain its conduction, and discharges when it maintains its conduction, and then recharges when the lower bridge arm switch tube is turned on next time. This cycle is repeated, thereby achieving the normal operation of the upper and lower bridge arm switch tubes. When the semiconductor circuit is powered on, that is, when the drive circuit is powered on, the general MCU will not output an effective lower bridge arm switch tube control signal LIN to charge the bootstrap circuit 200. This will cause the bootstrap capacitor to not be charged and store electrical energy, and cannot output a reliable voltage to ensure the effective conduction of the upper bridge arm switch tube when powered on, thereby causing the semiconductor circuit to malfunction. To solve this problem, the driving circuit of an embodiment of the present invention adds a pre-charging control circuit 100, which determines whether the driving circuit is in a power-on state by detecting changes in the signal of the low-voltage power supply. If it is detected to be in a power-on state, the pre-charging control circuit 100 outputs a valid control signal to control the bootstrap circuit 200 to work for charging, so that the MCU can effectively control the upper bridge arm switch tube to be normally turned on when in the power-on state, thereby ensuring the normal operation of the semiconductor circuit.

[0043] Specifically, in some embodiments of the present invention, Figure 2As shown, the pre-charge control circuit 100 includes a voltage rise detection circuit 10, a charging timing circuit 20 and a control logic circuit 30; the input end of the voltage rise detection circuit 10 is the voltage detection end of the pre-charge control circuit 100, the first output end and the second output end of the voltage rise detection circuit 10 are respectively connected to the charging start control end of the control logic circuit 30 and the timing start control end of the charging timing circuit 20, the output end of the charging timing circuit 20 is connected to the charging end control end of the control logic circuit 30, and the control output end of the control logic circuit 30 is the control output end of the pre-charge control circuit 100; the voltage rise detection circuit 10 detects the rising edge signal when the low-voltage power supply is powered on, and outputs a charging start signal to the control logic circuit 30 at the first output end, so that the control logic circuit 30 outputs a bootstrap working signal to control the bootstrap circuit 20 to start working, and at the same time, outputs a timing start signal to the charging timing circuit 20 at the second output end to start timing. When the timing time is up, the charging timing circuit 20 outputs a charging end signal to the charging end control end to control the control logic circuit 30 to control the bootstrap circuit 20 to end working. Specifically, the voltage rise detection circuit 10 detects the rising edge signal of the low-voltage power supply VCC of the semiconductor circuit's driver circuit to identify the driver circuit's power-on state. After identifying the power-on state, the voltage rise detection circuit 10 simultaneously outputs a charging start signal and a timing start signal from the first and second output terminals of the voltage rise detection circuit 10 to the control logic circuit 30 and the charging timing circuit 20, respectively. This causes the control output terminal of the control logic circuit 30 to output a valid control signal to control the bootstrap circuit 200 to start charging and simultaneously control the charging timing circuit 20 to start timing. After the charging timing circuit 20 reaches a preset time, it outputs a charging end signal to the control logic circuit 30 to control the bootstrap circuit 200 to stop operating, that is, to stop internal charging, thereby charging the bootstrap circuit 200 to a preset voltage, thereby providing a suitable voltage for turning on the high-arm switch. Through these three unit circuits of the pre-charge control circuit 100, it is achieved that when the power-on state is detected, the bootstrap voltage is controlled to charge to a reasonable preset voltage to provide a suitable voltage for turning on the high-arm switch.

[0044] In some embodiments of the present invention, Figure 3As shown, the above-mentioned voltage rise detection circuit 10 includes a voltage comparison unit 11 and a detection logic unit 12; the input end of the voltage comparison unit 11 is the input end of the voltage rise detection circuit 10, the first output end and the second output end of the voltage comparison unit 11 are respectively connected to the detection logic unit 12, the charging start signal output end of the detection logic unit 12 is the first output end of the voltage rise detection circuit 10, and the timing start signal output end of the detection logic unit 12 is the second output end of the voltage rise detection circuit 10; the voltage comparison unit 11 detects the first level and the second level higher than the first level of the low-voltage power supply VCC input to the input end of the voltage comparison unit 11, and outputs detection signals corresponding to the first level and the second level to the detection logic unit 12 at the first output end of the voltage comparison unit 11 and the second output end of the power supply of the voltage comparison unit 11 respectively. When the detection logic unit 12 determines that the interval time between the two detection signals is less than the preset time, it outputs the charging start signal and the timing start signal from the charging start signal output end and the timing start signal output end respectively. Figure 3 As can be seen, the voltage comparison unit 11 is primarily composed of two comparators, specifically a first comparator and a second comparator. The inverting inputs of the two comparators are connected to two reference voltages, V1 and V2, respectively. V1 is lower than V2, corresponding to a first voltage level and a second voltage level. For example, when the low-voltage power supply VCC is 15V, the first voltage level V1 can be set to 1V and the second voltage level V2 can be set to 5V. The first comparator is used to determine the comparison status of the low-voltage power supply VCC with the first voltage level V1 and output the result to the detection logic unit 12. The second comparator is used to determine the comparison status of the low-voltage power supply VCC with the first voltage level V2 and output the result to the detection logic unit 12. If the detection logic unit 12 detects that the low-voltage power supply VCC is lower than the first voltage level V1 and then detects that the low-voltage power supply VCC is higher than the second voltage level V2 within a preset time, such as 1ms, the low-voltage power supply VCC generates a rising edge signal, indicating a power-on state. The RC delay circuit within the detection logic unit 12 is used to generate the preset time, providing an accurate timing reference for the detection logic unit 12's determination.

[0045] Furthermore, if Figure 4As shown, the charging timing circuit 20 includes an input logic circuit 21, a timing comparison circuit 22, and an output logic circuit 23 connected in sequence; the input end of the input logic circuit 21 is the timing start control end of the charging timing circuit 20, and the output end of the output logic circuit 23 is the output end of the charging timing circuit 20; when the input logic circuit 21 detects that the timing start signal is valid, it controls the timing comparison circuit 22 to start charging. When the timing comparison circuit 22 detects that the charging voltage is greater than a preset voltage threshold, it outputs a valid level signal to the output logic circuit 23 to control the output logic circuit 23 to output a charging end signal. Input logic circuit 21 is used to detect whether the timing start signal is valid. Upon detecting the timing start signal, it outputs a valid charging voltage to timing comparator circuit 22. Timing comparator circuit 22 primarily comprises an RC charging circuit and a fifth comparator IC5. Its inverting input receives a reference voltage V3, and its non-inverting input is connected to the RC charging circuit. When the charging voltage is applied to the RC charging circuit, it begins charging first capacitor C1 via third resistor R3 of the RC charging circuit. The voltage at the non-inverting input rises. When it exceeds the input reference voltage V3, the output voltage of fifth comparator IC5 switches from a low level to a high level, thereby controlling output logic circuit 23, which then processes and outputs a charging end signal. By configuring the resistance and capacitance parameters of the RC charging circuit, the charging timing circuit 20 can be set to a preset time. Typically, the RC constant can be set to 5ms to 10ms, such as 7ms, to control the charging time of bootstrap circuit 200 to reach a reasonable preset voltage within this time.

[0046] Specifically, the timing comparison circuit 22 includes a third resistor R3, a first capacitor C1, a reference voltage source V3 and a fifth comparator IC5. One end of the third resistor R3 is the input end of the timing comparison circuit 22, the other end of the third resistor R3 and one end of the first capacitor C1 are connected to the non-inverting input end of the fifth comparator IC5, the other end of the first capacitor C1 is grounded, the output end of the reference voltage source V3 is connected to the inverting input end of the fifth comparator IC5, and the output end of the fifth comparator IC5 is the output end of the timing comparison circuit 22.

[0047] Furthermore, the timing comparison circuit 22 also includes a third inverter IC3 and a fourth inverter IC4, the input end of the third inverter IC3 is the input end of the timing comparison circuit 22, the output end of the third inverter IC3 is connected to the fourth inverter IC4, the output end of the fourth inverter IC4 is connected to one end of the third resistor R3, and the third inverter IC3 and the fourth inverter IC4 realize the isolation of the charging voltage signal output by the input logic circuit 21.

[0048] Furthermore, if Figure 5As shown, the control logic circuit 30 includes a sixth inverter IC6, a seventh NAND gate IC7, an eighth inverter IC8, a ninth NAND gate IC9 and a tenth inverter IC10; the input end of the sixth inverter IC6 is the charging end control end of the control logic circuit 30, and the output end of the sixth inverter IC6 is connected to the second input end of the seventh NAND gate IC7; the first input end of the seventh NAND gate IC7 is the charging start control end of the control logic circuit 30, and the output end of the seventh NAND gate IC7 is connected to the input end of the eighth inverter IC8; the output end of the eighth inverter IC8 is connected to the first input end of the ninth NAND gate IC9; the output end of the ninth NAND gate IC9 is connected to the input end of the tenth inverter IC10, and the output end of the tenth inverter IC10 is the control output end of the control logic circuit 30. The above-mentioned gate circuit can conveniently infer the logical relationship between its input and output signals. That is, when the signal input to the charge start control terminal of the control logic circuit 30 is a valid high level and the signal input to the charge end control terminal is an invalid low level, the control signal BS output from the control output terminal of the control logic circuit 30 is a high level to control the bootstrap circuit 200 to charge; when the signal input to the charge end control terminal is a valid high level, the control signal BS output from the control output terminal of the control logic circuit 30 is a low level to control the bootstrap circuit 200 to stop charging.

[0049] Furthermore, the control logic circuit 30 also includes an enable signal output terminal EN-, and the enable signal output terminal EN- is connected to the enable control terminal of the low-voltage working circuit 300. When the pre-charge control circuit 100 controls the bootstrap circuit 200 to work and charge, the enable control terminal outputs a valid control signal to stop the low-voltage working circuit 300. The enable signal output terminal EN- outputs an enable signal, so that when the pre-charge control circuit 100 controls the bootstrap circuit 200 to work and charge, the low-voltage working circuit 300 and the high-voltage working circuit 400 stop working, so that the corresponding upper-arm switch tube and lower-arm switch tube are in a closed state, so that the upper-arm switch tube and the lower-arm switch tube will not affect the charging process of the bootstrap circuit 200. Specifically, as Figure 5 As shown, the output terminal of the ninth NAND gate IC9 is also commonly connected to the enable signal output terminal EN- of the control logic circuit 30. That is, when the control signal BS outputted from the control output terminal of the control logic circuit 30 is active high, the enable signal outputted from the enable signal output terminal EN- is active low.

[0050] Furthermore, if Figure 5As shown, in some embodiments of the present invention, the control logic circuit 30 further includes a protection logic input terminal. The protection signal output terminal of the low-voltage operating circuit 300 or the high-voltage operating circuit 400 is connected to the protection logic input terminal. When the low-voltage operating circuit 300 or the high-voltage operating circuit 400 triggers a protection action, the signal input to the protection logic input terminal is valid, causing the pre-charge control circuit 100 to stop operating. When the main circuit of the driving circuit, i.e., the low-voltage operating circuit 300 or the high-voltage operating circuit 400, triggers a protection action such as overcurrent protection or overtemperature protection, all circuits of the driving circuit should be stopped to ensure the safety of the driving circuit. Therefore, when the low-voltage operating circuit 300 or the high-voltage operating circuit 400 triggers a protection action, the protection signal is output to the protection logic input terminal to control the bootstrap circuit 200 to stop operating. Specifically, in order to add the function corresponding to the protection logic input terminal, the control logic circuit 30 adds an eleventh inverter IC11 on the basis of the above circuit. The input terminal of the eleventh inverter IC11 is the protection logic input terminal of the control logic circuit 30, and the output terminal of the eleventh inverter IC11 is connected to the second input terminal of the ninth NAND gate IC9. In this way, when the protection signal input to the protection logic input terminal is a valid high level, the conversion logic of the eleventh inverter IC11 ultimately controls the control signal BS output from the control output terminal of the control logic circuit 30 to be a low level, thereby controlling the bootstrap circuit 200 to stop working.

[0051] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0052] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0054] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0055] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0056] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A driving circuit for a semiconductor circuit, characterized in that: The driving circuit includes a low-voltage working circuit, a high-voltage working circuit, a bootstrap circuit and a pre-charge control circuit; The input end of the low-voltage working circuit is the input end of the driving circuit, and the output end of the low-voltage working circuit is connected to the input end of the high-voltage working circuit; The output end of the high-voltage working circuit is the output end of the driving circuit, and the bootstrap circuit supplies power to the high-voltage working circuit; The control output end of the pre-charge control circuit is connected to the control input end of the bootstrap circuit, and the voltage detection end of the pre-charge control circuit is connected to the low-voltage power supply of the driving circuit. When the pre-charge control circuit detects the power-on state, it controls the bootstrap circuit to work to complete the charging process; The pre-charge control circuit includes a voltage rise detection circuit, a charge timing circuit and a control logic circuit; The input end of the voltage rise detection circuit is the voltage detection end of the pre-charge control circuit, the first output end and the second output end of the voltage rise detection circuit are respectively connected to the charge start control end of the control logic circuit and the timing start control end of the charge timing circuit, the output end of the charge timing circuit is connected to the charge end control end of the control logic circuit, and the control output end of the control logic circuit is the control output end of the pre-charge control circuit; The voltage rise detection circuit detects a rising edge signal when the low-voltage power supply is powered on, and outputs a charging start signal to the control logic circuit at the first output terminal, so that the control logic circuit outputs a bootstrap operation signal to control the bootstrap circuit to start working. At the same time, the second output terminal outputs a timing start signal to the charging timing circuit to start timing. When the timing time expires, the charging timing circuit outputs a charging end signal to the charging end control terminal, so as to control the control logic circuit to control the bootstrap circuit to end working. The voltage rise detection circuit includes a voltage comparison unit and a detection logic unit; The input end of the voltage comparison unit is the input end of the voltage rise detection circuit, the first output end and the second output end of the voltage comparison unit are respectively connected to the detection logic unit, the charging start signal output end of the detection logic unit is the first output end of the voltage rise detection circuit, and the timing start signal output end of the detection logic unit is the second output end of the voltage rise detection circuit; the voltage comparison unit detects a first level of the voltage of the low-voltage power supply input to the input end of the voltage comparison unit and a second level higher than the first level, and outputs detection signals corresponding to the first level and the second level to the detection logic unit at the first output end and the second output end of the voltage comparison unit respectively; when the detection logic unit determines that the interval time between the two detection signals is less than a preset time, the charging start signal and the timing start signal are output from the charging start signal output end and the timing start signal output end respectively; The voltage comparison unit is composed of two comparators, specifically a first comparator and a second comparator, the inverting input terminals of the two comparators are respectively connected to two reference voltages V1 and V2, wherein V1 is lower than V2, V1 corresponds to the first level, and V2 corresponds to the second level.

2. The driving circuit according to claim 1, wherein: The control logic circuit also includes a protection logic input terminal, and the protection signal output terminal of the low-voltage working circuit or the high-voltage working circuit is connected to the protection logic input terminal. When the low-voltage working circuit or the high-voltage working circuit undergoes a protection action, the signal input to the protection logic input terminal is valid so that the bootstrap circuit stops working.

3. The driving circuit according to claim 2, wherein: The control logic circuit includes a sixth inverter, a seventh NAND gate, an eighth inverter, a ninth NAND gate, a tenth inverter and an eleventh inverter; The input end of the sixth inverter is the charging end control end of the control logic circuit, and the output end of the sixth inverter is connected to the second input end of the seventh NAND gate; The first input terminal of the seventh NAND gate is the charging start control terminal of the control logic circuit, and the output terminal of the seventh NAND gate is connected to the input terminal of the eighth inverter; The output end of the eighth inverter is connected to the first input end of the ninth NAND gate; The output end of the ninth NAND gate is connected to the input end of the tenth inverter, and the output end of the tenth inverter is the control output end of the control logic circuit; The input end of the eleventh inverter is the protection logic input end of the control logic circuit, and the output end of the eleventh inverter is connected to the second input end of the ninth NAND gate.

4. The driving circuit according to claim 3, wherein: The control logic circuit also includes an enable signal output end, which is connected to the enable control end of the low-voltage working circuit. When the pre-charge control circuit controls the bootstrap circuit to work and charge, the enable control end outputs a valid control signal to stop the low-voltage working circuit from working.

5. The driving circuit according to claim 4, wherein: The output end of the ninth NAND gate is also commonly connected to the enable signal output end of the control logic circuit.

6. The driving circuit according to claim 1, wherein: The charging timing circuit includes an input logic circuit, a timing comparison circuit and an output logic circuit connected in sequence; The input end of the input logic circuit is the timing start control end of the charging timing circuit, and the output end of the output logic circuit is the output end of the charging timing circuit; When the input logic circuit detects that the timing start signal is valid, it controls the timing comparison circuit to start charging. When the timing comparison circuit detects that the charging voltage is greater than a preset voltage threshold, it outputs a valid level signal to the output logic circuit to control the output logic circuit to output the charging end signal.

7. The driving circuit according to claim 6, wherein: The timing comparison circuit includes a third resistor, a first capacitor, a reference voltage source and a fifth comparator; One end of the third resistor is the input end of the timing comparison circuit, the other end of the third resistor and one end of the first capacitor are connected to the non-inverting input end of the fifth comparator, the other end of the first capacitor is grounded, the output end of the reference voltage source is connected to the inverting input end of the fifth comparator, and the output end of the fifth comparator is the output end of the timing comparison circuit.

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