Cryogenic CMOS Interface for Controlling Qubits

Abstract

Systems and methods related to cryogenic CMOS interfaces for controlling qubit gates are provided. A system for controlling a qubit gate includes a first device that includes a quantum device, and the quantum device includes a qubit gate. The system further includes a second device that includes a control system configured to operate at cryogenic temperatures. The control system includes charge locking circuits, wherein each charge locking circuit in the charge locking circuits is coupled via an interconnect to at least one qubit gate such that each charge locking circuit in the charge locking circuits is configured to provide a voltage signal to the at least one qubit gate. The control system further includes a control circuit that includes a finite state machine configured to provide at least one control signal to selectively enable at least one of the charge locking circuits in the charge locking circuits and to selectively support providing a voltage signal to a selected one of the charge locking circuits in the charge locking circuits.

Description

BACKGROUND OF THE INVENTION

[0001] Semiconductor-based integrated circuits used in electronic devices such as digital processors include digital circuits based on complementary metal oxide semiconductor (CMOS) technology. An additional method of using processors and related components based on CMOS technology is to use devices based on superconducting logic. Devices based on superconducting logic can also be used to process quantum information, such as qubits. SUMMARY OF THE INVENTION

[0002] In one aspect, the present disclosure relates to a system for controlling qubit gates. The system may include a first packaged device including a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system may also include a second packaged device including a control circuit configured to operate at a cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit includes a plurality of charge locking circuits, where each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnect to at least one qubit gate of the plurality of qubit gates such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

[0003] In another aspect, the present disclosure relates to a method in a system for controlling qubit gates, the system including a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature, and a control circuit configured to operate at a cryogenic temperature, and where the control circuit includes a plurality of charge locking circuits, where each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnect to at least one qubit gate of the plurality of qubit gates such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate, and where each charge locking circuit of the plurality of charge locking circuits includes a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, and where the first voltage amount is greater than the second voltage amount. The method may include operating a first subset of the plurality of charge locking circuits in a capacitive mode such that the voltage signal output to the at least one qubit gate includes a pulse signal having a first controlled amplitude, where the first controlled amplitude depends on the amount of the input voltage signal and each of the first voltage amount and the second voltage amount. The method may also include operating a second subset of the plurality of charge locking circuits in a direct mode such that the voltage signal output to the at least one qubit gate includes a signal having a second controlled amplitude, where the second controlled amplitude depends on the input voltage signal and only one of the first voltage amount or the second voltage amount.

[0004] In yet another aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system can also include a control circuit configured to operate at cryogenic temperatures, where the control circuit includes a plurality of charge locking circuits, where each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnect to at least one qubit gate of the plurality of qubit gates such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate, and where each charge locking circuit of the plurality of charge locking circuits includes an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate, and where the control circuit further includes control logic configured to provide at least one control signal associated with each charge locking circuit of the plurality of charge locking circuits.

[0005] In yet another aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a first packaged device that includes a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system can also include a second packaged device that includes a control system configured to operate at cryogenic temperatures, where the first packaged device is coupled to the second packaged device. The control system can include a plurality of charge locking circuits, where each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnect to at least one qubit gate of the plurality of qubit gates such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate. The control system can also include a control circuit that includes a finite state machine configured to provide at least one control signal to selectively enable at least one charge locking circuit of the plurality of charge locking circuits and to selectively support providing at least one voltage signal to a selected one of the plurality of charge locking circuits.

[0006] In another aspect, the present disclosure relates to a system for controlling qubit gates. The system may include a first encapsulated device including a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system may further include a second encapsulated device including a control system configured to operate at cryogenic temperatures, where the first encapsulated device is coupled to the second encapsulated device. The control system may include a plurality of charge locking circuits, where each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnect to at least one qubit gate of the plurality of qubit gates such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate. The control system may further include a control circuit that includes control logic configured to provide at least one control signal to selectively enable at least one charge locking circuit of the plurality of charge locking circuits.

[0007] In yet another aspect, the present disclosure relates to a system for controlling qubit gates. The system may include a first encapsulated device including a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system may further include a second encapsulated device including a control system configured to operate at cryogenic temperatures, where the first encapsulated device is coupled to the second encapsulated device. The control system may include a plurality of charge locking circuits, where each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnect to at least one qubit gate of the plurality of qubit gates such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate. The control system may further include a digital-to-analog converter for generating at least one voltage signal. The control system may further include a control circuit that includes a finite state machine configured to provide at least one control signal to selectively enable at least one charge locking circuit of the plurality of charge locking circuits and to selectively support providing the at least one voltage signal to a selected one of the plurality of charge locking circuits.

[0008] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is illustrated by way of example and not limited by the accompanying drawings, in which like reference numerals indicate similar elements. Elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0010] Figure 1 A system 100 for controlling qubits according to one example is shown;

[0011] Figure 2 shows a common substrate including a cryogenic CMOS control chip, a qubit chip, and a resonator chip according to an example;

[0012] Figure 3 shows a block diagram of a control system associated with fast control multiplexing according to an example;

[0013] Figure 4 shows a plan view of a cryogenic CMOS control chip including a control system according to an example;

[0014] Figure 5 shows a charge-locked fast gating (CLFG) unit according to an example;

[0015] Figure 6 shows an example waveform 600 associated with the operation of the Figure 5 CLFG unit;

[0016] Figure 7A and Figure 7B shows various blocks associated with a cryogenic CMOS control chip 700 according to an example;

[0017] Figure 8 shows a block diagram of charge locking and fast gating according to an example;

[0018] Figure 9 shows an example of a fast gating circuit;

[0019] Figure 10 shows a finite state machine for controlling the operation of a CLFG unit according to an example;

[0020] Figure 11A and Figure 11B shows an example system that can be used to generate an enable signal as part of an example cryogenic CMOS control chip;

[0021] Figure 12 shows an array of CLFG units according to an example;

[0022] Figure 13 shows an example CLFG unit configured to operate in a capacitive mode according to an example;

[0023] Figure 14 shows an example CLFG unit configured to operate in a dual mode, including a capacitive mode and a direct mode, according to an example;

[0024] Figure 15 shows an example waveform 600 associated with the operation of the Figure 13 and Figure 14Example waveforms associated with signals of the CLFG unit shown;

[0025] Figure 16 Example waveforms associated with the simulation of the CLFG unit in the capacitive mode are shown;

[0026] Figure 17 First and second views of the active region of an example qubit device during a charge locking test are shown;

[0027] Figure 18 A view showing the variation of voltage and current associated with a quantum dot contact (QPC) according to an example is shown;

[0028] Figure 19 Example waveforms corresponding to a cryogenic CMOS control chip during testing of fast gating operations with quantum dots are shown;

[0029] Figure 20 Example readout waveforms corresponding to readout signals through quantum dots during testing of a cryogenic CMOS control chip are shown;

[0030] Figure 21 An FDSOI digital device according to an example is shown;

[0031] Figure 22 An FDSOI analog device according to an example is shown; and

[0032] Figure 23 A flowchart corresponding to a method associated with the system described in the present disclosure is shown. Detailed Description

[0033] Examples described in the present disclosure relate to a cryogenic CMOS interface for controlling qubit gates. Controlling quantum devices requires generating a large number of static and dynamic voltage signals, preferably at low temperatures in close integration with the quantum devices. As used in the present disclosure, the term "(multiple) cryogenic" refers to any temperature equal to or less than 300 Kelvin. This is a significant challenge considering that the cryogenic environment strongly limits the power consumption of any active electronic device. Additionally, a large number of voltage signals also need to be coupled to qubit gates in a quantum computing device. This is because potentially thousands of leads need to be connected to voltage sources to drive qubit gates in a quantum computing device. Also, conventionally, qubits have been controlled using room temperature pulse generators, which must generate large signals that decay in a cryostat. The power required to overcome this decay and the power required to drive the cable impedance are obstacles to scaling quantum computers.

[0034] The examples described in this disclosure relate to cryogenic control circuits and architectures for quantum computing devices. The control architecture includes an integrated circuit control chip that includes cryogenic control circuits tightly integrated with the qubit plane. As an example, the control chip can be wire-bonded or flip-chip mounted to the qubit plane. Additionally, the control chip stores charge on capacitors (including interconnect capacitance) to generate bias voltages. A single digital-to-analog converter can be used to set the charge on each capacitor, and due to the extremely low leakage paths at these temperatures, the capacitors hold their charge for a long time at cryogenic temperatures. The refreshing of the charge can be cycled on a time scale commensurate with qubit operations. By deploying a "charge shuffle" circuit - moving charge between capacitors to generate voltage pulses, the challenges associated with dissipating the generated heat are addressed. Through the tight integration between the cryogenic CMOS control chip and the qubit plane, the capacitance is minimized as much as possible. This tight integration (e.g., via chip stacking packaging methods) can significantly reduce capacitance, thereby affecting the dissipated power.

[0035] In one example, the cryogenic CMOS control chip can be implemented using a fully depleted silicon-on-insulator (FDSOI) process. In one example, a device based on the FDSOI process can include an undoped gate channel, an ultra-thin body, a source, a drain, and an ultra-thin buried oxide (BOX) under the gate and complete dielectric isolation from adjacent devices. The capacitors for charge storage are implemented using on-chip devices. The back-gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address the effects associated with cooling. The control chip includes circuit blocks partitioned into domains that are given a common back-gate bias. Example domains with separate biases include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different back-gate biases are provided for transistors with different aspect ratios.

[0036] The qubit plane can include topological computing gates that can operate at approximately 20 millikelvin (~20 mK). The quantum computing device can process quantum information, such as qubits. Qubits can be implemented using various physical systems, including photons, electrons, Josephson junctions, quantum dots, or heterostructures. (Multiple) quantum states can be encoded as spin direction, another aspect of spin, charge, energy, or the excitation level that is part of the qubit or the topological phase of a superconducting material. Example qubits can operate based on low-frequency DC signals (e.g., bias current) or high-frequency radio frequency signals (e.g., 10 GHz signals) or a combination of both. In certain examples, microwave signals can be used to control superconducting devices, including for example the state of a qubit (quantum bit). Certain implementations of qubit (quantum bit) gates may require high-frequency microwave signals.

[0037] Figure 1Shows a system 100 for controlling qubits according to an example. In this example, system 100 can include multiple energy levels, each of which can be configured to operate at different temperatures. Thus, system 100 can include energy levels 110, 130, and 150. Energy level 110 can include components configured to operate at room temperature (e.g., ambient temperature) or between 4 Kelvin and room temperature. Energy level 130 can include components configured to operate at 300 Kelvin or below 300 Kelvin and up to 4 Kelvin. Energy level 150 can include components configured to operate at 20 millikelvin (mK) or approximately 20 millikelvin (mK). Energy level 110 can include a microcontroller 112 (or microprocessor), a digital-to-analog converter (DAC) 114, a signal generator 116, and a measurement device 118. The microcontroller 112 can generate control signals configured to control the qubits and other aspects of system 100. The DAC 114 can receive digital control signals from the microcontroller 112 (or from other components) and convert these signals to analog form. The analog signals can then be transmitted to other energy levels as needed. As needed, the signal generator 116 can include a microwave signal generator and other clock signal generators. The measurement device 118 can include instruments such as a spectrum analyzer.

[0038] Continuing to refer to Figure 1 , energy level 130 can include components configured to interconnect energy level 110 and energy level 150 in a manner that reduces the thermal load and allows for effective connectivity between components at room temperature and components at 20 millikelvin (mK). Thus, in this example, energy level 130 can include components 132, interconnects 134, 136, and 138. In one example, component 132 can be implemented as a (multi) high electron mobility transistor ((multi) HEMT) low noise amplifier. Interconnects 134, 136, and 138 can be implemented as cables including conductors such as niobium and copper. The conductors can be insulated within the interconnects using a suitable dielectric material such as polyimide.

[0039] Still referring to Figure 1, energy level 150 may include a coupler 152, a readout multiplexer 154, a fast control multiplexer 156, and qubits 160. The coupler 152 may couple signals from a signal generator (such as signal generator 116) to the readout multiplexer 154. The coupler 152 may also direct any reflected signals to component 132. The readout multiplexer 154 and the fast control multiplexer 156 may be implemented on a single control chip (sometimes referred to as a cryogenic control CMOS chip). In one example, the readout multiplexer 154 may be implemented using superconducting materials, such as niobium on an inert substrate (such as sapphire). The readout multiplexer 154 chip may include a plurality of inductance, capacitance, and resistance elements of appropriate sizes to form a resonator bank. At cryogenic temperatures, the resonator circuit exhibits superconductivity and produces resonators with high quality factors. This may provide an effective low-loss frequency multiplexing mechanism. In one example, a cryogenic CMOS control chip (such as an ASIC fabricated using semiconductor technology such as CMOS) may be mounted on the same substrate as the qubits (such as qubits 160) and may be configured to operate at the same cryogenic temperature as the qubits (such as 20 mK).

[0040] Figure 2 A common substrate 200 including a cryogenic CMOS control chip 210, a qubit chip 250, and a resonator chip 280 is shown according to one example. The cryogenic CMOS control chip 210 may be coupled to contact pads (such as contact pads 222 and 224) via wire bonds (such as wire bonds 212 and 214). The cryogenic CMOS control chip 210 may also be coupled to contact pads (such as contact pads 226 and 228) via wire bonds (such as wire bonds 216 and 218). The cryogenic CMOS control chip 210 may also be coupled to other contacts (such as contacts 234 and 236) via wire bonds (such as wire bonds 230 and 232). The qubit chip 250 may be coupled to contact pads (such as contact pads 256 and 258) via wire bonds (such as wire bonds 252 and 254). The qubit chip 250 may be coupled to the resonator chip 280 via wire bonds (such as wire bonds 260 and 262). The resonator chip 280 may be coupled to contacts (such as contacts 290 and 292) via wire bonds (such as wire bonds 282 and 284). Although not shown in Figure 2As shown, but to mitigate unnecessary heating of the quantum device, the chip packaging arrangement may also include thermal management by bonding each chip to a separate gold-plated copper pillar, which is in parallel thermal contact with the mixing chamber level of a dilution refrigerator. While this example shows a tight integration between the control chip and the qubits via wire bonding, other techniques may also be used. As an example, the control chip may be flip-chip bonded to a substrate having qubits. Alternatively, a stacked package, a system-in-package, or other multi-chip assemblies may also be used.

[0041] In this example, the cryogenic CMOS control chip may be implemented in 28nm-FDSOI technology, which is an inherently low-power, low-leakage CMOS platform suitable for cryogenic operation. Transistors in FDSOI may provide the utility of configuring the back-gate bias to counteract the change in threshold voltage with temperature. This example platform provides high (1.8V) and low (1V) voltage cells and also allows separate back-gate control of n-type and p-type transistors or entire circuit blocks, which is a useful aspect in mixed-signal circuit design, such as the example control system.

[0042] Figure 3 A block diagram of a control system 300 associated with a fast control multiplexer 156 according to one example is shown. The control system 300 may be used to control the behavior of a charge lock and fast gating (CLFG) unit 360 incorporated as part of a control chip. The control system 300 may include a serial peripheral interface (SPI) interface 310, a waveform memory 320, a voltage-controlled oscillator (VCO) 330, a clock selection multiplexer (C SEL )340, and a finite state machine 350. As shown, three different voltage levels may be coupled to the unit, including V HOLD 、V HIGH and V LOW . C SEL 340 is used to select the clock signal provided to the finite state machine. Additional details regarding the finite state machine and associated registers are provided later.

[0043] In one example, the control system 300 may be implemented as part of a cryogenic CMOS control chip. Figure 4 A plan view of a cryogenic CMOS control chip 400 according to one example is shown, including a control system 420 (similar to Figure 1control system 300). The cryogenic CMOS control chip 400 may include digital and analog blocks. In this example, the cryogenic CMOS control chip 400 may include a Charge Locking and Fast Gating (CLFG) unit and components corresponding to the control system 420. In this example, the cryogenic CMOS control chip 400 may include logic 410 and the CLFG unit. In one example, the logic 410 may include a series of coupled digital logic circuits that provide the chip's communication, waveform memory, and autonomous operation via two FSMs. The logic 410 may include a control system 420, which may include an oscillator 422, one or more Finite State Machines (FSMs), and an SPI interface (e.g., FSM + SPI interface) 424 and a memory 426. The oscillator 422 may be implemented as a ring oscillator and a frequency divider with a configurable length. Additional details regarding the FSM are provided later. The memory 426 may be configured as a 128-bit register that allows any pulse pattern to be stored. Tiled along the left and bottom edges of the chip may be repeating analog circuit blocks "CLFG" that generate the static and dynamic voltages required to control qubits. The CLFG unit may include cells 432, 434, 436, and 438. In the example described herein, although the CLFG units are implemented on a single die, they are capable of being formed on multiple dies that are packaged together or otherwise interconnected. Although Figure 4 shows a certain floor plan of the cryogenic CMOS control chip 400, which may have different floor plans. Additionally, although Figure 4 shows a certain number of components arranged in a certain manner, the cryogenic CMOS control chip 400 may include additional or fewer components arranged differently.

[0044] Figure 5 shows a CLFG unit 500 according to one example. The CLFG unit 500 may be configured to lock charge and provide a voltage output. Each CLFG unit 500 may correspond to any one of an N number of units. The CLFG unit 500 may include two parts: for coupling a static voltage to an output terminal (labeled GATE <n>) section 510 and for coupling a dynamic voltage (based on voltage V HIGH or voltage V LOW of one of the voltages) to the output terminal. Section 510 of the CLFG unit 500 may include a switch 512, which may operate in response to signal G LOCK,N . This signal may be provided under the control of a suitable finite state machine or another type of control logic or instruction. When the switch 512 is closed, voltage V HOLD may be coupled to one plate of a capacitor labeled C PULSE,N , which represents the on-chip capacitance. Section 550 of the CLFG unit 500 may also include a switch 552 and a switch 554. The CLFG unit 500 may also include an inverter 556. The CLFG unit 500 may be configured such that only one of these switches (switch 552 and switch 554) is closed at a certain time. In this example, the signal labeled GFG,N may control switch 552, and the inverted version of this signal (e.g., inverted by inverter 556) may control switch 554. Thus, at a certain time, voltage V HIGH or voltage V LOW may be coupled to the second plate of a capacitor labeled C PULSE,N , which represents the on-chip capacitance.

[0045] Continuing to refer to Figure 5 , C P may be the sum of the parasitic capacitances due to the wiring in the cryogenic CMOS control chip and the (multiple) qubit chips and the leads (or other interconnections) used to interconnect the two. The unit may first be selected for configuration by an on-chip finite state machine (FSM), which connects an external voltage source to the input terminal of the CLFG unit 500 (labeled IN in Figure 5 ), thereby raising its potential to V HOLD . In this example, a single channel of a room temperature digital-to-analog converter (DAC) may be used as the source, and the FSM sequentially switches each CLFG unit into contact with this bias voltage to power the capacitor and then generate the charge required to lock in a static voltage at the high impedance output. The circuit includes the on-chip capacitance C PULSE and the parasitic capacitance C P , which includes contributions from bond pads, bond leads, and gate interconnections on the qubit chip. After charging, the switch 512 is opened by the FSM (e.g., by withdrawing the G LOCK,N signal), floating the charge on the capacitor and the qubit gate. Even when the CLFG unit 500 is deactivated, this locked charge remains, thereby establishing a static voltage that can be used to configure the offset bias of the qubit device. Although Figure 5 A certain number of components are shown arranged in a certain manner, but the CLFG unit 500 may include additional or fewer components arranged differently.

[0046] Figure 6 An example waveform 600 associated with the operation of the CLFG unit 500 is shown. For dynamic control, voltage pulses are required to rapidly change the gate potential and energy state of the qubit. Generating such pulses remotely from the qubit plane requires a large amount of energy because the generator must drive the cable impedance even if the power is not dissipated at the end of the open line. Alternatively, by redistributing local charges in a circuit with a small capacitance, a relatively large voltage pulse can be generated with very little energy. In this example, this concept is used to implement the dynamic operation of the CLFG unit 500. Under the control of the second FSM, the unit is selected for pulsing, and the pre-loaded pulse pattern stored in the register memory is applied to switch G FG .

[0047] Switches 552 and 554 are controlled in such a way as to toggle the lower plate of capacitor C HIGH between two voltage sources V LOW . These sources can be external to the chip or derived from locally pre-charged capacitors. As the potential of the lower plate of C PULSE switches to V PULSE or V LOW , charge is induced onto the top plate, thereby changing the output voltage V HIGH with respect to the ground reference. OUT .

[0048] In this example, the amplitude of the pulse is given by ΔV PULSE =(C PULSE / (C P +C PULSE ))(V HIGH -V LOW ), and the dissipated power P PULSE is given by the total capacitance, the pulse frequency f, and the voltage of the two levels, P PULSE =((C P *C PULSE ) / (C P +C PULSE ))(V HIGH -V LOW ) 2 f. Since C P and C PULSE are chip-level capacitances (pF), they require very little power to charge.

[0049] Figure 7A and Figure 7B Shows various blocks associated with a cryogenic CMOS control chip 700 according to an example. As previously explained, the cryogenic CMOS control chip 700 can include analog and digital components. In this example, the cryogenic CMOS control chip can include an analog-to-digital converter (ADC) buffer 702, an ADC 704, an ADC SRAM 706, and an ADC control 708. The cryogenic CMOS control chip 700 can also include a clock driver 710, a waveform generator 720, and a reference and bias generator 722. These components can be coupled via various buses. Each bus can include at least one signal line. As Figure 7A and Figure 7B shown, the cryogenic CMOS control chip 700 can receive various external signals, including clock signals, various voltages, and control signals. As shown, some clocks are generated and received externally via pins associated with the control chip.

[0050] Continuing to refer to Figure 7A , the cryogenic CMOS control chip 700 can also include a main control and register 730 and various miscellaneous blocks 740. The main control and register 730 can include a serial peripheral interface (SPI), which can allow communication with an external processor. The miscellaneous blocks 740 can include a sample and hold (S&H) block 742, a comparator 744, and a radio frequency (RF) multiplexer (MUX) 746. The RF MUX 746 can allow selection between two radio frequency signals (RFIN1 and RFIN2). In this example, there is an advanced peripheral block clock (APBCLK) input for the main control and register 730 and a separate APBCLK input pin for the charge lock and fast gating block 750. As Figure 7B shown, for the charge lock and fast gating 750, it is also possible to switch to a local oscillator (e.g., VCO 754). The local oscillator can also be divided down by a configuration register. The SPI clock (SCLK) comes from the SPI host. In this example, there is a clock ratio requirement between the APBCLK and the SCLK from the SPI host. In one example, APBCLK must >= 4 * SCLK. To ensure correct timing, clock domain crossing (CDC) logic is arranged between the SCLK and the APBCLK, and another CDC logic is arranged between the APBCLK and the divided oscillator clock.

[0051] Figure 7B A diagram showing some aspects of charge locking and fast gating 750. Charge locking and fast gating 750 may include a main control and register 752, a voltage controlled oscillator (VCO) 754, and a CLFG cell array 760. The control and register 752 may include an SPI interface. The control and register 752 may include a register read / write block, which may in turn be coupled to a register bank. The VCO 754 may be configured to provide another clock signal for use with some aspects of charge locking and fast gating 750. The CLFG cell array 760 may include CLFG cells 762 and 764, each of which may be similar to Figure 5 the CLFG cell 500.

[0052] Figure 8 A block diagram showing charge locking and fast gating (CLFG) 800 according to one example. CLFG 800 may include an SPI interface 810, coupled via a bus (e.g., APB) to a register read / write interface 820, which in turn may be coupled to a register 830 (e.g., the register may be included as part of a register bank). CLFG 800 may also include a finite state machine 840, which may be configured to receive inputs from the register and provide output signals to a CLFG cell array 880, which in turn may provide voltages to qubits. CLFG 800 may also include an oscillator 850, a frequency divider (FDIV) 860, and a multiplexer 870. The multiplexer 870 may receive the APB clock as one input, and the frequency divider output as another input. Thus, in this example, the finite state machine is able to copy the APBCLK or a clock signal from a local oscillator. A clock control module may be used to divide down the local oscillator clock by an integer value from 1 to 255, and the multiplexer 870 may be used to allow switching between the APBCLK and the divided oscillator clock. The divided clock has no duty cycle requirement. The clock output of the clock control module is referred to as XCLK, and it is used to time the finite state machine.

[0053] Table 1 below lists some signals of the cryogenic CMOS control chip and their descriptions.

[0054]

[0055] Table 1

[0056] Table 2 lists some registers associated with the cryogenic CMOS control chip. Since the descriptions of most registers are self-explanatory, only some registers and their functionality are described to explain the operation of the cryogenic CMOS control chip.

[0057]

[0058]

[0059]

[0060]

[0061]

[0062]

[0063] Table 2

[0064] Although Table 2 shows certain registers and their arrangements, additional or fewer registers may be used. Additionally, the information presented in the table may be conveyed to the cryogenic CMOS control chip via modalities other than registers. As an example, special instructions may be used to encode the information included in the registers. The architecture enabled by the registers described in Table 2 assumes 32 charge-locked fast gating (CLFG) units. In this example, each CLFG unit can be independently DC charged and can perform fast pulsing according to the waveform stored in the FGSR register. In this implementation, 128 bits can be stored in four 32-bit registers (e.g., registers FGSR0-3), and any charge-locked fast gating unit can perform fast pulsing according to the bit patterns stored in these registers. The bit patterns can be continuously repeated or played once under the control of the FSM. This implementation is suitable for two-level pulses, however it can be extended to multi-level pulses. In this example architecture, the REG_CTL1 register described in Table 2 includes information used by the initiated finite state machine to initiate and complete unit charging. As an example, bit 8 of this register controls when the counter for FGSR selection is enabled and increments at each clock cycle of the XCLK clock until it reaches 127, then the counter flips. As another example, bits 4 and 5 of the REG_CTL1 register control whether a complete DC charge sequence occurs for all 32 units, or whether a selective DC charge sequence occurs only on a subset of the 32 units.

[0065] Figure 9 An example of the fast gating circuit 900 is shown. As described earlier, as part of Table 2, four 32-bit registers can control the output of the fast gating circuit 900. The fast gating circuit 900 may include a counter 910, a multiplexer 920, which may be coupled to receive the output of the counter 910 as one input and receive the value corresponding to register REG_CTL<3> as another input. The fast gating circuit 910 may also include an AND gate 930, a multiplexer 940, and a gate 950, which may be as Figure 9 shown to be coupled to each other. These logic elements may also receive Figure 9 the signals shown. The counter 910 selects bit positions of a 128-bit value for output on the CL_FG terminal. In this example, this is a 128-to-1 multiplexer. Each clock cycle (e.g., corresponding to Figure 9 the clock XCLK shown), the counter 910 is incremented by 1. The counter 910 wraps around to 0 and continues counting. The value of the bit stored in REG_CTL[8] enables the counter 910. Thus, in this example, when REG_CTL[8] = 0, the counter remains at 0 and is not incremented. If the charge lock state machine is not idle, then the fast gate output CL_FG is 0. In this case, as long as REG_CTL[8] = 1, the counter continues to increment.

[0066] Continuing to refer to Figure 9 , in one example, the programming sequence to update the 128-bit FGSR and initiate a new fast gate sequence is as follows: (1) Clear REG_CTL1[8] to hold the counter at 0, or set REG_CTL1[1] to stop XCLK, (2) Write new values to four 32-bit FGSR registers, and (3) Set REG_CTL1[8] to allow the counter to increment, or clear REG_CTL1[1] to resume XCLK. In one example, the FG output can also be overridden. When REG_CTL1[2] = 1, the CL_FG output is equal to REG_CTL1[3]. Although Figure 9 the fast gate circuit 900 is shown with a certain number of components arranged in a certain manner, the fast gate circuit 900 may include additional or fewer components arranged differently. Additionally, other signals may be used to provide additional or fewer controls.

[0067] Figure 10 Shows a finite state machine 1000 according to an example. In this example, the finite state machine 1000 includes two finite state machines: FSM A and FSM B. Each finite state machine in the finite state machine is configured for DC charging of the CLFG unit (such as the CLFG unit 500). FSM A corresponds to the finite state machine that is configured to charge only those CLFG units enabled according to the bits in the CL_EN register simultaneously. FSM B corresponds to the finite state machine that is configured to charge all the CLFG units in the CLFG array (such as all 32 units in a CLFG array with 32 units) sequentially. In this example, the bit values stored in the register (such as the 4th and 5th bits of the 32-bit register REG_CTL1 corresponding to the field BEGIN_CHRG described in Table 2) determine which of the two finite state machines is active. In this example, when the BEGIN_CHRG field transitions from 00 to 01, FSM A is started; alternatively, when the BEGIN_CHRG field transitions from 00 to 10, FSM B is started. The output signals from FSM A and FSM B are provided as the CHRG signal, which is coupled to one of the inputs of the multiplexer 1002. The other inputs of the multiplexer 1002 include the bit value stored in REG_CTL<6> (described in Table 2). The output of the multiplexer 1002 is the global DC charge signal and is labeled as CL_CHRG. The value of the 7th bit (such as REG_CTL<7>) determines whether the outputs of FSM A and FSM B are provided as the DC charge signal, or whether the DC charge signal is user-selected as the value of the 6th bit of the REG_CTL register described in Table 2.

[0068] Continuing to refer to Figure 10 , at startup, FSM A starts from the IdleA0 state and transitions to the countdown A state. As part of this transition, FSM A maintains the CHRG signal and starts counting down to perform DC charging on the enabled CLFG units. During the entire operation of FSM A, the CL_EN value remains the same as previously specified by the user. In this example, when the local enable signal of a specific CLFG unit is high (such as CL_EN When i = 1, the i-th CLFG unit is enabled. Thus, by gating the CHRG signal, the local enable signal ensures that the CLFG unit is charged only when it is capable of being charged. After charging is complete, FSM A enters the idle state IdleA1. Table 3 below shows the Figure 10 example correspondence between the transitions / states referenced in

[0069]

[0070] Table 3

[0071] Still referring to Figure 10 , at startup, FSM B enters the START_CHRG state, and assuming there are 32 CLFG units, when the CL_EN<32> bit is set to 1 and each of the other enable bits is set to 0, charging of the 32nd CLFG unit begins. As part of this process, FSM B enters the countdown B state and counts down the clock cycles (e.g., DCSR clock cycles) required for sequential charging of the CLFG units. Except in the START_CHRG and countdown B states, the CL_EN value remains the same as previously specified by the user throughout the operation of FSM B. When the CL_EN<31> bit is set to 1 and the remaining enable bits are set to 0, the DC charging of the 32nd CLFG unit is complete and the DC charging of the 31st CLFG unit begins. In this example, these steps are repeated until all 32 CLFG cells are charged. Then, FSM B transitions to the idle state (e.g., the IdleB1 state). Table 4 below shows the Figure 10 example correspondence between the transitions / states referenced in

[0072]

[0073] Table 4

[0074] Although Figure 10 shows a specific finite state machine operating in a certain way, other state machines can also be used. Although Tables 3 and 4 refer to the specific bits and signals and their corresponding values of two finite state machines, other bits and signals and their corresponding values can also be used. Additionally, the functionality associated with the state machine can be implemented using other logic or instructions.

[0075] Figure 11A and Figure 11B Illustrates an example system 1100 that can be used to generate an enable signal as part of an example cryogenic CMOS control chip. The previously described FSM can be used to interface with system 1100, which can be used to generate an enable signal that is used to select charged CLFG cells. This example also assumes that there are 1024 CLFG cells (arranged in a grid including 32 rows and 32 columns) that need to be controlled. System 1100 can include a host logic and clock section 1110, a row decoder 1120, and a column decoder 1130. The host logic and clock section 1110 can include circuitry and logic configured to store and interpret instructions or commands in a manner similar to a memory controller. The row decoder 1120 can be configured to receive a row address from the host logic and clock section 1110 and maintain one or more signals labeled R0 to R 31 and the column decoder 1130 can be configured to receive a column address from the host logic and clock section 1110 and maintain one or more signals labeled C0 to C 31 and D0 to D 31 .

[0076] Now referring to Figure 11B , system 1100 can also include a bus system to couple the signals generated by the row decoder 1120 and the column decoder 1130 to circuitry 1140. Circuitry 1140 can be configured to generate a signal labeled OUT I,FG at its output terminals. This signal can be coupled to qubit gate 1160. Circuitry 1140 is an example implementation of the "direct mode" similar to the previously described CLFG cells. Thus, in this example, when the corresponding row (R J ) signal and the corresponding column (C I ) signal are high respectively and the drive line (D) signal is high or low, circuitry 1160 can be connected to voltage bus V LFG or V HFG . Circuitry 1140 can also be implemented as an array of CLFG cells (such as shown and previously described in Figure 5 ). Although FIG. 11 shows system 1100 as having certain components arranged in a certain manner, there can be more or fewer components with different arrangements.

[0077] Figure 12 Shows a CLFG cell array 1200 according to an example. As an example, the CLFG cell array 1200 may correspond to the CLFG cell array 760 of FIG. 7 and may be included as part of a cryogenic CMOS control chip. In this example, the CLFG cell array 1200 may include 32 CLFG cells (e.g., CLFG cells 1210, 1220, 1230, 1240, and 1250). Each of these CLFG cells may be configured to generate one of the OUTCL signals, and the OUTCL signal may be used to provide control or other types of voltages to qubits. Each CLFG cell may receive signals labeled CL_FG, CL_CHRG, VICL, VHFG, and VLFG. These signals will be described in more detail with respect to Figure 13 and Figure 14 . Additionally, some of these signals have also been described earlier as part of the description associated with the cryogenic CMOS control chip. Each CLFG cell may also receive enable signals (e.g., CL_EN<0>, CL_EN<1>, CL_EN<2>, CL_EN<30>, or CL_EN<31>, as shown in Figure 12 ). The enable signals may allow for selective or sequential DC charging, as explained earlier with respect to the finite state machine description in Figure 10 . Figure 12 Each of the CLFG cells shown in Figure 12 may also include electrostatic discharge (ESD) circuitry, including ESD circuits 1212, 1222, 1232, 1242, and 1252. The CLFG cells may operate in either a capacitive mode or a dual mode, including a capacitive mode and a direct mode. As an example, the CLFG cell array 1200 may consist of 32 CLFG cells - 16 CLFG cells are configured to operate in the capacitive mode, and 16 CLFG cells are configured to operate in the direct mode. In one example, half of each type of CLFG cell may also contain custom analog pads with reduced ESD protection to further minimize leakage through the standard pad structure. Although Figure 12 shows the CLFG cell array 1200 as having certain components arranged in a certain way, there can be more or fewer components with different arrangements.

[0078] Figure 13 Shows an example of a CLFG cell 1300 configured to operate in the capacitive mode. Unless otherwise indicated, the signals referenced in Figure 13 have the same meaning as described earlier with respect to Figures 5 to 7B as well as Tables 1 and 2. The CLFG cell 1300 operates in the same manner as Figure 5 configured in a manner similar to the CLFG unit 500. The CLFG unit 1300 is configured to lock charges and provide a voltage output at an output terminal (OUT) associated with the CLFG unit. Each CLFG unit 1300 can correspond to any one of N number of units. The dynamic voltage (based on one of the voltages received via the VHFG terminal (referred to as V Figure 5 in HIGH ) or via the VLFG terminal (referred to as V Figure 5 in LOW )) can be coupled to the output terminal. The CLFG unit 1300 can include circuitry that can respond to the signal CL_EN <n>A switch 1312 that operates based on a signal. The signal can be provided under the control of a suitable finite state machine or another type of control logic, as described with respect to Figure 10 . When the switch 1312 is closed, the voltage received via the input terminal (IN) on the signal line VICL (referred to as V Figure 5 in HOLD ) can be coupled to one plate of a capacitor labeled C PULSE,N , which represents the on-chip capacitance. The CLFG unit 1300 may further include a switch 1314 and a switch 1316. The CLFG unit 1300 may further include an inverter 1318. The CLFG unit 1300 may be configured such that only one of these switches is closed at a certain time. In this example, the one labeled CL_EN <n>The signal can control switch 1314, and the inverted version of this signal (e.g., inverted by inverter 1318) can control switch 1316. Thus, at a certain time, voltage V HIGH or voltage V LOW can be coupled to the second plate of the capacitor labeled C PULSE,N , which represents the on-chip capacitance. The CLFG unit 1300 may also include an ESD 1320 coupled to the output terminal (OUT). The CLFG unit 1300 operates only in the capacitive mode because the output voltage supplied to the qubit gate is provided via the Figure 13 shown capacitive arrangement. Although Figure 13 shows a certain number of components arranged in a certain way, the CLFG unit 1300 may include additional or fewer components arranged differently. As an example, the CLFG unit 1300 may not include the ESD 1320.

[0079] Figure 14 shows an example of a CLFG unit 1400 configured to operate in a dual mode (including capacitive mode and direct mode). Unless otherwise indicated, the signals referred to in Figure 14 have the same meaning as described earlier with respect to Figures 5 to 7B and Tables 1 and 2. The CLFG unit 1400 is configured to lock charge and provide a voltage output at the output terminal (OUT) associated with the CLFG unit. Each CLFG unit 1400 may correspond to any one of an N number of units. In the capacitive mode (enabled by maintaining the signal labeled CL_MODE via switch 1414), a dynamic voltage (based on one of the voltages received via the VHFG terminal (referred to as V Figure 5 in HIGH ) or via the VLFG terminal (referred to as V Figure 5 in LOW )) can be coupled to the output terminal. The CLFG unit 1400 may include components that can respond to CL_EN <n>A switch 1416 that operates based on a signal. This signal can be provided under the control of a suitable finite state machine or another type of control logic, as described with respect to Figure 10 . When the switch 1416 is closed, the voltage received via the input terminal (IN) on the signal line VICL (referred to as V Figure 5 in HOLD ) can be coupled to one plate of a capacitor labeled C PULSE,N , which represents the on-chip capacitance. The CLFG unit 1400 may also include the switch 1416 and the switch 1418. The CLFG unit 1400 may also include an inverter 1420. The CLFG unit 1400 can be configured such that only one of these switches (1416 and 1418) is closed at a given time. In this example, the one labeled CL_EN <n>The signal can control switch 1416, and the inverted version of this signal (e.g., inverted by inverter 1420) can control switch 1418. Thus, at a certain time, voltage V HIGH or voltage V LOW can be coupled to the second plate of the capacitor labeled C PULSE,N via one of the two switches, which represents the on-chip capacitance. When the CL_MODE signal is maintained, the CLFG unit 1400 operates in capacitive mode because the output voltage supplied to the qubit gate is provided via the Figure 14 shown capacitive arrangement.

[0080] Continuing to refer to Figure 14 , when the CL_MODE signal is revoked, the CLFG unit 1400 can operate in direct mode. Thus, when the CL_MODE signal is revoked, switch 1434 closes and depends on CL_EN <n>For the state of the signal, switch 1436 or switch 1438 is closed. Thus, at some time, voltage V HIGH or voltage V LOW can be coupled to the same terminal via one of the two switches, and V IN voltage is coupled to this terminal via the input terminal (IN). The CLFG unit 1400 may also include an ESD 1450 coupled to the output terminal (OUT). Although Figure 14 a certain number of components are shown arranged in a certain manner, the CLFG unit 1400 may include additional or fewer components arranged differently. As an example, the CLFG unit 1400 may not include the ESD 1450.

[0081] In the case of the CLFG unit 1300 and the CLFG unit 1400, once the capacitors are charged, the low leakage in the low-temperature environment ensures that they need to be refreshed less frequently. Each CLFG unit in the CLFG unit can receive voltage from a single DAC. Using a technique similar to that of a rasterized display, a single DAC voltage can be used to charge all CLFG units (such as the 32 CLFG units in the example described earlier). Thus, in this example, the DAC voltage is provided to the capacitor by closing the switch in the path between the DAC voltage line and the capacitor; after the capacitor is charged, the switch is opened, and the DAC voltage is used to charge the next capacitor in a cyclic manner. By using a shared DAC, the number of input / output lines between the control chip (including the CLFG unit array) and the room-temperature electronics is significantly reduced. As described earlier, the interconnection between the low-temperature CMOS control chip and the qubit plane is formed using wire bonding, flip-chip bonding, or other low-impedance interconnection techniques.

[0082] Figure 15 An example waveform 1500 associated with the signals of the CLFG unit 1300 and the CLFG unit 1400 is shown. In this example, each CLFG unit in the CLFG unit 1300 and the CLFG unit 1400 is shown operating with respect to a clock labeled XCLK. The CL_CHRG signal is maintained for a period of time based on a clock cycle (or another metric) specified in a control register (such as REG_DCSR) associated with the low-temperature CMOS control chip. The CL_FG control signal is used for charge shuffling. For the CLFG unit 1300 and the CLFG unit 1400, whenever this control signal is high, the voltage at the OUTCL terminal is at VICL + V HIGH voltage and V LOW Pulses are made between the differences in voltage. Whenever the CL_FG control signal is low, both the CLFG unit 1300 and the CLFG unit 1400 operate in the DC mode, such that the output voltage (represented by the waveform labeled OUTCL in the DC mode) is held at the voltage to which the capacitor was initially charged (e.g., via the CL_CHRG signal), and it may dissipate over time without being refreshed. The waveform labeled OUTCL in the capacitive mode shows the output signal of the CLFG unit 1300. This same waveform also shows the output of the CLFG unit 1400 when operating in the capacitive mode. The waveform labeled OUTCL in the direct mode shows the output signal of the CLFG unit 1400 when operating in the direct mode. Each of these modes was earlier explained with respect to Figure 13 and 14 Explained.

[0083] Continuing to refer to Figure 15 , the fast gating operation cycle using the CLFG 1400 in the capacitive mode includes a DC charge of the storage capacitor, followed by a series of pulses. In one example, the DC charge period is determined by the REG_DCSR value. The period and number of the pulses are determined by the content of the CL_FGSR register (explained earlier) which is set to 128 bits. In this example, the content of this register is read one bit at a time (e.g., by a waveform generator) and applied as a control signal labeled: CL_FG. When using the direct drive mode, the fast gating consists of a series of pulses where the output is directly connected to VLFG or VHFG. In the direct drive mode, the charge cycle still exists and its behavior is the same as a "0" value on the CL_FGSR. Each of these modes was earlier explained with respect to Figure 13 and 14 Explained.

[0084] Figure 16 Shows an example waveform 1600 associated with the simulation of the CLFG unit 1400 in the capacitive mode. The waveform labeled OUTCL represents the simulated output signal of the CLFG unit 1400 when operating in the capacitive mode. The waveform labeled CL_EN corresponds to the enable signal which is used to enable the CLFG unit for charging. The CL_CHRG signal is used to charge the capacitor (or capacitors) associated with the CLFG unit. As explained earlier, the CL_CHRG signal is maintained over a period of time based on the clock period (or another metric) specified in a control register (e.g., REG_DCSR) associated with the cryogenic CMOS control chip. For the CLFG unit 1400, whenever the CL_FG control signal is high, the voltage at the OUTCL terminal is at VICL + V HIGH Voltage and V LOW Pulses are performed between the differences in voltage. The VICL voltage corresponds to the voltage at the input terminal of the CLFG unit, which can be received from the DAC (as explained earlier). V HIGH The voltage is received via the VHFG terminal, and the waveform is also labeled as VHFG in Figure 16 . The V LOW voltage is received via the VLFG terminal, and the waveform is also labeled as VLFG in Figure 16 .

[0085] Continuing to refer to Figure 16 , part 1602 of the OUTCL waveform shows the locking of the DC voltage (e.g., 1.8 volts) in the CLFG unit. Part 1604 of the OUTCL waveform shows the fast gating of the voltage to generate pulses that can be used as control signals for qubits. Part 1606 shows the locked DC voltage restored after pulse generation. Part 1608 shows the voltage at the OUTCL terminal when the locked DC voltage is not refreshed or restored. Part 1610 shows the locking of a DC voltage level different from the voltage level locked in part 1602 (e.g., 0.6 volts). Part 1612 shows the fast gating of the voltage to generate pulses with different amplitudes, which can also be used to control qubits or other such devices. Although Figure 16 the OUTCL waveform is shown as having rectangular pulses, the pulses can have different shapes. Although Figure 16 the OUTCL waveform is shown as having two different amplitudes, there can be other variations in the amplitude of the OUTCL waveform. Similarly, the pulse frequency of the OUTCL waveform can also be controlled via the cryogenic CMOS control chip described earlier. Additionally, the OUTCL waveform can be used to modulate high-frequency signals, such as microwave tones, to generate control signals for qubit gates or another type of qubit device.

[0086] Figure 17 Shows a first view 1710 and a second view 1750 of the active region of an example qubit device 1700 during a charge locking test. The qubit device 1700 can be a gallium arsenide (GaAs)-based quantum dot device. In this example, as shown in view 1710 and view 1750, multiple signals can be used to control the quantum dot. The cryogenic CMOS control chip described earlier can be used to generate any control signals using the capacitive mode or the direct mode associated with the CLFG unit described earlier. The signals used to control the qubit can include a left wall (LW) signal, a left plunger (LP) signal, a center wall (CW) signal, a right plunger (RP) signal, and a right wall (RW signal). Additional signals related to the quantum dot 1730 in the sense qubit gate can include a sense point top gate (SD T ), a sense point plunger (SD P ) and a bottom gate of the sensing point (SD B ). In this example, as shown in view 1710, the potentials of the control signals LW, LP, CW, RP, and RW can be locked using five CLFG units based on a programmed finite state machine. Although Figure 17 qubit device 1700 with certain control signals is shown, other types of qubit devices with other control signals can also withstand the voltages generated by the previously described cryogenic CMOS control chip.

[0087] Figure 18 View 1800 showing the variations of voltage and current associated with a quantum dot contact (QPC) according to an example is shown. Graph 1810 shows the variation of the QPC current over time. Graph 1820 shows the variation of the QPC current as a function of the left wall voltage change. Graph 1830 shows the variation of the hold voltage of the cryogenic CMOS control chip over time.

[0088] Figure 19 Example waveform 1900 corresponding to the cryogenic CMOS control chip during the test of fast gating operation with a quantum dot is shown. Example waveform 1910 corresponds to the readout signal when the fast gating is performed at 140 KHz. Example waveform 1920 corresponds to the readout signal when the fast gating is performed at 1.26 MHz. Example waveform 1930 corresponds to the readout signal when the fast gating is performed at 2.45 MHz. The frequency can be changed using a frequency divider. The waveforms do not share a common time scale. Although Figure 19 a specific duty cycle and amplitude of the voltage pulse associated with the waveform are shown, the duty cycle and amplitude can be changed by the cryogenic CMOS control chip. This advantageously eliminates the need to control qubit gates from room temperature devices.

[0089] Controlling qubits from room temperature would require attenuating voltage pulses generated at room temperature, resulting in the need to dissipate a large amount of heat from the room temperature voltage pulses. Additionally, a voltage signal from room temperature is not required to handle the load of a one-meter-long (or longer) cable (e.g., a 50-ohm transmission line with a capacitive load greater than 200 pF), and the cryogenic CMOS control chip only needs to handle the capacitance of the flip-chip bond and the very short interconnect between the control chip and the qubit gates. This capacitance can be as low as 0.1 pF. This allows the cryogenic CMOS control chip to control the states of thousands of qubits without significant heat dissipation. Additionally, the power consumption from fast gating is very small, so it allows the control chip to effectively manage potentially thousands of qubits. In terms of the power requirements for controlling qubits, in one example, assuming the readout clock frequency is set to 1 MHz and the qubit interconnect has a capacitance of 1 pF, the power consumption for every 1000 qubit gates for a 0.1-volt pulse is 10 μW. Assuming 10 gates per qubit, 1 mW of power can be used to control 10,000 qubits at a 1 MHz clock frequency or 1000 qubits at a 10 MHz clock frequency.

[0090] Figure 20 An example readout waveform 2000 corresponding to the readout signal through the quantum dot during testing of the cryogenic CMOS control chip is shown. When the CLFG unit voltages V HIGH and V LOW are used to generate pulses for controlling the quantum dot and the voltage on the sense-dot plunger (SD P ) gate is scanned, the waveform 2000 is generated. Waveform 2010 shows the variation of the V HIGH voltage, and waveform 2020 shows the variation of the V LOW voltage. Waveform 2030 shows the pulse applied to the CLFG unit.

[0091] As described earlier, in one example, the cryogenic CMOS control chip can be implemented using a fully depleted silicon-on-insulator (FDSOI) process. In one example, a device based on the FDSOI process can include an undoped gate channel, an ultra-thin body, a source, a drain, and an ultra-thin buried oxide (BOX) under the gate, as well as complete dielectric isolation from adjacent devices. As described earlier, a device based on the FDSOI process can include digital and analog devices (e.g., transistors or other devices). Figure 21 Shows an FDSOI digital device 2100 according to an example. The FDSOI digital device 2100 may include a substrate 2102. In this example, the substrate 2102 may be a silicon-on-insulator (SOI) substrate. By doping the substrate with an n-type dopant, a deep n-well 2104 may be formed in the substrate 2102. Additional wells may be formed in the substrate 2102 and the deep n-well 2104. As an example, a p-well 2106 and an n-well 2108 may be formed. Next, using multiple lithography steps, transistor devices 2120 and transistor devices 2130 may be formed. In this example, the transistor device 2120 is a p-type transistor having a gate channel 2122 formed above a block 2126. The transistor device 2120 may also include p+-type source / drain regions and contacts S and D to the source / drain. In this example, the transistor device 2130 is an n-type transistor having a gate channel 2132 formed above a block 2136. The transistor device 2130 may also include n+-type source / drain regions and contacts S and D to the source / drain. Capacitors for charge storage are implemented using such transistor devices. Various types of devices and regions may be isolated using shallow trench isolation (STI) regions, which are formed using a dielectric. Example STI regions formed in the FDSOI digital device 2100 include STI 2150, STI 2152, STI 2154, STI 2156, STI 2158, and STI 2160.

[0092] Continuing to refer to Figure 21 , the back gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address effects associated with cooling. Thus, in this example, the FDSOI digital device 2100 includes a back gate bias for n-type devices via an N BG terminal and a back gate bias for p-type devices via a P BG terminal. In this example, although the FDSOI digital device 2100 includes the ability to vary the back gate bias of n-type and p-type devices, the back gate voltage of the n-type devices is not allowed to be lower than the back gate voltage of the p-type devices.

[0093] Still referring to Figure 21 , the backgate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address the effects associated with cooling of the chip in a low-temperature environment. The transistor devices and associated control circuitry are designed such that, using backgate bias control, the threshold voltage of the transistor devices can be tuned despite large variations in the operating temperature of the transistor devices. The low-temperature CMOS control chip can include circuit blocks partitioned into domains that are given a common backgate bias. Example domains with separate biases include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different backgate biases are provided for transistors with different aspect ratios. Although Figure 21 shows a FDSOI digital device 2100 including a certain number and type of wells, the FDSOI digital device 2100 can include additional or fewer other types of wells. Additionally, the transistor devices can be planar or non-planar (e.g., FinFET devices).

[0094] Figure 22 shows a FDSOI analog device 2200 according to one example. Different from the FDSOI digital device 2100, the FDSOI analog device 2200 includes independent backgate bias control, where the backgate voltage of the p-type device can be raised to a voltage V DD above, independent of the backgate voltage of the n-type transistor. The FDSOI analog device 2200 can include a substrate 2202. In this example, the substrate 2202 can be a silicon-on-insulator (SOI) substrate. By doping the substrate with an n-type dopant, a deep n-well 2204 can be formed in the substrate 2202. A p-well 2206 can be formed in the deep n-well 2204, and an n-well 2208 can be formed in the substrate 2202. Next, using multiple lithography steps, transistor devices 2220 and transistor devices 2230 can be formed. In this example, the transistor device 2220 is a p-type transistor with a gate channel 2222 formed above a block 2226. The transistor device 2220 can also include p+-type source / drain regions and contacts S and D to the source / drain. In this example, the transistor device 2230 is an n-type transistor with a gate channel 2232 formed above a block 2236. The transistor device 2230 can also include n+-type source / drain regions and contacts S and D to the source / drain. Various types of devices and regions can be isolated using shallow trench isolation (STI) regions, which are formed using a dielectric. Example STI regions formed in the FDSOI analog device 2200 include STI 2250, STI 2252, STI 2254, STI 2256, STI 2258, STI2260, STI 2262, and STI 2164.

[0095] Continuing to refer to Figure 22 , the back-gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address the effects associated with cooling. Thus, in this example, the FDSOI analog device 2200 includes a back-gate bias for n-type devices via the N BG terminal and a back-gate bias for p-type devices via the P BG terminal. In this example, unlike the FDSOI digital device 2100, the FDSOI analog device 2200 includes independent back-gate bias control, where the back-gate voltage of the p-type device can be raised to a voltage V DD or higher, independent of the back-gate voltage of the n-type device.

[0096] Still referring to Figure 22 , the back-gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address the effects associated with the cooling of the chip in a low-temperature environment. The transistor device and associated control circuitry are designed such that, using back-gate bias control, the threshold voltage of the transistor device can be tuned despite large variations in the operating temperature of the transistor device. In some examples, different back-gate biases are provided for transistors having different aspect ratios. Although Figure 22 the FDSOI analog device 2200 is shown including a certain number and type of wells, the FDSOI analog device 2200 may include additional or fewer other types of wells. Additionally, the transistor device can be planar or non-planar (e.g., a FinFET device).

[0097] In one example low-temperature CMOS control chip, the FDSOI digital device 2100 can be used as part of a circuit block that only requires the difference between a low value and a high value of voltage and does not involve intermediate values. Since the FDSOI digital device 2100 occupies less area than the FDSOI analog device 2200, it is advantageous to use it for most circuits as long as they are not too sensitive. In one example, only the FDSOI analog device 2200 is fabricated such that there is independent back-gate bias control for n-type and p-type devices and independent back-gate bias control based on the aspect ratio of these devices. As described earlier, the low-temperature CMOS control chip can be partitioned into domains such that each domain includes multiple transistor devices but shares a common back-gate bias. In one example, there may be eight domains based on the combination of n-type and p-type devices and the different aspect ratios associated with each type of device.

[0098] Figure 23 FIG. 2300 is a flow chart showing a method corresponding to a system described in the present disclosure. In one example, a system for controlling a qubit gate may include a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. As an example, the quantum device may correspond to Figure 1 qubit 160. The system may also include control circuitry configured to operate at cryogenic temperatures, and where the control circuitry includes a plurality of charge locking circuits. As an example, the control circuitry may correspond to the circuitry included in the cryogenic CMOS control chip described earlier. Each of the plurality of charge locking circuits may be coupled via an interconnect to at least one of the plurality of qubit gates such that each of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate, where each of the plurality of charge locking circuits includes a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, where the first voltage amount is greater than the second voltage amount. As an example, the charge locking circuit may be included as part of CLFG unit 360. Each charge locking circuit may correspond to any one of the CLFG unit 500, CLFG unit 1300, or CLFG unit 1400 described earlier.

[0099] Step 2310 may include operating a first subset of the plurality of charge locking circuits in a capacitive mode such that the voltage signal output to the at least one qubit gate includes a pulse signal having a first controlled amplitude, where the first controlled amplitude depends on the amount of the input voltage signal and each of the first voltage amount and the second voltage amount. In one example, this step may be related to the operation of CLFG unit 1300. As described earlier, CLFG unit 1300 may include circuitry that may respond to CL_EN <n>A switch 1312 that operates based on a signal. The signal can be provided under the control of a suitable finite state machine or another type of logic, as described with respect to Figure 10 . When the switch 1312 is closed, the voltage received via the input terminal (IN) on the signal line VICL (referred to as V Figure 5 in HOLD ) can be coupled to one plate of a capacitor labeled C PULSE,N , which represents the on-chip capacitance. The CLFG unit 1300 may also include a switch 1314 and a switch 1316. The CLFG unit 1300 may also include an inverter 1318. The CLFG unit 1300 may be configured such that only one of these switches is closed at a given time. In this example, the one labeled CL_EN <n>The signal can control switch 1314, and an inverted version of the signal (e.g., inverted by inverter 1318) can control switch 1316. Thus, at a certain time, voltage V HIGH or voltage V LOW can be coupled to the second plate of the capacitor labeled C PULSE,N via one of the two switches, which represents the on-chip capacitance.

[0100] Step 2320 can include operating a second subset of the plurality of charge lock circuits in direct mode such that the voltage signal output to at least one qubit gate includes a signal having a second controlled amplitude, where the second controlled amplitude depends on the input voltage signal and only one of a first voltage quantity or a second voltage quantity. In one example, this step can be related to the operation of the CLFG unit 1400. As described earlier, when the CL_MODE signal is deasserted, the CLFG unit 1400 can operate in direct mode. Thus, when the CL_MODE signal is deasserted, switch 1434 closes and depends on CL_EN <n>Depending on the state of the signal, switch 1436 or switch 1438 is closed. Thus, at some time, voltage V HIGH or voltage V LOW can be coupled to the same terminal via one of the two switches, and V IN voltage is coupled to this terminal via the input terminal (IN).

[0101] In summary, in one aspect, the present disclosure relates to a system for controlling qubit gates. The system may include a first encapsulated device including a quantum device that includes a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system may also include a second encapsulated device including a control system configured to operate at cryogenic temperatures, where the first encapsulated device is coupled to the second encapsulated device. The control system may include a plurality of charge-locking circuits, where each charge-locking circuit of the plurality of charge-locking circuits is coupled via an interconnect to at least one qubit gate of the plurality of qubit gates such that each charge-locking circuit of the plurality of charge-locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system may also include a control circuit that includes a finite state machine configured to provide at least one control signal to selectively enable at least one of the plurality of charge-locking circuits and selectively support providing at least one voltage signal to a selected one of the plurality of charge-locking circuits.

[0102] A subset of the plurality of charge-locking circuits may include capacitors, and where the control logic is also configured to selectively support providing at least one voltage signal to a capacitor associated with a selected one of at least one subset of the plurality of charge-locking circuits. The control system may also include a waveform generator and a register for storing a bit pattern corresponding to a waveform for generation by the waveform generator.

[0103] Each charge-locking circuit of the plurality of charge-locking circuits may include an input terminal for receiving an input voltage signal and an output terminal for selectively providing a voltage signal to at least one qubit gate. Each charge-locking circuit of the plurality of charge-locking circuits may also include a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount.

[0104] The control system may further include a control register for specifying an amount of time, and wherein the finite state machine is configured to selectively support providing at least one voltage signal to a capacitor associated with a selected one of the plurality of charge locking circuits within the amount of time specified in the control register. Each of the plurality of charge locking circuits may also be configured to generate a voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on a first amount of voltage and a second amount of voltage.

[0105] In another aspect, the present disclosure relates to a system for controlling a qubit gate. The system may include a first encapsulated device that includes a quantum device that includes a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may further include a second encapsulated device that includes a control system configured to operate at cryogenic temperatures, wherein the first encapsulated device is coupled to the second encapsulated device. The control system may include a plurality of charge locking circuits, wherein each of the plurality of charge locking circuits is coupled via an interconnect to at least one of the plurality of qubit gates such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system may further include a control circuit that includes control logic configured to provide at least one control signal to selectively enable at least one of the plurality of charge locking circuits.

[0106] The control logic may include a finite state machine configured to selectively support providing at least one voltage signal to a selected one of the plurality of charge locking circuits. At least one subset of the plurality of charge locking circuits may include a capacitor, and wherein the control logic is further configured to selectively support providing at least one voltage signal to a capacitor associated with a selected one of the at least one subset of the plurality of charge locking circuits. The control system may further include a waveform generator and a register for storing a bit pattern corresponding to a waveform for generation by the waveform generator.

[0107] Each of the plurality of charge locking circuits may include an input terminal for receiving an input voltage signal and an output terminal for selectively providing a voltage signal to at least one qubit gate. Each of the plurality of charge locking circuits may further include a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount. The control system may further include a control register for specifying an amount of time, and wherein a finite state machine is configured to selectively support providing at least one voltage signal to a capacitor associated with a selected one of the plurality of charge locking circuits within the amount of time specified in the control register. Each of the plurality of charge locking circuits may further be configured to generate a voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage amount and the second voltage amount.

[0108] In yet another aspect, the present disclosure relates to a system for controlling qubit gates. The system may include a first packaged device including a quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may further include a second packaged device including a control system configured to operate at cryogenic temperatures, wherein the first packaged device is coupled to the second packaged device. The control system may include a plurality of charge locking circuits, wherein each of the plurality of charge locking circuits is coupled via an interconnect to at least one of the plurality of qubit gates such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system may further include a digital-to-analog converter for generating at least one voltage signal. The control system may further include a control circuit including a finite state machine configured to provide at least one control signal to selectively enable at least one of the plurality of charge locking circuits and selectively support providing at least one voltage signal to a selected one of the plurality of charge locking circuits.

[0109] The control system may further include a waveform generator and a register for storing a bit pattern corresponding to a waveform for generation by the waveform generator. Each of the plurality of charge locking circuits may include an input terminal for receiving an input voltage signal and an output terminal for selectively providing a voltage signal to at least one qubit gate, and wherein each of the plurality of charge locking circuits further includes a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount.

[0110] The control system may further include a control register for specifying an amount of time, and wherein the finite state machine is configured to selectively enable providing at least one voltage signal to a capacitor associated with a selected one of the plurality of charge locking circuits within the amount of time specified in the control register. Each of the plurality of charge locking circuits may also be configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends on at least the first voltage amount and the second voltage amount.

[0111] It is to be understood that the methods, modules and components described herein are exemplary only. For example, but not limited to, illustrative types of superconducting devices may include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), etc.

[0112] Additionally, in an abstract but still definite sense, any arrangement of components that achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Thus, any two components herein combined to achieve a particular functionality can be considered to be "associated" with each other such that the desired functionality is achieved, regardless of architectures or intermediate components. Likewise, any two components so associated can also be considered to be "operably connected" or "coupled" to each other such that the desired functionality is achieved.

[0113] In addition, those skilled in the art will recognize that the boundaries between the functionality of the above-mentioned operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may be changed in various other embodiments.

[0114] Although the present disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the following claims. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems described herein with respect to specific examples are not intended to be construed as key, required, or essential features or elements of any or all claims.

[0115] Furthermore, as used herein, the term "a" or "an" is defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to mean that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" as well as the indefinite article (such as "a" or "an"). This also applies to the use of definite articles.

[0116] Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish elements described by such terms. Thus, these terms are not necessarily intended to indicate a temporal or other prioritization of such elements.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A system for controlling a qubit gate, comprising: A first encapsulation device, including a quantum device, the quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at a low temperature; and A second encapsulation device, including a control system configured to operate at the low temperature, wherein the first encapsulation device is coupled to the second encapsulation device, and wherein the control system includes: A plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnection to at least one qubit gate of the plurality of qubit gates, such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate, and A control circuit, including a finite state machine, the finite state machine being configured to provide at least one control signal to selectively enable at least one charge locking circuit of the plurality of charge locking circuits and selectively support providing at least one voltage signal to a selected one of the plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits further includes a capacitor having a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount.

2. The system according to claim 1, wherein the control system further comprises a waveform generator and a register, the register being configured to store a bit pattern corresponding to a waveform for generation by the waveform generator.

3. The system according to claim 2, wherein each of the plurality of charge locking circuits comprises an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to at least one qubit gate.

4. The system according to claim 1, wherein the control system further comprises a control register for specifying an amount of time, and wherein the finite state machine is configured to selectively support providing the at least one voltage signal to the capacitor within the amount of time specified in the control register, the capacitor being associated with one of the selected charge locking circuits of the plurality of charge locking circuits.

5. The system according to claim 4, wherein each of the plurality of charge locking circuits is configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first amount of voltage and the second amount of voltage.

6. The system according to claim 1, wherein the first amount of voltage is greater than the second amount of voltage.

7. The system according to claim 1, wherein the finite state machine comprises: (1) A first finite state machine, configured to charge only a subset of the plurality of charge locking circuits selectively enabled by the at least one control signal simultaneously, and (2) A second finite state machine, configured to charge each charge locking circuit of the plurality of charge locking circuits sequentially.

8. A system for controlling a qubit gate, comprising: A first encapsulation device, including a quantum device, the quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at a low temperature; and A second encapsulation device, including a control system configured to operate at the low temperature, wherein the first encapsulation device is coupled to the second encapsulation device, and wherein the control system includes: A plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits is coupled via an interconnection to at least one qubit gate of the plurality of qubit gates, such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate, and A control circuit, including control logic, the control logic being configured to provide at least one control signal to selectively enable at least one charge locking circuit of the plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits includes an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to at least one qubit gate, and wherein each charge locking circuit of the plurality of charge locking circuits further includes a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount.

9. The system according to claim 8, wherein the control logic comprises a finite state machine configured to selectively support providing at least one voltage signal to one of the selected charge locking circuits of the plurality of charge locking circuits.

10. The system according to claim 9, wherein the control system further comprises a waveform generator and a register, the register being configured to store a bit pattern corresponding to a waveform for generation by the waveform generator.

11. The system according to claim 9, wherein the control system further comprises a control register for specifying an amount of time, and wherein the finite state machine is configured to selectively support providing the at least one voltage signal to the capacitor within the amount of time specified in the control register, the capacitor being associated with one selected charge locking circuit of the plurality of charge locking circuits.

12. The system according to claim 11, wherein each charge locking circuit of the plurality of charge locking circuits is configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first amount of voltage and the second amount of voltage.

13. The system according to claim 8, wherein the first amount of voltage is greater than the second amount of voltage.

14. A system for controlling a qubit gate, comprising: A first encapsulation device, including a quantum device, the quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at a low temperature; and A second encapsulation device, including a control system configured to operate at the low temperature, wherein the first encapsulation device is coupled to the second encapsulation device, and wherein the control system includes: A plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnection, such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate, A digital-to-analog converter for generating at least one voltage signal, and A control circuit including a finite state machine, the finite state machine being configured to provide at least one control signal to selectively enable at least one charge locking circuit of the plurality of charge locking circuits and selectively support providing the at least one voltage signal to a selected one of the plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits includes an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to at least one qubit gate, and wherein each charge locking circuit of the plurality of charge locking circuits further includes a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount.

15. The system according to claim 14, wherein the control system further comprises a waveform generator and a register for storing a bit pattern corresponding to a waveform for generation by the waveform generator.

16. The system according to claim 14, wherein the control system further comprises a control register for specifying an amount of time, and wherein the finite state machine is configured to selectively support providing the at least one voltage signal to the capacitor within the amount of time specified in the control register, the capacitor being associated with one selected charge locking circuit of the plurality of charge locking circuits.

17. The system according to claim 16, wherein each charge locking circuit of the plurality of charge locking circuits is configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first amount of voltage and the second amount of voltage.

18. The system according to claim 14, wherein the first amount of voltage is greater than the second amount of voltage.

19. The system according to claim 14, wherein the finite state machine comprises: (1) A first finite state machine configured to charge only a subset of the plurality of charge locking circuits selectively enabled by the at least one control signal, and (2) a second finite state machine configured to charge each charge locking circuit of the plurality of charge locking circuits in sequence.

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