Mass production test system and method for multimedia interface

Abstract

The present invention discloses a mass production test system and method of a multimedia interface, the system comprising: ATE, providing power to a chip to be tested and sending a test start / end instruction; a PLD module, the PLD module is connected to the chip to be tested through a bridge submodule or directly, the chip type of the bridge submodule is determined according to the interface type and fan-out position of the docked chip to be tested; the chip to be tested enters a state to be tested after configuring its own multimedia interface to be tested, and configures the data FIFO, switch module, sending module and receiving module of the PLD module according to the loop to be tested; the chip to be tested enables the sending module to send test data and receives the test data through the PLD receiver at the same time; or sends data through the PLD generator, and the test data received by the chip to be tested is decoded and compared according to a preset data mode to obtain a comparison result. The present invention has low requirements on ATE resources, low test cost, and has the characteristics of high integration, easy expansion and easy transplantation.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip testing, and in particular to a mass production testing system and method for a multimedia interface. Background Art

[0002] After semiconductor chips are manufactured, they need to undergo mass production testing to determine / screen out chips without defects. The test needs to cover all functional modules of the chip. Among these modules, high-speed multimedia interfaces are of many types, fast speeds, and complex protocols, and are an important part of mass production testing.

[0003] The existing mass production test of multimedia interfaces of semiconductor chips is either based on protocol testing, relying on ATE high-speed digital boards to send and receive signals, measuring signal waveform quality and data correctness, or weakly relying on or not relying on ATE resources, sending and receiving data in normal working mode or close to working mode, to control the signal and compare the original data to determine whether there are defects. For the former, the signal waveform quality includes eye diagram test, setup / hold time, level, etc., which objectively and directly reflects the quality level of the signal, but this type of test has very high requirements for the chip to be tested, ATE and test board, etc. For example: the chip to be tested requires a specific DFT mode to synchronize and send and receive control signals, clock signals, and data signals with the ATE platform; the ATE platform must support high-speed mode and protocol editing functions. For the latter, only functional testing can be performed, that is, there is only Pass / Fail result, and it is difficult to characterize the specific value of the actual signal quality. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a mass production test system for multimedia interfaces, which can realize reliable and effective testing of multimedia interfaces of semiconductor chips at low cost.

[0005] The present invention also provides a mass production test method of a multimedia interface using the mass production test system of the multimedia interface.

[0006] According to a first aspect of the present invention, a mass production test system for a multimedia interface comprises: a PLD module, which is used to connect to the chip to be tested, including: a TX prbs / Color bar generator, a PLD receiver, a data FIFO, a control unit and a bridge submodule; the PLD module is connected to the chip to be tested through the bridge submodule or directly, and the chip type of the bridge submodule is determined according to the interface type and fan-out position of the connected chip to be tested; the chip to be tested enters a state to be tested after configuring its own multimedia interface to be tested, and configures the data FIFO, switch module, sending module and receiving module of the PLD module according to the loop to be tested; the chip to be tested enables the sending module to send test data and receives test data through the PLD receiver; or sends data through the PLD generator, and the test data received by the chip to be tested is decoded and compared according to a preset data mode to obtain a comparison result.

[0007] The mass production test system of the multimedia interface according to the embodiment of the present invention has at least the following beneficial effects: the chip to be tested is connected to the PLD module through the bridge module, and the chip to be tested serves as the master end and the PLD module serves as the slave end, so that various loop self-tests can be realized, and the requirements for ATE resources are low, and the test cost is low; interface iteration can be supported by only replacing the bridge module and performing PLD IO reallocation and reprogramming, and the system has the characteristics of high integration, easy expansion and easy transplantation.

[0008] According to some embodiments of the present invention, the chip under test is connected to the PLD module in groups, wherein each group has the same IO distribution, including a clock signal, a control signal and a lane data signal.

[0009] According to some embodiments of the present invention, the bridge sub-module is plugged into the PLD module via an HS interface.

[0010] According to some embodiments of the present invention, the PLD module and the bridge sub-module adopt a multi-layer stacking structure.

[0011] According to some embodiments of the present invention, in the transmitting module, the prbs data generated by the TX prbs generator or the color bar signal generated by the Color bar generator is received and converted into Lane data, which is then converted into differential pair output through the PHY module and the IO driver circuit.

[0012] According to some embodiments of the present invention, it also includes: the chip under test reads the comparison result and sends it to the sorting machine directly, or the chip under test reads the comparison result and sends it to the ATE, and the ATE sends it to the sorting machine; the sorting machine grabs the chip under test according to the comparison result and places it in a corresponding position.

[0013] According to the mass production test method of the multimedia interface of the second aspect of the present invention, the following steps are included: S100, determining the chip type of the bridge submodule according to the interface type and fan-out position of the chip to be tested, and plugging the bridge submodule into the PLD module through the HS interface; S200, ATE is connected to the chip to be tested, provides power to the chip to be tested, and sends a test start instruction to the chip to be tested; S300, the chip to be tested enters the test state after configuring its own multimedia interface to be tested, and configures the data FIFO, switch module, sending module and receiving module of the PLD module according to the loop to be tested; S400, the chip to be tested enables the sending module to send test data, and receives test data through the receiving module at the same time; or sends data through the PLD generator, and decodes and compares the test data received by the chip to be tested according to a preset data mode to obtain a comparison result.

[0014] The mass production test method of the multimedia interface according to the embodiment of the present invention has at least the following beneficial effects: the chip to be tested is connected to the PLD module through the bridge module, and the chip to be tested serves as the master end and the PLD module serves as the slave end, so that various loop self-tests can be realized, and the requirements for ATE resources are low and the test cost is low; interface iteration can be supported by only replacing the bridge module and performing PLD IO reallocation and reprogramming, and the method has the characteristics of high integration, easy expansion and easy transplantation.

[0015] According to some embodiments of the present invention, the PLD module enables the sending module to send test data, including: receiving prbs data generated by a TX prbs generator or receiving a color bar signal generated by a Color bar generator, converting it into Lane data, and then converting it into a differential pair output through a PHY module and an IO driver circuit.

[0016] According to some embodiments of the present invention, it also includes: the chip under test reads the comparison result and sends it to the sorting machine directly, or the chip under test reads the comparison result and sends it to the ATE, and the ATE sends it to the sorting machine; the sorting machine grabs the chip under test according to the comparison result and places it in a corresponding position.

[0017] According to some embodiments of the present invention, the further step includes: the PLD module simultaneously enables all of the sending modules to perform parallel testing on the chips to be tested.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 A schematic block diagram of the structure of a system according to an embodiment of the present invention;

[0021] Figure 2 Schematic diagram of the connection between the chip under test (DUT) and the PLD module in an embodiment of the present invention;

[0022] Figure 3 is a test flow chart in an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of a loop structure in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of test time variation during parallel testing in an embodiment of the present invention;

[0025] Figure 6 It is a front view of the connection structure when a stacking structure is adopted in an embodiment of the present invention;

[0026] Figure 7 This is a top view of the connection structure when a stacking structure is adopted in an embodiment of the present invention:

[0027] Figure 8 This is a custom schematic diagram of grouping different chips in an embodiment of the present invention:

[0028] Fig. 9 Schematic diagram of the structure of the transmitting end in the PLD module in an embodiment of the present invention;

[0029] Fig.10 It is a schematic diagram of prbs logic in an embodiment of the present invention;

[0030] Fig.11 The figure is a flowchart of the steps of the method according to the embodiment of the present invention. DETAILED DESCRIPTION

[0031] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0032] In the description of the present invention, the meaning of "several" is one or more, the meaning of "more" is two or more, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of the first and the second, it is only for the purpose of distinguishing the technical features, and it cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features. In the description of the present invention, the step numbers are only used for the convenience of description or citation. The size of the serial number of each step does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0033] Glossary:

[0034] LVDS (Low Voltage Differential Signaling) interface, also known as RS-644 bus interface, is a data transmission and interface technology proposed in the 1990s.

[0035] SERDES is the abbreviation of SERializer / DESerializer. It is a mainstream time division multiplexing (TDM) and point-to-point (P2P) serial communication technology. That is, multiple low-speed parallel signals are converted into high-speed serial signals at the sending end, and then transmitted through the transmission media (optical cable or copper wire). Finally, the high-speed serial signals are converted back into low-speed parallel signals at the receiving end.

[0036] High Definition Multimedia Interface (HDMI) is a fully digital video and sound transmission interface that can send uncompressed audio and video signals.

[0037] MIPI, or Mobile Industry Processor Interface, is an open standard and specification initiated by the MIPI Alliance for mobile application processors. It is mainly used to standardize the internal interfaces of mobile phones (camera, display interface, RF / baseband interface), thereby reducing the complexity of the internal interfaces of mobile phones and increasing the flexibility of design. The MIPI Alliance has different working groups that define a series of internal interface standards for mobile phones, such as the camera interface CSI and the display interface DSI.

[0038] The system structure block diagram of the embodiment of the present invention is as follows Figure 1The test system includes ATE (auto test equipment, automated test platform), PLD (programmable logic device, programmable logic device) module and DUT (device under test, chip to be tested).

[0039] ATE provides power and sends test instructions to control the start / end of the test. It should be understood that ATE can be tailored in some extreme application scenarios such as SLT testing.

[0040] The PLD module consists of a TX prbs / Color bar generator, a receiver, a data FIFO, a control unit, a bridge chip, etc. Because some PLD devices already have a PHY module, some high-speed interfaces do not need to be connected to a bridge chip, depending on the selection of the PLD device, such as Figure 1 The module is shown in the dotted box. There are many types of bridge chips, which need to be selected according to the type of chip to be tested and the IO fan-out position, such as D-PHY for mipi-csi and dsi, and TMDS for HDMI / DVI. Figure 1 The USB module is optional and can be used for multiple data transmission modules, otherwise the serial interface can be used.

[0041] The DUT and PLD modules can be connected by FPC (Flexible Printed Circuit) or high-speed interface in groups. Different groups use the same IO distribution. Each group includes a clock control signal and four Lane data. Figure 2 , such as groups G1, G2, G3, etc. The IO distribution of the group is set to one clock control signal and four Lane data because the mainstream high-speed multimedia interface is mostly four Lanes. Using the same IO distribution for different groups can improve scalability: for interfaces of different chips, only the bridge module needs to be switched without redesigning the PLD module. The same IO distribution refers to the same number and arrangement of IO pins; the IO electrical signal function can be changed for different interfaces, and the IO information can be changed through customization of the programmable logic device.

[0042] The test flow chart is as follows Figure 3 In the whole test process, DUT is the master end and PLD is the slave end.

[0043] Before the test begins, the DUT controls / configures its own high-speed interface to enter the test state, and configures the PLD's data FIFO (First Input First Output), switch module, TX module, and RX module according to the test loop. For a chip under test with a single TX, the DUT enables TX to send data, while RX receives data, and decodes and compares according to the configured data mode. The comparison result is read back by the DUT, and the DUT finally transmits the result to the ATE. The ATE communicates with the sorter to return the result (or the DUT directly sends it to the sorter without passing through the ATE). The sorter grabs the DUT and places it in the physical location of the corresponding classification (good product, defective product, etc.). For a chip under test with a single RX, the DUT is changed to enable the PLD's TX module to send data, and the RX of the chip under test receives data and decodes and compares it, and the result is returned to the ATE and the sorter. For the chip under test that has both TX and RX, the TX of the chip under test and the RX of the chip under test form a loop; or they are divided into the two independent paths mentioned above: the TX of the chip under test and the RX of the PLD, and the RX of the chip under test and the TX of the PLD; which path to use specifically can be freely defined.

[0044] The embodiment of the present invention can test different loop structures. Different chips to be tested have different interface modules, for example, some only have mipi-csi and HDMI, and some only have mipi-dsi and LVDS. The present invention can switch different bridge modules according to different chips, and implement different loop tests by redistributing PLD IO and changing codes, including: single TX, single RX, TX+RX, complex multi-interface TX+RX multiplexing, etc. Figure 4 shown.

[0045] The unit price of mass production testing is calculated based on the test time, so the shorter the test time, the lower the cost. In the embodiment of the present invention, the parallel testing of different test tasks of multiple modules can be achieved through the multiplexing of the loop self-test mode and the PLD module. Figure 5 As shown, the general test process is a serial test, in which each module is tested separately first, and then the next test is continued after one test is completed. The test time is the sum of each module. In the embodiment of the present invention, all TX modules are enabled at the same time, and RX reception and comparison are synchronously enabled in the PLD module or DUT. Obviously, the test time is the module time with the longest test time. It should be noted that when using parallelism, interrupts and multi-core parallelism need to be enabled for DUTs with multiple RXs to achieve multi-RX synchronous reception; and for DUTs with multiple TXs, there will be no impact because the PLD chip can easily reuse RX. General SOC chips have more TX interfaces and fewer RXs, so there are rarely situations where the chip under test needs to have multiple RXs and receive simultaneously.

[0046] The physical structure of the PLD module is as follows Figure 6(front view) and Figure 7 (Top view) as shown. The test board, PLD module, and bridge sub-module adopt a multi-layer stacking structure through a high-speed interface. The stacking structure mentioned in this article is connected through a high-speed socket interface, a flat cable, etc., and its structure is detachable.

[0047] The DUT and PLD module are connected via a high-speed HS (high speed) interface. The PLD module consists of a PLD chip and a bridge chip, where the bridge chip and the module are connected via a high-speed HS interface. One end of the HS interface is connected to the lane (differential pair) signal in the packet from the DUT, and the other end is connected to the PLD module chip IO.

[0048] In the embodiment of the present invention, the bridging sub-module is plugged in, which has the following advantages:

[0049] (1) Solve the problem of high-speed interface iteration. The protocols and interfaces of high-speed multimedia interfaces are updated quickly, which makes the old solutions no longer applicable or only backward compatible after technology iteration. For example, after changing from D-PHY1.1 to D-PHY2.0, only 1.1 can be tested using the old solution; after using the bridge sub-module, after iteration, only the sub-module needs to be replaced and the IO of the PLD can be reallocated to achieve compatibility.

[0050] (2) Ability to adapt to different interfaces of different DUT chips. Different chips under test have different high-speed interfaces, including interface type and fan-out position. Compatibility can be achieved by replacing the submodule according to the interface type and position of the chip under test. Figure 8 For example, for chip A, Group 1 is LVDS0, Group 2 is LVDS1, but there is no eDP; for chip B, there is an eDP module but no LVDS, so Group 1 can be changed to an eDP module; for chip C, the interface is similar to chip A, but the fan-out arrangement is different. In order to simplify the PCB layout, the Group distribution can be changed, for example, G1 is mipi-dsi, etc.

[0051] (3) Reduces the difficulty of test board design and layout. The test board only needs to connect the fan-out IO of the DUT to the HSinterface socket, which greatly reduces the BOM quantity and layout difficulty.

[0052] That is to say, different groups of bridge sub-modules in the embodiment of the present invention have the same input differential pairs, control signals and output bridge IO. The input differential pair is 4lane data + 1lane clock, which can meet the current mainstream multimedia interface. The control signal is an independent interface, generally implemented through a serial bus, mostly 2PIN / 4PIN. Output IO, because the output protocols and IOs of different PHYs are different, more IO connections with PLD chips will be reserved. The number of IOs of existing PLD chips is large. According to the number of IOs, 5 sub-modules can be reserved (according to the PLD chip IO, more can be done, but due to size requirements, the PLD chip is not suitable for being too large). The size of the PLD module is approximately 30*60mm; because of the use of plug-in, the spatial position of the PLD module on the test board can still layout BOM components and routing. The other end of the PLD module and the sub-board are fixed by support columns (see Figure 7 The two circles on the right).

[0053] In the embodiment of the present invention, a loopback-based DFT method is used to send data. Fig. 9 and Fig.10 .

[0054] Fig. 9 This is a simplified diagram of the data structure of the TX transmission loop. In normal working mode, the TX data is converted from the source video data to Lane data by the Lane Management Unit and the Logic Control Unit after a certain encoding (see the dotted box part), and then converted to differential pair output through the PHY module and IO driver circuits. Since the actual source video data is random and has no specific rules, it is necessary to compare the large RX receiving data with the TX sending data during the test, which consumes a lot of memory space and time.

[0055] Based on this, the embodiment of the present invention uses Color Bar or Prbs data to replace the source video data, see Fig. 9The double-frame rectangle in the image, that is, receiving the prbs data generated by the TX prbs generator or receiving the color bar signal generated by the Color bar generator, converting it into Lane data, and then converting it into a differential pair output through the PHY module and the IO driver circuit. The advantage of this method is that since the original TX data is known, the RX receiving end can easily decode and compare it, that is, the RX end does not need to know the TX data, it only needs to know the algorithm for inverse decoding to compare. Another advantage of this method is that the DFT circuit area of ​​the Color Bar and prbs is very small, and the Color Bar is a frame of static color block image with very small data. The prbs is a pseudo-random binary, which can be implemented by a multi-bit shift register plus an XOR gate, such as Fig.10 As shown in the figure (the structure is simplified), an N-bit shift register can generate a set of random sequence numbers, and the sequence numbers are reversibly decodable. The reason for decodability is that the sequence numbers are cyclically fixed, that is, the sequence numbers are continuously cyclical at a certain period. Fig.10 For a 3-bit shift register, a sequence number with a length of 7 bits can be generated. Both can be implemented with only a few logic circuit units. This mode can be used in the TX of the DUT or the TX of the PLD module.

[0056] Reference Fig.11 The method of the embodiment of the present invention includes: S100, determining the chip type of the bridge submodule according to the interface type and fan-out position of the chip to be tested, and plugging the bridge submodule into the PLD module through the HS interface; S200, ATE is connected to the chip to be tested, provides power to the chip to be tested, and ATE sends a test start instruction to the chip to be tested; S300, the chip to be tested enters the test state after configuring its own test multimedia interface, and configures the data FIFO, switch module, sending module and receiving module of the PLD module according to the test loop; S400, the chip to be tested enables the sending module to send test data, and receives the test data through the receiving module at the same time; or sends data through the PLD generator, and decodes and compares the test data received by the chip to be tested according to the preset data mode to obtain a comparison result.

[0057] The specific method of enabling the PLD module to send the test data includes: receiving the prbs data generated by the TX prbs generator or receiving the color bar signal generated by the Color bar generator, converting it into Lane data, and then converting it into a differential pair output through the PHY module and the IO driver circuit.

[0058] The method of an embodiment of the present invention (not marked in the figure) also includes: the comparison result of the chip to be tested is read and sent directly to the sorting machine, or the comparison result of the chip to be tested is read and sent to ATE, and then sent to the sorting machine by ATE; the sorting machine grabs the chip to be tested according to the comparison result and places it in the corresponding position.

[0059] In the embodiment of the present invention, the PLD module can also enable all the sending modules at the same time to perform parallel testing on the chip to be tested.

[0060] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0061] Some aspects of the present disclosure are described above with reference to the block diagram and flow chart of the system, method, system and / or computer program product according to the exemplary embodiments.It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively.Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full.In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0062] Therefore, the blocks in the block diagrams and flow charts support the combination of devices for performing the specified functions, the combination of elements or steps for performing the specified functions, and the program instruction devices for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts and the combination of blocks in the block diagrams and flow charts can be implemented by a special-purpose hardware computer system or a combination of special-purpose hardware and computer instructions that performs a specific function, element or step.

[0063] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0064] Software components can be encoded with any of various programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or an operating system platform. The software component comprising assembly language instructions may need to be converted to executable machine code by an assembler before being executed by hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be transplanted across multiple architectures. The software component comprising a higher-level programming language may need to be converted to an intermediate representation by an interpreter or a compiler before execution. Other examples of programming languages ​​include but are not limited to macro languages, shells or command languages, job control languages, scripting languages, database queries or search languages ​​or report writing languages. In one or more exemplary embodiments, the software component comprising the instruction of one of the above-mentioned programming language examples can be directly executed by an operating system or other software components, without first being converted into another form.

[0065] Software components may be stored as files or other data storage structures. Software components of similar type or related functions may be stored together, such as in a specific directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0066] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A mass production test system for a multimedia interface, characterized in that: include: A PLD module, used to connect with the chip to be tested, comprising: a TX prbs / Color bar generator, a PLD receiver, a data FIFO, a control unit and a bridge submodule; the PLD module is connected to the chip to be tested through the bridge submodule, and the chip type of the bridge submodule is determined according to the interface type and fan-out position of the docked chip to be tested; ATE, the ATE is used to provide power supply, the ATE is connected to the chip under test, and the ATE sends a test start instruction to the chip under test; The chip under test enters a state to be tested after configuring its own multimedia interface to be tested, and configures the data FIFO, switch module, sending module and receiving module of the PLD module according to the loop to be tested; The chip under test enables the sending module to send test data and receives the test data through the PLD receiver; or sends data through the PLD generator and decodes and compares the test data received by the chip under test according to a preset data mode to obtain a comparison result.

2. The mass production test system of multimedia interface according to claim 1, characterized in that: The chip under test is connected to the PLD module in groups, wherein each group has the same IO distribution, including clock signals, control signals, and lane data signals.

3. The mass production test system of multimedia interface according to claim 2, characterized in that: The bridge submodule is plugged into the PLD module via the HS interface.

4. The mass production test system of multimedia interface according to claim 1, characterized in that: The PLD module and the bridge sub-module adopt a multi-layer stacking structure.

5. The mass production test system of multimedia interface according to claim 1, characterized in that: In the transmitting module, the prbs data generated by the TX prbs generator or the color bar signal generated by the Color bar generator is received and converted into Lane data, and then converted into differential pair output through the PHY module and the IO driver circuit.

6. The mass production test system of multimedia interface according to claim 1, characterized in that: Also includes: The chip under test reads the comparison result and directly sends it to the sorting machine, or the chip under test reads the comparison result and sends it to the ATE, and the ATE sends it to the sorting machine; The sorting machine grabs the chip to be tested according to the comparison result and places it in a corresponding position.

7. A mass production test method for a multimedia interface, characterized in that: The following steps are involved: S100, determining the chip type of the bridge submodule according to the interface type and fan-out position of the chip to be tested, and plugging the bridge submodule into the PLD module through the HS interface; S200, ATE is connected to the chip under test, provides power to the chip under test, and sends a test start instruction to the chip under test; S300, the chip under test configures its own multimedia interface under test and enters a state under test, and configures the data FIFO, switch module, sending module and receiving module of the PLD module according to the loop under test; S400, the chip under test enables the sending module to send test data and receives test data through the receiving module; or sends data through the PLD generator and decodes and compares the test data received by the chip under test according to a preset data mode to obtain a comparison result.

8. The mass production test method of multimedia interface according to claim 7, characterized in that: The PLD module enables the sending module to send test data, including: Receive the prbs data generated by the TX prbs generator or the color bar signal generated by the Color bar generator, convert it into Lane data, and then convert it into differential pair output through the PHY module and IO driver circuit.

9. The mass production test method of multimedia interface according to claim 7, characterized in that: Also includes: The chip under test reads the comparison result and directly sends it to the sorting machine, or the chip under test reads the comparison result and sends it to the ATE, and the ATE sends it to the sorting machine; The sorting machine grabs the chip to be tested according to the comparison result and places it in a corresponding position.

10. The mass production test method of multimedia interface according to claim 7, characterized in that: Also includes: The PLD module enables all the sending modules at the same time to perform parallel testing on the chips to be tested.

Images