Array device and writing method thereof

Abstract

The present invention provides an array device and a writing method thereof, which can more accurately control the change of resistance value during setting writing through pulse width control. The synapse array device of the present invention includes: a cross array, in which variable resistance storage elements are connected at the intersections of multiple row lines and multiple column lines; a row selection / driving circuit, which selects the row lines of the cross array and applies a pulse signal to the selected row lines; a column selection / driving circuit, which selects the column lines of the cross array and applies a pulse signal to the selected column lines; and a writing component, which writes to the variable resistance storage elements connected to the selected row lines and the selected column lines. A first writing voltage with a controlled pulse width is applied to the selected row line, and a second writing voltage with a controlled pulse width is applied to the selected column line to perform setting writing of the variable resistance storage element.

Description

Technical Field

[0001] The present invention relates to a crossbar array device using a variable resistance memory element and a writing method thereof, and more particularly to a writing method of a synapse array device that can be used for a neuron network. Background Art

[0002] Artificial neural networks are introduced as software algorithms in recognition and classification technologies such as pattern recognition, and have become an essential technology for implementation using highly integrated digital complementary metal oxide semiconductor (CMOS) technology. Neural networks implemented using digital technology are gradually reaching their limits in terms of power and scale. On the other hand, in recent years, research and development of neural networks that use resistor elements as synapses have been conducted.

[0003] Learning in neural networks, i.e. setting the binding strength of synapses to appropriate values, is mainly performed by the back propagation algorithm (BPA). The most important part of BPA is how to fine-tune the strength of synapses during learning. When the adjustment of synaptic strength is nonlinear and steep, BPA has difficulty converging.

[0004] From the viewpoint of integration, a synapse array using variable resistance elements in a cross structure is the most preferred structure. It is particularly desirable to use metal transition oxides such as hafnium oxide, which have a high affinity with CMOS processes, as variable resistance elements. Figure 1 1 shows an example of a cross array using variable resistance elements. The cross array includes a plurality of row lines 10 extending in the row direction, a plurality of column lines 20 extending in the column direction in a manner orthogonal to the row lines 10, and variable resistance memory elements 30 connected to the intersections between the row lines 10 and the column lines 20. The variable resistance memory element 30 stores different resistance states by applying voltage or current.

[0005] The write speed to the variable resistive memory element, that is, the voltage dependence of the resistance change, is unique to metal transition oxides such as hafnium oxide. The voltage dependence of the resistance change on the setting side is very large compared to the reset side, so the controllability of the multi-level cell (MLC) storing multiple resistance states in a variable resistive memory cell is not excellent. This means that BPA is difficult to perform during the learning process. However, if a suitably low write power is used, the change in the resistance value of the setting write can be made more moderate by pulse width control.

[0006] Figure 2A This is a diagram showing the setting characteristics of a variable resistance memory element containing hafnium oxide, with the vertical axis being the conductance and the horizontal axis being the number of pulses applied to the write voltage. The conductance is shown when the pulse voltage for setting the write is changed to Vp = 0.7V, Vp = 0.8V, Vp = 0.9V, and Vp = 1.0V. It can be seen that the greater the pulse voltage, the greater the conductance. It should be noted here that when Vp = 1.0V, the resistance value changes sharply at a voltage within a range of only 300mV.

[0007] Figure 2B The graph in the middle top shows the conductance when the pulse voltage is fixed at Vp=0.9 and the pulse application time is changed to tp=10us, tp=100us, and tp=1ms. The graph below shows the relationship between the conductance and the pulse width (application time) at a certain pulse number. According to these graphs, the longer the pulse width, the greater the conductance. In this way, if the pulse voltage is set low and the pulse width is appropriately controlled, fine adjustment of the resistance value to be written can be achieved. Summary of the invention

[0008] The object of the present invention is to provide a variable resistance crossbar array device which can more accurately control the change of resistance value during setting writing by pulse width control.

[0009] The writing method of the present invention is a method for writing to a cross array using bipolar variable resistance storage elements, which applies a first writing voltage with a controlled pulse width to the selected row line of the cross array and applies a second writing voltage with a controlled pulse width to the selected column line, thereby writing to the selected variable resistance storage element.

[0010] The array device of the present invention includes: a cross array, in which variable resistance storage elements are connected at the intersections of multiple row lines and multiple column lines; a row selection component, which selects the row lines of the cross array; a column selection component, which selects the column lines of the cross array; and a writing component, which writes to the variable resistance storage elements connected to the row lines selected by the row selection component and the column lines selected by the column selection component, wherein the writing component applies a first writing voltage with a controlled pulse width to the row lines and applies a second writing voltage with a controlled pulse width to the column lines, thereby writing to the selected variable resistance storage elements.

[0011] According to the present invention, since writing to the variable resistance memory element is performed using a voltage with a controlled pulse width, the change in the resistance value of the variable resistance memory element can be controlled with high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing a structural example of a cross array;

[0013] Figure 2A is a graph showing the setting write characteristics of HfOx;

[0014] Figure 2B is a graph showing the setting write characteristics of HfOx;

[0015] Figure 3 is a block diagram showing an example of a synapse array device according to an embodiment of the present invention;

[0016] Figure 4 (A) represents the structure of the variable resistance memory element of this embodiment;

[0017] Figure 4 (B) is a graph showing the IV characteristics of the selector;

[0018] Figure 5 1 is a diagram showing a row selection circuit and a column selection circuit of a row selection / driving circuit and a column selection / driving circuit according to an embodiment of the present invention;

[0019] Figure 6 (A) is a block diagram showing the internal structure of the row selection / driving circuit of this embodiment, Figure 6 (B) is a block diagram showing the internal structure of the column selection / driving circuit;

[0020] Figure 7 is a diagram illustrating a variable resistance memory element subjected to set writing in a crossbar array;

[0021] Figure 8 is a diagram showing a pulse waveform applied when setting writing is performed sequentially in bit units;

[0022] Fig. 9 is a diagram showing a pulse waveform applied when setting writing is performed in units of columns and in parallel at the same time according to an embodiment of the present invention;

[0023] Fig.10 FIG. 1 is a diagram showing a pulse waveform applied when setting writing is performed in parallel in units of columns according to another embodiment of the present invention.

[0024] [Explanation of Symbols]

[0025] 10: Line

[0026] 20: Column Line

[0027] 30: Variable resistance memory element

[0028] 100: Synaptic Array Device

[0029] 110: Cross array

[0030] 112: Through hole

[0031] 114: Lower conductive layer

[0032] 116: Upper conductive layer

[0033] 120: Row selection / driving circuit

[0034] 122: Row selection circuit

[0035] 124, 126: Pulse generation circuit

[0036] 130: Column selection / driving circuit

[0037] 132: Column selection circuit

[0038] 134, 136: Pulse generation circuit

[0039] 140: Control Department

[0040] 150: Input / output unit

[0041] BE: Lower electrode

[0042] DT1, DT2, DT3, DT4: period

[0043] Icell: current

[0044] MC: variable resistance memory element

[0045] P1, P2, P3: Pulse width

[0046] RS: Resistor switching layer

[0047] S1, S2: control signal

[0048] SEL: Selector

[0049] t1, t2, t3, t4, t5, t6, t7, t8, t9: time

[0050] TE: Upper Electrode

[0051] tp: pulse application time

[0052] Vbe: lower electrode voltage

[0053] Vinh, Vinh2: Write-inhibit voltage / write-protect voltage

[0054] Vp: Pulse voltage

[0055] Vset_X, Vset_Y: set voltage

[0056] Vtb: bias voltage

[0057] Vte: upper electrode voltage

[0058] X[0], X[1], X[2], X[n]: lines

[0059] XD[0], XD[1], XD[2], XD[n], YD[0], YD[1], YD[2], YD[n]: pulse drive signals

[0060] XS[0], XS[1], XS[2], XSB[0], XSB[1], XSB[2], XS[n]: row selection signals

[0061] Y[0], Y[1], Y[2], Y[n]: column lines

[0062] YS[0], YS[1], YS[2], YSB[0], YSB[1], YSB[2], YS[n]: Column selection signals DETAILED DESCRIPTION

[0063] Embodiments of the present invention are described in detail with reference to the accompanying drawings. In one embodiment of the present invention, a cross array is used as a synaptic array device for constituting a neural network. The cross array includes a variable resistance storage element as a memristor at the intersection of the matrix. The variable resistance storage element is bipolar and can store different conductance states (high resistance state and low resistance state) by applying current or voltage of different polarities. The variable resistance storage element constitutes a synapse, and the cross array constitutes a synaptic array device. The synaptic array device is incorporated into a computer device or a computer system and is responsible for at least a part of the data processing or operation processing performed by a microprocessor or a central processing unit (CPU). In other embodiments of the present invention, the cross array is used as a multiplication and accumulation operation processing device for constituting artificial intelligence (AI) hardware. In the following embodiments, an example of applying a cross array to a synaptic array device of a neural network is described.

[0064] Figure 3 1 is a block diagram showing a configuration example of a synapse array device according to an embodiment of the present invention. The synapse array device 100 of this embodiment includes a crossbar array 110 having variable resistance memory elements, a row selection / driving circuit 120, a column selection / driving circuit 130, a control unit 140, and an input / output (I / O) unit 150. The synapse array device 100 is implemented in, for example, an AI chip or a semiconductor integrated circuit.

[0065] The crossbar array 110 includes a plurality of row lines (e.g., X lines) extending in the row direction, a plurality of column lines (e.g., Y lines) extending in the column direction, and variable resistive memory elements connected to the intersections between the row lines and the column lines. The variable resistive memory elements include, for example, metal transition oxides such as hafnium oxide (HfOx) or tantalum oxide (TaOx). In one embodiment, each variable resistive memory element is integrated with a selector such as a diode. However, the integration of the selector is not necessary.

[0066] Figure 4 (A) is a schematic cross-sectional view of a variable resistance memory element. The variable resistance memory element MC includes a resistance switching layer RS ​​including a metal transition oxide between an upper electrode TE and a lower electrode BE, and a selector SEL is formed on the upper electrode TE. The lower electrode BE is electrically connected to the lower conductive layer 114 via a through hole 112, and the selector SEL is connected to the upper conductive layer 116 via the through hole 112.

[0067] Figure 4(B) is a graph showing the IV characteristics of the selector SEL. The horizontal axis is the bias voltage Vtb (Vtb = upper electrode voltage Vte-lower electrode voltage Vbe) between the upper conductive layer 116 and the lower conductive layer 114, and the vertical axis is the current Icell flowing through the selector SEL. The selector SEL is a bidirectional diode having the following characteristics: when the forward bias voltage becomes above a certain level, current flows in the forward direction, and when the reverse bias voltage becomes above a certain level, current flows in the reverse direction. Vinh is a write-inhibit voltage or a write-protection voltage applied to the row and column lines of the non-selected variable resistance storage element when setting writing, and Vinh2 is a write-inhibit voltage or a write-protection voltage applied to the row and column lines of the non-selected variable resistance storage element when setting writing. The write-inhibit voltage Vinh and the write-inhibit voltage Vinh2 are voltages smaller than the threshold voltage when the current flows through the selector SEL.

[0068] Furthermore, the number, shape, conductive material, etc. of the row lines and column lines of the cross array 110 are arbitrary. In addition, the cross array 110 may also be a three-dimensional structure in which a plurality of cross arrays are stacked in a vertical direction.

[0069] The row selection / driving circuit 120 selects a row line of the crossbar array 110 based on a row selection signal or a control signal from the control unit 140, and applies a write voltage or a read voltage to the selected row line, or applies a write inhibit voltage to the non-selected row line. Figure 6 In (A)), the row selection / driving circuit 120 includes a row selection circuit 122 and a pulse generation circuit 124.

[0070] The column selection / driving circuit 130 selects the column lines of the crossbar array 110 based on the column selection signal or control signal from the control unit 140, and applies a write voltage or a read voltage to the selected column line, or applies a write inhibit voltage to the non-selected column line. Figure 6 (B)), the column selection / driving circuit 130 includes a column selection circuit 132 and a pulse generation circuit 134.

[0071] The control unit 140 is composed of hardware and / or software, and controls the read action, write action or other operations (for example, matrix multiplication and accumulation operations, etc.). In one embodiment, the control unit 140 includes a microcontroller, a microprocessor or a state machine having a read-only memory / random access memory (ROM / RAM), and controls the read action or the write action by, for example, executing software stored in the ROM / RAM. In addition, the control unit 140 may include a sensing circuit, and when performing a read action, the sensing circuit senses the voltage or current of the row or column selected by the row selection / driving circuit 120 or the column selection / driving circuit 130.

[0072] The input / output unit 150 is connected to the control unit 140 via an internal data bus, and provides data received from the outside to the control unit 140, or outputs data received from the control unit 140 to the outside. The control unit 140 can obtain data for writing to the variable resistance memory element MC from the input / output unit 150.

[0073] Figure 5 1 is a diagram showing the structure of the row selection circuit 122 included in the row selection / drive circuit 120 and the column selection circuit 132 included in the column selection / drive circuit 130. Here, an array of 3 rows × 3 columns is exemplified as a part of the crossbar array 110, and the row direction is set to the X direction and the column direction is set to the Y direction. The row selection circuit 122 includes, for each row line, a CMOS pass transistor to which the pulse drive signal XD[n] generated by the pulse generation circuit 126 is input, an inverter to which the row selection signal XS[n] is input, and an NMOS transistor to which the row selection signal XSB[n] is applied to the gate. When the row selection signal XS[n] is at the H level, the CMOS pass transistor is turned on, the pulse drive signal XD[n] is applied to the row line X[n], and the NMOS transistor is turned off. When the row selection signal XS[n] is at the L level, the CMOS pass transistor is turned off, the NMOS transistor is turned on, and the row line X[n] is connected to the GND level.

[0074] The column selection circuit 132 includes, for each column line, a CMOS pass transistor to which the pulse drive signal YD[n] generated by the pulse generation circuit 136 is input, an inverter to which the column selection signal YS[n] is input, and an NMOS transistor to which the column selection signal YSB[n] is applied. When the column selection signal YS[n] is at an H level, the CMOS pass transistor is turned on, the pulse drive signal YD[n] is applied to the column line Y[n], and the NMOS transistor is turned off. When the column selection signal YS[n] is at an L level, the CMOS pass transistor is turned off, the NMOS transistor is turned on, and the column line Y[n] is connected to the GND level.

[0075] Figure 6 (A) is a block diagram showing the internal structure of the row selection / driving circuit 120. The pulse generating circuit 124 generates a rectangular pulse driving signal XD[n] with a controlled pulse width based on the control signal S1 from the control unit 140. When performing a setting write, the pulse generating circuit 124 generates a pulse driving signal XD for applying a setting voltage Vset_X to the variable resistive storage element (the selected variable resistive storage element) that is the object of the setting write, and generates a pulse driving signal XD for applying a write inhibit voltage Vinh to the non-selected variable resistive storage element. When performing a reset write, the pulse generating circuit 124 generates a pulse driving signal XD for applying a reset voltage Vrst_X to the selected variable resistive storage element, and generates a pulse driving signal XD for applying a write inhibit voltage Vinh2 to the non-selected variable resistive storage element. The pulse generating circuit 124 controls the pulse width of the pulse driving signal XD of the set voltage Vset_X, the reset voltage Vrst_X, the write inhibit voltage Vinh, and the write inhibit voltage Vinh2 based on the control signal S1 of the control unit 140 .

[0076] Figure 6(B) is a block diagram showing the internal structure of the column selection / driving circuit 130. The pulse generating circuit 134 generates a rectangular pulse driving signal YD[n] with a controlled pulse width based on the control signal S2 from the control unit 140. When performing a set write, the pulse generating circuit 134 generates a pulse driving signal YD for applying a set voltage Vset_Y to the variable resistive storage element (the selected variable resistive storage element) that is the object of the set write, and generates a pulse driving signal YD for applying a write inhibit voltage Vinh to the non-selected variable resistive storage element. When performing a reset write, the pulse generating circuit 134 generates a pulse driving signal YD for applying a reset voltage Vrst_Y to the selected variable resistive storage element, and generates a pulse driving signal YD for applying a write inhibit voltage Vinh2 to the non-selected variable resistive storage element. The pulse generating circuit 134 controls the pulse width of the pulse driving signal YD of the set voltage Vset_Y, the reset voltage Vrst_Y, the write inhibit voltage Vinh, and the write inhibit voltage Vinh2 based on the control signal S2 of the control unit 140 .

[0077] Next, the setting writing operation of the synapse array device 100 of this embodiment will be described. Figure 7 A portion (3 rows×3 columns) of the crossbar array 110 is shown, and set writing is performed on the variable resistance memory element indicated by oblique lines. The relationship between the coordinate position of the variable resistance memory element to be set writing and the pulse width is as follows.

[0078] XY (coordinate position): P (pulse width) = (2, 0): 3, (1, 0): 2, (0, 0): 1, (2, 1): 1, (1, 1): 3, (1, 2): 1

[0079] For example, a drive signal XD[2] with a pulse width of P3 is applied to the storage elements X[2] and Y[0], a drive signal XD[1] with a pulse width of P2 is applied to the storage elements X[1] and Y[0], and a drive signal XD[0] with a pulse width of P1 is applied to the storage elements X[0] and Y[0]. The pulse widths P3, P2, and P1 are defined by a control signal S1 from the control unit 140.

[0080] Figure 8 The pulse width is controlled in bits. Figure 7 The pulse waveform when the variable resistive memory element is set and written is shown. At time t1, a non-selective bias is applied to the entire array. That is, GND is applied to all row lines X[0], row lines X[1], and row lines X[2], and GND is applied to all column lines Y[0], column lines Y[1], and column lines Y[2]. Here, the voltage Vset_Y = GND.

[0081] At time t2, a write inhibit voltage Vinh is applied to row lines X[0], X[1], X[2] and column lines Y[0], Y[1], Y[2]. The write inhibit voltage Vinh is a voltage lower than the threshold value when the current Icell flows in the selector SEL. Therefore, the setting of the variable resistance element is not written by the write inhibit voltage Vinh.

[0082] At time t3, a pulse drive signal XD[2] of a setting write voltage Vset_X of a pulse width P3 is applied to the row line X[2], and at the same time, a pulse drive signal YD[2] of a setting write voltage Vset_Y (GND) of a pulse width P3 is applied to the column line Y[0]. Vset_X is a voltage higher than the threshold voltage of the selector SEL, and a low resistance state corresponding to the pulse width P3 is stored in the variable resistance element. At time t4 when the pulse width P3 drops, a write inhibit voltage Vinh is applied to the row line X[2], and a write inhibit voltage Vinh is applied to the column line Y[0].

[0083] At time t5, a pulse drive signal XD[1] with a setting write voltage Vset_X of a pulse width P2 is applied to the row line X[1], and a pulse drive signal YD[1] with a setting write voltage Vset_Y (GND) of a pulse width P2 is applied to the column line Y[0]. In synchronization with the time when the pulse width P2 falls, a write inhibit voltage Vinh is applied to the row line X[1] and the column line Y[0]. During this write period, the storage element at the coordinate position (2, 0) is in a low resistance state and is therefore disturbed (the period indicated by the dotted line DT1 in the figure).

[0084] At time t6, a pulse drive signal XD[0] with a setting write voltage Vset_X of a pulse width P1 is applied to the row line X[0], and a pulse drive signal YD[0] with a setting write voltage Vset_Y (GND) of a pulse width P1 is applied to the column line Y[0]. In synchronization with the time when the pulse width P1 drops, a write inhibit voltage Vinh is applied to the row line X[0] and the column line Y[0]. During this write period, the storage elements at the coordinate position (2, 0) and the coordinate position (1, 0) are in a low resistance state and are therefore disturbed (the period indicated by the dotted line DT1 and the dotted line DT3 in the figure).

[0085] Next, at time t7, a pulse drive signal XD[2] having a pulse width P1 and a setting write voltage Vset_X is applied to the row line X[2], and a pulse drive signal YD[1] having a pulse width P1 and a setting write voltage Vset_Y (GND) is applied to the column line Y[1]. At time t8, a pulse drive signal XD[1] having a pulse width P3 and a setting write voltage Vset_X is applied to the row line X[1], and a pulse drive signal YD[1] having a pulse width P3 and a setting write voltage Vset_Y (GND) is applied to the column line Y[1]. By this writing, the storage element at the coordinate position (2, 1) is disturbed during the period represented by DT4. At time t9, a pulse drive signal XD[1] having a pulse width P1 and a setting write voltage Vset_X is applied to the row line X[1], and a pulse drive signal YD[2] having a pulse width P1 and a setting write voltage Vset_Y (GND) is applied to the column line Y[2].

[0086] The above-described writing method performs writing for each storage element, so the current density during writing is minimal, but the writing time depends on the data pattern set to be written.

[0087] On the other hand, the setting writing method provided by this embodiment is Figure 8 The writing method for each storage element is improved, and the column line is used as a common electrode of GND, and writing is performed simultaneously and in parallel on the storage elements in the row direction according to each column. Fig. 9 : shows the pulse waveform when setting writing is performed based on the pulse width control of this embodiment.

[0088] At time t1, a non-selective bias is applied to the entire array. That is, GND is applied to all row lines X[0], row lines X[1], and row lines X[2], and GND is applied to all column lines Y[0], column lines Y[1], and column lines Y[2]. At time t2, a write inhibit voltage Vinh is applied to row lines X[0], row lines X[1], row lines X[2] and column lines Y[0], column lines Y[1], and column lines Y[2].

[0089] At time t3, a pulse drive signal XD[2] with a pulse width of P3 is applied to row line X[2], a pulse drive signal XD[1] with a pulse width of P2 is applied to row line X[1], a pulse drive signal XD[0] with a pulse width of P1 is applied to row line X[0], and a pulse drive signal YD[0] with a set write voltage Vset_Y (GND) is applied to column line Y[0]. The rising edges of the pulse widths P1, P2, and P3 of the pulse drive signal XD applied to the row line are aligned with the falling edges of the voltage Vset_Y of the pulse drive signal YD applied to the column line. In addition, the pulse width of the set write voltage Vset_Y of the pulse drive signal YD is set to the maximum value of the pulse width applied to the row line, or is fixed to the maximum value of the algorithm. In the latter case, the write time becomes constant, which has the advantage of being easy to control for the host controller. Here, the pulse width of the pulse drive signal YD is set to P3.

[0090] During this writing process, the storage elements at coordinates (1, 0) and (0, 0) are disturbed during the periods DT1 and DT2. However, the disturbed period DT1 is P3-P2, and the period DT2 is P3-P1. Figure 8 Compared with the case where writing is performed on each storage element as shown, the disturb time is reduced.

[0091] At the next time t4, a pulse drive signal XD[2] with a pulse width of P1 is applied to the row line X[2], a pulse drive signal XD[1] with a pulse width of P3 is applied to the row line X[1], and a pulse drive signal YD[1] with a pulse width of P3 and a setting write voltage Vset_Y (GND) is applied to the column line Y[1]. Through this writing, the storage element at the coordinate (2, 1) is disturbed during the period represented by DT3, but the period of the disturbance DT3 is P3-P1, so it is the same as Figure 8 The interference can be reduced compared with the previous situation.

[0092] At the next time t5, a pulse drive signal XD[1] with a pulse width of P1 is applied to the row line X[1], and a pulse drive signal YD[2] with a pulse width of P3 and a setting write voltage Vset_Y (GND) is applied to the column line Y[2]. Through this writing, the storage element at the coordinate (1, 2) is disturbed during the period represented by DT4, but the period of the disturbance DT4 is P3-P1, so it is the same as Figure 8 The interference can be reduced compared with the previous situation.

[0093] Thus, according to the write setting method of this embodiment, multiple storage elements are written simultaneously in columns. Therefore, compared with the case of writing according to each storage element, the write time can be shortened, the interference with non-selected storage elements can be reduced, and the change of the resistance value of the storage element can be controlled more accurately.

[0094] According to the embodiment, the writing method synchronizes the rising edge of the pulse of the setting writing voltage Vset_X of the row line with the falling edge of the pulse of the setting writing voltage Vset_Y of the column line, thereby having the advantage of simplifying the circuit structure of the pulse generating circuit 124 and the pulse generating circuit 134. However, this means that the non-selected storage element in the low resistance state (LRS) will be disturbed.

[0095] exist Fig.10 2 shows a further improved writing method of the embodiment, so that the falling edge of the pulse of the setting writing voltage Vset_X of the row line is aligned with the rising edge of the pulse of the setting writing voltage Vset_Y of the column line. The falling edge of the pulse width P3 is aligned with the falling edges of the pulse widths P2 and P1.

[0096] When writing to column line Y[0], at time t3, a set write voltage Vset_X with a pulse width P3 is applied to row line X[2]. During the period represented by DT1 and DT2, row line X[1] and row line X[0] are at write inhibit voltage Vinh, and the storage elements at coordinate position (1, 0) and coordinate position (0, 0) are in high resistance state (HRS). Fig. 9 Similarly, when writing to column line Y[1] and column line Y[2], the non-selected storage element during the period represented by DT3 and DT4 is HRS, so Fig. 9 Compared with the writing method shown, the disturbance to non-selected storage elements can be reduced.

[0097] As described in detail above, according to the present embodiment, in the low voltage write condition, a write inhibit voltage is applied to the non-selected storage element, thereby suppressing interference by using the voltage difference. In addition, the change in the resistance value of the storage element (write level) can be adjusted by using the time based on the pulse width control, and this writing based on the pulse width control can coexist with the control of the cross array. In addition, when the pulses on the discharge side are jointly generated in the column direction and their pulse widths are set to the maximum fixed value, the control of the pulse width of each execution pulse can be achieved by controlling the pulse width on the charging side in the row direction. If the setting writing method provided by the present embodiment is used, it is easy to achieve a subtle change in the resistance value of the setting side of the synapse, and compared with the sequential bit-based writing method, high-speed writing and reduced interference can be achieved.

[0098] In addition, in the synapse array device of the present embodiment, the variable resistance memory element constituting the cross array is used as a synapse, and the control of the binding strength of the synapse is accurately controlled by the pulse duration. It is not easy to compensate the write power in the array structure where a voltage drop is expected, but in the control of the resistance value by the pulse duration, the compensation of the voltage drop in the array is low voltage and low current, so it can be ignored or minimized. In addition, when applied to synapses, the time penalty is not as large as when using a general memory, so the writing method based on the control of the pulse duration is effective.

[0099] In this embodiment, an example of applying a cross array to a synapse array is shown, but the invention is not limited thereto. The writing method of the cross array in this embodiment can also be applied to other devices (eg, memory, arithmetic logic, etc.).

[0100] Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A method for writing to a crossbar array using bipolar variable resistance memory elements, It is characterized in that The writing method applies first writing voltages with different pulse widths to selected row lines of a cross array, and applies a second writing voltage with a controlled pulse width to selected column lines, thereby writing to the selected variable resistance memory element, and controlling the change of the resistance value of the variable resistance memory element during setting writing by controlling the pulse widths of the first writing voltage and the second writing voltage. The pulse width of the second write voltage is set to be the maximum pulse width of the pulse width of the first write voltage.

2. The writing method according to claim 1, in, By applying the first writing voltage to the plurality of row lines, writing is performed on a plurality of variable resistance memory elements at the same time.

3. The writing method according to claim 1, in, The column lines serve as common electrodes that are grounded.

4. The writing method according to claim 1, in, A write-inhibit voltage is applied to unselected row lines and unselected column lines.

5. The writing method according to claim 1, in, A rising edge of a pulse of the first write voltage is aligned with a falling edge of a pulse of the second write voltage.

6. The writing method according to claim 1, in, A falling edge of a pulse of the first write voltage is aligned with a rising edge of a pulse of the second write voltage.

7. An array device, It is characterized in that include: A cross array, wherein variable resistance memory elements are connected to respective intersections of a plurality of row lines and a plurality of column lines; A row selection component for selecting a row line of the cross array; A column selection component selects the column lines of the cross array; as well as a writing means for writing to the variable resistance memory element connected to the row line selected by the row selecting means and the column line selected by the column selecting means, The writing means applies first writing voltages whose pulse widths are controlled to be different to the selected row lines respectively, and applies a second writing voltage whose pulse width is controlled to the column line, so as to write to the selected variable resistance memory element, and controls the change of the resistance value of the variable resistance memory element during setting writing by controlling the pulse widths of the first writing voltage and the second writing voltage, The writing component sets the pulse width of the second writing voltage to be the maximum pulse width of the pulse width of the first writing voltage.

8. The array device according to claim 7, in, The writing means applies the first writing voltage to the plurality of row lines to simultaneously write into the plurality of variable resistance memory elements.

9. The array device according to claim 7, in, The writing means aligns a rising edge of a pulse of the first writing voltage with a falling edge of a pulse of the second writing voltage.

10. The array device according to claim 7, in, The writing means aligns a falling edge of a pulse of the first writing voltage with a rising edge of a pulse of the second writing voltage.

11. The array device according to claim 7, in, Each of the variable resistance memory elements is integrated with a selector that allows a current to flow when a voltage exceeding a threshold value is applied in a forward bias or a reverse bias.

12. The array device according to claim 7, in, The crossbar array is applied to the synaptic array.

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