Integrated circuit structure having an avalanche junction to a doped semiconductor on a semiconductor well

Abstract

The present invention relates to an integrated circuit structure having an avalanche junction to a doped semiconductor on a semiconductor well. Embodiments of the present disclosure provide an integrated circuit (IC) structure comprising a doped well in a semiconductor substrate, and a base region, an emitter region, and a collector region in the doped well. An insulating material is located within the doped well and has a first end horizontally adjacent to the collector region and a second end opposite the first end. A doped semiconductor region is located within the doped well and adjacent to the second end of the insulating material. The doped semiconductor region is positioned across the doped well to define an avalanche junction between the collector region and the doped semiconductor region.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuit (IC) structures. More specifically, various embodiments of the present disclosure provide an IC structure having an avalanche junction to a doped semiconductor over a semiconductor well. Background Art

[0002] Integrated circuits (ICs) may include components for protecting device hardware from the effects of electrostatic discharge (ESD) voltages, which may result in electrical shorts, dielectric breakdown, and / or other failure modes. In an ideal setting, the ESD component has no effect on the operation of the device until an ESD event is seen through a pin on the IC, wherein the ESD event acts as a trigger voltage that turns on the ESD device and releases current to the power rail or ground rail through the ESD component. The ESD component can be designed to adjust its trigger voltage to allow the input voltage to be higher than the power supply voltage without causing excessive leakage through the ESD device at an elevated voltage. As ICs continue to shrink and their size decreases, it may be necessary to reduce the trigger voltage to comply with the manufacturing specifications of the device. However, conventional methods for reducing the trigger voltage can have an undesirable effect, which can increase the holding voltage of the ESD component (i.e., the voltage level to which the device returns after the ESD component stops working). The conventional construction of ESD components and / or other structures cannot provide a lower trigger voltage while keeping the holding voltage constant or reducing the holding voltage. Summary of the Invention

[0003] Some aspects of the present disclosure provide an integrated circuit (IC) structure comprising: a doped well located in a semiconductor substrate, the doped well having a first doping type; a base region located within the doped well and having the first doping type; an emitter region located within the doped well and having a second doping type opposite to the first doping type; a first insulator located within the doped well and horizontally between the base region and the emitter region; a collector region located within the doped well and having the second doping type; a second insulator located within the doped well and horizontally between the collector region and the emitter region; an insulating material located within the doped well, the insulating material having a first end horizontally adjacent to the collector region and a second end opposite to the first end; and a doped semiconductor region located within the doped well and adjacent to the second end of the insulating material, wherein the doped semiconductor region has the first doping type such that an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well.

[0004] Some other aspects of the present disclosure provide an integrated circuit (IC) structure comprising: a first doped well located in a semiconductor substrate and having a first doping type; a base region located within the first doped well and having the first doping type; a second doped well having a first end adjacent to the first doped well and a second end opposite to the first end, the second doped well having a second doping type opposite to the first doping type; a first insulator located within the first doped well and horizontally between the base region and the second doped well; a third doped well adjacent to the second end of the second doped well, the third doped well having the first doping type; an emitter region located within the third doped well, the emitter region having the second doping type; doping type; a second insulator located within the third doped well and horizontally between the emitter region and the second doped well; a collector region located within the third doped well and having the second doping type; a third insulator located within the third doped well and horizontally between the emitter region and the second doped well; an insulating material located within the third doped well, the insulating material having a first end horizontally adjacent to the collector region and a second end opposite to the first end; and a doped semiconductor region located within the third doped well and adjacent to the second end of the insulating material, wherein the doped semiconductor region has the first doping type such that an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well.

[0005] Yet another aspect of the present disclosure provides an integrated circuit (IC) structure comprising: a first doped well located in a semiconductor substrate and having a first doping type; a second doped well located within the first doped well, the second doped well having a second doping type opposite to the first doping type, wherein an upper surface of the second doped well is coplanar with an upper surface of the first doped well; a third doped well located within the first doped well and having the first doping type, wherein an upper surface of the third doped well is coplanar with the upper surface of the second doped well; a base region located within the third doped well and having the first doping type; a collector terminal located within the third doped well and laterally separated from the base region by a first insulator, the collector terminal comprising a first pair of oppositely doped semiconductor regions separated by a first insulating material within the third doped well, such that a first avalanche junction is defined between the first pair of oppositely doped semiconductor regions; and an emitter terminal located within the third doped well and laterally separated from the collector terminal by a second insulator, the emitter terminal comprising a second pair of oppositely doped semiconductor regions separated by a second insulating material within the third doped well, such that a second avalanche junction is defined between the second pair of oppositely doped semiconductor regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other features of the present disclosure will be more readily understood upon consideration of the detailed description of various aspects of the present disclosure taken in conjunction with the accompanying drawings which depict various embodiments of the present disclosure, in which:

[0007] Figure 1 Schematic diagrams of active elements of an integrated circuit (IC) structure connected via electrostatic discharge (ESD) elements according to embodiments of the present disclosure are provided.

[0008] Figure 2 A cross-sectional view of an IC structure according to an embodiment of the present disclosure is shown.

[0009] Figure 3 A cross-sectional view of an IC structure according to another embodiment of the present disclosure is shown.

[0010] Figure 4 A cross-sectional view of an IC structure according to still further embodiments of the present disclosure is shown.

[0011] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0012] In the description herein, reference is made to the accompanying drawings, which form a part of the specification, and in which are shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made within the scope of the present teachings. Therefore, this description is intended to be illustrative only.

[0013] Embodiments of the present disclosure provide an integrated circuit (IC) structure characterized by having an avalanche junction to a doped semiconductor region above a semiconductor well. In some cases, embodiments of the present disclosure can provide an electrostatic discharge (ESD) component in which the avalanche junction provides a bidirectional current path to provide a lower trigger voltage while maintaining substantially the same holding voltage as conventional ESD components. According to one example, embodiments of the present disclosure can include a doped well located in a semiconductor substrate and a base region located in the doped well. The base region and the doped well can have the same doping type. An emitter region having a second doping type opposite to the first doping type can be located in the semiconductor well and separated from the base region by a first insulator. The second insulator in the doped well can separate the emitter region from a collector region having the second doping type. An insulating material adjacent to the collector region can separate the collector region from the doped semiconductor region. A portion of the doped well below the insulating material (also located between the collector and the doped semiconductor region) can provide a diode in the form of an avalanche junction for bidirectionally controlling the current through the IC structure. The voltage applied to the avalanche junction affects whether current can flow between the emitter and the collector.

[0014] A diode is a two-terminal element that behaves differently between two electrical contacts than a conducting or insulating material. Specifically, a diode provides high conductivity from one contact to the other in one direction (i.e., the "forward" direction) and little or no conductivity in the opposite direction (i.e., the "reverse" direction). In the case of a PN junction, the forward and reverse orientations of a diode depend on the type and magnitude of the voltage applied to the material composition of one or both terminals, which affects the size of the potential barrier. In the case of a junction between two semiconductor materials, the potential barrier will form along the interface between the two semiconductor materials.

[0015] Embodiments of the present disclosure use different properties of an "avalanche junction" (also known as an "avalanche diode") to provide bidirectional control of current flowing through an IC structure. An avalanche junction is different from a PN diode and is characterized by having a conductive material adjacent to an insulating material between two terminals. In various embodiments, the size and position of the material can be set to substantially prevent any current from flowing between the two terminals. Applying a voltage to the material may accelerate minority carriers in the insulating material to a point where ionization occurs in the crystal lattice. In turn, the accelerated minority carriers generate more carriers and produce more ionization. This effect is called "avalanche breakdown." In this case, an electrical path can be formed in either direction from one terminal to the other. An avalanche diode is different from other diodes, for example, in that it provides a voltage drop across two terminals that is constant and independent of the amount of current flowing therethrough. Embodiments of the present disclosure use these properties to provide electrical protection features (e.g., ESD elements) in device structures.

[0016] refer to Figure 1 , which shows a schematic diagram of a device 100 according to an embodiment of the present disclosure. Device 100 provides an example configuration in which embodiments of the IC structures discussed in more detail with respect to the other figures may be deployed. Device 100 is configured to react to excess charge and current caused by an ESD event by preventing current from flowing into active components of device 100 (e.g., internal circuitry 102). Input / output (I / O) pads 104 may electrically couple input voltages and / or signals to internal circuitry 102 via any form of wiring. Excess charge generated by an ESD event may be transferred to device 100 via I / O pads 104. A power clamp 106 may be designed to short-circuit such excess charge from a power source to ground. Power clamp 106 may be provided in the form of any conceivable transistor element, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). A set of voltage nodes 108 (generally designated "VDD" for power rails and "VSS" for ground rails, respectively) can carry voltages (e.g., from a battery or other device for driving device 100) to drive power clamp 106. It should be understood that in alternative embodiments, the VDD and VSS designations can be interchanged for the power rails and ground rails. Power clamp 106 is not designed to operate under non-ESD conditions with varying voltages. In particular, power clamp 106 remains dormant during power-up and power-down operations, where voltages may fluctuate. Power clamp 106 will selectively allow current to flow upon detecting an ESD event.

[0017] A set of ESD elements 110 can be coupled between the internal circuit 102 and the power supply / power clamp (hereinafter referred to as "power clamp") 106 to activate the power clamp 106 during an ESD event. The ESD elements 110 can prevent current from flowing from the I / O pads 104 to the power clamp 106 unless or until a trigger voltage is applied to the corresponding terminals of the ESD elements 110. In various other examples, additional circuits and / or current paths can be located between the I / O pads 104 and the ESD elements 110, or between the ESD elements 110 and the power clamp 106, to further control the direction of current to the power clamp 106 during an ESD event.

[0018] Now refer to Figure 2 , embodiments of the present disclosure include the ability to provide an ESD element 110 ( Figure 1) or otherwise implement similar functions. The IC structure 120 may be formed from a substrate 122 comprising, for example, one or more semiconductor materials. The substrate 122 may comprise any currently known or later developed semiconductor material, which may include, but is not limited to, silicon, germanium, silicon germanium, silicon carbide, and a material consisting essentially of one or more semiconductor materials having the chemical formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 A material composed of a III-V compound semiconductor of a defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions, which are respectively greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 is the total relative molar amount). Other suitable substrates include those having a composition of Zn A1 Cd A2 Se B1 Te B2 II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, which are respectively greater than or equal to zero and A1+A2+B1+B2=1 (1 is the total molar amount). In addition, the entire substrate 122 or a portion thereof may be strained.

[0019] Portions of the substrate 122 may include dopants, thereby providing a first doped well 124 having a first doping type. According to one example, the first doping type may be P-type doping. When referring to dopants, a P-type dopant refers to an element introduced into a semiconductor material to create free holes by "accepting" electrons from semiconductor atoms and thereby "releasing" holes. The acceptor atom must have one fewer valence electron than the host semiconductor. P-type dopants suitable for the substrate 122 may include, but are not limited to, boron (B), indium (In), and gallium (Ga). Boron (B) is the most commonly used acceptor in silicon technology. Other alternatives include In and Ga. Ga has a high diffusion rate in silicon dioxide (SiO2), so the oxide cannot serve as a mask during Ga diffusion. The first doped well 124 may be formed in the substrate 122, for example, by vertical ion implantation, such that the upper surface of the first doped well 124 is aligned with and therefore shares a common surface with the upper surface of the substrate 122. Although the first doped well 124 may have the same doping type as the substrate 122, the first doped well 124 may have a higher or lower doping concentration than the substrate 122. Thus, the first doped well 124 may be distinguished from the substrate 122 based at least in part on its doping concentration, dopant material, etc., even if the first doped well 124 and the substrate 122 have the same doping type. The substrate 122 may include other doped wells of the same or different doping types, and these wells are shown separately for clarity purposes only. Figure 2 It should also be understood that the first doped well 124 may be located within and / or adjacent to a guard ring (not shown) that is used to separate the first doped well 124 from the device 100 ( Figure 1 Such a guard ring may take the form of, for example, an oppositely doped region of semiconductor material adjacent to and / or surrounding the first doped well 124.

[0020] The IC structure 120 can be configured to direct current from a "collector" terminal to an "emitter" terminal and, therefore, can include an arrangement of doped semiconductor material within the first doped well 124 that is the same as or similar to a bipolar junction transistor (BJT) architecture. However, the IC structure 120 is not configured to operate as a standard transistor forward biased (e.g., a BJT) because, as described herein, both terminals are coupled to ground. Therefore, the IC structure 120 can include a base region 130 located within the first doped well 124. The base region 130 can have the same doping type as the first doped well 124 (e.g., p-type doping) and, similarly, can be located at an upper surface of the first doped well 124. The base region 130 can have a higher doping concentration than the first doped well 124 and, therefore, can be located at an upper surface of the first doped well 124. Figure 2The base region 130 may be electrically coupled to ground (“GND / VSS”) via a first contact 132 formed of a conductive material (eg, one or more metals formed by deposition, patterning, and / or other processes) on the base region 130 .

[0021] IC structure 120 may also include an emitter region 136 located within first doped well 124. Emitter region 136 may have a second doping type (e.g., N-type doping) that is opposite to the doping type of first doped well 124 and base region 130. Emitter region 136 may be formed by implanting N-type dopants into substrate 122 and / or a precursor semiconductor material using any currently known or later developed technique (e.g., ion implantation). N-type dopants are elements introduced into semiconductor material to generate free electrons, for example, by "donating" electrons to the semiconductor. N-type dopants must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). Second contact 138 may be formed from any conductive material (e.g., one or more metals formed by deposition, patterning, and / or other processes) on emitter region 136. Second contact 138 may electrically couple emitter region 136 to ground GND / VSS, similar to the connection provided by first contact 132.

[0022] A first insulator 140 located within the first doped well 124 may be horizontally positioned between the base region 130 and the emitter region 136 to physically and electrically separate the base region 130 from the emitter region 136. The first insulator 140 may include any conceivable insulating material, such as, but not limited to, silicon nitride (Si3N4); silicon oxide (SiO2); fluorinated SiO2 (FSG); hydrogenated silicon oxycarbide (SiCOH); porous SiCOH; borophosphosilicate glass (BPSG); silsesquioxane; carbon (C)-doped oxides (i.e., organosilicates) including silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) atoms; thermosetting polyarylene ether; SiLK (polyarylene ether available from The Dow Chemical Company); spin-on silicon-carbon-containing polymer materials available from JSR Corporation; other low dielectric constant (<3.9) materials or layers thereof. In one example, the first insulator 140 can take the form of a shallow trench isolation (STI) located within the first doped well 124. STI is an insulating structure formed by etching a trench within a semiconductor material (e.g., the first doped well 124) and filling the trench with an insulating material such as an oxide and / or any other insulator discussed herein. STI can be used to isolate one region of the first doped well 124 from its adjacent regions, for example, isolating the base region 130 from the emitter region 136 as shown. Portions of the first insulator 140 can also be located, for example, near opposite horizontal ends of the base region 130 to further insulate the base region 130 from other materials within the doped well 124.

[0023] IC structure 120 includes a collector region 142 within first doped well 124. Collector region 142 has a second doping type (e.g., N-type doping) within first doped well 124, but is separated from base region 130 and emitter region 136. A collector contact 144 having a conductive material similar to or different from contacts 132, 138 may be located on collector region 142 to electrically couple collector region 142 to device 100 ( Figure 1 ), such as the internal circuit 102. A second insulator 146 located within the first doped well 124 can be horizontally located between the emitter region 136 and the collector region 142. The second insulator 146 can be formed of the same or similar insulating material as the first insulator 140, and in some cases can be STI, as described elsewhere herein.

[0024] To control whether current can flow from active components (e.g., internal circuitry 102) to ground GND / VSS through IC structure 120, additional components may form an avalanche junction 150 with collector region 142. For example, IC structure 120 may include insulating material 152 within first doped well 124, with a first horizontal end S1 of insulating material 152 adjacent to collector region 142. Insulating material 152 may be formed from any conceivable insulating material, and specifically may include one or more layers of nitride material located above first doped well 124. In some cases, insulating material 152 may take the form of a "silicide blocking insulator" or "SAB" material. Such materials may include, for example, silicon nitride insulators and / or less oxidized silicon insulators. Insulating material 152 may be formed using any now known or later developed technique for forming an insulator on a doped semiconductor material (e.g., a combination of etching and deposition performed selectively and / or non-selectively). A second end S2 of insulating material 152 may be adjacent to doped semiconductor region 154 within first doped well 124. The doped semiconductor region 154 may have a first doping type (i.e., the same doping type as the first doped well 124 and the base region 130). In an example configuration, the first doped well 124 may be a continuous doped semiconductor region underlying each of the base region 130, the emitter region 136, the collector region 142, and the doped semiconductor region 154.

[0025] Insulating material 152 can have a depth within first doped well 124 that is significantly less than the depth of collector region 142, or it can be a thin layer deposited above the surface of first doped well 124. In particular, insulating material 152 can be as thin as possible to avoid mechanical stress and other undesirable effects beneath the material. The presence of insulating material above first doped well 124 and between collector region 142 and insulating material 152 can provide an avalanche junction 150, thereby providing a bidirectional diode junction within IC structure 120. As discussed elsewhere herein, applying a voltage to collector region 142 can selectively allow current to flow across avalanche junction 150. To electrically couple doped semiconductor region 154 to a second active component (e.g., power clamp 106 in this example), a fourth contact 156 can be formed on doped semiconductor region 154. Fourth contact 156 can be formed of the same or similar conductive material as contacts 132, 138, 144, or any other currently known or later developed conductive material.

[0026] In this configuration, the internal circuit 102 ( Figure 1) can flow through the IC structure 120 to ground GND / VSS. During operation, a trigger voltage, such as an ESD event, can be applied to the collector region 142 and / or the doped semiconductor region 154. Such a voltage can cause current to flow across the avalanche junction 150, thereby electrically coupling two active components (e.g., the internal circuit 102 and the power clamp 106) through the IC structure 120. Thus, the IC structure 120 can route excess current to ground GND / VSS via the emitter region 136 and the collector region 142 in response to an ESD event. During operation, the IC structure 120 can be configured to have a maximum trigger voltage of approximately 11.0 volts (V) while maintaining a maximum holding voltage of approximately 5.0 V, depending on the doping profile. These trigger and holding voltages can have a wide range, typically ranging from 5 V to 200 V in silicon-based devices.

[0027] Now refer to Figure 3 , further embodiments of the present disclosure may include additional elements, for example, to change the trigger voltage and, therefore, the sensitivity of the IC structure 120 to ESD events. The IC structure 120 may include a substrate 122 having various regions thereon (e.g., a first doped well 124, a base region 130, an emitter region 136, a collector region 142, an avalanche junction 150, an insulating material 152, a doped semiconductor region 154, etc.), as described for other embodiments of the IC structure 120. Here, a second doped well 160 may be adjacent to the first doped well 124. The base region 130 and the first insulator 140 may be formed in the first doped well 124, and the second doped well 160 separates these elements from the rest of the IC structure. The second doped well 160 may have a second doping type (i.e., N-type doping where the first doped well 124 is P-type doping, and vice versa). Although in Figure 3 Not specifically shown, however, the second doped well may alternatively have various additional doped regions (e.g., N+ regions) formed therein, and / or may also be connected to any of the internal circuitry 102, the power clamp 106, GND / VSS, a power rail (not shown), etc.

[0028] The second doped well 160 may not have additional semiconductor regions and / or terminals located therein, and more specifically, may not include any of the base region 130, emitter region 136, collector region 142, and / or doped semiconductor region 154 located therein. A first end T1 of the second doped well 160 may be located adjacent to the first doped well 124, and a second end T2 of the second doped well 160 may be located adjacent to the third doped well 162. The third doped well 162 may have a first doping type (e.g., the same doping type as the first doped well 124). In this configuration, each of the emitter region 136, collector region 142, second insulator 146, insulating material 152, and doped semiconductor region 154 may be formed only within the third doped well 162, rather than within either the first doped well 124 or the second doped well 160.

[0029] In addition to the third insulator 164 positioned horizontally between the emitter region 136 and the collector region 142, the third doped well 162 may also include, for example, a second insulator 146 positioned horizontally between the emitter region 136 and the second doped well 160. This configuration of the IC structure 120 may operate substantially the same as other embodiments discussed herein, but with different trigger voltages and / or holding voltages. Such differences may be due to the additional electrical isolation between the base region 130 and the regions 136, 142 by the second doped well 160. In one example, based on the presence and size of the second doped well 160, the IC structure 120 coupled to the internal circuit 102 and the power clamp 106 may have a trigger voltage of a maximum of approximately 9.5V and a holding voltage of a maximum of approximately 5.0V.

[0030] Steering Figure 4Additional embodiments of the IC structure 120 may include rearranging the doped wells 124, 160 and / or changing the shape of the doped wells 124, 160, changing the amount of insulating material 152, and / or other modifications relative to other IC structure 120 embodiments. In such an example, the first doped well 124 may not include the base region 130, and / or any other doped regions, such as the emitter region 136, the collector region 142, the insulating material 152, and / or the doped semiconductor material 154. However, the first doped well 124 may include at least one externally doped semiconductor material 170, which is so-called because it is located outside the third doped well 162 and is coupled to ground GND / VSS via a fourth contact 172 formed of any currently known or later developed conductive material. The second doped well 160 may be formed entirely within the first doped well 124, and the third doped well 162 may be formed entirely within the second doped well 160. This arrangement of the doped wells 124, 160, 162 is referred to as a "triple well" configuration. Various other regions and / or materials of the IC structure 120 may be formed solely within and / or above the third doped well 162 .

[0031] IC structure 120 may include multiple avalanche junctions (e.g., Figure 4 ), which is different from having only one avalanche junction 150 (e.g., Figure 2 、 3 154). For example, an avalanche junction 150 may be located between the collector region 142 and the doped semiconductor region 154 substantially as provided in other embodiments. The collector region 142 and the doped semiconductor region 154 together provide a pair of oppositely doped semiconductor regions with an insulating material 152 therebetween, thereby defining an avalanche junction 150. The IC structure 120 may also include another region of, for example, insulating material 152 in a third doped well 162, located between one of the doped semiconductor regions 154 and the emitter region 136. Thus, the emitter region 136 and the doped semiconductor region 154 form another pair of oppositely doped semiconductor regions. Here, an active element (e.g., a power clamp 106) may be electrically coupled to each of the emitter region 136 and the doped semiconductor region 154 via one or more third contacts 156. The IC structure 120 remains similar to the other embodiments in other respects. The IC structure 120 may include a first insulator 140 to electrically isolate the base region 130 from other materials. Although in Figure 4Although not specifically shown, additional regions of the first insulator 140 and base region 130 may be formed on the third doped well 162 (e.g., on the left and right sides of the adjacent second doped well 160 in a mirror-image arrangement). The second insulator 146 may electrically isolate the emitter region 136 and the doped semiconductor region 154 of one avalanche junction 150 from other materials. The third insulator 164 may electrically isolate the collector region 142 and the doped semiconductor region 154 from other materials in the third doped well 162. During operation, such an embodiment of the IC structure 120 may feature a maximum trigger voltage of, for example, approximately 9.5 V and a holding voltage of approximately 5.0 V.

[0032] Embodiments of the present disclosure may provide several technical and commercial advantages, some of which are discussed herein by way of example. Figure 1 )) structure: This ESD device has a reduced triggering voltage but a holding voltage similar to other types of ESD devices that do not include the avalanche junction 150. In some cases, placing the doped well contacts outside the N-well (e.g., an N-well ring or an intermediate well) will increase the internal resistance of the IC structure 120, thereby further reducing the triggering voltage. The inclusion of the avalanche junction 150 also enables bipolar current to flow through the IC structure 120, making it suitable for offsetting the effects of various types of ESD events and / or operating settings. Compared to conventional ESD devices and / or operationally similar IC structures, embodiments of the IC structure 120 occupy a similar surface area within a device such as the device 100.

[0033] The descriptions of various embodiments of the present disclosure have been given for purposes of illustration, but are not intended to be exhaustive and / or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art within the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, and / or technical improvements over technologies found in the marketplace, and / or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An integrated circuit (IC) structure, comprising: a doped well in the semiconductor substrate, the doped well having a first doping type; a base region located in the doped well and having the first doping type; an emitter region located within the doped well and having a second doping type opposite to the first doping type; a first insulator located within the doped well and horizontally between the base region and the emitter region; a collector region located in the doped well and having the second doping type; a second insulator located within the doped well and horizontally between the collector region and the emitter region; an insulating material within the doped well, the insulating material having a first end horizontally adjacent to the collector region and a second end opposite the first end; and A doped semiconductor region is located within the doped well and adjacent the second end of the insulating material, wherein the doped semiconductor region has the first doping type such that an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well.

2. The IC structure according to claim 1, wherein: The insulating material includes nitride, and the nitride has a depth below an upper surface of the doped well that is less than a depth of the collector region and a depth of the doped semiconductor region below an upper surface of the doped well.

3. The IC structure according to claim 1 , further comprising: a first contact to the collector region; as well as a second contact to the doped semiconductor region, Wherein each of the base region and the emitter region is coupled to ground.

4. The IC structure according to claim 3, further comprising: a first active element coupled to the collector region via the first contact; as well as a second active element coupled to the doped semiconductor region via the second contact, The IC structure is an electrostatic discharge (ESD) component located between the first active component and the second active component.

5. The IC structure according to claim 4, wherein: The trigger voltage of the ESD element is a maximum of 11.0 volts (V).

6. The IC structure according to claim 5, wherein: The holding voltage of the ESD element is a maximum of 5.0 volts (V).

7. The IC structure according to claim 1, wherein: Each of the first insulator and the second insulator includes a shallow trench isolation (STI) region within the doped well.

8. The IC structure according to claim 1, wherein: The doped well is a continuous doped semiconductor region underlying each of the base region, the emitter region, the collector region, the insulating material, and the doped semiconductor region.

9. An integrated circuit (IC) structure comprising: a first doped well in the semiconductor substrate and having a first doping type; a base region located in the first doped well and having the first doping type; a second doped well having a first end adjacent to the first doped well and a second end opposite the first end, the second doped well having a second doping type opposite to the first doping type; a first insulator located within the first doped well and horizontally between the base region and the second doped well; a third doped well adjacent to the second end of the second doped well, the third doped well having the first doping type; an emitter region within the third doped well, the emitter region having the second doping type; a second insulator located within the third doped well and horizontally between the emitter region and the second doped well; a collector region located in the third doped well and having the second doping type; a third insulator located within the third doped well and horizontally between the emitter region and the collector region; an insulating material within the third doped well, the insulating material having a first end horizontally adjacent to the collector region and a second end opposite the first end; and A doped semiconductor region is located within the third doped well and adjacent to the second end of the insulating material, wherein the doped semiconductor region has the first doping type such that an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well.

10. The IC structure according to claim 9, further comprising: a first contact to the collector region; as well as a second contact to the doped semiconductor region, Wherein, each of the base region and the emitter region is coupled to ground.

11. The IC structure according to claim 10, further comprising: a first active element coupled to the collector region via the first contact; as well as a second active element coupled to the doped semiconductor region via the second contact, The IC structure is an electrostatic discharge (ESD) component located between the first active component and the second active component.

12. The IC structure according to claim 11, wherein: The trigger voltage of the ESD element is a maximum of 9.5 volts (V), and the holding voltage of the ESD element is a maximum of 5.0 volts (V).

13. The IC structure according to claim 9, wherein: The insulating material includes nitride, and the nitride has a depth below an upper surface of the third doped well that is less than a depth of the collector region and a depth of the doped semiconductor region below an upper surface of the third doped well.

14. The IC structure according to claim 9, wherein: The first insulator includes a first shallow trench isolation (STI) within the first doped well, and wherein each of the second insulator and the third insulator includes an STI within the third doped well.

15. An integrated circuit (IC) structure comprising: a first doped well in the semiconductor substrate and having a first doping type; a second doped well within the first doped well, the second doped well having a second doping type opposite to the first doping type, wherein an upper surface of the second doped well is coplanar with an upper surface of the first doped well; a third doped well within the second doped well and having the first doping type, wherein an upper surface of the third doped well is coplanar with the upper surface of the second doped well; a base region located in the third doped well and having the first doping type; an emitter terminal positioned within the third doped well and laterally separated from the base region by a first insulator, the emitter terminal comprising a first pair of oppositely doped semiconductor regions separated by a first insulating material within the third doped well such that a first avalanche junction is defined between the first pair of oppositely doped semiconductor regions; as well as A collector terminal is located within the third doped well and is laterally separated from the emitter terminal by a second insulator, the collector terminal comprising a second pair of oppositely doped semiconductor regions separated by a second insulating material within the third doped well such that a second avalanche junction is defined between the second pair of oppositely doped semiconductor regions.

16. The IC structure of claim 15, further comprising: a first contact coupling the base region to ground; a second contact coupling the emitter terminal to ground; a third contact to the collector terminal; as well as A fourth contact couples the first doped well to ground.

17. The IC structure of claim 15, further comprising: a first active element coupled to one of the pair of oppositely doped semiconductor regions of the collector terminal; as well as a second active element coupled to the other of the pair of oppositely doped semiconductor regions of the emitter terminal, The IC structure is an electrostatic discharge (ESD) component located between the first active component and the second active component.

18. The IC structure according to claim 15, wherein: The trigger voltage of the ESD element is a maximum of 9.5 volts (V), and the holding voltage of the ESD element is a maximum of 5.0 volts (V).

19. The IC structure according to claim 15, wherein: The first insulating material includes a first nitride, which has a depth below the upper surface of the third doped well that is less than the depth of the first pair of oppositely doped semiconductor regions below the upper surface of the third doped well, and wherein the second insulating material includes a second nitride, which has a depth below the upper surface of the third doped well that is less than the depth of the second pair of oppositely doped semiconductor regions below the upper surface of the third doped well.

20. The IC structure of claim 15, wherein: The first insulator includes a first shallow trench isolation (STI) within the third doped well, and wherein the second insulator includes a second STI within the third doped well.

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