Non-volatile memory layout and non-volatile memory

Abstract

The present invention provides a non-volatile memory layout and a non-volatile memory, wherein the non-volatile memory layout includes a control gate layout and a word line layout, wherein the control gate layout includes a plurality of control gate pattern groups, and each control gate pattern group includes two control gate patterns. The gate pattern includes a gate pattern in a straight strip shape and extending along a second direction and a protruding pattern extending from the middle position of the gate pattern, wherein the protruding pattern protrudes from the gate pattern in the first direction and is connected to the gate pattern as a whole, and the two protruding patterns in each control gate pattern group are arranged back to back. The spacing area between the two word line patterns is aligned with the protruding pattern, that is, the spacing area between the word line patterns is close to the back of the protruding pattern, so that the word line structure in the memory is spaced from the protruding portion of the control gate structure, thereby avoiding a short circuit between the protruding portion of the control gate structure and the word line.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a non-volatile memory layout and a non-volatile memory. Background Art

[0002] Flash memory is a safe and fast storage medium. It has become the main carrier of data and programs in embedded systems due to its advantages such as small size, large capacity, low cost, and no data loss during power failure. In recent years, with the rapid development of the smart electronic product market, the use of various MCUs (micro controller units) and SoCs (System-on-Chip) has penetrated into all aspects of daily life such as automotive electronics, industrial control, and medical products. In existing non-volatile memories (NORD flash), the connection structure used to electrically connect two control gates is usually in a Z-shape. As NORD flash devices shrink, the device design rules become smaller and smaller. The existing control gate connection structure is no longer applicable due to process limitations. Summary of the invention

[0003] The object of the present invention is to provide a non-volatile memory layout and a non-volatile memory, so as to increase the process window of the connection structure in the control gate of the non-volatile memory.

[0004] To achieve the above-mentioned object, the present invention provides a non-volatile memory layout, the non-volatile memory layout comprising: a control gate layout, comprising a plurality of control gate pattern groups arranged in parallel along a first direction and extending along a second direction, the first direction being perpendicular to the second direction, each of the control gate pattern groups comprising two control gate patterns in mirror symmetry, wherein the gate pattern comprises a gate pattern in a straight strip shape extending along the second direction and a protruding pattern extending from the middle position of the gate pattern, the protruding pattern protrudes from the gate pattern in the first direction and is connected to the gate pattern as a whole, and the two protruding patterns in each control gate pattern group are arranged opposite to each other;

[0005] A word line layout comprises a plurality of word line pattern groups arranged in parallel along the first direction and extending along the second direction, wherein one word line pattern group is arranged between the two control gate patterns in each control gate pattern group, wherein each word line pattern group comprises two straight strip-shaped word line patterns spaced apart along the second direction, and a spacing area between the two word line patterns is aligned with the protruding pattern.

[0006] Optionally, in the non-volatile memory layout, each of the gate patterns includes a first gate pattern and a second gate pattern arranged in parallel, and the protruding pattern is arranged between the first gate pattern and the second gate pattern and connected to the first gate pattern and the second gate pattern as a whole.

[0007] Optionally, in the non-volatile memory layout, the non-volatile memory layout also includes a contact hole layout, the contact hole layout includes a plurality of contact hole pattern groups, each control gate pattern group is provided with one contact hole pattern group, wherein each contact hole pattern group includes two contact hole patterns, and the two contact hole patterns respectively correspond to the two control gate patterns of the control gate pattern group.

[0008] Optionally, in the non-volatile memory layout, a projection of each of the contact hole patterns on the control gate layout is located within the protruding pattern.

[0009] Optionally, in the non-volatile memory layout, the two contact hole patterns in each contact hole pattern group are staggered in position.

[0010] Optionally, in the non-volatile memory layout, the non-volatile memory layout also includes an active area layout, the active area layout includes at least two active area patterns arranged in parallel along the second direction and extending along the first direction, and each of the word line patterns spans all the active area patterns.

[0011] Optionally, in the non-volatile memory layout, each of the control gate patterns spans across all of the active area patterns.

[0012] Based on the same inventive concept, the present invention also provides a non-volatile memory, wherein the non-volatile memory layout is formed, and the non-volatile memory comprises:

[0013] Semiconductor substrate;

[0014] A plurality of control gate structure groups formed on the semiconductor substrate, the plurality of control gate structure groups are arranged in parallel along a first direction and extend along a second direction, the first direction is perpendicular to the second direction, each of the control gate structure groups comprises two control gate structures in mirror symmetry, wherein each of the control gate structures comprises a gate portion in a straight strip shape and along the second direction and a convex portion extending from a middle position of the gate portion, the convex portion protrudes from the gate portion in the first direction and is connected to the gate portion as a whole, and the two convex portions in each of the control gate pattern groups are arranged opposite to each other;

[0015] A plurality of word line structure groups are formed on the semiconductor substrate, the plurality of word line structure groups are arranged in parallel along the first direction and extend along the second direction, one word line structure group is formed between the two control gate structures of each control gate structure group, wherein each word line structure group includes two straight-bar-shaped word line structures spaced apart along the second direction, and the spacing opening between the two word line structures is aligned with the protruding portion.

[0016] Optionally, in the non-volatile memory, each of the gate portions includes a first gate portion and a second gate portion arranged in parallel, and the protrusion is disposed between the first gate portion and the second gate portion and is connected to the first gate portion and the second gate portion as a whole.

[0017] Optionally, in the non-volatile memory, the non-volatile memory also includes: multiple contact structure groups formed on the multiple control gate structure groups, wherein one contact structure group is formed on each of the control gate structure groups, and each of the contact structure groups includes two contact structures, and the two contact structures respectively correspond to the two control gate structures in the control gate structure group.

[0018] Optionally, in the non-volatile memory, each of the contact structures is located on a protruding portion of a corresponding control gate structure and is electrically connected to the protruding portion.

[0019] Optionally, in the non-volatile memory, the two contact structures in each contact structure group are staggered in position.

[0020] In the non-volatile memory layout and non-volatile memory provided by the present invention, the non-volatile memory layout includes a control gate layout and a word line layout, the control gate layout includes a plurality of control gate pattern groups, each of the control gate pattern groups includes two control gate patterns that are mirror-symmetrical. The gate pattern includes a gate pattern that is in a straight strip shape and extends along the second direction and a protruding pattern extending from the middle position of the gate pattern, the protruding pattern protrudes from the gate pattern in the first direction and is connected to the gate pattern as a whole, and the two protruding patterns in each control gate pattern group are arranged opposite to each other. The word line layout includes a plurality of word line pattern groups, and one word line pattern group is arranged between the two control gate patterns in each control gate pattern group, wherein each word line pattern group includes two word line patterns in a straight strip shape arranged at intervals along the second direction, and the spacing area between the two word line patterns is aligned with the protruding pattern, that is, the spacing area between the word line patterns is close to the back of the protruding pattern, so that the word line structure in the memory can be spaced from the protruding portion of the control gate structure, thereby avoiding a short circuit between the protruding portion of the control gate structure and the word line, and increasing the process window of the protruding portion in the control gate structure. In addition, since the two protruding portions in each control gate structure group are arranged back to back, compared with the prior art, the area occupied by the connection structure (the protruding portion is used as the connection structure) can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 4 is a schematic diagram of a non-volatile memory layout according to an embodiment of the present invention;

[0022] Figure 5-6 is a schematic diagram of the structure of a non-volatile memory according to an embodiment of the present invention;

[0023] The reference numerals are described as follows:

[0024] 110 - control gate pattern group; 111, 112 - control gate patterns; 1111, 1121 - gate patterns; 1111a - first gate pattern; 1111b - second gate pattern; 1112, 1122 - protrusion patterns;

[0025] 120 - word line pattern group; 121, 122 - word line patterns;

[0026] 130 - contact hole pattern group; 131, 132 - contact hole patterns;

[0027] 140-active area pattern;

[0028] 200-semiconductor substrate; 201-shallow trench isolation structure; 202-inter-gate dielectric layer;

[0029] 210 - control gate structure group; 211, 212 - control gate structure; 2111, 2121 - gate portion; 2112, 2122 - raised portion; 2112 - control gate structure; 2111a, 2111b, 2112a, 2112b - gate portion;

[0030] 220 - word line structure group; 220a - spacing opening; 221, 222 - word line structure;

[0031] 230-contact structure group; 231, 232-contact structure. DETAILED DESCRIPTION

[0032] The non-volatile memory layout and the non-volatile memory proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] Figure 1 Schematic diagram of a non-volatile memory layout according to an embodiment of the present invention. Figure 1 As shown, the non-volatile memory layout includes a control gate layout, and the control gate layout is used to form a plurality of control gate structures of the non-volatile memory. The control gate layout includes a plurality of control gate pattern groups 110 arranged in parallel along a first direction Y and extending along a second direction X, wherein the first direction Y is perpendicular to the second direction X, and each of the control gate pattern groups 110 includes two control gate patterns 111 and a control gate 112 that are mirror-symmetrical. Since the control gate patterns 111 and the control gate patterns 112 are mirror-symmetrical, the shapes of the control gate pattern groups 110 can be made consistent.

[0034] like Figure 1 As shown, in this embodiment, the control gate pattern 111 includes a gate pattern 1111 in a straight strip shape and extending along the second direction X, and a protruding pattern 1112 extending from the middle position of the gate pattern 1111. The control gate pattern 112 includes a gate pattern 1121 in a straight strip shape and extending along the second direction X, and a protruding pattern 1122 extending from the middle position of the gate pattern 1121. The gate patterns 111 and 112 are used to form a control gate structure in a non-volatile memory, and the protruding patterns 1112 and 1121 are used to form a protruding portion in the memory to achieve electrical connection between two gate portions.

[0035] Each of the protruding patterns 1122 protrudes from the gate pattern 1121 in the first direction Y and is connected to the gate pattern 1121 as a whole, that is, the control gate pattern 111 is in a convex shape; each of the protruding patterns 1112 protrudes from the gate pattern 112 in the first direction and is connected to the gate pattern 1122 as a whole, that is, the control gate pattern 112 is in a convex shape, that is, the line segments of the gate pattern 1121 and the gate pattern 1121 away from the protruding pattern 1112 are flush line segments. The protruding patterns 1112 and the protruding patterns 1122 in each of the control gate pattern groups 110 are arranged opposite to each other, that is, the positions of the protruding patterns 1112 and the protruding patterns 1122 are located on a straight line parallel to the first direction Y, and the direction in which the protruding patterns 1112 protrude from the gate pattern 1111 is opposite to the direction in which the protruding patterns 1122 protrude from the gate pattern 1121.

[0036] Further, each of the gate patterns 1111 includes a first gate pattern 1111a and a second gate pattern 1111b arranged in parallel, and the protruding pattern 1112 is disposed between the first gate pattern 1111a and the second gate pattern 1111b and is connected to the first gate pattern 1111a and the second gate pattern 1111b as a whole. Each of the gate patterns 1121 includes a first gate pattern and a second gate pattern arranged in parallel, and the protruding pattern 1122 is disposed between the first gate pattern and the second gate pattern and is connected to the first gate pattern and the second gate pattern as a whole. The first gate pattern 1111a and the second gate pattern 1111b are used to form the gate portion (herein, the control gate) of two adjacent storage arrays (cell arrays), and the protruding pattern 1122 is used to form a protruding portion, which can be used as a connecting structure to connect the gate portions (herein, the first gate portion and the second gate portion in the device) of two adjacent storage arrays (cell arrays) and provide a contact area (pickup) for the device.

[0037] In this embodiment, Figure 2As shown, the non-volatile memory layout also includes a word line layout, and the word line layout structure includes a plurality of word line pattern groups 120 arranged in parallel along the first direction Y and extending along the second direction X, and the word line pattern group 120 is used to form a word line structure group in the non-volatile memory. One word line pattern group 120 is arranged between the two control gate patterns 111 and 112 in each control gate pattern group 110. Each word line pattern group 120 includes two word line patterns 121 and 122 spaced apart along the second direction X, and a spacing region A is provided between the word line pattern 121 and the word line pattern 122, and the spacing region A is aligned with the protruding patterns 1112 and 1122. Since the spacing region A is provided between the word line pattern 121 and the word line pattern 122, the process window of the protruding portion of the control gate structure is increased, and a short circuit between the protruding portion of the control gate structure and the word line can be avoided. The size of the protruding portion of the control gate structure in the actual non-volatile memory is reduced, thereby reducing the area occupied by the protruding portion.

[0038] like Figure 3 As shown, in this embodiment, the non-volatile memory layout also includes a contact hole layout structure, and the contact hole layout structure includes a plurality of contact hole pattern groups 130, and each of the control gate pattern groups 110 is provided with one contact hole pattern group 130, wherein each of the contact hole pattern groups 130 includes two contact hole patterns 131 and 132, and the contact hole pattern 131 corresponds to the control gate pattern 111, and the contact hole pattern 132 corresponds to the control gate pattern 112.

[0039] The contact hole patterns 131 and 132 are used to define the position of the contact structure in the memory. Preferably, the contact hole patterns 131 and the contact hole patterns 132 in each contact hole pattern group 130 are staggered in position, so that the contact hole patterns 131 and the contact hole patterns 132 are prevented from being connected together, thereby preventing two adjacent contact structures in the non-volatile memory from being connected together, thereby avoiding a short circuit.

[0040] like Figure 4 As shown, the non-volatile memory layout also includes an active area layout, and the active area layout includes at least two active area patterns 140 arranged in parallel along the second direction X and extending along the first direction Y, and the active area pattern 140 is used to define the position of the active area in the non-volatile memory.

[0041] In this embodiment, each of the control gate patterns 111 and 112 spans across all of the active area patterns 140 , and each of the word line patterns 121 and 122 spans across all of the active area patterns 140 .

[0042] It should be noted that in the layout structure, the patterns of each layer of the layout structure usually use the minimum design rule. Therefore, in this embodiment, the minimum area of ​​a single active region pattern 140 meets the DRC (design rule check) rule.

[0043] Based on the same inventive concept, the present invention also provides a non-volatile memory, which is formed by using the non-volatile memory layout provided by this embodiment.

[0044] Figure 5-6 FIG. 1 is a schematic diagram of the structure of a non-volatile memory according to an embodiment of the present invention. Figure 5 and Figure 6 As shown, the non-volatile memory comprises: a semiconductor substrate 200; a plurality of control gate structure groups 210 formed on the semiconductor substrate 200, wherein the plurality of control gate structure groups 210 are arranged in parallel along a first direction Y and extend along a second direction X, wherein the first direction Y is perpendicular to the second direction X, and here, the first direction Y and the second direction X are both horizontal directions of the semiconductor substrate 200. Each of the control gate structure groups 210 comprises a control gate structure 211 and a control gate structure 212 which are mirror-symmetrical.

[0045] Each of the control gate structures 211 includes a gate portion 2111 in a straight strip shape extending along the second direction X and a protruding portion 2112 extending from the middle of the gate portion 2111, wherein the protruding portion 2112 protrudes from the gate portion 2111 in the first direction Y and is connected to the gate portion 2111 as a whole. Each of the control gate structures 212 includes a gate portion 2121 in a straight strip shape extending along the second direction X and a protruding portion 2122 extending from the middle of the gate portion 2121, wherein the protruding portion 2122 protrudes from the gate portion 2121 in the first direction Y and is connected to the gate portion 2121 as a whole. Among them, the gate portion includes a first gate portion 2112a and a second gate portion 2112b, and the first gate portion 2112a and the second gate portion 2112b can be used as control gates of two adjacent storage arrays (cell arrays). The protrusions 2112 and 2122 are used to connect the control gates of two adjacent storage arrays (cell arrays) (i.e., the first gate portion 2112a and the second gate portion 2112b) to achieve electrical connection between the control gates of the two adjacent storage arrays (cell arrays) and provide a contact area (pickup) for the device.

[0046] The material of the semiconductor substrate 200 is silicon; in other embodiments, the material of the semiconductor substrate 200 may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0047] In this embodiment, the raised portions 2112 and the raised portions 2122 in each of the control gate structure groups 110 are arranged opposite to each other, so that the spacing between the word line structure 221 and the word line structure 222 and the raised portions 2112 and 2122 can be increased, thereby avoiding the short circuit between the raised portions 2112 and the word line structures 221 and 222 of the control gate structure, and increasing the process window of the raised portions 2112 and the raised portions 2122 in the control gate structure. In addition, the process window of the contact structure formed on the raised portions 2112 and 2122 can also be increased to avoid the short circuit between the contact structure and the word line structure. In this embodiment, the material of the control gate structures 211 and 212 can be doped polysilicon.

[0048] In addition, a floating gate layer and an inter-gate dielectric layer 202, as well as a shallow trench isolation structure 201 are formed between the semiconductor substrate 200 and the plurality of control gate structure groups 210, and the shallow trench isolation structure 201 penetrates the floating gate layer and the floating gate oxide layer. The inter-gate dielectric layer 202 includes a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially from bottom to top. In order to better illustrate the non-volatile memory of this embodiment, the description of the floating gate layer and the inter-gate dielectric layer is omitted, and the illustration of the floating gate layer is omitted. In addition, the protrusions 2112 and 2122 are aligned with the shallow trench isolation structure 201.

[0049] like Figure 5 As shown, the non-volatile memory further includes a plurality of word line structure groups 220 formed on the semiconductor substrate 200, the plurality of word line structure groups 220 are arranged in parallel along the first direction Y and extend along the second direction X, wherein each of the word line structure groups 220 includes two straight word line structures 221 and 222 arranged at intervals along the second direction X, a spacing region A is provided between the word line structure 221 and the word line structure 222, and the spacing region A between the word line structure 221 and the word line structure 222 is aligned with the protrusion 2112, that is, the spacing region between the word line structure 221 and the word line structure 222 is close to the back of the protrusion 2112, so that the distance between the contact structure formed on the protrusion and the word line structures 221 and 221 can be increased to avoid short circuit between the word line structures 221 and 222 and the contact structure. The material of the word line structures 221 and 222 in this embodiment is polysilicon.

[0050] In this embodiment, the nonvolatile memory further includes a plurality of contact structure groups 230 formed on the plurality of control gate structure groups 210, wherein one contact structure group 230 is formed on each of the control gate structure groups 210, and the contact structure group 230 includes two contact structures 231 and 232, wherein the contact structure 231 and the contact structure 232 correspond to the control gate structure 2111 and the control gate structure 2112, respectively, that is, the contact structure 231 corresponds to the control gate structure 2111, and the contact structure 232 corresponds to the control gate structure 2112. The contact structures 231 and 232 are made of metal, such as tungsten or copper.

[0051] In a preferred solution, the contact structures 231 and the contact structures 232 of each contact structure group 230 are arranged in staggered positions, so that a short circuit between the contact structures 231 and the contact structures 232 can be avoided.

[0052] In addition, in this embodiment, the non-volatile memory is a NORD flash memory.

[0053] In summary, in the non-volatile memory layout and non-volatile memory provided by the present invention, the non-volatile memory layout includes a control gate layout and a word line layout, the control gate layout includes a plurality of control gate pattern groups, each of the control gate pattern groups includes two control gate patterns that are mirror-symmetrical. The gate pattern includes a gate pattern that is in a straight strip shape and extends along the second direction and a protruding pattern extending from the middle position of the gate pattern, the protruding pattern protrudes from the gate pattern in the first direction and is connected to the gate pattern as a whole, and the two protruding patterns in each control gate pattern group are arranged opposite to each other. The word line layout includes a plurality of word line pattern groups, wherein one word line pattern group is arranged between the two control gate patterns in each control gate pattern group, wherein each word line pattern group includes two straight-strip word line patterns arranged at intervals along the second direction, and the spacing area between the two word line patterns is aligned with the raised pattern, that is, the spacing area between the word line patterns is close to the back of the raised pattern, so that the word line structure in the memory can be spaced from the raised portion of the control gate structure, thereby avoiding a short circuit between the raised portion of the control gate structure and the word line.

[0054] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A non-volatile memory layout, characterized in that: The non-volatile memory layout includes: A control gate pattern, comprising a plurality of control gate pattern groups arranged in parallel along a first direction and extending along a second direction, wherein the first direction is perpendicular to the second direction, and each of the control gate pattern groups comprises two control gate patterns in mirror symmetry, wherein the control gate pattern comprises a gate pattern in a straight strip shape extending along the second direction and a protruding pattern extending from a middle position of the gate pattern, wherein the protruding pattern protrudes from the gate pattern in the first direction and is connected to the gate pattern as a whole, and the two protruding patterns in each of the control gate pattern groups are arranged opposite to each other; A word line layout, comprising a plurality of word line pattern groups arranged in parallel along the first direction and extending along the second direction, wherein one word line pattern group is arranged between the two control gate patterns in each control gate pattern group, wherein each word line pattern group comprises two straight strip-shaped word line patterns spaced apart along the second direction, and a spacing area between the two word line patterns is aligned with the two raised patterns in each control gate pattern group.

2. The non-volatile memory layout according to claim 1, wherein: Each of the gate patterns includes a first gate pattern and a second gate pattern arranged in parallel, and the protruding pattern is disposed between the first gate pattern and the second gate pattern and connected to the first gate pattern and the second gate pattern as a whole.

3. The non-volatile memory layout according to claim 1 or 2, characterized in that: The non-volatile memory layout also includes a contact hole layout, which includes a plurality of contact hole pattern groups, wherein each control gate pattern group is provided with one contact hole pattern group, wherein each contact hole pattern group includes two contact hole patterns, and the two contact hole patterns respectively correspond to the two control gate patterns of the control gate pattern group.

4. The non-volatile memory layout according to claim 3, wherein: The projection of each of the contact hole patterns on the control gate layout is located within the protrusion pattern.

5. The non-volatile memory layout according to claim 4, wherein: The two contact hole patterns in each contact hole pattern group are staggered in position.

6. The non-volatile memory layout according to claim 5, wherein: The nonvolatile memory layout further includes an active area layout, wherein the active area layout includes at least two active area patterns arranged in parallel along the second direction and extending along the first direction, and each of the word line patterns spans across all the active area patterns.

7. The non-volatile memory layout according to claim 6, wherein: Each of the control gate patterns spans across all of the active area patterns.

8. A non-volatile memory, characterized in that: The non-volatile memory is formed by using the non-volatile memory layout according to any one of claims 1 to 7, and the non-volatile memory comprises: Semiconductor substrate; A plurality of control gate structure groups formed on the semiconductor substrate, the plurality of control gate structure groups are arranged in parallel along a first direction and extend along a second direction, the first direction is perpendicular to the second direction, each of the control gate structure groups comprises two control gate structures in mirror symmetry, wherein each of the control gate structures comprises a gate portion in a straight strip shape and extending along the second direction and a protruding portion extending from a middle position of the gate portion, the protruding portion protrudes from the gate portion in the first direction and is connected to the gate portion as a whole, and the two protruding portions in each of the control gate pattern groups are arranged opposite to each other; A plurality of word line structure groups are formed on the semiconductor substrate, the plurality of word line structure groups are arranged in parallel along the first direction and extend along the second direction, one word line structure group is formed between the two control gate structures of each control gate structure group, wherein each word line structure group includes two straight-bar-shaped word line structures spaced apart along the second direction, and the spacing opening between the two word line structures is aligned with the protruding portion.

9. The nonvolatile memory according to claim 8, wherein: Each of the gate portions includes a first gate portion and a second gate portion which are arranged in parallel, and the protrusion is disposed between the first gate portion and the second gate portion and connected to the first gate portion and the second gate portion as a whole.

10. The nonvolatile memory according to claim 9, wherein: The non-volatile memory also includes: a plurality of contact structure groups formed on the plurality of control gate structure groups, wherein one contact structure group is formed on each of the control gate structure groups, and each of the contact structure groups includes two contact structures, and the two contact structures correspond to the two control gate structures in the control gate structure group respectively.

11. The nonvolatile memory according to claim 10, wherein: Each of the contact structures is located on a protruding portion of a corresponding controlled gate structure and is electrically connected to the protruding portion.

12. The nonvolatile memory according to claim 11, wherein: The two contact structures in each contact structure group are staggered in position.

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