Semiconductor structure and method for manufacturing semiconductor structure

Abstract

The present invention relates to the field of semiconductor technology, and proposes a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a substrate; an isolation structure formed in the substrate; and a word line, wherein the word line includes a first convex portion and a second convex portion, wherein the first convex portion and the second convex portion are located in the isolation structure, and the depth of the first convex portion is greater than the depth of the second convex portion. The first convex portion has a longer depth, which can enhance the control ability of the word line on the transistor channel and improve the leakage current.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] As the size of DRAM (Dynamic Random Access Memory) continues to shrink, the size of transistors in the storage area is also shrinking, which brings about serious leakage current problems and affects device performance. Summary of the invention

[0003] The invention provides a semiconductor structure and a method for manufacturing the semiconductor structure to improve the performance of the semiconductor structure.

[0004] According to a first aspect of the present invention, there is provided a semiconductor structure comprising:

[0005] substrate;

[0006] an isolation structure formed in the substrate;

[0007] The word line includes a first convex portion and a second convex portion, wherein the first convex portion and the second convex portion are located in the isolation structure, and the depth of the first convex portion is greater than the depth of the second convex portion.

[0008] In one embodiment of the present invention, the word line further includes a main body portion connected to the first convex portion and the second convex portion.

[0009] In one embodiment of the present invention, there are a plurality of first convex portions and a plurality of second convex portions, and the plurality of first convex portions are spaced apart from the plurality of second convex portions.

[0010] In one embodiment of the present invention, the isolation structure includes a first isolation structure and a second isolation structure; the first convex portion is located in the first isolation structure, the second convex portion is located in the second isolation structure, and the bottom of the first isolation structure is lower than the bottom of the second isolation structure.

[0011] In one embodiment of the present invention, a depth ratio between the first protrusion and the second protrusion is greater than 1.05.

[0012] In one embodiment of the present invention, the depth of the first protrusion is greater than 30 nm.

[0013] In one embodiment of the present invention, the length of the first protrusion along the extending direction of the vertical word line is greater than the length of the second protrusion along the extending direction of the vertical word line.

[0014] In one embodiment of the present invention, the first protrusion comprises:

[0015] A convex lower portion, wherein a side wall of the convex lower portion has a first slope;

[0016] a convex upper portion, wherein a sidewall of the convex upper portion has a second slope;

[0017] The first slope is different from the second slope.

[0018] In one embodiment of the present invention, the sidewall of the second protrusion has a third slope, and the first slope is the same as the third slope.

[0019] In one embodiment of the present invention, the cross section of the convex upper portion along the substrate surface direction is circular or elliptical, and the cross section of the convex lower portion along the substrate surface direction is strip-shaped.

[0020] In one embodiment of the present invention, the strip includes two parallel line segments and two arc-shaped line segments connecting ends of the two line segments.

[0021] In one embodiment of the present invention, a plurality of active regions are disposed in the substrate, and the isolation structure is disposed between the plurality of active regions;

[0022] The main body portion intersects with the active area.

[0023] In one embodiment of the present invention, the plurality of active regions are arranged in a plurality of rows;

[0024] The first isolation structure is located between the ends of the two active regions, and the second isolation structure is located between the sides of the two adjacent active regions.

[0025] According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, comprising:

[0026] Providing a substrate having an isolation structure and a plurality of active regions, wherein the isolation structure is disposed between the plurality of active regions;

[0027] Forming a first groove and a second groove spaced apart from each other on the isolation structure, wherein the depth of the first groove is greater than the depth of the second groove;

[0028] A word line is formed in the substrate. The word line includes a main body, a first convex portion and a second convex portion. The first convex portion and the second convex portion are respectively disposed in the first groove and the second groove.

[0029] In one embodiment of the present invention, forming a first groove and a second groove on an isolation structure includes:

[0030] forming a groove on the isolation structure, wherein the groove is located between ends of two adjacent active regions;

[0031] A first groove and a second groove are formed on the isolation structure having the groove, and the first groove is formed at the position where the groove is located.

[0032] In one embodiment of the present invention, forming a groove on the isolation structure includes:

[0033] Forming a first photoresist layer having a photoresist opening on the substrate, wherein the photoresist opening is located between ends of two adjacent active regions;

[0034] The isolation structure is etched using a photoresist opening to form a groove.

[0035] In one embodiment of the present invention, before forming the first photoresist layer on the substrate, the method further includes:

[0036] forming a word line mask layer having a word line mask opening on the substrate;

[0037] A first photoresist layer is formed on the word line mask layer.

[0038] In one embodiment of the present invention, the word line mask opening has a first dimension perpendicular to its extension direction, and the photoresist opening on the first photoresist layer has a second dimension perpendicular to the word line mask opening extension direction, and the second dimension is greater than the first dimension.

[0039] In one embodiment of the present invention, forming a first groove and a second groove on an isolation structure includes:

[0040] Etching the isolation structure to form a groove using the photoresist opening on the first photoresist layer and the word line mask layer;

[0041] The isolation structure is etched by using the word line mask opening to form a first groove and a second groove.

[0042] The semiconductor structure of the present invention can enhance the control capability of the word line on the transistor channel and improve the leakage current by making the first convex portion of the word line have a longer depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Various objects, features and advantages of the present invention will become more apparent by considering the following detailed description of preferred embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present invention and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0044] Figure 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment;

[0045] Figure 2 yes Figure 1 Schematic diagram of the structure at AA in the middle;

[0046] Figure 3 yes Figure 1 Schematic diagram of the structure at BB in the middle;

[0047] Figure 4is a schematic structural diagram of a first protrusion of a semiconductor structure according to an exemplary embodiment;

[0048] Figure 5 is a schematic structural diagram of a first protrusion of a semiconductor structure according to another exemplary embodiment;

[0049] Figure 6 is a schematic structural diagram of a second protrusion of a semiconductor structure according to an exemplary embodiment;

[0050] Figure 7 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0051] Figure 8 is a schematic structural diagram of a method for manufacturing a semiconductor structure after forming a first photoresist layer according to an exemplary embodiment;

[0052] Fig. 9 is a schematic structural diagram of a method for manufacturing a semiconductor structure after a groove is formed according to an exemplary embodiment;

[0053] Figures 10A-10C is a structural schematic diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0054] Fig.11 It is a schematic structural diagram of a method for manufacturing a semiconductor structure after forming a first groove and a second groove according to an exemplary embodiment.

[0055] The following are the descriptions of the reference numerals:

[0056] 10. Substrate; 11. Active area; 20. First isolation structure; 30. Word line; 31. Main body; 32. First convex part; 33. Second convex part; 321. Convex lower part; 322. Convex upper part; 40. First photoresist layer; 41. Groove; 43. Photoresist opening; 44. Word line mask layer; 231. First groove; 232. Second groove; 45. Word line mask opening; 50. Second isolation structure. DETAILED DESCRIPTION

[0057] Typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments without departing from the scope of the present invention, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present invention.

[0058] In the following description of different exemplary embodiments of the present invention, reference is made to the accompanying drawings, which form a part of the present invention and in which different exemplary structures, systems and steps that can implement various aspects of the present invention are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present invention. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present invention, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present invention.

[0059] An embodiment of the present invention provides a semiconductor structure, please refer to Figures 1 to 6 The semiconductor structure includes: a substrate 10; an isolation structure formed in the substrate 10; a word line 30, wherein the word line 30 includes a first convex portion 32 and a second convex portion 33, wherein the first convex portion 32 and the second convex portion 33 are located in the isolation structure, and the depth of the first convex portion 32 is greater than the depth of the second convex portion 33.

[0060] The semiconductor structure of an embodiment of the present invention can enhance the control capability of the word line 30 over the transistor channel and improve the leakage current by making the first protrusion 32 of the word line 30 have a longer depth than the second protrusion 33. Specifically, the depth of the first protrusion 32 can be understood as the vertical distance from the bottom of the first protrusion 32 to the main body 31 of the word line 30. Similarly, the depth of the second protrusion 33 can be understood as the vertical distance from the bottom of the second protrusion 33 to the main body 31 of the word line 30.

[0061] In one embodiment, the word line 30 further includes a main body 31 , and the main body 31 is connected to the first protrusion 32 and the second protrusion 33 .

[0062] In one embodiment, there are multiple first protrusions 32 and multiple second protrusions 33, and the multiple first protrusions 32 are spaced apart from the multiple second protrusions 33. Specifically, under the same word line 30, the multiple first protrusions 32 and the multiple second protrusions 33 are spaced apart in the isolation structure.

[0063] In one embodiment, the isolation structure includes a first isolation structure 20 and a second isolation structure 50 ; the first protrusion 32 is located in the first isolation structure 20 , the second protrusion 33 is located in the second isolation structure 50 , and the bottom of the first isolation structure 20 is lower than the bottom of the second isolation structure 50 .

[0064] In one embodiment, Figure 1As shown, a plurality of active regions 11 are disposed in the substrate 10 , and the isolation structure is disposed between the plurality of active regions 11 ; wherein the main body 31 intersects with the active region 11 .

[0065] Specifically, an active region 11 is formed in the substrate 10, and isolation structures are filled between adjacent active regions 11. The depths of the isolation structures may be the same or different. Figure 1 It can be seen that the word line 30 crosses a plurality of active regions 11 , that is, the main body 31 intersects the active region 11 .

[0066] In one embodiment, the plurality of active regions 11 are arranged in a plurality of rows, wherein the first isolation structure 20 is located between ends of two adjacent active regions 11 , and the second isolation structure 50 is located between sides of two adjacent active regions 11 .

[0067] Specific, combined Figure 1 , multiple active areas 11 are arranged in multiple rows, and each row is set in parallel, and the word line 30 spans multiple rows of active areas 11, the distance between the sides of two adjacent active areas 11 in two adjacent rows is closer, and the distance between the ends of two adjacent active areas 11 in one row is farther.

[0068] In one embodiment, the depth ratio of the first convex portion 32 to the second convex portion 33 is greater than 1.05. It should be noted that in the related art, the depth dimensions of the convex portions of the word lines are all equal under ideal conditions, that is, when etching the grooves for accommodating the convex portions, the depths of the various grooves should also be the same, but due to the limitations of the etching process, during the specific etching, the depths of the various grooves will basically have small-scale fluctuations (but in terms of the fluctuation value, it can still be considered that the depths of the various grooves are equal), so that the various convex portions will also have corresponding fluctuations. However, in this embodiment, the depth ratio of the first convex portion 32 to the second convex portion 33 is greater than 1.05, which is different from the height difference caused by fluctuations in the related art, and is a semiconductor structure that meets miniaturization and high performance obtained through process control during the manufacturing process. In other embodiments, the depth ratio of the first convex portion 32 to the second convex portion 33 can be greater than 1.1, 1.2, 1.3, 1.4, 1.5 or 1.6.

[0069] In one embodiment, the substrate 10 may be a p-type silicon substrate, an n-type silicon substrate, a silicon germanium substrate, or the like.

[0070] In one embodiment, the depth of the first protrusion 32 is greater than 30 nm. In a specific molding process, the depth ratio of the first protrusion 32 to the second protrusion 33 is determined, and the depth of the second protrusion 33 is determined according to the depth value of the first protrusion 32 .

[0071] In one embodiment, the depth of the second protrusion 33 is less than 25 nm. In the specific molding process, the depth ratio of the first protrusion 32 to the second protrusion 33 is determined, and the depth of the first protrusion 32 is determined according to the depth value of the second protrusion 33 .

[0072] In one embodiment, the length of the first protrusion 32 on the word line 30 along the extending direction perpendicular to the word line 30 is greater than the length of the second protrusion 33 along the extending direction perpendicular to the word line 30 .

[0073] Specifically, the length of the first protrusion 32 on the same word line 30 in the direction perpendicular to the extension of the word line 30 can be understood as follows: the surface where the first protrusion 32 is connected to the main body 31 has a first dimension along the extension direction of the main body 31 and a second dimension perpendicular to the extension direction of the main body 31. Correspondingly, the second protrusion 33 also has a third dimension along the extension direction of the main body 31 and a fourth dimension perpendicular to the extension direction of the main body 31, and the second dimension is larger than the fourth dimension.

[0074] In one embodiment, the first convex portion 32 includes: a convex lower portion 321 , a sidewall of which has a first slope; and a convex upper portion 322 , a sidewall of which has a second slope; wherein the first slope is different from the second slope.

[0075] Combination Figure 4 and Figure 5 For illustration, for example, the side walls of the convex upper portion 322 and the convex lower portion 321 may be the side walls of the convex upper portion 322 and the convex lower portion 321 along the AA section; the first convex portion 32 is composed of the convex lower portion 321 and the convex upper portion 322, and the top of the convex upper portion 322 is connected to the main body portion 31. The first slope is different from the second slope, that is, the inclination of the side wall of the convex lower portion 321 relative to the vertical direction is different from the inclination of the side wall of the convex upper portion 322 relative to the vertical direction, and the side wall of the convex lower portion 321 and the side wall of the convex upper portion 322 are not parallel and are not on the same plane.

[0076] In one embodiment, the first slope is greater than the second slope, that is, the angle between the sidewall of the lower convex portion 321 and the vertical direction is smaller than the angle between the sidewall of the upper convex portion 322 and the vertical direction. When the angle between the sidewall of the lower convex portion 321 and the vertical direction is smaller than the angle between the sidewall of the upper convex portion 322 and the vertical direction, the process difficulty can be reduced and the process window can be increased. Specifically, the angle of the upper convex portion 322 is larger, which is conducive to the formation of the first convex portion of the word line.

[0077] In one embodiment, Figures 4 to 6As shown, the side wall of the second convex portion 33 has a third slope, and the first slope is the same as the third slope, that is, the angle between the side wall of the lower convex portion 321 and the vertical direction is the same as the angle between the side wall of the second convex portion 33 and the vertical direction. Specifically, the grooves at the positions of the lower convex portion 321 and the second convex portion 33 can be formed simultaneously by a one-step etching process, so that the slopes of the side walls of the lower convex portion 321 and the second convex portion 33 filled in the groove are the same, which can simplify the formation steps.

[0078] In one embodiment, a bottom dimension of the convex upper portion 322 is greater than or equal to a top dimension of the convex lower portion 321 .

[0079] like Figure 4 As shown, the top dimension of the convex upper portion 322 is larger than the bottom dimension of the convex upper portion 322, the top dimension of the convex lower portion 321 is larger than the bottom dimension of the convex lower portion 321, and the top dimension of the convex lower portion 321 is the same as the bottom dimension of the convex upper portion 322, that is, the portion where the convex upper portion 322 is connected to the convex lower portion 321 completely overlaps.

[0080] like Figure 5 As shown, the top size of the convex upper part 322 is larger than the bottom size of the convex upper part 322, the top size of the convex lower part 321 is larger than the bottom size of the convex lower part 321, and the top size of the convex lower part 321 is smaller than the bottom size of the convex upper part 322, that is, the portion where the convex upper part 322 is connected to the convex lower part 321 does not completely overlap. In this way, the process window is increased and the risk of direct contact between the convex lower part 321 and the active area is reduced.

[0081] In one embodiment, Figure 6 As shown, the top dimension of the second protrusion 33 is greater than the bottom dimension of the second protrusion 33 , so that the side wall of the second protrusion 33 has a third slope.

[0082] In one embodiment, the cross section of the convex upper portion 322 along the substrate surface direction is circular or elliptical, and the cross section of the convex lower portion 321 along the substrate surface direction is strip-shaped. The specific shapes of the convex upper portion 322 and the convex lower portion 321 can be controlled by the first groove 231 and the second groove 232, which are not limited here and can be selected according to actual needs.

[0083] In one embodiment, the strip includes two parallel line segments and two arc-shaped line segments connecting the ends of the two line segments. The cross section of the convex lower portion 321 is surrounded by two parallel line segments and two opposite arc-shaped line segments. Specifically, the line segments are parallel to the extension direction of the word line 30. The line segment edge of the convex lower portion 321 can reduce the risk of direct contact with the adjacent active area, and the arc-shaped line segment edge can reduce the difficulty of forming the convex lower portion. Specifically, the arc-shaped line segment edge is conducive to the filling of the conductor material.

[0084] An embodiment of the present invention also provides a method for manufacturing a semiconductor structure, such as Figures 7 to 11 As shown, the method for manufacturing a semiconductor structure includes:

[0085] S101, providing a substrate 10 having an isolation structure and a plurality of active regions 11, wherein the isolation structure is disposed between the plurality of active regions 11;

[0086] S103, forming a first groove 231 and a second groove 232 spaced apart from each other on the isolation structure, wherein the depth of the first groove 231 is greater than the depth of the second groove 232;

[0087] S105: forming a word line 30 in the substrate 10; the word line 30 includes a main body 31, a first convex portion 32 and a second convex portion 33; the first convex portion 32 and the second convex portion 33 are disposed in the first groove 231 and the second groove 232, respectively.

[0088] A method for manufacturing a semiconductor structure according to an embodiment of the present invention can effectively improve the leakage current phenomenon of the semiconductor structure by forming a first groove 231 and a second groove 232 on a substrate 10 having an isolation structure and multiple active areas 11, and forming a word line 30 in the substrate 10, and making the first protrusion 32 of the word line 30 have a longer depth.

[0089] It should be noted that if Figure 8 As shown, the provided substrate 10 is a substrate 10 having an isolation structure and a plurality of active regions 11, that is, regardless of the specific forming method of the isolation structure and the plurality of active regions 11, a first groove 231 and a second groove 232 are directly formed on the substrate 10, and a word line 30 is formed. Before forming the first groove 231 and the second groove 232, the substrate 10 may be planarized by dry etching or chemical mechanical polishing (CMP).

[0090] It should be noted that the word line 30 is a buried word line, and the material of the word line 30 includes one or any combination of conductive materials such as tungsten, titanium, nickel, aluminum, platinum, titanium nitride, etc. After the word line 30 is formed, the word line 30 can be planarized by dry etching or chemical mechanical polishing (CMP).

[0091] In one embodiment, forming a first groove 231 and a second groove 232 on an isolation structure includes: forming a groove 41 on the isolation structure, the groove 41 being located between the ends of two adjacent active regions 11; forming a first groove 231 and a second groove 232 on the isolation structure having the groove 41, the first groove 231 being formed at the location where the groove 41 is located. Specifically, a plurality of active regions 11 are arranged in a plurality of parallel rows, the isolation structure is located between the plurality of active regions 11, the isolation structure includes a first isolation structure 20 and a second isolation structure 50, the first isolation structure 20 being located between the ends of two adjacent active regions 11, and the second isolation structure 50 being located between the sides of two adjacent active regions 11. Part of the first isolation structure 20 is etched to form the groove 41, and then the first groove 231 and the second groove 232 are etched on the substrate 10 having the groove 41, and the first groove 231 is etched downward from the location where the groove 41 is located, so as to control the depth of the first groove 231 and the second groove 232, and also ensure that the first groove 231 with a larger depth is etched.

[0092] In one embodiment, forming the groove 41 on the isolation structure includes: forming a first photoresist layer 40 having a photoresist opening 43 on the substrate 10, wherein the photoresist opening 43 is located between the ends of two adjacent active regions 11; and etching the isolation structure using the photoresist opening 43 to form the groove 41. Specifically, the photoresist opening 43 is located above the first isolation structure 20, and a portion of the first isolation structure 20 is etched to form the groove 41.

[0093] In one embodiment, a word line mask layer 44 is formed on the substrate 10 , and a first photoresist layer 40 is located on the word line mask layer 44 . The word line mask layer 44 is first etched using the photoresist opening 43 , and then the first isolation structure 20 is etched using the etched word line mask layer 44 to form a groove 41 .

[0094] In one embodiment, forming a first groove 231 and a second groove 232 on an isolation structure having a groove 41 includes: forming a patterned second photoresist layer on a substrate 10; etching the isolation structure using the patterned second photoresist layer to form the first groove 231 and the second groove 232 on the isolation structure.

[0095] In one embodiment, a gate dielectric layer is formed in the first groove 231 and the second groove 232. The word line 30 is formed by filling the substrate 10 having the first groove 231 and the second groove 232 with one or any combination of conductive materials such as tungsten, titanium, nickel, aluminum, platinum, titanium nitride, etc. The word line 30 can be formed by chemical vapor deposition, physical vapor deposition or other deposition methods.

[0096] The gate dielectric layer may be a film layer based on silicon materials, such as silicon oxide (SiOx), silicon nitride (Si3Nx) and silicon oxynitride (SiON), or a film layer based on high-K materials, such as hafnium (Hf), zirconium (Zr), aluminum oxide (AlOx), etc. According to actual process requirements, at least one or a combination of the materials listed in this embodiment may be selected, and other materials may also be selected, which is not limited here.

[0097] For example, the gate dielectric layer can be obtained by chemical vapor deposition (CVD) process, or by first growing a thin layer of silicon dioxide by ISSG (in-situ steam generation) method, and then growing another thin layer of silicon dioxide by ALD (atomic layer deposition) method to form the gate dielectric layer.

[0098] In one embodiment, Figures 10A to 10C As shown, before forming the first photoresist layer 40 on the substrate 10, the method further includes: forming a word line mask layer 44 having a word line mask opening 45 on the substrate 10; and forming the first photoresist layer 40 on the word line mask layer 44. The first photoresist layer 40 has a photoresist opening 43. Specifically, the plurality of photoresist openings 43 are staggered in an array, and the photoresist opening 43 is located above the first isolation structure 20.

[0099] In one embodiment, the word line mask opening 45 has a first dimension perpendicular to its extension direction, and the photoresist opening 43 has a second dimension perpendicular to the extension direction of the word line mask opening 45, and the second dimension is greater than the first dimension. The word line mask layer 44 can ensure that only the portion of the photoresist opening 43 that falls in the word line mask opening 45 will be etched downward to the isolation structure, so that the size of the first groove 231 formed in the isolation structure is not too large to directly contact the adjacent active area and cause defects.

[0100] In one embodiment, forming a first groove 231 and a second groove 232 on the isolation structure includes: etching the isolation structure to form the groove 41 using the photoresist opening 43 on the first photoresist layer 40 and the word line mask layer 44; etching the isolation structure to form the first groove 231 and the second groove 232 using the word line mask opening 45.

[0101] like Fig. 10A As shown, a substrate having an isolation structure and a plurality of active regions 11 is provided, wherein the isolation structure is arranged between the plurality of active regions 11; Fig. 10B , forming a word line mask layer 44 having a word line mask opening 45; FIG. 10C to FIG. 11As shown, a first photoresist layer 40 is formed on the word line mask layer 44. At this time, the first photoresist layer 40 has a photoresist opening 43. Due to the existence of the word line mask layer 44, after forming the first photoresist layer 40, a groove 41 can be pre-etched on the isolation structure corresponding to the photoresist opening 43, and then the isolation structure is etched using the word line mask layer 44 to form a first groove 231 and a second groove 232. The word line mask layer 44 can prevent the groove 41 formed in the isolation structure from being directly in contact with the adjacent active area due to the excessive size of the photoresist opening 43, and can also serve as an etching mask for the isolation structure and the active area 11, which can simplify the process flow and reduce costs.

[0102] The semiconductor structure formed by the method has a longer first protrusion, which can enhance the control capability of the word line over the transistor channel and reduce the leakage current problem of the semiconductor structure, thereby improving the performance of the semiconductor structure and is suitable for small-size and high-performance DRAM devices.

[0103] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and example embodiments are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the preceding claims.

[0104] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; an isolation structure formed in the substrate; A plurality of active regions are arranged in a plurality of rows in the substrate, and the isolation structure is arranged between the plurality of active regions; a word line, the word line comprises a first convex portion and a second convex portion, wherein the first convex portion and the second convex portion are located in the isolation structure, and the depth of the first convex portion is greater than the depth of the second convex portion; the word line further comprises: a main body portion, the main body portion is connected to the first convex portion and the second convex portion, and the main body portion intersects with the active region; The isolation structure comprises a first isolation structure and a second isolation structure; the first convex portion is located in the first isolation structure, the second convex portion is located in the second isolation structure, and the bottom of the first isolation structure is lower than the bottom of the second isolation structure; The first isolation structure is located between ends of two adjacent active regions, and the second isolation structure is located between sides of two adjacent active regions.

2. The semiconductor structure according to claim 1, characterized in that: There are a plurality of the first convex portions and a plurality of the second convex portions, and the plurality of the first convex portions and the plurality of the second convex portions are arranged at intervals.

3. The semiconductor structure according to claim 1, characterized in that: A depth ratio between the first convex portion and the second convex portion is greater than 1.

05.

4. The semiconductor structure according to claim 1, characterized in that: The depth of the first protrusion is greater than 30 nm.

5. The semiconductor structure according to claim 1, characterized in that: A length of the first protrusion along a direction perpendicular to the word line extending direction is greater than a length of the second protrusion along a direction perpendicular to the word line extending direction.

6. The semiconductor structure according to claim 1, characterized in that The first convex portion comprises: A convex lower portion, wherein a side wall of the convex lower portion has a first slope; a convex upper portion, wherein a sidewall of the convex upper portion has a second slope; The first slope is different from the second slope.

7. The semiconductor structure according to claim 6, characterized in that: The side wall of the second protrusion has a third slope, and the first slope is the same as the third slope.

8. The semiconductor structure according to claim 6, characterized in that: The cross section of the convex upper portion along the substrate surface direction is circular or elliptical, and the cross section of the convex lower portion along the substrate surface direction is strip-shaped.

9. The semiconductor structure according to claim 8, characterized in that: The strip includes two parallel line segments and two arc-shaped line segments connecting ends of the two line segments.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate having an isolation structure and a plurality of active regions, wherein the plurality of active regions are arranged in a plurality of rows, and the isolation structure is disposed between the plurality of active regions; forming a first groove and a second groove spaced apart from each other on the isolation structure, wherein the depth of the first groove is greater than the depth of the second groove; A word line is formed in the substrate, the word line comprising a main body, a first convex portion and a second convex portion, the first convex portion and the second convex portion are respectively arranged in the first groove and the second groove; wherein the first groove and the second groove are formed on the isolation structure, comprising: forming a third groove on the isolation structure, wherein the third groove is located between ends of two adjacent active regions; The first groove and the second groove are formed on the isolation structure having the third groove, the first groove is formed at the location of the third groove, and the second groove is formed between the side portions of two adjacent active regions.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Forming a third groove on the isolation structure, comprising: Forming a first photoresist layer having a photoresist opening on the substrate, wherein the photoresist opening is located between ends of two adjacent active regions; The isolation structure is etched using the photoresist opening to form the third groove.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: Before forming the first photoresist layer on the substrate, the method further includes: forming a word line mask layer having a word line mask opening on the substrate; The first photoresist layer is formed on the word line mask layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The word line mask opening has a first dimension perpendicular to its extension direction, and the photoresist opening on the first photoresist layer has a second dimension perpendicular to the extension direction of the word line mask opening, and the second dimension is greater than the first dimension.

14. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: Forming a first groove and a second groove on the isolation structure, comprising: Etching the isolation structure using the photoresist opening on the first photoresist layer and the word line mask layer to form the third groove; The isolation structure is etched using the word line mask opening to form the first groove and the second groove.

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