A stacked ferroelectric tunnel junction with integrated storage and computing

Abstract

The present invention discloses a storage-computing integrated stacked ferroelectric tunnel junction. The structure of the stacked ferroelectric tunnel junction from bottom to top is: the first layer is a semiconductor substrate, used as a bottom electrode; the second layer is a ferroelectric; the third layer is a metal or a semiconductor, used as an intermediate electrode; the fourth layer is a ferroelectric; the fifth layer is a dielectric; the sixth layer is a metal, used as a top electrode; the bottom electrode and the top electrode are made of different materials, or the two are made of the same material but different thicknesses, or the two are made of different materials and thicknesses. In the device designed by the present invention, all ferroelectric tunnel junctions can be modulated independently, so that logical operations such as "AND", "OR", "NAND", and "NOR" can be realized, and it has a distinct storage-computing integrated characteristic. Moreover, since the ferroelectric tunnel junction switch has low power consumption and no other circuit elements consume energy, the overall power consumption generated by the device during the logical operation process is very low.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a storage-computing integrated stacked ferroelectric tunnel junction. Background Art

[0002] Modern electronic devices are developing rapidly towards intelligence, lightness and portability, but the challenge of intelligent big data processing and the bottleneck of von Neumann computing architecture have become one of the key contradictions in the current electronic information field; at the same time, the power consumption and reliability problems brought about by the miniaturization of device size (the failure of Moore's Law) have further aggravated the rapid deterioration of this contradiction. In recent years, new data-centric computing architectures, such as storage-computing technology, have attracted widespread attention. In the classic von Neumann computing architecture, data storage and processing are separated, and data is stored between the memory and the processor through the data bus. On the one hand, the limited bandwidth of the data bus seriously restricts the performance and efficiency of the processor, and on the other hand, there is a serious performance mismatch between the memory and the processor. The storage-computing technology aims to transform the traditional computing-centric architecture into a data-centric architecture. It directly uses the memory for data processing, thereby integrating data storage and computing in the same chip, which can completely eliminate the bottleneck of the von Neumann computing architecture, and is particularly suitable for large-scale parallel application scenarios such as deep learning neural networks with large amounts of data. With the hardware support of high-efficiency and low-cost intelligent storage-computing integrated chips, as 5G communication and Internet of Things technologies mature, the era of intelligent Internet of Everything is coming.

[0003] In recent years, various non-volatile memories (NRAM), such as resistive random access memory (RRAM), phase change memory (PCM), ferroelectric memory (FeRAM), magnetic random access memory (MRAM), flash memory (Flash), etc., have frequently appeared in major journals. The continuous breakthroughs in NRAM technology have brought new hope for the efficient implementation of storage and computing integration. The resistive storage principle of these non-volatile memories can provide inherent computing power, so data storage and data processing functions can be integrated at the same physical unit address. However, whether the energy efficiency of this storage-computing integrated computing architecture is sufficient to meet the requirements of future computing systems is rarely mentioned. The energy consumption of the storage-computing integrated system mainly comes from two aspects. One is that the resistance conversion process consumes energy, and the other is that other components in the circuit, such as resistors and transistors, will inevitably generate heat loss. How to reduce energy consumption as much as possible is an urgent problem to be solved for the commercial application of storage-computing integrated systems.

[0004] Ferroelectric memory is favored because of its extremely short resistance switching time (~ns) and extremely low power consumption for reading and writing. Traditional ferroelectric memory uses the polarization reversal characteristics of ferroelectrics to store information. The ferroelectric film (~100nm) is sandwiched between two electrodes, and the direction of the residual polarization is controlled by applying electric fields of different polarities between the electrodes. However, the excessive thickness of the ferroelectric film will result in a very small readout current, which seriously limits the miniaturization of the device. Researchers have found that when the thickness of the ferroelectric layer is reduced to a few lattice thicknesses, the tunneling effect of electrons is greatly enhanced and still has ferroelectricity. This heterostructure with ferroelectric ultra-thin film as the barrier layer and electrodes on both sides is called a ferroelectric tunnel junction (FTJ). The ferroelectric tunnel junction has two characteristics: quantum tunneling and resistance reversal. Its tunneling resistance (TER) can be adjusted by changing the polarization direction of the ferroelectric layer and thus changing the height and width of the barrier. There are polarized charges on the surface of ferroelectrics. These polarized charges interact with electrons near the ferroelectric / electrode interface within a certain range. Beyond this range, the influence of polarized charges will be shielded. This range is defined as the shielding length δ. This incomplete shielding will lead to the generation of electrostatic potential P at the interface between the ferroelectric film and the electrode. The size of P is positively correlated with δ. Due to the different shielding capabilities of the electrodes on both sides of the ferroelectric, under the influence of polarized charges at the interface, the barrier heights at the interfaces on both sides will be different, resulting in differences in tunnel junction resistance.

[0005] Complex Boolean logic operations cannot be completed by a single memristor alone, so they often need to be supplemented by peripheral circuits. At present, there are three main circuit structures based on memristor in-memory computing, namely, one memristor and one resistor (1M1R), one memristor and one transistor (1M1T), and one memristor, one transistor and one resistor (1M1T1R). The 1M1R structure is very simple and easy to construct, but the heat generated by the load resistor consumes a lot of energy, and logical operations such as "NAND" and "NOR" cannot be realized. 1M1T is more similar to the CMOS structure, with low static power consumption and excellent logical operation capabilities, but it introduces additional transistor units, which increases the difficulty of preparation and device area. 1M1T1R has excellent dynamic leakage current control capabilities, but it also has problems with power consumption and integration. Therefore, there is an urgent need for a new type of device unit or circuit structure to solve these pain points. Summary of the invention

[0006] In order to further reduce the total power consumption of the circuit during the in-memory computing process, the present invention provides a new integrated memory and computing device based on a stacked ferroelectric tunnel junction, which can realize a variety of logical operations, and the overall power consumption generated during the operation process is very low.

[0007] The technical solution adopted by the present invention is as follows:

[0008] A stacked ferroelectric tunnel junction with integrated storage and computing, whose structure from bottom to top is: the first layer is a semiconductor substrate, used as a bottom electrode; the second layer is a ferroelectric; the third layer is a metal or a semiconductor, used as an intermediate electrode; the fourth layer is a ferroelectric; the fifth layer is a dielectric; the sixth layer is a metal, used as a top electrode; the bottom electrode and the top electrode are made of different materials, or the two are made of the same material but different thicknesses, or the two are made of different materials and thicknesses.

[0009] Preferably, the material of the second layer is BaTiO3, Zr:HfO2 or BiFeO3, and the thickness is 1 to 5 nm.

[0010] Preferably, the thickness of the third layer is 10-30 nm.

[0011] Preferably, the material of the fourth layer is BaTiO3, Zr:HfO2 or BiFeO3, and the thickness is 1 to 5 nm.

[0012] Preferably, the fifth layer has a thickness of 1-3 nm.

[0013] Preferably, the sixth layer has a thickness of 30-50 nm.

[0014] Although the switching power consumption of the ferroelectric memristor itself is extremely low, other memristors or energy-consuming elements such as resistors and capacitors need to be introduced in specific complex logic operation circuits. In order to avoid the introduction of other energy-consuming elements, the present invention proposes to use the FTJ stacking method to integrate two FTJ memristors into the same device. To ensure the correct switching of the high and low levels of the electrode output signal, the stacked FTJ device must meet two conditions: (1) the current switching ratio of FTJ 1 and FTJ 2 is large enough (≥100); (2) the current switching ratio and off-state resistance of FTJ 1 and FTJ 2 are close. Considering the degree of shielding of polarization charges by the electrodes on both sides of the ferroelectric film, in order to meet condition (1), the top and bottom electrodes of FTJ 1 and FTJ 2 should be asymmetrically designed, that is, different electrode materials or different thicknesses are selected. To meet condition (2), the present invention chooses to insert a layer of oxide dielectric film in FTJ 2. The dielectric film has a certain control ability on the current switching ratio performance of FTJ (Ryu, H., Wu, H., Rao, F. et al. Ferroelectric Tunneling Junctions Based on Aluminum Oxide / Zirconium-Doped Hafnium Oxide for Neuromorphic Computing. Sci Rep 9, 20383 (2019)).

[0015] All ferroelectric tunnel junctions in the device of the present invention can be independently modulated, so as to realize logical operations such as "AND", "OR", "NAND", "NOR", etc., and have distinct storage and computing integrated characteristics. Compared with the existing 1M1T structure circuit, the present invention uses a stacked FTJ that only requires a single device, and the degree of integration can be higher. Moreover, the load resistor in the 1M1R structure consumes a lot of energy, which seriously limits the energy utilization efficiency of logical operations. Since the stacked FTJ device of the present invention has low power consumption of the ferroelectric tunnel junction switch and no other circuit elements consume energy, its energy utilization efficiency can theoretically reach 100%. Compared with the 1M1R structure, the energy utilization efficiency is greatly improved and the total power consumption of the circuit is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of the structure of a stacked FTJ device according to an embodiment of the present invention;

[0017] Figure 2 yes Figure 1 Simplified diagram of the device, with the locations of the top electrode (TE), middle electrode (ME), and bottom electrode (BE) marked.

[0018] Figure 3 It is the current switching ratio of FTJ 1 and FTJ 2 of the device of the embodiment of the present invention under ±5V, 100μs pulse stimulation.

[0019] Figure 4 It is the initial state and input and output state truth table of the device of the embodiment of the present invention in the logic operation (a) "AND", (b) "OR", (c) "NAND", and (d) "NOR". DETAILED DESCRIPTION

[0020] The specific structure of the storage and computing integrated stacked ferroelectric tunnel junction of the present invention is as follows from bottom to top: the first layer is a semiconductor substrate, such as Nb:SrTiO3, Si, used as a bottom electrode; the second layer is a ferroelectric, such as BaTiO3, Zr:HfO2, BiFeO3, etc., with a thickness of 1 to 5 nm; the third layer is a metal or semiconductor, such as LaSrMnO3, Pt, Au, etc., used as an intermediate electrode, with a thickness of 10 to 30 nm; the fourth layer is a ferroelectric, such as BaTiO3, Zr:HfO2, BiFeO3, etc., with a thickness of 1 to 5 nm; the fifth layer is a dielectric, such as Al2O3, ZnO, HfO2, etc., with a thickness of 1 to 3 nm; the sixth layer is a metal, such as Pt, Au, etc., used as a top electrode, with a thickness of 30 to 50 nm.

[0021] The stacked ferroelectric tunnel junction of the present invention is based on Pt / Al2O3 / BaTiO3 / La 0.67 Sr 0.33MnO3 / BaTiO3 / Nb:SrTiO3 is taken as an example, where Pt / Al2O3 / BaTiO3 / La 0.67 Sr 0.33 MnO3 forms the first ferroelectric tunnel junction (FTJ 1), La 0.67 Sr 0.33 MnO3 / BaTiO3 / Nb:SrTiO3 forms the second ferroelectric tunnel junction (FTJ 2). BaTiO3 thin film has extremely high stability and good crystal quality, and still has obvious ferroelectricity even when the thickness is reduced to a few nm. Due to the asymmetric design, BaTiO3 / La 0.67 Sr 0.33 The current switching ratio of the MnO3 heterojunction is significantly improved. The appropriate thickness of the Al2O3 dielectric layer makes the switching ratio and off-state resistance (~10MΩ) of the two FTJs almost consistent during resistance switching. The current switching of FTJ 1 and FTJ 2 under ±5V, 100μs pulse stimulation is shown in Figure 2. Figure 3 The structure of this embodiment is designed with three electrodes, namely Pt (top electrode), La 0.67 Sr 0.33 MnO3 (middle electrode), Nb:SrTiO3 (bottom electrode).

[0022] When a positive voltage V is applied to the top electrode SET , when the middle electrode is kept grounded, FTJ 1 will complete the SET process and change from a high resistance state (OFF) to a low resistance state (ON); if a negative voltage -V is applied to the top electrode SET , FTJ 1 will complete the RESET process and change from low resistance to high resistance. Similarly, keep the bottom electrode grounded and apply V to the middle electrode SET / -V SET , which enables FTJ 2 to complete the SET / RESET process.

[0023] This embodiment uses the above structure in logic calculation, selects two electrodes as input A and B, and grounds the remaining electrodes to modulate FTJ 1 and FTJ 2. Then, after applying a read pulse between the top electrode and the bottom electrode, the current (I TB ) to determine whether the device state is "0" or "1". If both FTJs are in a low resistance state, a larger current I TB , at this time it is a logic state "1"; if at least one FTJ is in a high impedance state, then I TB will be significantly smaller, which is the logical state "0".

[0024] Figure 4The computing power of the stacked FTJ device is demonstrated by taking the four logical operations of "AND", "OR", "NAND", and "NOR" as examples. Figure (a) shows the implementation method of the "AND" logic: the initial states of the two FTJs are modulated in the "OFF" state, the top and bottom electrodes are used as input ports A and B respectively, and the middle electrode is grounded. Only when the input terminal A is V SET , input terminal B is -V SET Only when (A=“1”, B=“1”) both FTJs are in the “ON” state, and the output logic state is “1”. For the rest of the input states, the output can only be the logic state “0”. Figure (b) shows the implementation of “OR” logic: FTJ 1 and FTJ 2 are initially modulated to the “ON” state and the “OFF” state, respectively, with the top electrode and the middle electrode as the input terminals A and B, and the bottom electrode grounded. Apply V to either terminal A or B. SET (A = "1", B = "0" or A = "0", B = "1") can make FTJ2 complete the SET process, so that both FTJs are in the "ON" state and the output logic state is "1". Obviously, if V is applied to both ends of A and B at the same time SET (A = "1", B = "1"), FTJ 2 can also complete the SET process, thereby outputting logic "1". Figure (c) shows the implementation method of "NAND" logic: the initial states of FTJ1 and FTJ 2 are pre-modulated to the "ON" state, and the top electrode is used as the input terminal A, and -V can be applied SET / 2 pulse signal, the middle electrode is used as input terminal B, and V SET / 2 pulse signal. Only when these two pulses are applied at the same time (A = "1", B = "1"), FTJ 1 can be turned into the "OFF" state, making the output logic state "0". In other cases, the output logic state is "1". Figure (d) shows the implementation method of "NOR" logic: the initial states of FTJ 1 and FTJ 2 are pre-modulated to the "ON" state, and the top electrode and bottom electrode can be applied with input pulses A (-V SET ) and B(V SET ), the middle electrode is grounded. If no pulse is applied to the A and B ends (A = "0", B = "0"), the two FTJs remain in the "ON" state, and the output logic state is "1"; if a corresponding pulse is applied to either end of A or B or a pulse is applied simultaneously (A = "1" or B = "1"), at least one FTJ can complete the RESET process and turn to the "OFF" state, and the output logic state is "0".

[0025] According to previous research (Xu, H., Xia, Y., Xu, B. et al. Encoding, training and retrieval in ferroelectric tunnel junctions. Sci Rep 6, 27022 (2016)), Pt / BaTiO3 / La 0.67 Sr 0.33 The ferroelectric tunnel junction of MnO3 structure has a switching speed of less than 100ns, a programming pulse of less than 5V, and a current limit of 10 -5 A is below, so the power consumption of a single FTJ switch does not exceed 5pJ. It is worth noting that logical operations such as "AND", "OR", "NAND", and "NOR" can be completed by only a single device, and the total energy consumption of a single operation does not exceed 20pJ.

[0026] This embodiment also provides a method for preparing a metal / dielectric / ferroelectric / semiconductor (metal) / ferroelectric / semiconductor stacked ferroelectric tunnel junction structure, and the selected substrate is a commercial semiconductor single crystal, such as: Nb:SrTiO3, Si, etc. The ferroelectric can be selected from BaTiO3, Zr:HfO2, BiFeO3, etc., and the deposition processes used are pulsed laser deposition, atomic layer deposition, magnetron sputtering, etc. The materials that can be used for the middle electrode are LaSrMnO3, Pt, etc. The dielectric layer is generally selected from Al2O3, HfO2, ZnO, etc., and can be prepared by radio frequency magnetron sputtering and atomic layer deposition processes. The top electrode is generally selected from Pt, Au, Co, etc., and can be prepared by DC magnetron sputtering and electron beam evaporation. The specific material selection needs to comprehensively consider factors such as whether the lattice matches and whether the process is compatible. Specifically, Pt / Al2O3 / BaTiO3 / La 0.67 Sr 0.33 The preparation method is described in detail by taking MnO3 / BaTiO3 / Nb:SrTiO3 as an example.

[0027] First, a single-sided polished, (100)-oriented strontium niobate titanate (Nb:SrTiO3) substrate was selected and treated with acetone, ethanol, deionized water, and buffered oxide etchant. The substrate was then annealed at 950°C in an oxygen atmosphere for 20 minutes. BaTiO3 (3 nm), La 0.67 Sr 0.33 MnO3 (10nm), BaTiO3 (2nm) thin films, laser energy density of 2.5J cm -2The deposition temperature of BaTiO3 film was 780℃ and the oxygen pressure was 10Pa. The deposition temperature of LSMO film was 780℃ and the oxygen pressure was 15Pa. Then the samples were heated at 750℃ and oxygen atmosphere (10 4 Pa) annealing for 20 minutes. Then, an atomic layer deposition process was used to grow a 1.5nm Al2O3 dielectric layer, with trimethylaluminum (Al(CH3)3, TMA) as the aluminum source and O3 as the oxygen source at a growth temperature of 200°C. Finally, a 50nm thick Pt electrode layer was deposited by DC magnetron sputtering, with an argon atmosphere and a pressure of 2Pa.

Claims

1. A storage and computing integrated stacked ferroelectric tunnel junction, characterized in that: The structure of the stacked ferroelectric tunnel junction from bottom to top is: the first layer is a semiconductor substrate, used as a bottom electrode; the second layer is a ferroelectric; the third layer is a metal or a semiconductor, used as an intermediate electrode; the fourth layer is a ferroelectric; the fifth layer is a dielectric; the sixth layer is a metal, used as a top electrode; the bottom electrode and the top electrode are made of different materials, or the two are made of the same material but different thicknesses, or both are made of different materials and thicknesses.

2. The storage-computing integrated stacked ferroelectric tunnel junction according to claim 1, characterized in that: The material of the second layer is BaTiO3, Zr:HfO2 or BiFeO3, and the thickness is 1-5nm.

3. The storage-computing integrated stacked ferroelectric tunnel junction according to claim 1, characterized in that: The thickness of the third layer is 10-30 nm.

4. The storage-computing integrated stacked ferroelectric tunnel junction according to claim 1, characterized in that: The material of the fourth layer is BaTiO3, Zr:HfO2 or BiFeO3, and the thickness is 1-5nm.

5. The storage-computing integrated stacked ferroelectric tunnel junction according to claim 1, characterized in that: The thickness of the fifth layer is 1-3 nm.

6. The storage-computing integrated stacked ferroelectric tunnel junction according to claim 1, characterized in that: The thickness of the sixth layer is 30-50 nm.

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