A filter and a method for preparing the same

Abstract

The present disclosure provides a filter and a preparation method thereof, which belongs to the technical field of radio frequency devices. The present disclosure provides a filter, which includes a first substrate and a second substrate arranged in a stacked manner. Among them, the first substrate includes a first dielectric substrate, and a filter circuit integrated on the first dielectric substrate. The second substrate includes a second dielectric substrate, and the second dielectric substrate includes a first surface and a second surface arranged opposite to each other along its thickness direction, and a switching circuit is arranged on the first surface. The switching circuit is electrically connected to the filter circuit, and a first connecting via hole penetrating through the second dielectric substrate in its thickness direction is arranged on the second dielectric substrate, a signal introduction electrode is arranged in the first connecting via hole, and a first connecting end is arranged on the second surface, one end of the signal introduction electrode is electrically connected to the first connecting end, and the other end is electrically connected to the switching circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency devices, and in particular relates to a filter and a preparation method thereof. Background Art

[0002] In the contemporary era, the consumer electronics industry is developing rapidly. Mobile communication terminals represented by mobile phones, especially 5G mobile phones, are developing rapidly. Mobile phones need to process more and more signal frequency bands, and the number of RF chips required is also rising. The mobile phone forms that are popular with consumers are constantly developing towards miniaturization, lightness, and long battery life. In traditional mobile phones, there are a large number of discrete devices such as resistors, capacitors, inductors, filters, etc. on the RF PCB board. They have the disadvantages of large size, high power consumption, many solder joints, and large changes in parasitic parameters, which are difficult to meet future needs. The interconnection and matching between RF chips require integrated passive devices with small area, high performance, and good consistency. The integrated passive devices on the market are mainly based on Si (silicon) substrates and GaAs (gallium arsenide) substrates. Si-based integrated passive devices have the advantage of low price, but Si itself has trace impurities (poor insulation), which leads to high microwave loss of the device and general performance; GaAs-based integrated passive devices have the advantage of excellent performance, but are expensive. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a filter and a method for preparing the same.

[0004] In a first aspect, the present disclosure provides a filter, comprising a first substrate and a second substrate arranged in a stacked manner; wherein the first substrate comprises a first dielectric substrate, and a filter circuit integrated on the first dielectric substrate; the second substrate comprises a second dielectric substrate, the second dielectric substrate comprises a first surface and a second surface arranged opposite to each other along a thickness direction thereof, a switching circuit is arranged on the first surface; the switching circuit is electrically connected to the filter circuit; wherein a first connecting via hole penetrating the second dielectric substrate in a thickness direction thereof is arranged, a signal introduction electrode is arranged in the first connecting via hole, a first connecting end is arranged on the second surface, one end of the signal introduction electrode is electrically connected to the first connecting end, and the other end is electrically connected to the switching circuit.

[0005] The first dielectric substrate comprises a third surface and a fourth surface arranged opposite to each other along the thickness direction thereof, and a second connecting via arranged along the thickness direction thereof; the filtering circuit comprises at least a first inductor; the first inductor comprises: a first substructure arranged on the third surface of the first dielectric substrate, a second substructure arranged on the fourth surface of the first dielectric layer, and a first connecting electrode arranged in the second connecting via to connect the first substructure and the second substructure in series.

[0006] Wherein, the filtering circuit also includes: a first capacitor; the first capacitor is arranged on the side of the third surface of the first dielectric substrate away from the first dielectric substrate, and includes a first electrode plate, a first interlayer dielectric layer and a second electrode plate arranged in sequence away from the first dielectric substrate.

[0007] Among them, the first substructure includes a first conductive film and a second conductive film; the first conductive film is arranged in the same layer as the first electrode plate of the first capacitor; a second interlayer dielectric layer and a third interlayer dielectric layer are sequentially arranged on the side of the first electrode plate of the first capacitor away from the first dielectric substrate; the second conductive film is arranged on the side of the third interlayer dielectric layer away from the first dielectric substrate; the second conductive film is electrically connected to the first conductive film through a third connecting via that penetrates the second interlayer dielectric layer and the third interlayer dielectric layer.

[0008] Among them, the filtering circuit also includes: a second connecting electrode arranged in the same layer as the second conductive film; the second connecting electrode is electrically connected to the second plate of the first capacitor through a fourth connecting via penetrating the third interlayer dielectric layer; a fourth interlayer dielectric layer and a fifth interlayer dielectric layer are arranged on the side of the second conductive film away from the first dielectric substrate; a first connecting pad and a second connecting pad are arranged on the side away from the fifth interlayer dielectric layer; the first connecting pad is electrically connected to the second connecting electrode through a fifth connecting via penetrating the fourth interlayer dielectric layer and the fifth interlayer dielectric layer; the second connecting pad is electrically connected to the second conductive film through a sixth connecting via penetrating the fourth interlayer dielectric layer and the fifth interlayer dielectric layer.

[0009] Wherein, the first connecting pad and the second connecting pad are respectively welded on the switching circuit.

[0010] Wherein, the filter circuit further includes: a sixth interlayer dielectric layer and a seventh interlayer dielectric layer which are sequentially arranged in a direction away from the fourth surface of the first dielectric substrate.

[0011] Wherein, the switching circuit at least includes: a second capacitor and a second inductor; the first end of the first inductor is electrically connected to one of the signal introduction electrodes, and the second end of the first inductor is connected to the first connecting pad; the first plate of the second capacitor is electrically connected to one of the signal introduction electrodes; the second plate of the second capacitor is connected to the second connecting pad.

[0012] Wherein, the first dielectric substrate and the second dielectric substrate include glass substrates.

[0013] In a second aspect, the present disclosure provides a method for preparing a filter, which includes forming a first substrate and a second substrate in a stacked arrangement; wherein forming the first substrate includes: providing a first dielectric substrate, and integrating a filter circuit on the first dielectric substrate; forming the second substrate includes: providing a second dielectric substrate; the second dielectric substrate includes a first surface and a second surface arranged opposite to each other along its thickness direction, and a switching circuit is formed on the first surface of the second dielectric substrate; the switching circuit is electrically connected to the filter circuit; a first connecting via hole is formed on the second dielectric substrate that penetrates along its thickness direction, and a signal introduction electrode is formed in the first connecting via hole; a first connecting end is formed on the second surface of the second dielectric substrate; one end of the signal introduction electrode is electrically connected to the first connecting end, and the other end is electrically connected to the switching circuit.

[0014] Wherein, the step of forming the first connecting via is before forming the switching circuit.

[0015] The step of forming the first connecting via hole further includes: forming a first connecting blind hole along the thickness direction on the first surface of the second dielectric substrate; and thinning the second dielectric substrate so that the first connecting blind hole forms the first connecting via hole penetrating along the thickness direction thereof.

[0016] The first dielectric substrate includes a third surface and a fourth surface that are arranged opposite to each other; the filter circuit includes at least a first inductor; the step of forming the filter circuit includes: forming a second connecting via hole that penetrates the first dielectric substrate; the step of forming the first inductor includes: forming a first connecting electrode in the second connecting via hole; forming a first substructure on the third surface of the first dielectric substrate; forming a second substructure on the fourth surface of the first dielectric substrate; the first substructure, the second substructure and the first connecting electrode constitute a coil structure of the first inductor.

[0017] The step of forming the second connecting via includes: forming a second connecting blind hole along the thickness direction on the third surface of the first dielectric substrate; and thinning the first dielectric substrate so that the second connecting blind hole forms the second connecting via penetrating along the thickness direction thereof.

[0018] The filtering circuit further includes a first capacitor; the steps of forming the first capacitor include: forming a pattern including a first plate of the first capacitor while forming the first substructure; forming a first interlayer dielectric layer on the side of the first plate of the first capacitor away from the first surface of the first dielectric substrate, so as to be used as the interlayer dielectric layer of the first capacitor; forming a second plate of the first capacitor on the side of the first interlayer dielectric layer away from the first dielectric substrate; and the orthographic projections of the first plate and the second plate of the first capacitor on the first dielectric substrate at least partially overlap.

[0019] The step of forming the first substructure includes: forming a first conductive film and a second conductive film; the first conductive film and the first electrode of the first capacitor are formed in a single patterning process; a second interlayer dielectric layer and a third interlayer dielectric layer are formed on the side of the first conductive film away from the first dielectric substrate, as well as a third connecting via penetrating the second interlayer dielectric layer and the third interlayer dielectric layer, and a fourth connecting via penetrating the third interlayer dielectric layer; the third connecting via at least partially overlaps with the orthographic projection of the first conductive film on the first dielectric substrate; the fourth connecting via at least partially overlaps with the orthographic projection of the second electrode of the first capacitor on the first dielectric substrate; a second conductive film and a second connecting electrode are formed on the side of the third interlayer dielectric layer away from the first dielectric substrate by a single patterning process; the second conductive film is electrically connected to the first conductive film through the third connecting via; and the second connecting electrode is electrically connected to the second electrode of the first capacitor through the fourth connecting via.

[0020] Among them, the step of forming the filter circuit also includes: forming a fourth interlayer dielectric layer and a fifth interlayer dielectric layer, and a fifth connecting via and a sixth connecting via penetrating the fourth interlayer dielectric layer and the fifth interlayer dielectric layer on the side of the second conductive film away from the first dielectric substrate; forming a first connecting pad and a second connecting pad on the side away from the fifth interlayer dielectric layer; the first connecting pad is electrically connected to the second connecting electrode through the fifth connecting via; and the second connecting pad is electrically connected to the second conductive film through the sixth connecting via.

[0021] Wherein, forming the filter circuit further comprises sequentially forming a sixth interlayer dielectric layer and a seventh interlayer dielectric layer on a side of the fourth surface of the first dielectric substrate away from the first dielectric substrate.

[0022] Wherein, the step of electrically connecting the switching circuit with the filtering circuit includes: connecting the first connecting pad and the second connecting pad with the switching circuit respectively through a welding process.

[0023] Among them, forming the switching circuit at least includes forming a second capacitor and forming a second inductor; the first end of the second inductor is electrically connected to one of the signal introduction electrodes, and the second end of the second inductor is connected to the first connecting pad; the first plate of the second capacitor is electrically connected to one of the signal introduction electrodes; the second plate of the second capacitor is connected to the second connecting pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a filter disclosed in the present invention;

[0025] Figure 2 is a top view of a first inductor disclosed in the present invention;

[0026] Figure 3 is a schematic diagram of a filter circuit disclosed in the present invention;

[0027] Figure 4 is a schematic diagram of a first substrate of the present disclosure;

[0028] Figure 5 is a flow chart of the preparation of the filter disclosed in the present invention;

[0029] Figure 6 is a flowchart of step S1 of an embodiment of the present disclosure;

[0030] Figure 7 is a schematic diagram of step S10 of an embodiment of the present disclosure;

[0031] Figure 8 is a schematic diagram of step S11 of an embodiment of the present disclosure;

[0032] Fig. 9 is a schematic diagram of step S12 of an embodiment of the present disclosure;

[0033] Fig.10 is a schematic diagram of step S13 of an embodiment of the present disclosure;

[0034] Fig.11 is a schematic diagram of step S14 of an embodiment of the present disclosure;

[0035] Fig.12 is a schematic diagram of step S15 of an embodiment of the present disclosure;

[0036] Fig.13 is a schematic diagram of step S16 of an embodiment of the present disclosure;

[0037] Fig.14 is a schematic diagram of step S17 of an embodiment of the present disclosure;

[0038] Fig.15 A schematic diagram of another method for preparing the filter circuit according to an embodiment of the present disclosure;

[0039] Fig.16 is another flowchart of step S1 of an embodiment of the present disclosure;

[0040] Fig.17 is a schematic diagram of step S20 of an embodiment of the present disclosure;

[0041] Fig.18 is a schematic diagram of step S21 of an embodiment of the present disclosure;

[0042] Fig.19 is a schematic diagram of step S22 of an embodiment of the present disclosure;

[0043] Fig. 20 is a flowchart of step S2 of an embodiment of the present disclosure;

[0044] Fig.21 is a schematic diagram of step S30 of an embodiment of the present disclosure;

[0045] Fig. 22 is a schematic diagram of step S31 of an embodiment of the present disclosure;

[0046] Fig.23 is a schematic diagram of step S32 of an embodiment of the present disclosure;

[0047] Fig.24 is a schematic diagram of step S33 of an embodiment of the present disclosure;

[0048] Fig.25 is a schematic diagram of step S34 of an embodiment of the present disclosure;

[0049] Fig.26 is a schematic diagram of step S35 of an embodiment of the present disclosure;

[0050] Fig. 27 is a schematic diagram of step S36 of an embodiment of the present disclosure;

[0051] Fig.28 is a schematic diagram of step S37 of an embodiment of the present disclosure;

[0052] Fig.29 is a schematic diagram of another step S2 of an embodiment of the present disclosure;

[0053] Fig.30 is a schematic diagram of step S40 of an embodiment of the present disclosure;

[0054] Fig.31 is a schematic diagram of step S41 of an embodiment of the present disclosure;

[0055] Fig.32 is a schematic diagram of step S42 of an embodiment of the present disclosure;

[0056] Fig.33Schematic diagram of step S3 of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0058] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0059] The present invention provides a filter and a method for preparing the same. Figure 1 As shown, the filter includes a first substrate 1 and a second substrate 2 which are stacked. The first substrate 1 includes a first dielectric substrate 3 and a filter circuit integrated on the first dielectric substrate 3. The second substrate 2 includes a second dielectric substrate 4, and the second dielectric substrate 4 includes a first surface and a second surface which are arranged opposite to each other along its thickness direction. A switching circuit is arranged on the first surface, and the switching circuit is electrically connected to the filter circuit. The second dielectric substrate 4 is provided with a first connecting via 5 which passes through the second dielectric substrate 4 in its thickness direction, a signal introduction electrode 7 is arranged in the first connecting via 5, and a first connecting terminal 8 is arranged on the second surface, one end of the signal introduction electrode 7 is electrically connected to the first connecting terminal 8, and the other end is electrically connected to the switching circuit.

[0060] In the embodiments of the present disclosure, continue to refer to Figure 1, the filter circuit on the first dielectric substrate 3 is connected to the switching circuit arranged on the first surface of the second dielectric substrate 4 by means including but not limited to welding, that is, the filter circuit is connected to some components in the switching circuit to realize the electrical connection between the filter circuit and the switching circuit. The first connection terminal 8 on the second surface of the second dielectric substrate 4 is electrically connected to the switching circuit through the signal introduction electrode 7 arranged in the first connection via 5 that penetrates the second dielectric substrate 4 along its thickness direction, wherein the first connection terminal 8 can be including but not limited to a solder ball. In this way, the first substrate 1 with the filter circuit and the second substrate 2 with the switching circuit form a laminated structure, and the signal connection electrode electrically connected to the first connection terminal 8 and the formed laminated structure writes the electrical signal required when the filter is working into the circuit composed of the filter circuit and the switching circuit. In this way, a three-dimensional packaging structure of the filter is realized, and the number of peripheral circuit routings is reduced, and signal distortion and loss are reduced. In addition, the miniaturization of the packaged device is realized, and the difficulty of the preparation process is reduced.

[0061] Meanwhile, in the embodiment of the present disclosure, the first dielectric substrate 3 may have a plurality of filter circuits. Figure 1 The structure shown is only described by taking a filter circuit as an example. The switching circuit on the first surface of the second dielectric substrate 4 includes at least passive components such as inductors, capacitors and resistors. The circuit structure in the switching circuit can be specifically adjusted according to the specific structure and number of the filter circuits connected thereto. In the embodiment disclosed herein, only part of the capacitors and part of the inductors in the switching circuit are described. Therefore, in this way, the switching circuit on the second dielectric substrate 4 can integrate the required external circuits therein, reduce the number of circuit traces, so as to reduce signal distortion and loss while improving the utilization rate of the second dielectric substrate 4. On the other hand, according to specific needs, the switching circuit can process signals between multiple filter circuits connected thereto, further simplify the structure of the filter, and reduce the difficulty and cost of its preparation. The filter structure of the embodiment disclosed herein is described in detail below.

[0062] In some embodiments, the first dielectric substrate 3 and the second dielectric substrate 4 include, but are not limited to, any one of a glass substrate, a flexible substrate, and an interlayer dielectric layer including at least an organic insulating layer. Since integrated circuits on a glass substrate have the advantages of small size, light weight, high performance, and low power consumption, in the embodiments of the present disclosure, the first dielectric substrate 3 and the second dielectric substrate 4 are glass substrates.

[0063] In some embodiments, continue to refer to Figure 1The first dielectric substrate 3 includes a third surface and a fourth surface arranged opposite to each other in the thickness direction and a second connecting via 6 arranged in the thickness direction. A first connecting electrode 11 is arranged in the second connecting via 6, a first substructure 9 is formed on the third surface of the first dielectric substrate 3, and a second substructure 10 is formed on the fourth surface of the first dielectric substrate 3. The first substructure 9, the first connecting electrode 11 and the second substructure 10 are connected in series to form a first inductor L1 in the filter circuit. Figure 2 , the specific structure of the first inductor L1 is described.

[0064] Figure 2 is a top view of the first inductor L1 of the embodiment of the present disclosure, referring to Figure 2 , each first substructure 9 of the first inductor L1 extends along the first direction and is arranged side by side along the second direction. Each second substructure 10 of the first inductor L1 extends along the third direction and is arranged side by side along the second direction. Among them, the first direction, the second direction, and the third direction are all different directions. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are arranged non-perpendicularly. Of course, the extension directions of the first substructure 9 and the second substructure 10 can also be interchanged, both within the protection scope of the embodiment of the present disclosure. In addition, in the present embodiment, the first inductor L1 includes N first substructures 9 and N-1 second substructures 10 as an example for explanation, wherein N≥2, and N is an integer. The first end and the second end of the first substructure 9 respectively overlap with the orthographic projection of a first connecting via 5 on the first dielectric substrate 3 at least partially. And the first end and the second end of a first substructure 9 correspond to different first connecting vias 5, that is, the orthographic projection of a first substructure 9 and two first connecting vias 5 on the first dielectric substrate 3 at least partially overlap. At this time, the first end of the i-th second substructure 10 of the first inductor L1 is connected to the first end of the i-th first substructure 9 and the second end of the i+1-th first substructure 9 to form an inductor coil, where 1≤i≤N-1, and i is an integer.

[0065] It should be noted that the first lead terminal 37 is connected to the second end of the first first substructure 9 of the inductor, and the second lead terminal 38 is connected to the first end of the Nth first substructure 9. Further, the first lead terminal 37 and the second lead terminal 38 can be arranged in the same layer as the second substructure 10 and made of the same material. In this case, the first lead terminal 37 can be connected to the second end of the first first substructure 9 through the first connecting via 5, and correspondingly, the second lead terminal 38 can be connected to the first end of the Nth first substructure 9 through the first connecting via 5.

[0066] In this way, a first inductor L1 having a three-dimensional structure is formed on a first dielectric substrate 3 whose material is glass-based, so that the first inductor L1 has a higher quality factor Q, and the performance of the filter circuit having the first inductor L1 is better. It should also be noted that the first dielectric substrate 3 may include one or more inductors having the structure of the first inductor L1, and multiple first inductors L1 may form a series or parallel structure according to the specific circuit performance requirements. In the embodiment of the present disclosure, only the first inductor L1 is used as an example for explanation. For those skilled in the art, it is easy to think that the filter circuit has multiple inductors having the same structure as the first inductor L1, and therefore it is also within the protection scope of the present disclosure.

[0067] In some embodiments, Figure 3 As shown, the filter circuit also includes a first capacitor arranged on the side of the third surface of the first dielectric substrate 3 away from the first dielectric substrate 3. The first capacitor includes a first plate, a first interlayer dielectric layer 12 and a second plate, which are sequentially arranged on the side of the third surface of the first dielectric substrate 3 away from the first dielectric substrate 3. The capacitor structure of the first capacitor is formed in this way, so that the first capacitor is electrically connected to the first inductor L1 in the filter circuit to achieve the filtering function of the circuit. It should also be noted that the first dielectric substrate 3 may include one or more capacitors with a first capacitor structure, and multiple first capacitors may form a series or parallel structure according to specific circuit performance requirements. In the embodiment of the present disclosure, only the first capacitor is used as an example for explanation. For those skilled in the art, it is easy to think that the filter circuit has multiple capacitors with the same first capacitor structure, so it is also within the protection scope of the present disclosure.

[0068] Continue to refer to Figure 3 In some embodiments, the first substructure 9 may include a first conductive film 91 and a second conductive film 92. The first conductive film 91 is disposed in the same layer as the first electrode of the first capacitor, and the first conductive film 91 is electrically connected to the first electrode of the first capacitor. A second interlayer dielectric layer 14 and a third interlayer dielectric layer 15 are sequentially disposed on the side of the first electrode of the first capacitor away from the first dielectric substrate 3. The second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 are used as an interlayer insulating layer and a planarization layer, respectively, to prevent conduction between interlayer metal layers and to prevent water and oxygen corrosion. The second conductive film 92 is disposed on the side of the third interlayer dielectric layer 15 away from the first dielectric substrate 3. The second conductive film 92 is electrically connected to the first conductive film 91 through a third connecting via penetrating the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15, so as to realize the structure of the first inductor L1 on the third surface of the first dielectric layer.

[0069] like Figure 4As shown, in some embodiments, the filter circuit further includes a second connection electrode 16 disposed in the same layer as the second conductive film 92, and the second connection electrode 16 penetrates the fourth connection via of the third interlayer dielectric layer 15 and is electrically connected to the second electrode plate 13 of the first capacitor, and is used as a connection electrode of the first capacitor. A fourth interlayer dielectric layer 17 and a fifth interlayer dielectric layer 18 are sequentially disposed on the side of the second conductive film 92 away from the first dielectric substrate 3, which are used as a protective layer and a planarization layer. A first connection pad 19 and a second connection pad 20 are disposed on the side of the fifth interlayer dielectric layer 18 away from the third interlayer dielectric layer 15, and the first connection pad 19 is electrically connected to the second connection electrode 16 through a fifth connection via 21 penetrating the fourth interlayer dielectric layer 17 and the fifth interlayer dielectric layer 18. The second connection pad 20 is electrically connected to the second conductive film 92 through a sixth connection via 22 penetrating the fourth interlayer dielectric layer 17 and the fifth interlayer dielectric layer 18. The first connection pad 19 and the second connection pad 20 are used as signal input terminals of the filter circuit to input or transmit the corresponding electrical signal to the filter circuit. In some embodiments, the filter circuit can be welded to the other sub-circuits by welding process, such as welding the filter circuit to the connection circuit in the embodiment of the present disclosure. In some embodiments, in order to make it easier to arrange the first connection pad 19 and the second connection pad 20 on the fifth interlayer dielectric layer 18, the material of the fifth interlayer dielectric layer 18 can be a photosensitive organic material.

[0070] Continue to refer to Figure 4 In some embodiments, the filter circuit further includes a sixth interlayer dielectric layer 23 and a seventh interlayer dielectric layer 24 disposed on the fourth surface of the first dielectric substrate 3 and away from the first dielectric substrate 3. The sixth interlayer dielectric layer 23 and the seventh interlayer dielectric layer 24 are used as a protective layer and a planarization layer to protect the second substructure 10 from being corroded by water and oxygen during the manufacturing and use process.

[0071] Continue to refer to Figure 4In some embodiments, the switching circuit in the disclosed embodiment includes at least a second capacitor and a second inductor L2; the first end of the first inductor L1 is electrically connected to a signal introduction electrode 7, and the second end of the first inductor L1 is connected to the first connection pad 19; the first plate 25 of the second capacitor is electrically connected to a signal introduction electrode 7; the second plate 26 of the second capacitor is connected to the second connection pad 20. In this way, the switching circuit writes an electrical signal transmitted by a signal introduction electrode 7 into the filter circuit via the first connection pad 19 and writes an electrical signal transmitted by another signal introduction electrode 7 into the filter circuit via the second connection pad 20, so as to complete the introduction of the electrical signal into the filter circuit through the signal introduction electrode 7. On the other hand, the switching circuit can be adjusted according to the actual needs of the filter circuit and the filter to effectively process the signal between the circuits electrically connected to the switching circuit. In this way, the external wiring is reduced, the signal loss is reduced, and the filter packaging is miniaturized. It should be noted that the switching circuit in the embodiment of the present disclosure includes at least the second capacitor and the second inductor L2. It is conceivable that the switching circuit also includes other inductors or capacitors to achieve its function. The embodiment of the present disclosure only takes the second capacitor and the second inductor L2 as an example for description.

[0072] Continue to refer to Figure 4 In some embodiments, the second inductor L2 in the switching circuit includes at least a planar laminated inductor and a planar spiral inductor. The second capacitor includes a first plate, an eighth interlayer dielectric layer 27 and a second plate, which are sequentially arranged on the first surface side away from the second dielectric substrate 4, wherein the eighth interlayer dielectric layer 27 is used as an interlayer dielectric layer of the second capacitor, and the first plate 25 of the second capacitor is electrically connected to a signal introduction electrode 7.

[0073] Continue to refer to Figure 4 In some embodiments, the switching circuit further includes: a third connection electrode 28 disposed on the first surface side away from the second dielectric substrate 4, the third connection electrode 28 is disposed in the same layer as the first plate 25 of the second capacitor, and is electrically connected to a signal introduction electrode 7. A ninth interlayer dielectric layer 29 and a tenth interlayer dielectric layer 30 are also disposed in sequence on the first surface side away from the second dielectric substrate 4. It is used as an interlayer insulation and planarization layer to prevent conductivity between interlayer metal layers and prevent water and oxygen corrosion. A fourth connection electrode 31 and a second inductor L2 are disposed on the tenth interlayer dielectric layer 30 away from the second dielectric substrate 4. The fourth connection electrode 31 is electrically connected to the second plate 26 of the second capacitor through the seventh connection via penetrating the tenth interlayer dielectric layer 30, and is used as a connection electrode of the second capacitor. The first end of the second inductor L2 is electrically connected to the third connection electrode 28 through the eighth connection via 33 penetrating the ninth interlayer dielectric layer 29 and the tenth interlayer dielectric layer 30.

[0074] Continue to refer to Figure 4 In some embodiments, the switching circuit further includes an eleventh interlayer dielectric layer 32 disposed on the tenth interlayer dielectric layer 30 on a side away from the second dielectric substrate 4, and used as a planarization layer. The eleventh interlayer dielectric layer 32 is provided with an eighth connection via 33 and a ninth connection via 34 penetrating the eleventh interlayer dielectric layer 32. The eighth connection via 33 at least partially overlaps with the orthographic projection of the second end of the second inductor L2 on the second dielectric substrate 4, and the ninth connection via 34 at least partially overlaps with the orthographic projection of the fourth connection electrode 31 on the second dielectric substrate 4. In this way, the first connection pad 19 and the second connection pad 20 in the filter circuit are electrically connected to the switching circuit through the eighth connection via 33 and the ninth connection via 34 by a welding process.

[0075] The structural parameters of each device in the filter of the embodiment of the present disclosure are explained one by one in the following preparation method, so they will not be described in detail here.

[0076] The present disclosure provides a method for preparing a filter, and the filter may be the above-mentioned filter, such as Figure 5 As shown, the preparation method comprises the following steps:

[0077] Formed as Figure 1 The first substrate 1 and the second substrate 2 are stacked as shown, wherein forming the first substrate 1 includes: providing a first dielectric substrate 3, and integrating a filter circuit on the first dielectric substrate 3;

[0078] The second substrate 2 is formed by: providing a second dielectric substrate 4; the second dielectric substrate 4 includes a first surface and a second surface which are arranged opposite to each other along the thickness direction thereof, and forming a switching circuit on the first surface of the second dielectric substrate 4; and electrically connecting the switching circuit to the filter circuit;

[0079] A first connecting via 5 is formed on the second dielectric substrate 4 and penetrates through the second dielectric substrate 4 in the thickness direction thereof. A signal introducing electrode 7 is formed in the first connecting via 5 and a first connecting terminal 8 is formed on the second surface of the second dielectric substrate 4. One end of the signal introducing electrode 7 is electrically connected to the first connecting terminal 8, and the other end is electrically connected to the switching circuit.

[0080] In order to make the preparation method in the embodiment of the present disclosure clear, the preparation method in the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings and specific embodiments.

[0081] S1, forming a first substrate 1. Figure 6 As shown, the steps of forming the first substrate 1 include:

[0082] S10, providing a first dielectric substrate 3, and processing the first dielectric substrate 3 to form a second connecting via 6 penetrating along the thickness direction thereof, such as Figure 7 shown.

[0083] In some examples, the second connection vias 6 on the first dielectric substrate 3 can be punched by methods including but not limited to mechanical punching, laser punching, photolithography punching, etc. The following describes the process of forming the second connection vias 6 by taking laser punching as an example.

[0084] Furthermore, step S10 may include the following steps:

[0085] For example: (1) Cleaning: The first dielectric substrate 3 enters a cleaning machine for cleaning.

[0086] In some examples, the thickness of the first dielectric substrate 3 is about 0.3 mm-2 mm.

[0087] (2) Laser drilling: A laser is used to vertically incident the laser beam onto the third surface of the first dielectric substrate 3 to modify the surface, so as to form a first sub-via hole on the third surface side of the first dielectric substrate 3. Similarly, a laser is used to vertically incident the laser beam onto the fourth surface of the first dielectric substrate 3 to modify the surface, so as to form a second sub-via hole on the fourth surface side of the first dielectric substrate 3. The second sub-via hole is connected to the first sub-via hole to form a second connecting via hole 6.

[0088] Specifically, when the laser beam interacts with the first dielectric substrate 3, the atoms in the first dielectric substrate 3 are ionized and ejected out of the third surface of the first dielectric substrate 3 due to the high energy of the laser photons. As time goes by, the hole is gradually deepened until the first sub-via hole is formed. The first dielectric substrate 3 is turned over and the second sub-via hole is formed according to the same principle. Among them, the generally available laser wavelength is 532nm, 355nm, 266nm, 248nm, 197nm, etc., the laser pulse width can be selected from 1-100fs, 1-100ps, 1-100ns, etc., and the type of laser can be selected from continuous laser, pulse laser, etc. The laser drilling method can include but is not limited to the following two methods. In the first method, when the spot diameter is large, the relative position of the laser beam and the first dielectric substrate 3 is fixed, and the first dielectric substrate 3 is directly punched to a preset depth by high energy. At this time, the shape of the first sub-via hole formed is an inverted cone, and the diameter of the inverted cone decreases from top to bottom (from the third surface to the fourth surface). In the second method, when the spot diameter is small, the laser beam scans in a circle on the first dielectric substrate 3, the spot focus is constantly changing, the focus depth is also constantly changing, and a spiral line is drawn from the lower surface (fourth surface) of the first dielectric substrate 3 to the upper surface (third surface) of the first dielectric substrate 3, and the spiral radius decreases from bottom to top. The first dielectric substrate 3 is laser cut into a truncated cone shape to form a first sub-via, and the shape of the first blind hole is the first sub-via; the second sub-via is formed in the same way as the first sub-via, so it will not be repeated. It can be seen that the second connecting via 6 formed by the first sub-via and the second sub-via is in the shape of an hourglass.

[0089] Of course, the first sub-connection via in the embodiment of the present disclosure may also be formed by irradiating only the third surface or the fourth surface of the first dielectric substrate 3 with a laser beam to form a truncated cone or cylindrical connection via, and the formation method may be the same as the above method, so it will not be repeated here.

[0090] (3) HF etching: Since a stress zone is formed in the area of ​​about 5-20 microns on the upper surface of the inner wall of the second connecting via 6 near the hole during the laser drilling process, the surface of the first dielectric substrate 3 in this area is uneven and presents a molten state with many burrs, and there are a large number of microcracks and macrocracks, and there is residual stress. At this time, a 2%-20% HF etching solution is used, and wet etching is performed at an appropriate temperature for a certain period of time to etch away the glass in the stress zone, so that the interior of the second connecting via 6 and the area near the hole on the surface are smooth and flat, without microcracks and macrocracks, and the stress zone is completely etched away.

[0091] S11, forming a first connection electrode 11 located at the second connection via 6, forming a first conductive film 91 of the first substructure 9 of the first inductor L1 and a first electrode plate of the first capacitor, such as Figure 8 shown.

[0092] In some examples, step S11 may specifically be as follows:

[0093] (1) Growing a seed layer: depositing a first metal material on the fourth surface of the first dielectric substrate 3 by magnetron sputtering, flipping the first dielectric substrate 3, and depositing the first metal material on the third surface by magnetron sputtering. At this time, the first metal material is formed on the side wall of the second connecting via 6 as a seed layer.

[0094] In some examples, the first metal material includes but is not limited to at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal material is about 0.2 μm to 10 μm. In the following description, the material of the first metal film layer is copper as an example.

[0095] In some examples, in order to increase the adhesion between the first metal material and the third surface of the first dielectric substrate 3, before forming the first metal material, an auxiliary metal film layer may be formed on the third surface of the first dielectric substrate 3 by a method including but not limited to magnetron sputtering. The material of the auxiliary metal film layer includes but is not limited to at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, for example, MoNb, and the thickness of the auxiliary metal film layer is about 2nm-20nm.

[0096] (2) Electroplating: Place the first dielectric substrate 3 on the electroplating machine carrier, press the power pad, place it in the hole-filling electroplating tank (special hole-filling electrolyte is used in the tank), add current, and keep the electroplating solution flowing rapidly on the third surface of the first dielectric substrate 3. The cations in the electroplating solution on the inner wall of the second connecting via 6 obtain electrons and become atoms and deposit on the inner wall. Through the special hole-filling electrolyte with a special ratio, it is possible to deposit metal copper at a high speed (deposition rate 0.5-3um / min) mainly in the second connecting via 6, while the third surface of the first dielectric substrate 3 is a flat area, and the deposition rate of metal copper on these two surfaces is extremely low (0.005-0.05um / min). As time goes by, the metal copper on the inner wall of the second connecting via 6 gradually grows thicker to form a first metal film layer. At this time, the thickness of the first metal film layer can be 3 microns to 10 microns. At this time, the first metal film layer fills the second connecting via 6.

[0097] In some examples, the first metal film layer may not fully fill the second connection via 6. In this step, a filling medium needs to be formed in the second connection via 6 to support the circuit structure disposed on the first surface of the first dielectric layer. The material of the filling medium may include an organic insulating material, such as a resin material including polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc. For another example, the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc.

[0098] It should be noted that, in the embodiment of the present disclosure, an example is taken in which the first metal film layer fills up the second connecting via hole 611 .

[0099] (3) Patterning of the first metal film layer on the third surface: coating, exposing, developing, and then etching the first metal film layer on the third surface. After etching, stripping is performed to form the first conductive film 91 of the first substructure 9 and the first electrode of the first capacitor located on the third surface.

[0100] S12, forming a first interlayer dielectric layer 12 on the side of the first electrode plate of the first capacitor away from the first dielectric substrate 3, and forming a second electrode plate 13 pattern including the first capacitor on the side of the first interlayer dielectric layer 12 away from the first dielectric substrate 3, such as Fig. 9 shown.

[0101] In some examples, the material of the first interlayer dielectric layer 12 is an inorganic insulating material. For example, the first interlayer dielectric layer 12 is an inorganic insulating layer formed of silicon nitride (SiNx), or a silicon oxide (SiO 2 ) or an inorganic insulating layer formed by SiNx inorganic insulating layer and SiO 2 Several types of stacked inorganic insulating layers are combined into a film layer. Of course, the first interlayer dielectric layer 12 also serves as the intermediate dielectric layer of the capacitor. The thickness of the first interlayer dielectric layer 12 can be 0.1 micron to 0.5 micron.

[0102] In some examples, the second plate 13 of the first capacitor can form a second metal film layer on the side of the first interlayer dielectric layer 12 away from the first dielectric substrate 3 by magnetron sputtering, and then perform glue coating, exposure, development, and subsequent wet etching. After etching, the glue is stripped to form a pattern including the second plate 13 of the first capacitor.

[0103] S13, forming a second interlayer dielectric layer 14 and a third interlayer dielectric layer 15 on the side of the first conductive film 91 away from the first dielectric substrate 3, and forming a third connecting via hole penetrating the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15, and a fourth connecting via hole penetrating the third interlayer dielectric layer 15, such as Fig.10shown.

[0104] The materials of the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 may be the same as the materials of the first interlayer dielectric layer 12, so they will not be described again. The thickness of the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 may be 2 micrometers to 5 micrometers.

[0105] S14, on the side of the third interlayer dielectric layer 15 away from the first dielectric substrate 3, a pattern including the second conductive film 92 of the first substructure 9 and the second connecting electrode 16 is formed by a patterning process, the second conductive film 92 is connected to the first conductive film 91 through a third connecting via hole. The second connecting electrode 16 is connected to the second plate 13 of the first capacitor through a fourth connecting via hole, as shown in FIG. Fig.11 shown.

[0106] In some examples, step S14 may include forming a third metal film layer by magnetron sputtering, applying glue, exposing, developing, and then wet etching, and stripping the glue after etching to form a pattern including the second conductive film 92 of the first substructure 9 and the second connecting electrode 16. The material of the third metal film layer may be the same as that of the first metal film layer, so it will not be repeated here.

[0107] In some examples, the thickness of the third metal film layer may be 3 micrometers to 10 micrometers, and the thickness of the formed second conductive film 92 is greater than the thickness of the first conductive film 91 .

[0108] S15, forming a fourth interlayer dielectric layer 17 and a fifth interlayer dielectric layer 18 in sequence on the side of the second conductive film 92 away from the first dielectric substrate 3, and forming a fifth connecting via 21 and a sixth connecting via 22 penetrating the fourth interlayer dielectric layer 17 and the fifth interlayer dielectric layer 18, as shown in FIG. Fig.12 shown.

[0109] The fifth interlayer dielectric layer is used to prevent water and oxygen from corroding the devices formed on the third surface of the first dielectric substrate 3. The thickness of the fifth interlayer dielectric layer 18 is between 2 microns and 5 microns; the material of the fifth interlayer dielectric layer 18 can be an inorganic insulating material. For example, the fifth interlayer dielectric layer 18 can be an inorganic insulating layer formed of silicon nitride (SiNx), or a silicon oxide (SiO 2 ) or an inorganic insulating layer formed by SiNx inorganic insulating layer and SiO 2Several stacked composite film layers of inorganic insulating layers. The thickness of the sixth interlayer dielectric layer 23 is above 2 μm; the material of the sixth interlayer dielectric layer 23 may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials. For another example, the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc. In some embodiments, the material of the sixth interlayer dielectric layer 23 may be a photosensitive organic material to make it easier to form the connection pads formed thereon.

[0110] S16, forming a second substructure 10 pattern including the first inductor L1 through a patterning process, such as Fig.13 shown.

[0111] In some examples, step S16 may include forming a fourth metal film layer on the fourth surface of the first dielectric substrate 3 by magnetron sputtering, and then coating, exposing, developing, and then wet etching, and stripping after etching to form a second substructure 10 pattern including the first inductor L1.

[0112] The thickness of the fourth metal film layer is 3 micrometers to 5 micrometers or more. The material of the fourth metal film layer can be the same as that of the first metal film layer, so it will not be described in detail here.

[0113] S17, forming a sixth interlayer dielectric layer 23 and a seventh interlayer dielectric layer 24 in sequence on the side of the second substructure 10 away from the first dielectric substrate 3, such as Fig.14 shown.

[0114] In some examples, the material of the sixth interlayer dielectric layer 23 may be the same as that of the fourth interlayer dielectric layer 17, so it is not repeated here. The material of the seventh interlayer dielectric layer 24 may be the same as that of the fifth interlayer dielectric layer 18, so it is not repeated here. The thickness of the sixth interlayer dielectric layer 23 may be 2 microns to 5 microns, and the thickness of the seventh interlayer dielectric layer 24 may be greater than 2 microns.

[0115] S18, forming a first connection pad 19 and a second connection pad 20 in the fifth connection via hole 21 and the sixth connection via hole 22 respectively. The first connection pad 19 and the second connection pad 20 may be solder balls, and finally forming Figure 4 The structure shown.

[0116] At this point, the manufacturing of the first substrate 1 is completed.

[0117] It should be noted that, in some embodiments, Fig.15As shown, the step of forming the second connecting via 6 is before the step of forming the second substructure 10. That is, the film layer structure located on the first surface of the first dielectric substrate 3 is formed first, and then the second connecting via 6 and the first connecting electrode 11 located in the second connecting via 6 are formed, and then the second substructure 10 and the fifth interlayer dielectric layer 18 and the sixth interlayer dielectric layer 23 are formed on the second surface of the second dielectric substrate 4 in sequence. Among them, the preparation methods and materials in each step of this preparation method are the same as the preparation methods and materials in the above S10-S18, so they will not be described in detail here.

[0118] In some embodiments, the step of forming the second connecting via 6 further includes: forming a first connecting blind hole 35 along the thickness direction on the third surface of the first dielectric substrate 3. The first dielectric substrate 3 is thinned so that the first connecting blind hole 35 forms a second connecting via 6 penetrating along the thickness direction thereof. Fig.16 The step S1 of forming the first substrate 1 is specifically as follows:

[0119] S20, providing a first dielectric substrate 3, and processing the first dielectric substrate 3 to form a first connecting blind hole 35 along the thickness direction thereof, such as Fig.17 At this time, the thickness of the first dielectric substrate 3 may be 1 mm-2 mm. In some embodiments, the first connection blind hole 35 on the first dielectric substrate 3 may be punched by, but not limited to, mechanical punching, laser punching, photolithography punching, etc. The specific punching method is the same as that in step S10, so it will not be repeated here.

[0120] S21, forming a film layer structure on the third surface of the first dielectric substrate 3. Fig.18 As shown, a first connection electrode 11 is formed at the first connection blind hole 35, a first conductive film 91 of the first substructure 9 of the first inductor L1 and a first plate of the first capacitor are formed. A first interlayer dielectric layer 12 is formed on the side of the first plate of the first capacitor away from the first dielectric substrate 3, and a pattern including a second plate 13 of the first capacitor is formed on the side of the first interlayer dielectric layer 12 away from the first dielectric substrate 3. A second interlayer dielectric layer 14 and a third interlayer dielectric layer 15 are formed on the side of the first conductive film 91 away from the first dielectric substrate 3, and a third connection via hole penetrating the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 and a fourth connection via hole penetrating the third interlayer dielectric layer 15 are formed. On the side of the third interlayer dielectric layer 15 away from the first dielectric substrate 3, a pattern including a second conductive film 92 of the first substructure 9 and a second connection electrode 16 is formed by a patterning process. A fourth interlayer dielectric layer 17 and a fifth interlayer dielectric layer 18 are sequentially formed on the side of the second conductive film 92 away from the first dielectric substrate 3 , and a fifth connecting via 21 and a sixth connecting via 22 penetrating the fourth interlayer dielectric layer 17 and the fifth interlayer dielectric layer 18 are formed.

[0121] Specific as Fig.18 The specific steps and materials in step S21 are the same as those in steps S11-S15, so they will not be described again.

[0122] S22, thinning the first dielectric substrate 3 until the first connection electrode 11 is exposed on the side away from the first dielectric substrate 3, so that the first connection blind hole 35 forms the second connection via 6. Fig.19 shown.

[0123] S23, the second substructure 10 is formed by patterning the thinned first dielectric substrate 3. The second substructure 10, the first connecting electrode 11 and the first substructure 9 form the structure of the first inductor L1. A sixth interlayer dielectric layer 23 and a seventh interlayer dielectric layer 24 are sequentially formed on the side of the second substructure 10 away from the first dielectric substrate 3. The specific steps and materials in step S23 are the same as those in steps S16-S17, so they are not repeated here.

[0124] S24, forming a first connection pad 19 and a second connection pad 20 on the seventh interlayer dielectric layer 24. The specific steps and materials in step S24 are the same as those in step S18, so they are not repeated here.

[0125] At this point, the preparation of the first substrate 1 is completed.

[0126] S2, forming a second substrate 2, such as Fig. 20 The specific steps of forming the second substrate 2 include:

[0127] S30, providing a second dielectric substrate 4, and forming a first electrode 25 and a third connecting electrode 28 of a second capacitor on a first surface of the second dielectric substrate 4. Fig.21 As shown: Step S30 has the following specific steps:

[0128] The first plate 25 and the second connecting electrode 16 of the second capacitor can form a fifth metal film layer on the first surface of the second dielectric substrate 4 by magnetron sputtering, and then perform glue coating, exposure, development, and subsequent wet etching. After etching, the strip is stripped to form the first plate 25 and the third connecting electrode 28 of the second capacitor. In the embodiment of the present disclosure, the thickness of the fifth metal film layer can be 3-10 microns, and the thickness of the second dielectric substrate 4 can be 200 microns-500 microns. The material of the fifth metal film layer can be, but is not limited to, metal materials such as copper, silver, aluminum, and molybdenum, and can also be an alloy composed of the above metal materials.

[0129] S31, forming an eighth interlayer dielectric layer 27 and a second plate 26 of the second capacitor on the side of the first plate 25 of the second capacitor away from the first dielectric substrate 3. In some examples, such as Fig. 22 As shown, the specific steps of forming the eighth interlayer dielectric layer 27 and the second electrode plate 26 of the second capacitor in step S31 are the same as the specific steps in step S13, so they are not repeated here.

[0130] S32, forming a ninth interlayer dielectric layer 29 and a tenth interlayer dielectric layer 30, and forming a seventh connecting via hole penetrating the tenth interlayer dielectric layer 30, and an eighth connecting via hole 33 penetrating the ninth interlayer dielectric layer 29 and the tenth interlayer dielectric layer 30. The orthographic projections of the seventh connecting via hole and the second electrode plate 26 of the second capacitor on the second dielectric substrate 4 at least partially overlap, and the orthographic projections of the eighth connecting via hole 33 and the first end of the second inductor L2 on the second dielectric substrate 4 at least partially overlap.

[0131] In some examples, such as Fig.23 As shown, the ninth interlayer dielectric layer 29 is used to isolate the first electrode plate and the second electrode plate of the first capacitor, and the tenth interlayer dielectric layer 30 is used to insulate and protect the film layer thereunder to prevent it from reacting with air and being oxidized during and after the substrate manufacturing process of the disclosed embodiment.

[0132] S33 , forming a pattern including a fourth connection electrode 31 through a patterning process.

[0133] In some examples, such as Fig.24 As shown, step S33 may specifically include: forming a sixth metal film layer on the tenth interlayer dielectric layer 30, then performing glue coating, exposure, development, and subsequent wet etching, and stripping after etching to form a pattern including a fourth connection electrode 31. The fourth connection electrode 31 is electrically connected to the second plate 26 of the second capacitor through the seventh connection via.

[0134] S34, forming a second inductor L2. In some examples, such as Fig.25 As shown, step S34 may specifically include the following steps:

[0135] A second inductor L2 is formed on the side of the tenth dielectric layer away from the second dielectric substrate 4. The first end of the second inductor L2 is electrically connected to the third connection electrode 28 through the eighth connection via 33. In some embodiments, according to the specific structure of the second inductor L2, the step of forming a part of the structure in the second inductor L2 can be performed simultaneously with the step of forming the first plate or the second plate of the first capacitor. For example, some metal layers in the second inductor L2 can be formed in one patterning process with the first plate or the second plate of the first capacitor. In the embodiment of the present disclosure, the step of forming the second inductor L2 is after the step of forming the first capacitor, and the second inductor L2 is formed on the side away from the second capacitor.

[0136] S35, forming an eleventh interlayer dielectric layer 32, and forming an eighth connecting via 33 and a ninth connecting via 34 penetrating the eleventh interlayer dielectric layer 32, wherein the eighth connecting via 33 at least partially overlaps with the orthographic projection of the second end of the second inductor L2 on the second dielectric substrate 4, and the ninth connecting via 34 at least partially overlaps with the orthographic projection of the fourth connecting electrode 31 on the second dielectric substrate 4. In some examples, step S35 is as follows: Fig.26 The eleventh interlayer dielectric layer 32 can be used for planarization and to protect the devices thereunder from being corroded by water and oxygen.

[0137] The preparation method of the second substrate 2 also includes:

[0138] S36, forming a first connecting via 5 penetrating through the thickness direction of the second dielectric substrate 4. At least one first connecting via 5 at least partially overlaps with the orthographic projection of the first connecting electrode 11 on the second dielectric substrate 4. And at least one first connecting via 5 at least partially overlaps with the orthographic projection of the second plate 26 of the second capacitor on the second dielectric substrate 4. In some embodiments, Fig. 27 As shown, the specific steps of forming the first connecting via 5 in step S30 are the same as the specific steps of forming the second connecting via 6 in step S10, so they will not be described again.

[0139] S37 , forming a signal introduction electrode 7 located at the first connection via hole 5 .

[0140] In some embodiments, Fig.28 As shown, the signal introduction electrode 7 is electrically connected to the third connection electrode 28 and the second plate 26 of the second capacitor. The specific steps of forming the signal introduction electrode 7 in step S37 are the same as the steps of forming the first connection electrode 11 in step S11, so they are not repeated here.

[0141] It should be noted that, in some embodiments, the step of forming the first connecting via 5 is before forming the switching circuit. That is, step S36 and step S37 can be before steps S30-S35, that is, the switching circuit is formed on the second dielectric substrate 4 having the first connecting via 5. This preparation method has a mature process and a high yield rate.

[0142] In some embodiments, when step S36 precedes steps S30-S35, Fig.29 As shown, the preparation method of the switching circuit may further include:

[0143] S40, providing a second dielectric substrate 4, and processing the second dielectric substrate 4 to form a second connecting blind hole 36 along the thickness direction thereof, such as Fig.30In some embodiments, the second connection blind hole 36 on the second dielectric substrate 4 can be punched by methods including but not limited to mechanical punching, laser punching, photolithography punching, etc. The specific punching method is the same as that in step S10, so it will not be repeated here.

[0144] S41, forming a signal introduction electrode 7 located at the second connection blind hole 36. In some embodiments, Fig.31 As shown, the specific method of forming the signal introduction electrode 7 is the same as the method of forming the signal introduction electrode 7 in step S37, so it will not be repeated here.

[0145] S42, forming a second plate 26 and a third connecting electrode 28 of a second capacitor on the first surface of the second dielectric substrate 4. A second plate 26 of a second capacitor and a third connecting electrode 28 are electrically connected to the signal introduction electrode 7, respectively. An eighth interlayer dielectric layer 27 and a second plate 26 of the second capacitor are formed on the first plate 25 of the second capacitor. A ninth interlayer dielectric layer 29 and a tenth interlayer dielectric layer 30 are formed, and a seventh connecting via penetrating the tenth interlayer dielectric layer 30 and an eighth connecting via 33 penetrating the ninth interlayer dielectric layer 29 and the tenth interlayer dielectric layer 30 are formed. The orthographic projections of the seventh connecting via and the second plate 26 of the second capacitor on the second dielectric substrate 4 at least partially overlap, and the orthographic projections of the eighth connecting via 33 and the first end of the second inductor L2 on the second dielectric substrate 4 at least partially overlap. A fourth connecting electrode 31 is formed, a second inductor L2 is formed, and an eleventh interlayer dielectric layer 32 is formed. In some embodiments, as Fig.32 As shown, the specific steps in step S42 are the same as the specific steps in steps S30-S35, so they are not repeated here.

[0146] At this point, the fabrication of the switching circuit is completed. In the embodiment of the present disclosure, the method for preparing the second substrate 2 further includes:

[0147] S43, thinning the second dielectric substrate 4 until the signal introduction electrode 7 is exposed on the side away from the second dielectric substrate 4, and the second connecting blind hole 36 forms the first connecting via hole 5. In this way, the following is formed: Fig.28 The structure shown in the figure makes it possible to form a switching circuit on the thicker second dielectric substrate 4, which is beneficial to improving the yield rate.

[0148] This concludes the production of the second substrate 2.

[0149] S3, stacking the first substrate 1 and the second substrate 2. In some embodiments, Fig.33As shown, through the welding process, the first connection pad 19 and the second connection pad 20 on the first substrate 1 are respectively welded and connected to the second substrate 2 through the eighth connection via 33 and the ninth connection via 34 on the second substrate 2. It should be noted that a plurality of filter circuits can be arranged on the second substrate 2, and it is obvious to those skilled in the art that a plurality of pads are connected to the second substrate 2 through a plurality of connection vias on the second substrate 2, and therefore it is also within the protection scope of the present disclosure.

[0150] S4, forming a plurality of first connection terminals 8 on the second surface of the second dielectric substrate 4. In some embodiments, one first connection terminal 8 is electrically connected to one signal introduction electrode 7. It should be noted that the step of forming the first connection terminal 8 may be performed after step S37 or step S44, and is also within the scope of protection of the present disclosure.

[0151] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A filter, characterized in that: It includes a first substrate and a second substrate which are stacked; wherein, The first substrate includes a first dielectric substrate, and a filter circuit integrated on the first dielectric substrate, wherein the filter circuit includes at least a first inductor and a first capacitor; The second substrate includes a second dielectric substrate, the second dielectric substrate includes a first surface and a second surface arranged opposite to each other along the thickness direction thereof, a switching circuit is arranged on the first surface; the switching circuit is electrically connected to the filter circuit; wherein, The second dielectric substrate is provided with a first connecting via hole penetrating in the thickness direction thereof, a signal introduction electrode is provided in the first connecting via hole, a first connecting end is provided on the second surface, one end of the signal introduction electrode is electrically connected to the first connecting end, and the other end is electrically connected to the switching circuit; The switching circuit at least includes: a second capacitor and a second inductor; the first end of the second inductor is electrically connected to one of the signal introduction electrodes, the second end of the second inductor is connected to the first connecting pad, and the first connecting pad is electrically connected to the first capacitor; the first plate of the second capacitor is electrically connected to one of the signal introduction electrodes; the second plate of the second capacitor is connected to the second connecting pad, and the second connecting pad is electrically connected to the first inductor.

2. The filter according to claim 1, characterized in that The first dielectric substrate comprises a third surface and a fourth surface arranged opposite to each other along the thickness direction thereof, and a second connecting via arranged along the thickness direction thereof; The first inductor includes: a first substructure disposed on the third surface of the first dielectric substrate, a second substructure disposed on the fourth surface of the first dielectric substrate, and a first connecting electrode disposed in the second connecting via hole to connect the first substructure and the second substructure in series.

3. The filter according to claim 2, characterized in that The first capacitor is arranged on a side of the third surface of the first dielectric substrate away from the first dielectric substrate, and comprises a first electrode plate, a first interlayer dielectric layer and a second electrode plate which are arranged in sequence away from the first dielectric substrate.

4. The filter according to claim 3, characterized in that The first substructure includes a first conductive film and a second conductive film; the first conductive film is arranged in the same layer as the first electrode plate of the first capacitor; a second interlayer dielectric layer and a third interlayer dielectric layer are sequentially arranged on the side of the first electrode plate of the first capacitor away from the first dielectric substrate; The second conductive film is arranged on a side of the third interlayer dielectric layer away from the first dielectric substrate; the second conductive film is electrically connected to the first conductive film through a third connecting via that penetrates the second interlayer dielectric layer and the third interlayer dielectric layer.

5. The filter according to claim 4, characterized in that The filter circuit also includes: a third connection electrode arranged in the same layer as the second conductive film; the third connection electrode is electrically connected to the second plate of the first capacitor through a fourth connection via penetrating the third interlayer dielectric layer; a fourth interlayer dielectric layer and a fifth interlayer dielectric layer are arranged on the side of the second conductive film away from the first dielectric substrate; a first connection pad and a second connection pad are arranged on the side away from the fifth interlayer dielectric layer; the first connection pad is electrically connected to the second connection electrode through a fifth connection via penetrating the fourth interlayer dielectric layer and the fifth interlayer dielectric layer; the second connection pad is electrically connected to the second conductive film through a sixth connection via penetrating the fourth interlayer dielectric layer and the fifth interlayer dielectric layer.

6. The filter according to claim 5, characterized in that The first connecting pad and the second connecting pad are respectively welded on the switching circuit.

7. The filter according to claim 5, characterized in that The filter circuit further includes: a sixth interlayer dielectric layer and a seventh interlayer dielectric layer which are sequentially arranged in a direction away from the fourth surface of the first dielectric substrate.

8. The filter according to any one of claims 1 to 7, characterized in that: The first dielectric substrate and the second dielectric substrate include glass substrates.

9. A method for preparing a filter, characterized in that: including a first substrate and a second substrate forming a stacked arrangement; Wherein, forming the first substrate comprises: providing a first dielectric substrate, and integrating a filter circuit on the first dielectric substrate, wherein the filter circuit comprises at least a first inductor and a first capacitor; Forming the second substrate includes: providing a second dielectric substrate; the second dielectric substrate includes a first surface and a second surface arranged opposite to each other along the thickness direction thereof, and forming a switching circuit on the first surface of the second dielectric substrate; electrically connecting the switching circuit to the filter circuit; wherein forming the switching circuit at least includes forming a second capacitor and a second inductor; a first end of the second inductor is electrically connected to a signal introduction electrode, a second end of the second inductor is connected to a first connecting pad, and the first connecting pad is electrically connected to the first capacitor; a first plate of the second capacitor is electrically connected to one of the signal introduction electrodes; a second plate of the second capacitor is connected to a second connecting pad, and the second connecting pad is electrically connected to the first inductor; A first connecting via hole is formed on the second dielectric substrate and penetrates along the thickness direction thereof, and a signal introduction electrode is formed in the first connecting via hole; a first connecting end is formed on the second surface of the second dielectric substrate; one end of the signal introduction electrode is electrically connected to the first connecting end, and the other end is electrically connected to the switching circuit.

10. The preparation method according to claim 9, characterized in that: The step of forming the first connecting via hole is before forming the switching circuit.

11. The preparation method according to claim 10, characterized in that: The step of forming the first connecting via also includes: forming a first connecting blind hole along the thickness direction on the first surface of the second dielectric substrate; and thinning the second dielectric substrate so that the first connecting blind hole forms the first connecting via penetrating along the thickness direction thereof.

12. The preparation method according to any one of claims 9, characterized in that: The first dielectric substrate includes a third surface and a fourth surface that are arranged opposite to each other; The step of forming the filter circuit includes: forming a second connection via hole penetrating the first dielectric substrate; the step of forming the first inductor includes: forming a first connection electrode in the second connection via hole; forming a first substructure on the third surface of the first dielectric substrate; forming a second substructure on the fourth surface of the first dielectric substrate; the first substructure, the second substructure and the first connection electrode constitute a coil structure of the first inductor.

13. The preparation method according to claim 12, characterized in that: The step of forming the second connecting via hole includes: forming a second connecting blind hole along the thickness direction on the third surface of the first dielectric substrate; and thinning the first dielectric substrate so that the second connecting blind hole forms the second connecting via hole penetrating along the thickness direction thereof.

14. The preparation method according to claim 12, characterized in that: The step of forming the first capacitor includes: While forming the first substructure, forming a pattern including a first plate of the first capacitor; Forming a first interlayer dielectric layer on a side of the first electrode plate of the first capacitor away from the first surface of the first dielectric substrate, so as to be used as an interlayer dielectric layer of the first capacitor; A second plate of the first capacitor is formed on a side of the first interlayer dielectric layer away from the first dielectric substrate; the orthographic projections of the first plate and the second plate of the first capacitor on the first dielectric substrate at least partially overlap.

15. The preparation method according to claim 14, characterized in that: The step of forming the first substructure includes: forming a first conductive film and a second conductive film; the first conductive film and the first electrode of the first capacitor are formed in one patterning process; A second interlayer dielectric layer and a third interlayer dielectric layer are formed on the side of the first conductive film away from the first dielectric substrate, as well as a third connecting via hole penetrating the second interlayer dielectric layer and the third interlayer dielectric layer, and a fourth connecting via hole penetrating the third interlayer dielectric layer; the third connecting via hole at least partially overlaps with the orthographic projection of the first conductive film on the first dielectric substrate; the fourth connecting via hole at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the first dielectric substrate; A second conductive film and a second connecting electrode are formed on the side of the third interlayer dielectric layer away from the first dielectric substrate through a single patterning process; the second conductive film is electrically connected to the first conductive film through the third connecting via; and the second connecting electrode is electrically connected to the second plate of the first capacitor through the fourth connecting via.

16. The preparation method according to claim 15, characterized in that: The step of forming the filter circuit further includes: forming a fourth interlayer dielectric layer and a fifth interlayer dielectric layer on a side of the second conductive film away from the first dielectric substrate, and a fifth connecting via hole and a sixth connecting via hole penetrating the fourth interlayer dielectric layer and the fifth interlayer dielectric layer; A first connection pad and a second connection pad are formed on the side away from the fifth interlayer dielectric layer; the first connection pad is electrically connected to the second connection electrode through the fifth connection via; and the second connection pad is electrically connected to the second conductive film through the sixth connection via.

17. The preparation method according to claim 16, characterized in that: Forming the filter circuit further includes sequentially forming a sixth interlayer dielectric layer and a seventh interlayer dielectric layer on a side of the fourth surface of the first dielectric substrate away from the first dielectric substrate.

18. The preparation method according to claim 16, characterized in that: The step of electrically connecting the switching circuit to the filter circuit includes: connecting the first connection pad and the second connection pad to the switching circuit respectively through a welding process.

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