Memory device and method of operating the same

Abstract

The present application relates to a memory device and an operation method of the memory device. A storage device includes: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from a storage controller; a temperature information controller configured to generate a first temperature code corresponding to an internal temperature during the execution of an internal operation corresponding to a first internal operation command among the plurality of internal operation commands, and temperature code generation information indicating information that the first temperature code has been generated during a set period; and an operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command based on the first temperature code and the temperature code generation information in response to the second internal operation command input after the input of the first internal operation command among the plurality of internal operation commands.

Description

Technical Field

[0001] The present disclosure generally relates to an electronic device, and more particularly, to a memory device and an operation method of the memory device. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device for storing data and a storage controller for controlling the memory device. The memory device is classified into a volatile memory device and a non-volatile memory device.

[0003] A volatile memory device is a memory device that stores data only while power is supplied, and the stored data disappears when the power supply is interrupted. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0004] A non-volatile memory device is a memory device in which data does not disappear even when the power supply is interrupted. The non-volatile memory device may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable ROM (EEROM), a flash memory, and the like. Summary of the Invention

[0005] According to an aspect of the present disclosure, a memory device may be provided. The memory device includes: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from a storage controller; a temperature information controller configured to generate a first temperature code corresponding to an internal temperature when performing an internal operation corresponding to a first internal operation command among the plurality of internal operation commands and temperature code generation information indicating information that the first temperature code has been generated during a set period; and an operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command based on the first temperature code and the temperature code generation information in response to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input.

[0006] According to another aspect of the present disclosure, a method of operating a memory device may be provided. The method includes the steps of: receiving a first internal operation command input from a storage controller; generating a first temperature code corresponding to an internal temperature when performing an internal operation corresponding to the first internal operation command in response to the first internal operation command; generating temperature code generation information indicating information that the first temperature code has been generated during a set period; receiving a second internal operation command input from a storage controller; and performing an internal operation corresponding to the second internal operation command based on the first temperature code and the temperature code generation information in response to the second internal operation command.

[0007] According to another aspect of the present disclosure, a memory device may be provided. The memory device includes: a first memory chip configured to receive a first internal operation command input from a storage controller and store a temperature code generated according to the first internal operation command and temperature code generation information indicating information that the temperature code has been generated during a set period; and a second memory chip configured to receive a second internal operation command input from the storage controller after the first internal operation command is input to the first memory chip, and perform an internal operation corresponding to the second internal operation command based on the temperature code and the temperature code generation information stored on the first memory chip in response to the second internal operation command. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Examples of embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0009] In the drawings, for clarity of illustration, the dimensions may be exaggerated. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or there may be one or more intervening elements. Like reference numerals always denote like elements.

[0010] Figure 1 is a diagram showing a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram showing Figure 1 the structure of the memory device shown.

[0012] Figure 3 is a diagram showing Figure 2 an embodiment of a memory cell array shown.

[0013] Figure 4 is a diagram showing Figure 3 a circuit diagram of any one of the storage blocks shown.

[0014] Figure 5 is a diagram showing Figure 3 a circuit diagram of another embodiment of one of the storage blocks shown.

[0015] Figure 6 is a diagram showing, for example, Figure 1 the connection relationship between a storage controller and a plurality of memory devices shown.

[0016] Figure 7 is a diagram showing the internal operation of the memory device.

[0017] Figure 8 It is a diagram showing an example of a memory device according to an embodiment of the present disclosure.

[0018] Figure 9 It is a diagram showing an example of performing internal operations according to an embodiment of the present disclosure.

[0019] Figure 10 It is a diagram showing another example of a memory device according to an embodiment of the present disclosure.

[0020] Figure 11 It is a flowchart showing a method of operating a memory device according to an embodiment of the present disclosure.

[0021] Figure 12 It is a flowchart showing a method of generating a temperature code according to an embodiment of the present disclosure.

[0022] Figure 13 It is a flowchart showing a method of changing temperature code generation information according to an embodiment of the present disclosure.

[0023] Figure 14 It is shown Figure 1 a diagram of the storage controller shown.

[0024] Figure 15 It is a block diagram showing a memory card system applying a storage device according to an embodiment of the present disclosure.

[0025] Figure 16 It is a block diagram showing, for example, a solid state drive (SSD) system applying a storage device according to an embodiment of the present disclosure.

[0026] Figure 17 It is a block diagram showing a user system applying a storage device according to an embodiment of the present disclosure. Detailed Description

[0027] To describe embodiments according to the concepts of the present disclosure, the specific structures or functional descriptions disclosed herein are merely illustrative. Embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0028] Embodiments can provide a memory device having an improved operation speed and a method of operating the memory device.

[0029] Figure 1 It is a diagram showing a storage device according to an embodiment of the present disclosure.

[0030] Referring to Figure 1, the storage device 50 may include a memory device 100 and a storage controller 200 for controlling the operation of the memory device 100. The storage device 50 may be a device that stores data under the control of a host 300 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0031] According to the host interface as a communication scheme with the host 300, the storage device 50 may be manufactured as any one of various types of storage devices. For example, the storage device 50 may be implemented using any one of various types of storage devices such as a solid state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro MMC (micro-MMC), secure digital (SD) card, mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash storage (UFS) device, compact flash (CF) card, smart media card (SMC), memory stick, etc.

[0032] The storage device 50 may be manufactured as any one of various types of package types. For example, the storage device 50 may be manufactured as any one of various types of package types such as a package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer level package (WFP), and wafer level stack package (WSP).

[0033] The memory device 100 may store data. The memory device 100 may operate under the control of the storage controller 200. The memory device 100 may include a memory cell array (not shown), and the memory cell array includes a plurality of memory cells for storing data.

[0034] Each memory cell may operate as any one of a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, and a quad-level cell (QLC) that stores four data bits.

[0035] The memory cell array (not shown) may include a plurality of storage blocks. Each storage block may include a plurality of memory cells. One storage block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A storage block may be a unit for erasing data.

[0036] In an embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for convenience of description, it is assumed and described that the memory device 100 is a NAND flash memory.

[0037] The memory device 100 may receive a command CMD and an address ADDR from a storage controller 200 and access a region selected by the address ADDR in a memory cell array. The memory device 100 may perform an operation indicated by the command CMD on the region selected by the address ADDR. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. In the programming operation, the memory device 100 may program data in the region selected by the address ADDR. In the read operation, the memory device 100 may read data from the region selected by the address ADDR. In the erase operation, the memory device 100 may erase data stored in the region selected by the address ADDR.

[0038] In an embodiment, the memory device 100 may include an operation controller 131 and a temperature information controller 140.

[0039] The operation controller 131 may control the memory device 100 to perform internal operations according to an internal operation command input from the storage controller 200. The internal operations may include a read operation, a programming operation, and an erase operation.

[0040] In an embodiment, the operation controller 131 may control the memory device 100 to perform internal operations based on a temperature code generated by the temperature information controller 140. For example, the operation controller 131 may control the memory device 100 to generate an internal voltage for performing internal operations based on the temperature code generated by the temperature information controller 140. In addition, the operation controller 131 may control the memory device 100 to perform internal operations using the internal voltage compensated according to the temperature code.

[0041] The temperature information controller 140 may measure the internal temperature of the memory device 100.

[0042] The temperature information controller 140 may generate a temperature code corresponding to the measured internal temperature. In an embodiment, the temperature information controller 140 may include a digital temperature sensing circuit. For example, the temperature information controller 140 may convert the measured internal temperature into a temperature code as a digital signal and output the temperature code.

[0043] For example, the temperature information controller 140 may sense the temperature of the memory device 100 in response to a command (e.g., a temperature measurement command) sent from the memory device 100 or the storage controller 200, and output a code corresponding to the sensed temperature. Additionally, whenever an internal operation is performed, the temperature information controller 140 may perform the operation of sensing the temperature of the memory device 100 and outputting a code, regardless of a command sent from the memory device 100 or the storage controller 200.

[0044] When the memory device 100 performs a programming operation, a read operation, or an erase operation, the internal temperature of the memory device 100 may change. The internal temperature may correspond to the temperature of the memory device 100. Alternatively, the internal temperature may correspond to the temperature of the memory cell array. The internal temperature of the memory device 100 may increase as the memory device 100 frequently performs a programming operation, a read operation, or an erase operation. When the internal temperature of the memory device 100 becomes too high, the probability that the programming operation, the read operation, or the erase operation will fail may increase. That is, when the internal temperature of the memory device 100 becomes too high, the performance of the memory device 100 may deteriorate. Therefore, whenever an internal operation of the memory device 100 is performed, the storage controller 200 may control the temperature information controller 140 to measure the temperature.

[0045] However, when the interval between multiple internal operations is short, since the temperature is measured whenever each internal operation is performed, the time required to perform these multiple internal operations is prolonged. Therefore, according to an embodiment of the present disclosure, the memory device 100 omits the operation of measuring the internal temperature for internal operation commands input during a set period, and performs an internal operation corresponding to the internal operation command based on a pre-generated temperature code, so that the operation speed of the memory device 100 can be improved.

[0046] In an embodiment, the memory device may generate temperature code generation information indicating that a temperature code has been generated during a set period.

[0047] In addition, the memory device 100 may determine whether to measure the internal temperature according to the temperature code generation information in response to an internal operation command input from the storage controller 200. For example, the memory device 100 may omit the operation of measuring the internal temperature according to the determination of whether to measure the internal temperature. The memory device 100 may perform an internal operation corresponding to the internal operation command based on a pre-generated temperature code. In addition, the memory device 100 may measure the internal temperature according to the determination of whether to measure the internal temperature. The memory device 100 may perform an internal operation corresponding to the internal operation command based on the temperature code corresponding to the measured internal temperature.

[0048] The storage controller 200 may control the overall operation of the storage device 50.

[0049] When power is applied to the storage device 50, the storage controller 200 may execute firmware (FW). When the memory device 100 is a flash memory device, the FW may include a host interface layer (HIL) for controlling communication with the host 300, a flash translation layer (FTL) for controlling communication between the host and the memory device 100, and a flash interface layer (FIL) for controlling communication with the memory device 100.

[0050] In an embodiment, the storage controller 200 may receive data and a logical block address (LBA) from the host 300, and convert the LBA into a physical block address (PBA) representing the address of the memory cells in the memory device 100 where the data is to be stored. In this specification, LBA and "logical address" may be used interchangeably. In this specification, PBA and "physical address" may be used interchangeably.

[0051] The storage controller 200 may control the memory device 100 to perform programming operations, read operations, erase operations, etc. in response to a request from the host 300. In a programming operation, the storage controller 200 may provide a programming command, a PBA, and data to the memory device 100. In a read operation, the storage controller 200 may provide a read command and a PBA to the memory device 100. In an erase operation, the storage controller 200 may provide an erase command and a PBA to the memory device 100.

[0052] In an embodiment, the storage controller 200 may autonomously generate commands, addresses, and data regardless of any request from the host 300, and send the commands, addresses, and data to the memory device 100. For example, the storage controller 200 may provide commands, addresses, and data for performing read operations and programming operations (which are accompanied by performing wear leveling, read recovery, garbage collection, etc.) to the memory device 100.

[0053] In an embodiment, the storage controller 200 may control at least two memory devices 100. The storage controller 200 may control the memory devices according to an interleaving technique to improve operational performance. The interleaving technique may be a method for controlling the operations of at least two memory devices 100 to overlap with each other.

[0054] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial ATA (SATA), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), High-Speed Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM).

[0055] Figure 2 is a diagram showing Figure 1 the structure of the memory device 100 shown.

[0056] Referring to Figure 2 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, a control logic 130, and a temperature information controller 140. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0057] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to a page buffer group 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as one page. Thus, one memory block may include a plurality of pages.

[0058] The row lines RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line.

[0059] Each memory cell included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0060] The peripheral circuit 120 can perform a programming operation, a read operation, or an erase operation on a selected area of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and the bit lines BL1 to BLm or discharge the applied voltages under the control of the control logic 130.

[0061] In an embodiment, the peripheral circuit 120 can perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller 200.

[0062] The peripheral circuit 120 can include a row decoder 121, a voltage generator 122, a page buffer bank 123, a column decoder 124, an input / output circuit 125, and a sense circuit 126.

[0063] The row decoder 121 is connected to the memory cell array 110 through the row lines RL. The row lines RL can include at least one source selection line, a plurality of word lines, and at least one drain selection line. In an embodiment, the word lines can include normal word lines and dummy word lines. In an embodiment, the row lines RL can further include a transistor selection line.

[0064] The row decoder 121 operates under the control of the control logic. The row decoder 121 receives a row address RADD from the control logic 130.

[0065] The row decoder 121 decodes the row address RADD. The row decoder 121 selects at least one of the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 can select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0066] For example, in a programming operation, the row decoder 121 can apply a programming voltage to the selected word line and apply a programming pass voltage having a level lower than the programming voltage to the unselected word lines. In a programming verification operation, the row decoder 121 can apply a verification voltage to the selected word line and apply a verification pass voltage having a level higher than the verification voltage to the unselected word lines.

[0067] In a read operation, the row decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage having a level higher than the read voltage to the unselected word lines.

[0068] In an embodiment, the erase operation of the memory device 100 is performed in units of memory blocks. In an erase operation, the row decoder 121 can select one memory block according to the decoded address. In an erase operation, the row decoder 121 can apply a ground voltage to the word lines connected to the selected memory block.

[0069] The voltage generator 122 operates under the control of the control logic 130. The voltage generator 122 generates a plurality of voltages using an external power supply voltage supplied to the memory device 100. For example, the voltage generator may generate various operation voltages Vop used in a programming operation, a read operation, and an erase operation in response to an operation signal OPSIG. For example, the voltage generator 122 may generate a programming voltage, a verify voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic 130.

[0070] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operation voltage of the memory device 100.

[0071] In an embodiment, the voltage generator 122 may use the external power supply voltage or the internal power supply voltage to generate a plurality of voltages.

[0072] For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving the internal power supply voltage, and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 130.

[0073] The plurality of generated voltages may be supplied to the memory cell array 110 through the row decoder 121.

[0074] The page buffer group 123 includes a first page buffer PB1 to an m-th page buffer PBm. The first page buffer PB1 to the m-th page buffer PBm are respectively connected to the memory cell array 110 through a first bit line BL1 to an m-th bit line BLm. The first bit line BL1 to the m-th bit line BLm operate under the control of the control logic 130. For example, the first bit line BL1 to the m-th bit line BLm may operate in response to a page buffer control signal PBSIGNALS. For example, the first page buffer PB1 to the m-th page buffer PBm may temporarily store data received through the first bit line BL1 to the m-th bit line BLm, or sense the voltage or current of the bit lines BL1 to BLm in a read operation or a verify operation.

[0075] For example, in a programming operation, when a programming voltage is applied to a selected word line, the first page buffer PB1 to the m-th page buffer PBm may transfer data DATA received through the input / output circuit 125 to the selected memory cells through the first bit line BL1 to the m-th bit line BLm. The memory cells of the selected page are programmed according to the transferred data DATA. The memory cells connected to the bit lines to which a programming enable voltage (e.g., ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibit voltage (e.g., power supply voltage) is applied may be maintained. In a programming verification operation, the first page buffer PB1 to the m-th page buffer PBm read page data from the selected memory cells through the first bit line BL1 to the m-th bit line BLm.

[0076] In a read operation, the first page buffer PB1 to the m-th page buffer PBm read data DATA from the memory cells of the selected page through the first bit line BL1 to the m-th bit line BLm, and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0077] In an erase operation, the first page buffer PB1 to the m-th page buffer PBm may float the first bit line BL1 to the m-th bit line BLm.

[0078] The column decoder 124 may communicate data between the input / output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may communicate data with the first page buffer PB1 to the m-th page buffer PBm through a data line DL, or communicate data with the input / output circuit 125 through a column line CL.

[0079] The input / output circuit 125 may transfer a command CMD and an address ADDR received from the memory controller 200 described with reference to Figure 1 to the control logic 130 or exchange data DATA with the column decoder 124.

[0080] In a read operation or a verification operation, the sense circuit 126 may generate a reference current in response to an enable bit VRYBIT signal, and output a pass signal or a fail signal PASS / FAIL by comparing a sense voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current.

[0081] The control logic 130 may control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR. Additionally, the control logic 130 may determine whether a verification operation passes or fails in response to a pass signal PASS or a fail signal FAIL.

[0082] In an embodiment, the control logic 130 may include an operation controller 131.

[0083] The operation controller 131 may control the peripheral circuit 120 to perform an internal operation according to an internal operation command input from the storage controller 200.

[0084] In an embodiment, the operation controller 131 may control the peripheral circuit 120 to perform an internal operation based on a temperature code TEMPCODE generated by the temperature information controller 140. For example, the operation controller 131 may control the voltage generator 122 to generate an internal voltage for performing an internal operation based on the temperature code TEMP CODE generated by the temperature information controller 140. Additionally, the operation controller 131 may control the peripheral circuit 120 to perform an internal operation using the internal voltage compensated according to the temperature code TEMP CODE.

[0085] The temperature information controller 140 may measure the temperature of the memory device 100. The temperature information controller 140 may provide the control logic 130 with temperature codes TEMP CODE having different voltage levels according to the measured temperature.

[0086] Figure 3 It is a diagram showing Figure 2 an embodiment of the memory cell array shown.

[0087] Referring to Figure 3 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate (not shown). The plurality of memory cells may be arranged along the +X, +Y, and +Z directions. The structure of each memory block will be described in more detail with reference to Figure 4 and Figure 5 more specifically.

[0088] Figure 4 It is a circuit diagram showing Figure 3 any one memory block BLKa among the memory blocks BLK1 to BLKz shown.

[0089] Referring to Figure 4 , the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 4 It shows that two cell strings are arranged in the column direction (i.e., the +Y direction). However, this is for convenience of description, and it will be understood that three cell strings may be arranged in the column direction.

[0090] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, first memory cells MC1 to nth memory cells MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0091] The select transistors SST and DST and the memory cells MC1 to MCn may have similar structures to each other. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing the channel layer may be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating layer, the charge storage layer, and the blocking insulating layer may be provided in each cell string.

[0092] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCp.

[0093] In an embodiment, the source select transistors of the cell strings arranged on the same row are connected to a source select line extending in the row direction, and the source select transistors of the cell strings arranged on different rows are connected to different source select lines. In Figure 4 this case, the source select transistors of the cell strings CS11 to CS1m on the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m on the second row are connected to the second source select line SSL2.

[0094] In another embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source select line.

[0095] The first memory cells MC1 to nth memory cells MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

[0096] The first memory cell MC1 to the n-th memory cell MCn can be divided into the first memory cell MC1 to the p-th memory cell MCp and the (p + 1)-th memory cell MCp+1 to the n-th memory cell MCn. The first memory cell MC1 to the p-th memory cell MCp are arranged in turn in the opposite direction of the +Z direction and are connected in series between the source selection transistor SST and the pipe transistor PT. The (p + 1)-th memory cell MCp+1 to the n-th memory cell MCn are arranged in turn in the +Z direction and are connected in series between the pipe transistor PT and the drain selection transistor DST. The first memory cell MC1 to the p-th memory cell MCp and the (p + 1)-th memory cell MCp+1 to the n-th memory cell MCn are coupled through the pipe transistor PT. The gate electrodes of the first memory cell MC1 to the n-th memory cell MCn of each cell string are respectively connected to the first word line WL1 to the n-th word line WLn.

[0097] The gate electrodes of the pipe transistors PT of each cell string are connected to the pipeline PL.

[0098] The drain selection transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m on the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m on the second row are connected to the second drain selection line DSL2.

[0099] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. In Figure 4 the cell strings CS11 and CS21 on the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m on the m-th column are connected to the m-th bit line BLm.

[0100] The memory cells in the cell strings arranged in the row direction that are connected to the same word line form a page. For example, the memory cells in the cell strings CS11 to CS1m on the first row that are connected to the first word line WL1 form a page. The memory cells in the cell strings CS21 to CS2m on the second row that are connected to the first word line WL1 form another page. When any one of the drain selection lines DSL1 and DSL2 is selected, the cell strings arranged in one row direction can be selected. When any one of the word lines WL1 to WLn is selected, a page can be selected in the selected cell string.

[0101] In another embodiment, instead of the first bit lines BL1 to the m-th bit lines BLm, even bit lines and odd bit lines may be provided. Additionally, the even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be respectively connected to the even bit lines, and the odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be respectively connected to the odd bit lines.

[0102] In an embodiment, at least one of the first memory cells MC1 to the n-th memory cells MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the reliability of the operation of the memory block BLKa improves. On the other hand, the size of the memory block BLKa increases. When the number of dummy memory cells decreases, the size of the memory block BLKa decreases. On the other hand, the reliability of the operation of the memory block BLKa may deteriorate.

[0103] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Before or after the erase operation of the memory block BLKa, a programming operation can be performed on all or some of the dummy memory cells. When the erase operation is performed after the programming operation, the threshold voltage of the dummy memory cell controls the voltage applied to the dummy word line connected to each dummy memory cell so that the dummy memory cell can have a desired threshold voltage.

[0104] Figure 5 is a diagram showing Figure 3 Another embodiment BLKb of one of the memory blocks BLK1 to BLKz shown in the figure.

[0105] Referring to Figure 5 , the memory block BLKb may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, the first memory cells MC1 to the n-th memory cells MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0106] The source selection transistors SST of each cell string are connected between the common source line CSL and the memory cells MC1 to MCn. The source selection transistors of the cell strings arranged on the same row are connected to the same source selection line. The source selection transistors of the cell strings CS11’ to CS1m’ arranged on the first row are connected to the first source selection line SSL1. The source selection transistors of the cell strings CS21’ to CS2m’ arranged on the second row are connected to the second source selection line SSL2. In another embodiment, the source selection transistors of the cell strings CS11’ to CS1m’ and CS21’ to CS2m’ can be commonly connected to one source selection line.

[0107] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected in series between the source selection transistor SST and the drain selection transistor DST. The gate electrodes of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0108] The drain selection transistors DST of each cell string are connected between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors of the cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11’ to CS1m’ on the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21’ to CS2m’ on the second row are connected to the second drain selection line DSL2.

[0109] Therefore, except for excluding the pipe transistors PT from each cell string of Figure 5 the memory block BLKb has a circuit similar to that of Figure 5 the memory block BLKa of Figure 4

[0110] In another embodiment, instead of the first bit line BL1 to the mth bit line BLm, even bit lines and odd bit lines can be provided. Additionally, the even-numbered cell strings among the cell strings CS11’ to CS1m’ or CS21’ to CS2m’ arranged in the row direction can be respectively connected to the even bit lines, and the odd-numbered cell strings among the cell strings CS11' to CS1m’ or CS21’ to CS2m’ arranged in the row direction can be respectively connected to the odd bit lines.

[0111] ​In an embodiment, at least one of the first memory cell MC1 to the n-th memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the reliability of the operation of the memory block BLKb improves. On the other hand, the size of the memory block BLKb increases. When the number of dummy memory cells decreases, the size of the memory block BLKb decreases. On the other hand, the reliability of the operation of the memory block BLKb may deteriorate.

[0112] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Before or after the erase operation of the memory block BLKb, a program operation can be performed on all or some of the dummy memory cells. When the erase operation is performed after the program operation, the threshold voltage of the dummy memory cell controls the voltage applied to the dummy word line connected to each dummy memory cell so that the dummy memory cell can have a desired threshold voltage.

[0113] Figure 6 is a diagram showing, for example Figure 1 the connection relationship between the storage controller and a plurality of memory devices as shown.

[0114] Referring to Figure 6 , the storage controller 200 can be connected to a plurality of memory devices (memory device_11 to memory device_24) through a plurality of channels CH1 and CH2. In an embodiment, it will be understood that the number of channels or the number of memory devices connected to each channel can be modified differently. However, in this specification, it is assumed that the storage controller 200 is connected to the memory devices through two channels and four memory devices are connected to each channel.

[0115] For convenience of description, the operations of the memory device_11, memory device_12, memory device_13, and memory device_14 connected to the first channel CH1 will be described. It will be understood that the memory devices (memory device_21 to memory device_24) connected to the other channel CH2 also operate similarly to the memory device_11, memory device_12, memory device_13, and memory device_14.

[0116] Memory devices _11 to _14 can be commonly connected to the first channel CH1. Memory devices _11 to _14 can communicate with the storage controller 200 through the first channel CH1. Since memory devices _11 to _14 are commonly connected to the storage controller 200 through the first channel CH1, only one memory device can communicate with the storage controller 200 at a time. However, operations respectively performed inside memory devices _11 to _14 can be executed simultaneously. As used herein, the terms "simultaneously" and "at the same time" mean occurring over overlapping time intervals. For example, if a first occurs during a first time interval and a second occurs simultaneously during a second time interval, the first interval and the second interval overlap at least partially with each other such that there is a time when both the first and the second occur.

[0117] A storage device using multiple memory devices can use Figure 1 the interleaving techniques described in to improve performance. For the purpose of the interleaving technique, memory devices can be managed in units of channels and paths. To maximize the parallelization of memory devices connected to respective channels, the storage controller 200 can distribute and allocate consecutive logical memory areas in units of channels and paths.

[0118] For example, the storage controller 200 can send commands, control signals including addresses, and data to the memory device _11 through the first channel CH1. When the memory device _11 programs the received data in the memory cells included therein, the storage controller can send commands, control signals including addresses, and data to the memory device _12.

[0119] In Figure 6 multiple memory devices can constitute four paths WAY1 to WAY2. The first path WAY1 can include the memory device _11 and the memory device _21. The second path WAY2 can include the memory device _12 and the memory device _22. The third path WAY3 can include the memory device _13 and the memory device _23. The fourth path WAY4 can include the memory device _14 and the memory device _24.

[0120] Each of the channels CH1 and CH2 can be a signal bus that is shared and uses the memory devices connected to the corresponding channel.

[0121] Although Figure 6 the interleaving of a 2-channel / 4-path structure is described in, as the number of channels increases and as the number of paths increases, the interleaving can become more efficient.

[0122] Figure 7 is a diagram showing the internal operations of a memory device.

[0123] Reference Figure 7 As shown in Figure 7 , the memory device 100 may perform internal operations corresponding to internal operation commands input from the storage controller 200. The internal operations may include a read operation, a program operation, and an erase operation. In addition, for convenience of description, Figure 7 the operation of measuring the internal operation of the memory device 100 in the read operation is shown in Figure 7 . However, the operation of measuring the internal operation of the memory device 100 may also be performed even in the program operation or the erase operation.

[0124] In an embodiment, the read operation of the memory device 100 may include a page buffer setup operation PB Setup, a storage block precharge operation BLK Precharge, a temperature measurement operation DST, a word line rise operation WL Rise, a sensing operation Sensing, and a discharge operation Discharge. However, the above set of operations included in the read operation is only an example, and another operation may be added in some embodiments.

[0125] For example, at the start of the read operation, the memory device 100 may perform the temperature measurement operation DTS together with the page buffer setup operation PB Setup or the storage block precharge operation BLK Precharge. The memory device 100 may perform the word line rise operation WL Rise after the temperature measurement operation DTS is completed. Therefore, the word line rise operation WL Rise is not performed before the temperature measurement operation DTS is completed, and thus, an overhead may occur in the read operation.

[0126] Since the memory device 100 performs the temperature measurement operation whenever the read operation is executed, when the interval between multiple read operations is short, the time required to perform multiple read operations is extended.

[0127] Therefore, according to an embodiment of the present disclosure, the memory device 100 omits the temperature measurement operation for internal operation commands input during a set period, and performs internal operations corresponding to the internal operation commands based on a pre-generated temperature code, so that the operation speed of the memory device 100 can be improved.

[0128] Hereinafter, reference will be made to Figure 8 to describe the memory device 100 according to an embodiment of the present disclosure.

[0129] Figure 8 is a diagram showing an example of a memory device according to an embodiment of the present disclosure.

[0130] Reference Figure 8 As shown in Figure 8 , the memory device 100 may include a peripheral circuit 120, an operation controller 131, and a temperature information controller 800.

[0131] In Figure 8Among them, the peripheral circuit 120 and the operation controller 131 can be configured and operated in the same manner as the peripheral circuit 120 and the operation controller 131 described with reference to Figure 2 respectively. The temperature information controller 800 can represent Figure 2 the temperature information controller 140 shown.

[0132] The temperature information controller 800 can include a temperature sensor 810, a temperature code generator 820, a temperature information storage unit 830, a temperature measurement controller 840, and a time period counter 850.

[0133] The temperature sensor 810 can measure the internal temperature according to the internal operation command input from the storage controller 200. For example, at the start of the internal operation corresponding to the internal operation command, the temperature sensor 810 can measure the internal temperature. In an embodiment, when performing the internal operation corresponding to the first internal operation command among a plurality of internal operation commands input from the storage controller 200, the temperature sensor 810 can measure the internal temperature. The first internal operation command can be input in a state where no temperature code is generated.

[0134] In addition, the temperature sensor 810 can omit the temperature measurement operation for the internal operation corresponding to the internal operation command under the control of the temperature measurement controller 840. That is, under the control of the temperature measurement controller 840, the temperature sensor 810 may not measure the internal temperature for the internal operation.

[0135] The temperature code generator 820 can generate a temperature code corresponding to the measured internal temperature. For example, the temperature code generator 820 can generate a first temperature code corresponding to the measured internal temperature according to the first internal operation command.

[0136] The temperature information storage unit 830 can store the temperature code and the temperature code generation information indicating the information that the temperature code has been generated during the set time period. The set time period can be a time period set by the user or a time period set during the manufacturing process of the memory device 100.

[0137] In an embodiment, the temperature code generation information can have a first state value indicating the information that the temperature code has been generated. In addition, in an embodiment, the temperature code generation information can have a second state value indicating the information that the temperature code has not been generated. The first state value can be "1" (or "0"), and the second state value can be "0" (or "1").

[0138] In an embodiment, the temperature information storage unit 830 can store the first temperature code generated according to the first internal operation command and the temperature code generation information indicating the information that the first temperature code has been generated.

[0139] The temperature measurement controller 840 can determine whether to measure the internal temperature based on the information generated from the temperature code. For example, the temperature measurement controller 840 can determine whether to measure the internal temperature when performing an internal operation corresponding to a second internal operation command input after the first internal operation command among multiple internal operation commands, based on the information generated from the temperature code.

[0140] In an embodiment, the temperature measurement controller 840 can control the temperature sensor 810 to omit measuring the internal operation according to the determination of whether to measure the internal temperature. The operation controller 131 can control the peripheral circuit 120 to perform the internal operation corresponding to the second internal operation command based on the first temperature code generated according to the first internal operation command and the temperature code generation information. For example, when the temperature code generation information has a first state value when performing the internal operation corresponding to the second internal operation command, the operation controller 131 can control the peripheral circuit 120 to perform the internal operation corresponding to the second internal operation command based on the first temperature code generated according to the first internal operation command.

[0141] In an embodiment, the temperature measurement controller 840 can control the temperature sensor 810 to measure the internal temperature according to the determination of whether to measure the internal operation. For example, when the temperature code generation information has a second state value when performing the internal operation corresponding to the second internal operation command, the temperature measurement controller 840 can control the temperature sensor 810 to measure the internal temperature when performing the internal operation corresponding to the second internal operation command. The temperature code generator 820 can generate a second temperature code corresponding to the internal temperature measured when performing the internal operation corresponding to the second internal operation command. The operation controller 131 can control the peripheral circuit 120 to perform the internal operation corresponding to the second internal operation command based on the second temperature code generated according to the second internal operation command.

[0142] In an embodiment, the temperature measurement controller 840 can change the state value of the temperature code generation information. For example, when generating a first temperature code according to the first internal operation command, the temperature measurement controller 840 can change the state value of the temperature code generation information to the first state value. Additionally, when generating a second temperature code according to the second internal operation command, the temperature measurement controller 840 can change the state value of the temperature code generation information to the first state value. The first state value of the temperature code generation information can be maintained during a set period.

[0143] Furthermore, when the set period has elapsed, the temperature measurement controller 840 can change the state value of the temperature code generation information to the second state value. For example, when it is determined that the period set by the period counter 850 has elapsed, the temperature measurement controller 840 can change the state value of the temperature code generation information from the first state value to the second state value.

[0144] The time period counter 850 may generate a time period count value that decreases every set time period starting from the time when the internal temperature is measured. For example, when a first temperature code is generated according to a first internal operation command, the time period counter 850 may generate a time period count value. Additionally, when a second temperature code is generated according to a second internal operation command, the time period counter 850 may generate a time period count value.

[0145] In an embodiment, the time period counter 850 may determine whether the set time period has elapsed based on whether the decreasing time period count value matches a target count value. The target count value may be "0". For example, when the decreasing time period count value becomes 0 when the time period count value is decreased for each set time period, the time period counter 850 may determine that the set time period has elapsed, such that the temperature code generation information has a first state value. The time period counter 850 may provide information that the set time period has elapsed to the temperature measurement controller 840, and the temperature measurement controller 840 may change the state value of the temperature code generation information to a second state value in response to the information provided from the time period counter 850.

[0146] Figure 9 FIG. is a diagram illustrating an example of performing an internal operation according to an embodiment of the present disclosure.

[0147] In Figure 9 it is assumed that the memory device 100 includes a plurality of planes, Plane1 to Plane4. Although the case where the memory device 100 includes four planes is described, this is for convenience of description, and the number of planes included in one memory device is not limited to Figure 9 the embodiment shown. In an embodiment, a plane may be a unit for independently performing a programming operation, a read operation, or an erase operation on a set of memory blocks within the plane. Additionally, Figure 1 the interleaving technique described in

[0148] When the memory device 100 receives a read command a (Read1_a) for the first plane Plane1 from the storage controller 200, the memory device 100 may perform a read operation corresponding to the read command a (Read1_a) for the first plane Plane1. The memory device 100 may generate a temperature code DTS_CODE. For example, the memory device 100 may generate a temperature code A (Temp Code A) by measuring the internal temperature to perform a read operation corresponding to the read command a (Read1_a) for the first plane Plane1. Additionally, the memory device 100 may change the status value of the temperature code generation information DTS_FLAG indicating the information that the temperature code has been generated to a first status value. The first status value of the temperature code generation information DTS_FLAG may be maintained during a set period DTS_Interval. The memory device 100 may store the temperature code A (Temp CodeA) during the set period DTS_Interval.

[0149] Subsequently, the memory device 100 may receive a read command a (Read2_a) for the second plane Plane2, a read command a (Read3_a) for the third plane Plane3, and a read command a (Read4_a) for the fourth plane Plane4 from the storage controller 200. When performing read operations corresponding to the read command a (Read2_a) for the second plane Plane2, the read command a (Read3_a) for the third plane Plane3, and the read command a (Read4_a) for the fourth plane Plane4, respectively, the temperature code generation information DTS_FLAG has a first status value. The memory device 100 may omit the operation of measuring the internal temperature. Accordingly, the memory device 100 may perform read operations corresponding to the read command a (Read2_a) for the second plane Plane2, the read command a (Read3_a) for the third plane Plane3, and the read command a (Read4_a) for the fourth plane Plane4, respectively, based on the temperature code A (Temp Code A).

[0150] Additionally, when generating the temperature code A (Temp Code A), the memory device 100 may generate a period count value DTS_CNT. In an embodiment, the period count value DTS_CNT may include a start value FFh and an end value 00h. The memory device 100 may decrease the period count value DTS_CNT every set period. When the decreased period count value DTS_CNT corresponds to "0" (00h), the memory device 100 may change the status value of the temperature code generation information DTS_FLAG to a second status value. In some embodiments, the memory device 100 may remove the temperature code A (Temp Code A).

[0151] Subsequently, the memory device 100 may receive a read command b (Read2_b) for the second plane Plane2 from the storage controller 200. The memory device 100 may regenerate the temperature code DTS_CODE. For example, since the status value of the temperature code generation information DTS_FLAG is in a state where the status value changes to a second status value, the memory device 100 may generate a temperature code B (Temp Code B) by measuring the internal temperature to perform a read operation corresponding to the read command b (Read2_b) for the second plane Plane2. Additionally, the memory device 100 may change the status value of the temperature code generation information DTS_FLAG to a first status value. The first status value of the temperature code generation information DTS_FLAG may be maintained during a set period DTS_Interval. The memory device 100 may store the temperature code B (Temp Code B) during the set period DTS_Interval.

[0152] Subsequently, the memory device 100 may receive a read command b (Read3_b) for the third plane Plane3 and a read command c (Read2_c) for the second plane Plane2 from the storage controller 200. When performing read operations corresponding to the read command b (Read3_b) for the third plane Plane3 and the read command c (Read2_c) for the second plane Plane2 respectively, the temperature code generation information DST_FLAG has a first status value. The memory device 100 may omit the operation of measuring the internal temperature. Therefore, the memory device 100 may perform read operations corresponding to the read command b (Read3_b) for the third plane Plane3 and the read command c (Read2_c) for the second plane Plane2 respectively based on the temperature code B (Temp Code B).

[0153] Additionally, when generating the temperature code B (Temp Code B), the memory device 100 may generate a period count value DST_CNT. In an embodiment, the period count value DTS_CNT may include a start value FFh and an end value 00h. The memory device 100 may decrease the period count value DTS_CNT every set period. When the decreased period count value DTS_CNT corresponds to "0" (00h), the memory device 100 may change the status value of the temperature code generation information DTS_FLAG to a second status value. In some embodiments, the memory device 100 may remove the temperature code B (Temp Code B).

[0154] Thus, according to an embodiment of the present disclosure, since each read operation corresponding to the read command a (Read1_a) for the first plane Plane1 and the read command b (Read2_b) for the second plane Plane2 performs an operation of measuring an internal operation, the time (tDTS1) required to perform the read operation is long. On the other hand, since each read operation corresponding to other read commands except the read command a (Read1_a) for the first plane Plane1 and the read command b (Read2_b) for the second plane Plane2 does not perform an operation of measuring an internal temperature, the time (tDTS2) required to perform the read operation is reduced.

[0155] Figure 10 FIG. is a diagram showing another example of a memory device according to an embodiment of the present disclosure.

[0156] In Figure 10 FIG., the memory device 100 may be a memory package including a plurality of memory chips 100_1 and 100_2. Although the case where the memory device 100 includes two memory chips is described, this is for convenience of description, and the number of memory chips included in one memory device is not limited to Figure 10 the embodiment shown. In addition, Figure 1 the interleaving technique described in FIG. may be applied to the plurality of memory chips 100_1 and 100_2.

[0157] In an embodiment, each of the first memory chip 100_1 and the second memory chip 100_2 may include Figure 8 the temperature information controller 800 shown in FIG. However, the present disclosure is not necessarily limited thereto. In some embodiments, one temperature information controller may generate a temperature code and temperature code generation information regarding each of the first memory chip 100_1 and the second memory chip 100_2.

[0158] The first memory chip 100_1 may receive a first internal operation command from the storage controller 200. In addition, the first memory chip 100_1 may store a temperature code generated according to the first internal operation command and temperature code generation information indicating information that the temperature code has been generated during a set period. The status value of the temperature code generation information may have a first status value.

[0159] After the first internal operation command is input to the first memory chip 100_1, the second memory chip 100_2 may receive a second internal operation command from the storage controller 200. In addition, the second memory chip 100_2 may perform an internal operation corresponding to the second internal operation command based on the temperature code stored in the first memory chip 100_1 in response to the second internal operation command.

[0160] For example, assume that no temperature code is generated in the second memory chip 100_2, and the temperature code generation information stored in the second memory chip 100_2 has a second status value. For example, the second memory chip 100_2 may first check the temperature code generation information stored in the second memory chip 100_2. Since the temperature code generation information of the second memory chip 100_2 has a second status value, the temperature code generation information of the first memory chip 100_1 may be checked. For example, the second memory chip 100_2 may request the temperature code generation information stored in the first memory chip 100_1 from the first memory chip 100_1. Since the temperature code generation information stored in the first memory chip 100_1 has a first status value, the second memory chip 100_2 may perform an internal operation corresponding to the second internal operation command based on the temperature code stored in the first memory chip 100_1.

[0161] In addition, the first memory chip 100_1 and the second memory chip 100_2 may further include an interface for controlling communication between the memory chips to perform an operation of sharing the above temperature code.

[0162] In addition, although Figure 10 the sharing of temperature codes among multiple memory chips is described, the present disclosure is not necessarily limited thereto. In some embodiments, temperature codes may be shared among multiple memory devices.

[0163] Figure 11 is a flowchart showing an operation method of a memory device according to an embodiment of the present disclosure.

[0164] Figure 11 The operation method shown may be performed by, for example, Figure 2 or Figure 8 the memory device 100 shown.

[0165] In step S1101, the memory device 100 may receive a first internal operation command from the storage controller 200.

[0166] In step S1103, the memory device 100 may generate a first temperature code corresponding to the internal temperature when performing an internal operation corresponding to the first internal operation command in response to the first internal operation command.

[0167] In step S1105, the memory device 100 may generate temperature code generation information representing information that the first temperature code has been generated during a set period. For example, the memory device 100 may generate temperature code generation information having a first status value representing information that the first temperature code has been generated according to the first internal operation command.

[0168] In step S1107, the memory device 100 may receive a second internal operation command from the storage controller 200. For example, after the memory device 100 receives the first internal operation command, the memory device 100 may receive the second internal operation command.

[0169] In step S1109, the memory device 100 may perform an internal operation corresponding to the second internal operation command in response to the second internal operation command based on the first temperature code generated according to the first internal operation command and the temperature code generation information.

[0170] Figure 12 is a flowchart showing a method of generating a temperature code according to an embodiment of the present disclosure.

[0171] Figure 12 The method shown may be performed by, for example Figure 2 or Figure 8 the memory device 100 shown.

[0172] In step S1201, the memory device 100 may receive a second internal operation command from the storage controller 200.

[0173] In step S1203, the memory device 100 may determine whether the temperature code generation information has a first state value in response to the second internal operation command. For example, the memory device 100 may determine whether to measure the internal temperature based on the temperature code generation information in response to the second internal operation command.

[0174] When, based on the determination result in step S1203, the temperature code generation information has the first state value, the memory device 100 may not measure the internal temperature. The memory device 100 may perform an internal operation corresponding to the second internal operation command based on the first temperature code generated according to the first internal operation command.

[0175] Alternatively, when, based on the determination result in step S1203, the temperature code generation information does not have the first state value, in step S1205, the memory device 100 may generate a period count value that decreases every set period starting from the time when the internal temperature is measured. For example, when the temperature code generation information has a second state value instead of the first state value, the memory device 100 may generate a period count value.

[0176] In step S1207, the memory device 100 may generate a second temperature code corresponding to the internal temperature when performing an internal operation corresponding to the second internal operation command in response to the temperature code generation information having the second state value. The memory device 100 may perform an internal operation corresponding to the second internal operation command based on the second temperature code generated according to the second internal operation command.

[0177] Figure 13 is a flowchart showing a method of generating temperature code generation information according to an embodiment of the present disclosure.

[0178] Figure 13 The method shown can be performed by, for example, Figure 2 or Figure 8 the memory device 100 shown.

[0179] In step S1301, the memory device 100 may generate a time period count value. For example, the time period count value may be generated when measuring the internal temperature.

[0180] In step S1303, the memory device 100 may decrease the time period count value. For example, the memory device may count down the time period count value from the time period count value to "0". The time period during which the time period count value counts down from the time period count value to "0" may correspond to the time period during which the temperature code generation information maintains a first state value.

[0181] In step S1305, the memory device 100 may determine whether the time period count value is equal to a target count value. For example, the target count value may be "0".

[0182] When, based on the determination result in step S1305, the time period count value is not equal to the target count value, the memory device 100 may proceed to step S1303 to decrease the time period count value. That is, the memory device 100 executes steps S1303 and S1305 until the time period count value becomes "0". When the time period count value becomes "0", the memory device 100 may determine that a set time period has elapsed. The set time period may be the time period during which the temperature code generation information maintains a first state value. Therefore, the memory device 100 can manage the time period during which the temperature code generation information maintains a first state value through steps S1303 and S1305.

[0183] When, based on the determination result in step S1305, the time period count value is equal to the target count value, in step S1307, the memory device 100 may change the state value of the temperature code generation information to a second state value when the set time period has elapsed.

[0184] Figure 14 is a diagram showing Figure 1 the storage controller shown.

[0185] Referring to Figure 1 and Figure 14 , the storage controller 200 may include a processor 220, a RAM 230, an error correction circuit 240, a ROM 250, a host interface 270, and a flash memory interface 280.

[0186] The processor 220 can control the overall operation of the storage controller 200. The RAM 230 can be used as a buffer memory, cache memory, working memory, etc. of the storage controller 200.

[0187] The error correction circuit 240 can perform error correction. The error correction circuit 240 can perform error correction code (ECC) encoding on data to be written to the memory device through the flash memory interface 280. The ECC-decoded data can be transmitted to the memory device through the flash memory interface 280. The error correction circuit 240 can perform ECC decoding on data received from the memory device through the flash memory interface 280. For example, the error correction circuit 240 can be included in the flash memory interface 280 as a component of the flash memory interface 280.

[0188] The ROM 260 can store various information required in the operation of the storage controller 200 in the form of firmware.

[0189] The storage controller 200 can communicate with an external device (e.g., the host 300, application processor, etc.) through the host interface 270.

[0190] The storage controller 200 can communicate with the memory device 100 through the flash memory interface 280. The storage controller 200 can send commands CMD, addresses ADDR, control signals CTRL, etc. to the memory device 100 through the flash memory interface 280, and receive data DATA. For example, the flash memory interface 280 can include a NAND interface.

[0191] Figure 15 is a block diagram of a memory card system of an application storage device according to an embodiment of the present disclosure.

[0192] Refer to Figure 15 , the memory card system 2000 includes a storage controller 2100, a memory device 2200, and a connector 2300.

[0193] The storage controller 2100 is connected to the memory device 2200. The storage controller 2100 can access the memory device 2200. For example, the storage controller 2100 can control read operations, write operations, erase operations, and background operations of the memory device 2200. The storage controller 2100 provides an interface between the memory device 2200 and the host Host. The storage controller 2100 drives the firmware for controlling the memory device 2200. The storage controller 2100 can be implemented in the same way as the storage controller 200 described with reference to Figure 1 The memory device 2200 can be implemented in the same way as the memory device 100 described with reference to Figure 2 described.

[0194] For example, the storage controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC circuit.

[0195] The storage controller 2100 may communicate with an external device through the connector 2300. The storage controller 2100 may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the storage controller 2100 may communicate with an external device through at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0196] For example, the memory device 2200 may be implemented using various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0197] The storage controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the storage controller 2100 and the memory device 2200 may form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash (CF) card, a SmartMedia card (SM and SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a Universal Flash Storage (UFS).

[0198] Figure 16 is a block diagram of, for example, a solid state drive (SSD) system applying a storage device according to an embodiment of the present disclosure.

[0199] Referring to Figure 16 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0200] In an embodiment, the SSD controller 3210 can be used as the storage controller 200 described with reference to Figure 1 Description.

[0201] The SSD controller 3210 can control a plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG can be a signal based on the interface between the host 3100 and the SSD 3200. For example, the signal SIG can be a signal defined by at least one of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0202] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. When the power supply from the host 3100 is not smooth, the auxiliary power supply 3230 can provide power to the SSD 3200. For example, the auxiliary power supply 3230 can be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to the SSD 3200.

[0203] The buffer memory 3240 operates as the buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or temporarily store metadata (e.g., mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0204] Figure 17 is a block diagram of a user system of an application storage device according to an embodiment of the present disclosure.

[0205] Referring to Figure 17 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0206] The application processor 4100 can drive components, an operating system (OS), user programs, etc. included in the user system 4000. For example, the application processor 4100 can include a controller, an interface, a graphics engine, etc. for controlling components included in the user system 4000. The application processor 4100 can be provided as a system on a chip (SoC).

[0207] The memory module 4200 can operate as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 can include volatile random access memories such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM or non-volatile random access memories such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be provided as one semiconductor package through a package on package (PoP) package.

[0208] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0209] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can send the data stored therein to the application processor 4100. For example, the storage module 4400 can be implemented using non-volatile semiconductor memory devices such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory having a three-dimensional structure. For example, the storage module 4400 can be provided as a removable drive or an external drive such as a memory card of the user system 4000.

[0210] For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate in the same manner as the memory device 100 described with reference to Figure 1 The storage module 4400 can operate in the same manner as the storage device 50 described with reference to Figure 1

[0211] ​The user interface 4500 may include an interface for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric element. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), organic light emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0212] According to the present disclosure, a memory device having an improved operation speed and an operation method of the memory device may be provided.

[0213] Although the present disclosure has been shown and described with reference to specific examples of its embodiments, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0214] In the above embodiments, all steps may be selectively executed, or some steps may be omitted. In each embodiment, the steps do not necessarily have to be executed in the order described, but may be rearranged. The embodiments disclosed in this specification and the drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0215] In addition, examples of embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms have been used herein, those terms are only used to describe the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many variations may be made within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0216] Cross-reference to related applications

[0217] This application claims priority to Korean Patent Application No. 10-2020-0105550, filed on August 21, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device including a plurality of planes, the memory device comprising: A peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from a memory controller; A temperature information controller configured to generate a first temperature code and temperature code generation information, the first temperature code corresponding to an internal temperature during an internal operation corresponding to a first internal operation command for performing an internal operation on a first plane among the plurality of planes among the plurality of internal operation commands, and the temperature code generation information indicating information that the first temperature code has been generated during a set period; And An operation controller configured to, in response to a second internal operation command for performing an internal operation on a second plane among the plurality of planes, which is input after the first internal operation command among the plurality of internal operation commands, control the peripheral circuit to perform an internal operation corresponding to the second internal operation command based on the first temperature code and the temperature code generation information, Wherein a plane is a unit for independently performing the internal operation on a group of memory blocks within the plane.

2. The memory device according to claim 1, wherein, The temperature information controller includes: A temperature sensor configured to measure the internal temperature according to the first internal operation command; A temperature code generator configured to generate the first temperature code corresponding to the measured internal temperature; A temperature information storage unit configured to store the first temperature code and the temperature code generation information; and A temperature measurement controller configured to determine whether to measure the internal temperature during the internal operation corresponding to the second internal operation command based on the temperature code generation information.

3. The memory device according to claim 2, wherein, When the first temperature code is generated, the temperature measurement controller changes a state value of the temperature code generation information to a first state value indicating information that the first temperature code has been generated.

4. The memory device according to claim 3, wherein, When the temperature code generation information has the first state value during the internal operation corresponding to the second internal operation command, the operation controller controls the peripheral circuit to perform the internal operation corresponding to the second internal operation command based on the first temperature code.

5. The memory device according to claim 2, wherein, The temperature information controller further includes a period counter configured to generate a period count value that decreases every set period starting from the time when the internal temperature is measured when the first temperature code is generated.

6. The memory device according to claim 5, wherein, The period counter determines whether the set period has elapsed based on whether the decreased period count value is equal to a target count value.

7. The memory device according to claim 6, wherein, When the set period elapses, the temperature measurement controller changes the state value of the temperature code generation information to a second state value indicating information that the first temperature code has not been generated.

8. The memory device according to claim 7, wherein, When the temperature code generation information has the second state value when performing the internal operation corresponding to the second internal operation command, the temperature measurement controller controls the temperature sensor to measure the internal temperature when performing the internal operation corresponding to the second internal operation command, and wherein, the temperature code generator generates a second temperature code corresponding to the internal temperature measured when performing the internal operation corresponding to the second internal operation command.

9. The memory device according to claim 8, wherein, The operation controller controls the peripheral circuit to perform the internal operation corresponding to the second internal operation command based on the second temperature code.

10. The memory device according to claim 1, wherein, The plurality of internal operations includes at least one of a read operation, a programming operation, and an erase operation.

11. A method of operating a memory device including a first memory chip and a second memory chip, the method comprising the steps of: receiving, by the first memory chip, a first internal operation command input from a storage controller; generating, by the first memory chip, a first temperature code corresponding to the internal temperature when performing the internal operation corresponding to the first internal operation command in response to the first internal operation command; generating, by the first memory chip, temperature code generation information representing information that the first temperature code has been generated during a set period; receiving, by the second memory chip, a second internal operation command input from the storage controller; and performing, by the second memory chip, an internal operation corresponding to the second internal operation command based on the first temperature code and the temperature code generation information in response to the second internal operation command.

12. The method according to claim 11, the method further comprising the following steps: Determining whether to measure the internal temperature when performing the internal operation corresponding to the second internal operation command based on the temperature code generation information in response to the second internal operation command.

13. The method according to claim 12, wherein, In the step of generating the temperature code generation information, temperature code generation information having a first state value representing information that the first temperature code has been generated is generated.

14. The method according to claim 13, wherein, In the step of performing the internal operation corresponding to the second internal operation command, the internal operation corresponding to the second internal operation command is performed based on the first temperature code in response to the temperature code generation information having the first state value.

15. The method according to claim 12, the method further comprising the following steps: Generating a period count value that decreases every set period starting from the time when the internal temperature is measured.

16. The method according to claim 15, the method further comprising the following steps: Determining whether the set period has elapsed according to whether the decreased period count value is equal to a target count value.

17. The method according to claim 16, the method further comprising the steps of: When the set period has elapsed, changing the state value of the temperature code generation information to a second state value representing information that the first temperature code has not been generated yet.

18. The method according to claim 17, the method further comprising the steps of: Generating a second temperature code corresponding to the internal temperature measured when performing the internal operation corresponding to the second internal operation command in response to the temperature code generation information having the second state value.

19. The method according to claim 18, wherein, In the step of performing the internal operation corresponding to the second internal operation command, the internal operation corresponding to the second internal operation command is performed based on the second temperature code.

20. A memory device, the memory device comprising: A first memory chip, the first memory chip being configured to receive a first internal operation command input from a storage controller, and store a temperature code generated according to the first internal operation command and temperature code generation information indicating information that the temperature code has been generated during a set period; And A second memory chip, the second memory chip being configured to receive a second internal operation command input from the storage controller after the first internal operation command is input to the first memory chip, and execute an internal operation corresponding to the second internal operation command based on the temperature code and the temperature code generation information stored on the first memory chip in response to the second internal operation command.

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