Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a base structure; an etching hole (700) connected to an epitaxial layer (100) is formed by etching at a position of the base structure near a gate (200); an ALD layer (910) is deposited on a portion of the inner wall of the etching hole (700) close to the opening; and a metal contact (800) is filled in the etching hole (700). The semiconductor device and the manufacturing method thereof of the present invention are novel in design and highly practical.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate; and patterning the multiple material layers using photolithography to form circuit components and elements thereon.

[0003] Figure 1 A schematic diagram showing a first step state of a conventional method for manufacturing a semiconductor device is shown; Figure 2 Shows Figure 1 A schematic diagram of the second step of the manufacturing method shown; Figure 3 Shows Figure 1 The third step state schematic diagram of the manufacturing method shown in the figure; the manufacturing method of the semiconductor device comprises: step S1, providing a basic structure, the basic structure comprises a substrate (not shown in the figure) and an epitaxial layer 100 formed on the substrate, a gate 200 is arranged on the epitaxial layer 100, and a barrier layer 210 is formed on the side wall of the gate 200, the basic structure also comprises a first dielectric layer 300 covering the epitaxial layer 100 and being flush with the gate 200 and the barrier layer 210, a masking layer 400 covering the gate 200, the first dielectric layer 300 and the barrier layer 210, and a second dielectric layer 500 covering the masking layer 400; step S2, coating a photoresist 600 on the second dielectric layer 500, as shown in FIG. Figure 1 Step S3, using the photoresist 600 through the photolithography process, the base structure is located near the gate 200 to form an etching hole 700 connected to the epitaxial layer 100, and then remove the photoresist 600, such as Figure 2 Step S4, forming a metal contact 800 with an isolation layer 810 in the etching hole 700, as shown Figure 3 As shown. The isolation layer 810 is generally made of Ti or TiN. For this manufacturing method, since the masking layer 400 is also etched at the same time during the formation of the window of the etching hole 700 connected to the epitaxial layer 100, a trade-off needs to be made between the two.

[0004] Figure 4 A schematic diagram showing the first step of another conventional method for manufacturing a semiconductor device is shown; Figure 5 Shows Figure 4 A schematic diagram of the second step of the manufacturing method shown; Figure 6 Shows Figure 4 A schematic diagram of the third step of the manufacturing method shown; Figure 7 Shows Figure 4A schematic diagram of the fourth step of the manufacturing method shown; Figure 8 Shows Figure 4 The fifth step state diagram of the manufacturing method shown in the figure. The manufacturing method of the semiconductor device comprises: step S1, providing a basic structure, the basic structure comprises a substrate (not shown in the figure) and an epitaxial layer 100 formed on the substrate, a gate 200 is arranged on the epitaxial layer 100, and a barrier layer 210 is formed on the side wall of the gate 200, the basic structure also comprises a first dielectric layer 300 covering the epitaxial layer 100 and being flush with the gate 200 and the barrier layer 210, a masking layer 400 covering the gate 200, the first dielectric layer 300 and the barrier layer 210, and a second dielectric layer 500 covering the masking layer 400; step S2, coating a photoresist 600 on the second dielectric layer 500, as shown in FIG. Figure 4 Step S3, using the photoresist 600 through the photolithography process, the base structure is located near the gate 200 to form an etching hole 700 connected to the epitaxial layer 100, and then remove the photoresist 600, such as Figure 5 Step S4, by ALD (atomic layer deposition) technology, the SiN layer 900 is deposited on the inner wall of the etching hole 700, as shown Figure 6 Step S5, by etching technology, the SiN layer 900 is etched away at the bottom of the etching hole 700, as shown in FIG. Figure 7 Step S6, forming a metal contact 800 with an isolation layer 810 in the etching hole 700, as shown in FIG. Figure 8 As shown. The isolation layer 810 is generally made of Ti or TiN. For this manufacturing method, due to the use of ALD (atomic layer deposition) technology, the diameter of the etching hole 700 is reduced, especially the window where the etching hole 700 connects with the epitaxial layer 100 is reduced; two etching steps are used, causing two damages to the epitaxial layer 100. Summary of the invention

[0005] The purpose of the present invention is to solve the above technical problems and provide a semiconductor device and a method for manufacturing the same.

[0006] The technical solution of the present invention to solve the technical problem is:

[0007] The present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0008] Step S1, providing a basic structure, the basic structure comprising a substrate and an epitaxial layer formed on the substrate, a gate being arranged on the epitaxial layer, and a barrier layer being formed on the sidewall of the gate; the basic structure further comprising a first dielectric layer covering the epitaxial layer and being flush with the gate and the barrier layer, a masking layer covering the gate, the first dielectric layer and the barrier layer, and a second dielectric layer covering the masking layer;

[0009] Step S2, coating photoresist on the second dielectric layer;

[0010] Step S3, using photoresist through a photolithography process to etch a hole connected to the epitaxial layer at a position of the base structure near the gate, and then removing the photoresist;

[0011] Step S4, filling the etching hole with a spin coating material, thereby forming a filling body in the etching hole;

[0012] Step S5, etching the filling body; and retaining a portion of the filling body located at the bottom of the etching hole as a support body;

[0013] Step S6, depositing an ALD layer on the top surface of the second dielectric layer, the top surface of the support body, and the inner wall of the etching hole located above the support body by using the ALD technology;

[0014] Step S7, etching away the portion of the ALD layer covering the top surface of the second dielectric layer and the top surface of the support body by etching technology, and stripping off the support body at the same time;

[0015] Step S8: Fill the etched holes to form metal contacts.

[0016] In the method for manufacturing the semiconductor device of the present invention, the height of the top surface of the support body is lower than the height of the top surface of the gate.

[0017] In the above-mentioned method for manufacturing a semiconductor device of the present invention, the barrier layer is made of the following materials: SiN, SiCN, SiO2, SiOC, SiOCN or a combination thereof.

[0018] In the above-mentioned method for manufacturing a semiconductor device of the present invention, the ALD layer is made of a dielectric material.

[0019] In the above-mentioned method for manufacturing a semiconductor device of the present invention, the metal contact is made of tungsten, copper, aluminum or a combination thereof.

[0020] The present invention also proposes a semiconductor device, comprising a basic structure, the basic structure comprising a substrate and an epitaxial layer formed on the substrate, a gate is arranged on the epitaxial layer, and a barrier layer is formed on the sidewall of the gate; the basic structure also comprises a first dielectric layer covering the epitaxial layer and being flush with the gate and the barrier layer, a masking layer covering the gate, the first dielectric layer and the barrier layer, and a second dielectric layer covering the masking layer;

[0021] An etching hole connected to the epitaxial layer is formed by etching at a position of the basic structure near the gate; an ALD layer is deposited on a portion of the inner wall of the etching hole close to the opening; and a metal contact is filled in the etching hole.

[0022] In the semiconductor device of the present invention, the bottom surface of the ALD layer is lower than the top surface of the gate.

[0023] In the semiconductor device of the present invention, the barrier layer is made of the following materials: SiN, SiCN, SiO2, SiOC, SiOCN or a combination thereof.

[0024] In the semiconductor device of the present invention, the ALD layer is made of dielectric material.

[0025] In the semiconductor device of the present invention, the metal contact is made of tungsten, copper, aluminum, etc. or a combination thereof.

[0026] The semiconductor device and the manufacturing method of the present invention adopt the ALD (atomic layer deposition) technology, which causes the diameter of the etching hole 700 to be reduced, but the window where the etching hole 700 connects with the epitaxial layer 100 is enlarged; at the same time, although the manufacturing method of the preferred embodiment of the present invention adopts three etching steps, only one damage is caused to the epitaxial layer 100. The semiconductor device and the manufacturing method of the present invention are novel in design and highly practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0028] Figure 1 A schematic diagram showing a first step state of a conventional method for manufacturing a semiconductor device is shown;

[0029] Figure 2 Shows Figure 1 A schematic diagram of the second step of the manufacturing method shown;

[0030] Figure 3 Shows Figure 1 A schematic diagram of the third step of the manufacturing method shown;

[0031] Figure 4 A schematic diagram showing the first step of another conventional method for manufacturing a semiconductor device is shown;

[0032] Figure 5 Shows Figure 4 A schematic diagram of the second step of the manufacturing method shown;

[0033] Figure 6 Shows Figure 4 A schematic diagram of the third step of the manufacturing method shown;

[0034] Figure 7 Shows Figure 4 A schematic diagram of the fourth step of the manufacturing method shown;

[0035] Figure 8 Shows Figure 4 A schematic diagram of the fifth step of the manufacturing method shown;

[0036] Fig. 9 A schematic diagram showing the first step of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention is shown;

[0037] Fig.10 Shows Fig. 9 A schematic diagram of the second step of the manufacturing method shown;

[0038] Fig.11 Shows Fig. 9 A schematic diagram of the third step of the manufacturing method shown;

[0039] Fig.12 Shows Fig. 9 A schematic diagram of the fourth step of the manufacturing method shown;

[0040] Fig.13 Shows Fig. 9 A schematic diagram of the fifth step of the manufacturing method shown;

[0041] Fig.14 Shows Fig. 9 A schematic diagram of the sixth step of the manufacturing method shown;

[0042] Fig.15 Shows Fig. 9 FIG. 2 is a schematic diagram of the seventh step state of the manufacturing method shown. DETAILED DESCRIPTION

[0043] In order to make the technical purpose, technical scheme and technical effect of the present invention clearer and to facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Fig. 9 A schematic diagram showing the first step of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention is shown; Fig.10 Shows Fig. 9 A schematic diagram of the second step of the manufacturing method shown; Fig.11 Shows Fig. 9 A schematic diagram of the third step of the manufacturing method shown; Fig.12 Shows Fig. 9 A schematic diagram of the fourth step of the manufacturing method shown; Fig.13 Shows Fig. 9 A schematic diagram of the fifth step of the manufacturing method shown; Fig.14 Shows Fig. 9 A schematic diagram of the sixth step of the manufacturing method shown; Fig.15 Shows Fig. 9Specifically, the method for manufacturing a semiconductor device according to a preferred embodiment of the present invention comprises the following steps:

[0045] Step S1, providing a basic structure, the basic structure comprising a substrate (not shown) and an epitaxial layer 100 formed on the substrate, a gate 200 is arranged on the epitaxial layer 100, and a barrier layer 210 is formed on the sidewall of the gate 200; the basic structure also includes a first dielectric layer 300 covering the epitaxial layer 100 and being flush with the gate 200 and the barrier layer 210, a masking layer 400 covering the gate 200, the first dielectric layer 300 and the barrier layer 210, and a second dielectric layer 500 covering the masking layer 400;

[0046] In this step, the barrier layer 210 may be made of the following materials: SiN, SiCN, SiO 2 , SiOC, SiOCN or a combination thereof.

[0047] Step S2: coating a photoresist 600 on the second dielectric layer 500. Fig. 9 As shown;

[0048] Step S3, using the photoresist 600 through a photolithography process, etching a hole 700 connected to the epitaxial layer 100 at a position near the gate 200 of the base structure, and then removing the photoresist 600. Fig.10 As shown;

[0049] Step S4: fill the etching hole 700 with a spin coating material, thereby forming a filling body 710 in the etching hole 700. Fig.11 As shown;

[0050] Step S5, etching the filling body 710; and retaining a portion of the filling body 710 located at the bottom of the etching hole 700 as a support body 720, such as Fig.12 As shown;

[0051] The height of the top surface of the support body 720 is lower than the height of the top surface of the gate 200 .

[0052] Step S6: ALD (atomic layer deposition) technology is used to deposit an ALD layer 910 on the top surface of the second dielectric layer 500, the top surface of the support body 720, and the inner wall of the etching hole 700 located above the support body 720. Fig.13 As shown;

[0053] The ALD layer 910 is made of a dielectric material, which may be nitride or oxide.

[0054] Step S7: etching away the portion of the ALD layer 910 covering the top surface of the second dielectric layer 500 and the top surface of the support body 720 by etching technology, and at the same time removing the support body 720. Fig.14 As shown;

[0055] Step S8: Fill the etching hole 700 to form a metal contact 800, such as Fig.15 As shown. For this manufacturing method, due to the use of ALD (atomic layer deposition) technology, the diameter of the etching hole 700 is reduced, but the window where the etching hole 700 connects with the epitaxial layer 100 is enlarged; at the same time, although the manufacturing method of the preferred embodiment of the present invention adopts three etching steps, the epitaxial layer 100 is only damaged once.

[0056] The metal contact 800 may be made of tungsten, copper, aluminum, etc. or a combination thereof.

[0057] Preferably, the outer surface of the metal contact 800 is provided with an isolation layer 810 , and the isolation layer 810 is generally made of Ti or TiN.

[0058] Furthermore, if Fig.15 As shown, a preferred embodiment of the present invention further proposes a semiconductor device, including a basic structure, the basic structure including a substrate (not shown in the figure) and an epitaxial layer 100 formed on the substrate, a gate 200 is arranged on the epitaxial layer 100, and a barrier layer 210 is formed on the sidewall of the gate 200; the basic structure also includes a first dielectric layer 300 covering the epitaxial layer 100 and being flush with the gate 200 and the barrier layer 210, a masking layer 400 covering the gate 200, the first dielectric layer 300 and the barrier layer 210, and a second dielectric layer 500 covering the masking layer 400;

[0059] An etching hole 700 connected to the epitaxial layer 100 is formed by etching at a position of the base structure near the gate 200 ; an ALD layer 910 is deposited on a portion of the inner wall of the etching hole 700 close to the opening; and a metal contact 800 is filled in the etching hole 700 .

[0060] Due to the use of the ALD layer 910 , the diameter of the etching hole 700 is reduced, but the window where the etching hole 700 connects with the epitaxial layer 100 is enlarged.

[0061] Furthermore, in this embodiment, the bottom surface height of the ALD layer 910 is lower than the top surface height of the gate 200 .

[0062] Further, in this step, the barrier layer 210 may be made of the following materials: SiN, SiCN, SiO 2 , SiOC, SiOCN or a combination thereof.

[0063] The ALD layer 910 is made of a dielectric material, which may be nitride or oxide.

[0064] The metal contact 800 may be made of tungsten, copper, aluminum, etc. or a combination thereof. Preferably, the outer surface of the metal contact 800 is provided with an isolation layer 810, and the isolation layer 810 is generally made of Ti or TiN.

[0065] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Step S1, providing a basic structure, the basic structure comprising a substrate and an epitaxial layer (100) formed on the substrate, a gate (200) being arranged on the epitaxial layer (100), and a barrier layer (210) being formed on the side wall of the gate (200); the basic structure also comprises a first dielectric layer (300) covering the epitaxial layer (100) and being flush with the gate (200) and the barrier layer (210), a masking layer (400) covering the gate (200), the first dielectric layer (300) and the barrier layer (210), and a second dielectric layer (500) covering the masking layer (400); Step S2, coating a photoresist (600) on the second dielectric layer (500); Step S3, using the photoresist (600) through a photolithography process, etching a hole (700) connected to the epitaxial layer (100) at a position of the base structure near the gate (200), and then removing the photoresist (600); Step S4, using a spin coating material to fill the etching hole (700), thereby forming a filling body (710) in the etching hole (700); Step S5, etching the filling body (710); and retaining a portion of the filling body (710) located at the bottom of the etching hole (700) as a support body (720); Step S6, using ALD technology, depositing an ALD layer (910) on the top surface of the second dielectric layer (500), the top surface of the support body (720), and the inner wall of the etching hole (700) located above the support body (720); Step S7, etching away the portion of the ALD layer (910) covering the top surface of the second dielectric layer (500) and the top surface of the support body (720) by etching technology, and stripping off the support body (720); Step S8: Fill the etched hole (700) to form a metal contact (800).

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The height of the top surface of the support body (720) is lower than the height of the top surface of the gate (200).

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The barrier layer (210) is made of the following materials: SiN, SiCN, SiO2, SiOC, SiOCN or a combination thereof.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The ALD layer (910) is made of dielectric material.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The metal contact (800) is made of tungsten, copper, aluminum or a combination thereof.

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