A semiconductor package including stacked semiconductor chips

Abstract

The present application relates to a semiconductor package including stacked semiconductor chips. A semiconductor package includes: a plurality of semiconductor chips that are stacked with an offset to expose an edge region adjacent to a first side surface; chip pads that are disposed in each of the edge regions of the plurality of semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to a second chip pad of one of the plurality of semiconductor chips and the other end connected to a first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to a second chip pad of the uppermost semiconductor chip that is electrically connected to a first chip pad of the uppermost semiconductor chip, the first chip pad of the uppermost semiconductor chip being connected to the horizontal common interconnector.

Description

Technical Field

[0001] This patent document relates to semiconductor packages, and more particularly, to semiconductor packages in which a plurality of semiconductor chips are stacked. Background Art

[0002] Electronic products require high-capacity data processing while becoming smaller in size. Therefore, there is an increasing need to improve the integration of semiconductor devices used in such electronic products.

[0003] However, due to the limitations of semiconductor integration technology, it is difficult to meet the required functions with only one semiconductor chip. Therefore, semiconductor packages in which a plurality of semiconductor chips are embedded have been manufactured. Summary of the Invention

[0004] In one embodiment, a semiconductor package may include: a first semiconductor chip to an Nth semiconductor chip, having a first side surface extending in a first direction and stacked with a substantial offset toward the opposite side of the first side surface to expose an edge region adjacent to the first side surface, where N is a natural number of 2 or more; chip pads provided in each of the edge regions of the first semiconductor chip to the Nth semiconductor chip, the chip pads including a plurality of first chip pads arranged in a first column in the first direction and a plurality of second chip pads arranged in a second column in the first direction, the first column being closer to the first side surface than the second column in a second direction intersecting the first direction, and the first chip pads and the second chip pads adjacent to each other in the second direction being electrically connected to each other; a horizontal common interconnector having one end connected to a second chip pad of a kth semiconductor chip among the first semiconductor chip to the Nth semiconductor chip and the other end connected to a first chip pad of the (k + 1)th semiconductor chip, where k is a natural number of 1 or more and N - 1 or less; and a vertical common interconnector having one end connected to a second chip pad of the Nth semiconductor chip electrically connected to a first chip pad of the Nth semiconductor chip, and the first chip pad of the Nth semiconductor chip being connected to the horizontal common interconnector.

[0005] In another embodiment, a semiconductor package may include: a first chip stack including a first semiconductor chip to an Nth semiconductor chip, the first semiconductor chip to the Nth semiconductor chip having a first side surface extending in a first direction and being stacked with an offset toward a side opposite to the first side surface of the first semiconductor chip to the Nth semiconductor chip to expose an edge region adjacent to the first side surface of the first semiconductor chip to the Nth semiconductor chip, where N is a natural number of 2 or more; a second chip stack formed above the first chip stack and including an (N + 1)th semiconductor chip to a Tth semiconductor chip, the (N + 1)th semiconductor chip to the Tth semiconductor chip having a first side surface substantially opposite to the first side surface of the first semiconductor chip to the Nth semiconductor chip and being stacked with an offset in a direction substantially opposite to the offset stacking direction of the first semiconductor chip to the Nth semiconductor chip to expose an edge region adjacent to the first side surface of the (N + 1)th semiconductor chip to the Tth semiconductor chip, where T is a natural number of N + 2 or more; chip pads provided in each of the edge regions of the first semiconductor chip to the Tth semiconductor chip, the chip pads including a plurality of first chip pads arranged in a first column along the first direction and a plurality of second chip pads arranged in a second column along the first direction, the first column being closer to the first side surface than the second column in a second direction intersecting the first direction, and the first chip pads and the second chip pads adjacent to each other in the second direction being electrically connected to each other; a first horizontal common interconnector having one end connected to a second chip pad of a kth semiconductor chip among the first semiconductor chip to the Nth semiconductor chip and the other end connected to a first chip pad of the (k + 1)th semiconductor chip, where k is a natural number of 1 or more and N - 1 or less; a second horizontal common interconnector having one end connected to a second chip pad of a qth semiconductor chip among the (N + 1)th semiconductor chip to the Tth semiconductor chip and the other end connected to a first chip pad of the (q + 1)th semiconductor chip, where q is a natural number of N + 1 or more and T - 1 or less; a first vertical common interconnector having one end connected to a second chip pad of the Nth semiconductor chip electrically connected to the first chip pad of the Nth semiconductor chip, and the first chip pad of the Nth semiconductor chip being connected to the first horizontal common interconnector; and a second vertical common interconnector having one end connected to a second chip pad of the Tth semiconductor chip electrically connected to the first chip pad of the Tth semiconductor chip, and the first chip pad of the Tth semiconductor chip being connected to the second horizontal common interconnector. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a plan view illustrating an active surface of a semiconductor chip according to an embodiment of the present disclosure.

[0007] Figure 1B is a cross-sectional view taken along line A1 - A1' of Figure 1A ​

[0008] Figure 2A is a plan view illustrating an example of a conductive layer located at the uppermost part of a semiconductor chip located at Figure 1A and Figure 1B of the semiconductor chip.

[0009] Figure 2B is a cross-sectional view taken along line A2-A2' of Figure 2A of the semiconductor chip.

[0010] Figure 3A and Figure 4A are plan views of a semiconductor package according to an embodiment of the present disclosure as viewed from the active surface direction.

[0011] Figure 3B and Figure 4B are cross-sectional views taken along line A3-A3' of Figure 3A and Figure 4A of the semiconductor chip.

[0012] Figure 3C and Figure 4C are cross-sectional views taken along line A4-A4' of Figure 3A and Figure 4A of the semiconductor chip.

[0013] Figure 5 is a diagram illustrating a sweeping phenomenon of vertical bonding wirings.

[0014] Figure 6A is a plan view of a semiconductor package according to another embodiment of the present disclosure as viewed from the active surface direction.

[0015] Figure 6B is a cross-sectional view taken along line B1-B1' of Figure 6A of the semiconductor chip.

[0016] Figure 6C is a cross-sectional view taken along line B2-B@' of Figure 6A of the semiconductor chip.

[0017] Figure 7A is a plan view of a semiconductor package according to another embodiment of the present disclosure as viewed from the active surface direction.

[0018] Figure 7B is a cross-sectional view taken along line C1-C1' of Figure 7A of the semiconductor chip.

[0019] Figure 7C is a cross-sectional view taken along line C2-C2' of Figure 7A of the semiconductor chip.

[0020] Figure 8A block diagram of an exemplary electronic system is shown, which employs a memory card including a semiconductor package according to an embodiment.

[0021] Figure 9 A block diagram of another exemplary electronic system is shown, which includes a semiconductor package according to an embodiment. Detailed Description

[0022] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0023] The drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated to clearly illustrate some features of the described embodiments. When presenting specific examples in the drawings or descriptions of a multi-layer structure having two or more layers, the relative positional relationship of the layers shown or the arrangement order of these layers reflects the specific implementation of the described or illustrated examples and examples, and different relative positional relationships or arrangement orders of these layers are also possible. Additionally, the described or illustrated examples of the multi-layer structure may not reflect all the layers present in that specific multi-layer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in a described or illustrated multi-layer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0024] Before describing the semiconductor package of the present embodiment and the method for manufacturing the semiconductor package, the semiconductor chip included in the semiconductor package of the present embodiment will be first described.

[0025] Figure 1A is a plan view of an active surface of a semiconductor chip according to an embodiment of the present disclosure, and Figure 1B is a cross-sectional view taken along line Figure 1A A1 - A1' of

[0026] Referring to Figure 1A and Figure 1B, the semiconductor chip 100 of the present embodiment may include: an active surface 101, on which chip pads 110P are provided; a passive surface 102, which is disposed opposite to the active surface 101; and a side surface, which connects the active surface 101 and the passive surface 102. In the present embodiment, the semiconductor chip 100 may have a rectangular shape including four side surfaces in a plan view. Among these four side surfaces, the side surface adjacent to the chip pad 110P will be referred to as the first side surface 105. As an example, the first side surface 105 may correspond to the left side surface in the second direction.

[0027] The chip pad 110P may be a conductive element or terminal exposed from the active surface 101 of the semiconductor chip 100 while being electrically connected to a circuit and / or a wiring structure (not shown) of the semiconductor chip 100. As a reference, the circuit and / or the wiring structure of the semiconductor chip 100 may be implemented in various ways according to the function and / or type of the semiconductor chip 100. The semiconductor chip 100 may be a non-volatile memory chip including NAND flash memory, phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc. Alternatively, the semiconductor chip 100 may be a volatile memory including dynamic random access memory (DRAM), static random access memory (SRAM), etc. However, the present disclosure is not limited thereto, and the semiconductor chip 100 may be a non-memory chip such as a logic chip.

[0028] The chip pad 110P may be provided in an edge region of the semiconductor chip 100 adjacent to the first side surface 105. That is, the chip pad 110P may be provided in an edge pad type. When a plurality of chip pads 110P arranged in a row along the first side surface 105 in the first direction are referred to as a column of chip pads 110P, two columns of chip pads 110P may be provided in the edge region of the semiconductor chip 100 adjacent to the first side surface 105. The column of chip pads 110P closer to the first side surface 105 than the other column will be referred to as the first column C1, and the column of chip pads 110P farther from the first side surface 105 than the other column will be referred to as the second column C2. In addition, each chip pad 110P included in the first column C1 will be referred to as the first chip pad 110P1, and each chip pad 110P included in the second column C2 will be referred to as the second chip pad 110P2.

[0029] As an example, the first chip pad 110P1 can be a pad for evaluating the characteristics of the semiconductor chip 100, and the second chip pad 110P2 can be a pad for electrically connecting the semiconductor chip 100 to other components. For this purpose, a probe can contact the first chip pad 110P1. Additionally, a conductive interconnect such as a wire can be connected to the second chip pad 110P2. However, the present disclosure is not limited thereto, and the second chip pad 110P2 can be used to evaluate the characteristics of the semiconductor chip 100, while the first chip pad 110P1 can be used for electrical connection. Alternatively, the first chip pad 110P1 or the second chip pad 110P2 can be used for characteristic evaluation and can also be used for electrical connection. That is, after a probe test is performed on the first chip pad 110P1 or the second chip pad 110P2, the conductive interconnect can be connected to the first chip pad 110P1 or the second chip pad 110P2 on which the probe test was performed.

[0030] The first chip pad 110P1 and the second chip pad 110P2 adjacent to each other in the second direction can be electrically connected to each other. Hereinafter, the first chip pad 110P1 and the second chip pad 110P2 adjacent to each other in the second direction are referred to as a pair of the first chip pad 110P1 and the second chip pad 110P2. In Figure 1B 's cross-sectional view, the electrical connection between a pair of the first chip pad 110P1 and the second chip pad 110P2 is shown as a line (refer to EC), but this is merely for representing the electrical connection function, and the line EC may not show the actual wiring. The electrical connection between a pair of the first chip pad 110P1 and the second chip pad 110P2 can be made in various ways. As an example, a pair of the first chip pad 110P1 and the second chip pad 110P2 can be connected to each other using a conductive layer provided at the uppermost part of the semiconductor chip 100. For example, this will be described with reference to the following Figure 2A and Figure 2B Regarding this. As a reference, the uppermost part of the semiconductor chip 100 can refer to the part of the semiconductor chip 100 closest to the active surface 101 in a direction parallel to the side surface of the semiconductor chip 100.

[0031] Figure 2A is an example of a plan view illustrating a conductive layer located at the uppermost part of the semiconductor chip located at Figure 1A and Figure 1B . Figure 2A shows an example of a part corresponding to part P1 corresponding to Figure 1A . Figure 2B is a cross-sectional view taken along line A2 - A2' of Figure 2A . In Figure 2A and Figure 2B , the conductive layer located at the uppermost part of the semiconductor chip can be, for example, a redistribution conductive layer 110.Figure 2A is a plan view showing the height at the upper surface of the redistributed conductive layer 110, and for ease of description, the chip pad 110P is also shown. Figure 2B The configuration of the semiconductor chip 100 and the redistributed conductive layer 110 is also shown. Figure 2B Also shown is the configuration of the semiconductor chip 100 and the redistributed conductive layer 110.

[0032] Referring Figure 2A and Figure 2B , the semiconductor chip 100 of the present embodiment may include: a lower structure UL; a redistributed conductive layer 110 formed above the lower structure UL; and a protective layer 120 that covers the lower structure UL and the redistributed conductive layer 110 while exposing a part of the redistributed conductive layer 110. A part of the redistributed conductive layer 110 exposed by the protective layer 120 may be a redistributed pad. The redistributed pad may form the above-mentioned chip pad 110P.

[0033] The lower structure UL may include: a semiconductor substrate S including a semiconductor material such as silicon; a multilayer conductive pattern ML formed above the upper surface of the semiconductor substrate S to constitute an integrated circuit; and an interlayer insulating layer ILD in which the multilayer conductive pattern ML is buried. Although not shown, the interlayer insulating layer ILD may also have a multilayer structure.

[0034] The multilayer conductive pattern ML may include a plurality of conductors arranged in multiple layers in a direction perpendicular to the upper surface of the semiconductor substrate S and having various shapes. For example, the multilayer conductive pattern ML may include a combination of a line L or a pad P and a contact plug C. The line L or the pad P may be located in different layers in the vertical direction, and the contact plug C may connect the line L or the pad P to each other in the vertical direction. The multilayer conductive pattern ML may be connected to a part of the semiconductor substrate S, for example, the junction of a transistor.

[0035] Materials for forming the multilayer conductive pattern ML and the interlayer insulating layer ILD can be appropriately selected to meet the required characteristics of the semiconductor chip 100. As an example, at least a part of the multilayer conductive pattern ML can include a metal with low resistance such as copper (Cu), and at least a part of the interlayer insulating layer ILD can include a material with a low dielectric constant, such as a low-k material with a low dielectric constant of 2.7 or less. However, if the semiconductor chip is covered with a protective layer in a state where the multilayer conductive pattern ML and the interlayer insulating layer ILD are formed and the semiconductor chip is packaged through fab-out, moisture may penetrate through the low-k material that is relatively easy to absorb moisture. The moisture can cause the electro-movement of metal ions (especially copper ions), resulting in the loss of the multilayer conductive pattern ML or an electrical short circuit with other adjacent conductors. Therefore, in the first semiconductor chip 100 of the present embodiment, it can be aimed at preventing moisture penetration by further forming a thick insulating layer 107 above the interlayer insulating layer ILD.

[0036] The insulating layer 107 can include an insulating material having a higher dielectric constant and / or a lower moisture absorption rate compared to the low-k material. For example, the insulating layer 107 can include silicon oxide, silicon nitride, or a combination thereof. Additionally, the insulating layer 107 can have a single-layer structure or a multilayer structure. The insulating layer 107 can be formed relatively thick to prevent moisture penetration. Specifically, the insulating layer 107 can be thicker than any layer in the interlayer insulating layer ILD having a multilayer structure. For example, the insulating layer 107 can have a thickness of tens of thousands of angstroms.

[0037] However, since it is necessary to connect the multilayer conductive pattern ML to the outside, a contact plug 108 can be further formed, which penetrates the insulating layer 107 to connect to the multilayer conductive pattern ML; and a redistribution conductive layer 110, which is formed above the insulating layer 107 to connect to the contact plug 108. For ease of description, in the present disclosure, the insulating layer 107 and the contact plug 108 are also included in the lower structure UL.

[0038] The redistribution conductive layer 110 can include various conductive materials, for example, a metal such as aluminum (Al), and can have a single-layer structure or a multilayer structure. Additionally, the redistribution conductive layer 110 can be formed relatively thick to enable smooth signal transmission and balance with the insulating layer 107. The redistribution conductive layer 110 can have a thickness the same as or similar to that of the insulating layer 107. For example, the redistribution conductive layer 110 can have a thickness of tens of thousands of angstroms.

[0039] The protective layer 120 may be disposed over the redistribution conductive layer 110. The protective layer 120 may serve to define the chip pad 110P while protecting the first semiconductor chip 100. The protective layer 120 may have a single-layer structure or a multi-layer structure including various insulating materials such as an insulating polymer. Specifically, the protective layer 120 may include a polyimide material such as PIQ (Polyimide Isoindro Quindzoline).

[0040] The process of forming the lower structure UL, the process of forming the redistribution conductive layer 110, and the process of forming the protective layer 120 may all be performed before the manufacturing is completed (i.e., in the front-end process). As an example, the lower structure UL and the redistribution conductive layer 110 may be formed by repeating the process of depositing a conductive material or an insulating material and patterning the conductive material or the insulating material by a mask and an etching process. The protective layer 120 may be formed by a coating method.

[0041] In a plan view, the redistribution conductive layer 110 may have various shapes according to patterning. As part of the redistribution conductive layer 110, as described above, the chip pads 110P may be arranged in two columns in an edge region of the semiconductor chip 100 adjacent to the first side surface 105, and may include a first column of first chip pads 110P1 and a second column of second chip pads 110P2. At this time, the first chip pad 110P1 and the second chip pad 110P2 adjacent to each other in the second direction (i.e., a pair of the first chip pad 110P1 and the second chip pad 110P2) may be connected to each other using the redistribution conductive layer 110. The redistribution conductive layer 110 may overlap with a pair of the first chip pad 110P1 and the second chip pad 110P2 at the same time. In addition, the redistribution conductive layer 110 may extend in a direction away from the first side surface 105 when overlapping with a pair of the first chip pad 110P and the second chip pad 110P2 at the same time. As needed, the extended portion of the redistribution conductive layer 110 may have various curved shapes, plate shapes, or a combination thereof. In these figures, the redistribution conductive layer 110 overlapping with any pair of the first chip pad 110P1 and the second chip pad 110P2 may be separated from the redistribution conductive layer 110 overlapping with another pair of the first chip pad 110P1 and the second chip pad 110P2. However, although not shown, if needed, the extended portion of the redistribution conductive layer 110 overlapping with any pair of the first chip pad 110P1 and the second chip pad 110P2 may be connected to the extended portion of the redistribution conductive layer 110 overlapping with another pair of the first chip pad 110P1 and the second chip pad 110P2. As an example, when the same power is applied to a pair of the first chip pad 110P1 and the second chip pad 110P2 and another pair of the first chip pad 110P1 and the second chip pad 110P2, the connection of the extended portions may form a PDN (power distribution network), and thus, power supply may be stably performed.

[0042] In the embodiment described above Figure 2A and Figure 2B the redistribution conductive layer 110 formed before manufacturing is completed may be a conductive layer located at the uppermost part of the semiconductor chip 100, and the redistribution pads of the redistribution conductive layer 110 may form the chip pads 110P of the semiconductor chip 100. However, the present disclosure is not limited thereto. As long as the chip pads 110P of the semiconductor chip 100 are arranged in two columns in the edge region of the semiconductor chip 100, and a pair of chip pads 110P belonging to different columns and adjacent to each other are connected to each other using a conductive layer located at the uppermost part of the semiconductor chip 100 or other methods, the semiconductor package of this embodiment may be formed.

[0043] In addition, a plurality of semiconductor chips 100 may be stacked in the vertical direction to form a semiconductor package. The following will refer toFigures 3A to 4C Describe this.

[0044] Figures 3A to 4C are views illustrating a semiconductor package and a method of manufacturing the same according to an embodiment of the present disclosure. For example, Figure 3A and Figure 4A are plan views of a semiconductor package according to an embodiment of the present disclosure as viewed from the active surface direction. Figure 3B and Figure 4B are respectively cross-sectional views taken along line A3-A3' of Figure 3A and Figure 4A . Figure 3C and Figure 4C are respectively cross-sectional views taken along line A4-A4' of Figure 3A and Figure 4A . Detailed descriptions of components that are substantially the same as those previously described in Figures 1A to 2B will be omitted.

[0045] First, the manufacturing method will be described.

[0046] Referring to Figures 3A to 3C , a carrier substrate 200 can be provided. The carrier substrate 200 can be a glass carrier substrate, a silicon carrier substrate, a ceramic carrier substrate, etc. Alternatively, the carrier substrate 200 can be a wafer, and a plurality of packages can be formed above the carrier substrate 200.

[0047] Subsequently, a first semiconductor chip 210 and a second semiconductor chip 220 can be stacked above the surface 201 of the carrier substrate 200 in a direction perpendicular to the surface 201 of the carrier substrate 200. Each of the first semiconductor chip 210 and the second semiconductor chip 220 can be substantially the same as the semiconductor chip 100 of the above-described embodiment.

[0048] Accordingly, the first semiconductor chip 210 can include chip pads 213P provided on its active surface 211. The chip pads 213P can be arranged in two columns along a first direction in an edge region of the first semiconductor chip 210 adjacent to the first side surface 215, and can include a first column of first chip pads 213P1 and a second column of second chip pads 213P2. At this time, although not shown in this figure, the first chip pads 213P1 and the second chip pads 213P2 (i.e., a pair of first chip pads 213P1 and second chip pads 213P2) adjacent to each other in a second direction can be electrically connected to each other.

[0049] Similarly, the second semiconductor chip 220 may include chip pads 223P disposed on its active surface 221. The chip pads 223P may be arranged in two columns in a first direction in an edge region of the second semiconductor chip 220 adjacent to the first side surface 225, and may include a first column of first chip pads 223P1 and a second column of second chip pads 223P2. At this time, although not shown in the figure, the first chip pad 223P1 and the second chip pad 223P2 adjacent to each other in a second direction (i.e., a pair of the first chip pad 223P1 and the second chip pad 223P2) may be electrically connected to each other.

[0050] The first semiconductor chip 210 and the second semiconductor chip 220 may be stacked above the carrier substrate 200 in a state where the active surfaces 211 and 221 face upward instead of facing the surface 201 of the carrier substrate 200 (i.e., face-up type). Although not shown, an adhesive layer may be formed on the surfaces of the first semiconductor chip 210 and the second semiconductor chip 220 opposite to the active surfaces 211 and 221. Through this adhesive layer, the first semiconductor chip 210 may be attached to the carrier substrate 200, and the second semiconductor chip 220 may be attached to the first semiconductor chip 210.

[0051] In addition, in a state where the first side surfaces 215 and 225 are parallel to each other and are arranged to face the same side (e.g., the left side in a second direction), the first semiconductor chip 210 and the second semiconductor chip 220 may be stacked with a predetermined offset in a predetermined direction such that an edge region of the first semiconductor chip 210 adjacent to the first side surface 215 is exposed. Accordingly, the chip pad 213P may be exposed. Here, the predetermined direction may be a direction toward the opposite side of the first side surfaces 215 and 225, e.g., the right direction in the second direction. Since the second semiconductor chip 220 is located at the uppermost portion, the chip pad 223P may be exposed. As used herein, the term "predetermined" with respect to a parameter (such as a predetermined direction and a predetermined offset) means that the value of the parameter is determined before using the parameter in a process or an algorithm. For some embodiments, the value of the parameter is determined before the start of the process or the algorithm. In other embodiments, the value of the parameter is determined during the process or the algorithm but before using the parameter in the process or the algorithm.

[0052] Subsequently, in order to electrically connect the first semiconductor chip 210 and the second semiconductor chip 220 to external components, interconnects 216, 226, 217, and 227 connected to the chip pads 213P and 223P may be formed. Before describing the interconnects 216, 226, 217, and 227, signals or power transmitted between the first semiconductor chip 210 and the second semiconductor chip 220 and external components will be described below.

[0053] As an example, there may be signals or power that are commonly used in the first semiconductor chip 210 and the second semiconductor chip 220. For example, when the first semiconductor chip 210 and the second semiconductor chip 220 are memory chips such as NAND flash memories, common signals such as data input / output (DQ) signals, command address (CA) signals, etc. may be commonly sent to the first semiconductor chip 210 and the second semiconductor chip 220. In addition, common power such as ground voltage or another voltage having the same level in the first semiconductor chip 210 and the second semiconductor chip 220 may be commonly applied to the first semiconductor chip 210 and the second semiconductor chip 220. Therefore, the chip pads 213P and 223P of the first semiconductor chip 210 and the second semiconductor chip 220 to which the common signals or common power are applied may be electrically connected to each other.

[0054] On the other hand, there may be signals or power that are separately used in each of the first semiconductor chip 210 and the second semiconductor chip 220. For example, when the first semiconductor chip 210 and the second semiconductor chip 220 are memory chips such as NAND flash memories, chip select (CS) signals, calibration input (ZQ) signals, etc. may be separately sent to each of the first semiconductor chip 210 and the second semiconductor chip 220. In addition, when it is necessary to apply voltages of different levels to the first semiconductor chip 210 and the second semiconductor chip 220, these voltages may be separately applied to the first semiconductor chip 210 and the second semiconductor chip 220. Therefore, the chip pad 213P of the first semiconductor chip 210 to which the separate signal or separate power is applied may be electrically separated from the chip pad 223P of the second semiconductor chip 220 to which the separate signal or separate power is applied.

[0055] Among the interconnectors 216, 226, 217, and 227, the interconnectors connected to the chip pads 213P and 223P to which the common signals or common power are applied will be referred to as the common interconnectors 216 and 226. Reference will be made to Figure 3A and Figure 3B to describe the common interconnectors 216 and 226. The common interconnectors 216 and 226 may include a horizontal common interconnector 216 and a vertical common interconnector 226. The horizontal common interconnector 216 may connect the chip pad 213P of the first semiconductor chip 210 and the chip pad 223P of the second semiconductor chip 220 to each other, and thus, at least a part of the horizontal common interconnector 216 may extend in the horizontal direction. The vertical common interconnector 226 may be electrically connected to the chip pad 223P of the second semiconductor chip 220 and extend in the vertical direction.

[0056] As an example, one end of the horizontal common interconnector 216 may be connected to the second chip pad 213P2 of the first semiconductor chip 210, while the other end of the horizontal common interconnector 216 may be connected to the first chip pad 223P1 of the second semiconductor chip 220. The second chip pad 213P2 of the first semiconductor chip 210 and the first chip pad 223P1 of the second semiconductor chip 220 connected to one horizontal common interconnector 216 may be adjacent to each other in the second direction, or may be located on a straight line in the second direction. In this case, the length of the horizontal common interconnector 216 may be the shortest, and thus, signal / power transmission through the horizontal common interconnector 216 may be facilitated. The horizontal common interconnector 216 may be a bonding wire whose two ends are respectively connected to the chip pads 213P and 223P.

[0057] In addition, as an example, the vertical common interconnector 226 may extend in the vertical direction while being connected to the second chip pad 223P2 of the second semiconductor chip 220 at one end. In this case, the second chip pad 223P2 of the second semiconductor chip 220 connected to the vertical common interconnector 226 may be electrically connected to the first chip pad 223P1 of the second semiconductor chip 220 connected to the horizontal common interconnector 216. The vertical common interconnector 226 may be a vertical bonding wire whose one end is connected to the second chip pad 223P2 of the second semiconductor chip 220. For reference, a method of forming the vertical bonding wire will be briefly described below. One end of the wire may be bonded to the chip pad using a wire bonder (not shown). The wire may include a metal such as gold, silver, copper, platinum, or an alloy thereof that can be welded to the chip pad by ultrasonic energy and / or heat. Then, the other end of the wire (e.g., from bottom to top) may be pulled away from the chip pad in the vertical direction using a wire bonder. Subsequently, when the other end of the wire extends to a desired position, the other end of the wire may be cut. Thus, a vertical bonding wire may be obtained.

[0058] Therefore, an electrical connection path passing through the second chip pad 213P2 of the first semiconductor chip 210, the horizontal common interconnector 216, the first chip pad 223P1 of the second semiconductor chip 220, and the vertical common interconnector 226 may be formed. That is, a path for commonly transmitting signals and / or power to the first semiconductor chip 210 and the second semiconductor chip 220 may be formed.

[0059] On the other hand, among the interconnectors 216, 226, 217, and 227, the interconnectors connected to the chip pads 213P and 223P to which a separate signal or separate power is applied will be respectively referred to as the first vertical interconnector 217 and the second vertical interconnector 227. The first vertical interconnector 217 and the second vertical interconnector 227 will be described with reference to Figure 3A and Figure 3C description of the first vertical interconnector 217 and the second vertical interconnector 227.

[0060] As an example, the first vertical interconnect 217 may be a vertical bonding wire extending in the vertical direction, and one end thereof may be connected to the chip pad 213P of the first semiconductor chip 210. The first vertical interconnect 217 may be connected to the chip pad 213P other than the second chip pad 213P2 connected to the horizontal common interconnect 216 and the first chip pad 213P1 electrically connected to the second chip pad 213P2. In addition, the first vertical interconnect 217 may be connected to the chip pad 213P on which the probe test is not performed. When a probe test is performed on a chip pad, the surface of the chip pad may be deformed due to contact with the probe. For this reason, it may be difficult to perform the wire bonding process on such a chip pad on which the probe test has been performed. Specifically, since only one end of the vertical wire is bonded to the chip pad, the wire bonding process may be more important. Therefore, by connecting the first vertical interconnect 217 to the chip pad 213P that has not been contacted by the probe, defects in the wire bonding process can be reduced. In the present embodiment, the probe test may be performed on the first chip pads 213P1 and 223P1 in the first column. Therefore, the first vertical interconnect 217 may be connected to the second chip pad 213P2 of the first semiconductor chip 210 that is not connected to the horizontal common interconnect 216. In the embodiment, the deformation of the chip pad surface may be regarded as any deformation of the original form of the chip pad caused by the probe test. In the embodiment, the deformation of the chip pad surface may be regarded as any deformation of the original form of the chip pad caused by the probe.

[0061] In addition, as an example, the second vertical interconnect 227 may be a vertical bonding wire extending in the vertical direction, and one end thereof may be connected to the chip pad 223P of the second semiconductor chip 220. The second vertical interconnect 227 may be connected to the chip pad 223P other than the chip pad 223P connected to the horizontal common interconnect 216 and the vertical common interconnect 226. In addition, the second vertical interconnect 227 may be connected to the chip pad 223P on which the probe test is not performed. In the present embodiment, the probe test may be performed on the first chip pads 213P1 and 223P1 in the first column. Therefore, the second vertical interconnect 227 may be connected to the second chip pad 223P2 of the second semiconductor chip 220 that is not connected to the vertical common interconnect 226.

[0062] The electrical connection path passing through the chip pad 213P of the first semiconductor chip 210 and the first vertical interconnector 217 can be separated from the electrical connection path passing through the chip pad 223P of the second semiconductor chip 220 and the second vertical interconnector 227. That is, the path for transmitting signals and / or power to the first semiconductor chip 210 and the path for transmitting signals and / or power to the second semiconductor chip 220 can be separated from each other.

[0063] In addition, although not shown, the vertical interconnectors (i.e., the vertical common interconnector 226 and the second vertical interconnector 227) connected to the uppermost second semiconductor chip 220 can be different types of interconnectors rather than bonding wirings. As an example, the vertical common interconnector 226 and the second vertical interconnector 227 can include metal bumps.

[0064] Next, referring to Figures 4A to 4C , a molding layer 230 can be formed above the carrier substrate 200, and the first semiconductor chip 210 and the second semiconductor chip 220 and the interconnectors 216, 226, 217, and 227 are formed on the molding layer 230.

[0065] The molding layer 230 can be formed using a molding process in which an empty space of a molding die (not shown) is filled with a molding material and the molding material is cured. The molding material can include a thermosetting resin such as EMC (Epoxy Mold Compound).

[0066] The molding layer 230 can cover the first semiconductor chip 210 and the second semiconductor chip 220 and the interconnectors 216, 226, 217, and 227 while exposing the other ends of the first vertical interconnector 217, the vertical common interconnector 226, and the second vertical interconnector 227. The other ends can be, for example, upper ends. To this end, the molding layer 230 can be formed to a thickness that sufficiently covers the first semiconductor chip 210 and the second semiconductor chip 220 and the interconnectors 216, 226, 217, and 227, and then, a grinding process can be performed on the molding layer 230. The grinding process can be performed by mechanical polishing or chemical polishing. Alternatively, instead of performing the grinding process, by adjusting the shapes of the first vertical interconnector 217, the vertical common interconnector 226, and the second vertical interconnector 227 and / or the shape of the molding die, the other ends of the first vertical interconnector 217, the vertical common interconnector 226, and the second vertical interconnector 227 can be exposed.

[0067] Therefore, the molding layer 230 can have a surface 231 that is located at substantially the same level as the other ends of the first vertical interconnector 217, the vertical common interconnector 226, and the second vertical interconnector 227 and exposes them.

[0068] Subsequently, an encapsulation redistribution layer 240 can be formed above the surface 231 of the molding layer 230. In order to distinguish the encapsulation redistribution layer 240 from the redistribution conductive layers provided in the above semiconductor chip (see Figure 2A and Figure 2B 110 therein), it is referred to as the encapsulation redistribution layer 240.

[0069] The encapsulation redistribution layer 240 can include encapsulation redistribution conductive layers 244, 243, and 245 electrically connected to the first vertical interconnector 217, the vertical common interconnector 226, and the second vertical interconnector 227, respectively. The encapsulation redistribution conductive layer 243 electrically connected to the vertical common interconnector 226 will be referred to as the first encapsulation redistribution conductive layer 243. The portion of the first encapsulation redistribution conductive layer 243 that overlaps and connects to the other end of the vertical common interconnector 226 will be referred to as the first redistribution pad 243L. The encapsulation redistribution conductive layer 244 electrically connected to the first vertical interconnector 217 will be referred to as the second encapsulation redistribution conductive layer 244. The portion of the second encapsulation redistribution conductive layer 244 that overlaps and connects to the other end of the first vertical interconnector 217 will be referred to as the second redistribution pad 244L. The encapsulation redistribution conductive layer 245 electrically connected to the second vertical interconnector 227 will be referred to as the third encapsulation redistribution conductive layer 245. The portion of the third encapsulation redistribution conductive layer 245 that overlaps and connects to the other end of the second vertical interconnector 227 will be referred to as the third redistribution pad 245L.

[0070] The encapsulation redistribution layer 240 may further include a first encapsulation redistribution insulating layer 241 and a second encapsulation redistribution insulating layer 242.

[0071] The first encapsulation redistribution insulating layer 241 can cover the surface 231 of the molding layer 230 and can have openings respectively exposing the other ends of the first vertical interconnector 217, the vertical common interconnector 226, and the second vertical interconnector 227. The encapsulation redistribution conductive layers 243, 244, and 245 can be patterned to have various shapes above the first encapsulation redistribution insulating layer 241 while filling these openings. The portions of the encapsulation redistribution conductive layers 243, 244, and 245 filled in these openings can form the above-mentioned first redistribution pad 243L, second redistribution pad 244L, and third redistribution pad 245L. For ease of description, in Figure 4AIn the plan view, the overall shapes of the package redistribution conductive layers 243, 244, and 245 are omitted, and only the first redistribution pad 243L to the third redistribution pad 245L are shown. The second package redistribution insulating layer 242 may cover the first package redistribution insulating layer 241 and the package redistribution conductive layers 243, 244, 245, and may have openings exposing a part of the package redistribution conductive layers 243, 244, 245.

[0072] Subsequently, external connection terminals 250 may be formed above the package redistribution layer 240. The external connection terminals 250 are electrically connected to the package redistribution conductive layers 243, 244, 245 through the openings of the second package redistribution insulating layer 242. In this embodiment, solder balls may be used as the external connection terminals 250, but the present disclosure is not limited thereto, and various types of electrical connectors may be used as the external connection terminals 250.

[0073] Therefore, an electrical connection path can be formed through the second chip pad 213P2 of the first semiconductor chip 210, the horizontal common interconnect 216, the first chip pad 223P1 of the second semiconductor chip 220 and the second chip pad 223P2 electrically connected to the first chip pad 223P1, the vertical common interconnect 226, the first package redistribution conductive layer 243, and the external connection terminal 250 connected to the first package redistribution conductive layer 243. That is, signals and / or power can be jointly transmitted between the first semiconductor chip 210 and the second semiconductor chip 220 and external components (not shown) to be connected to the external connection terminals 250. In addition, an electrical connection path can be formed through the second chip pad 213P2 of the first semiconductor chip 210, the first vertical interconnect 217, the second package redistribution conductive layer 244, and the external connection terminal 250 connected to the second package redistribution conductive layer 244. That is, signals and / or power can be transmitted only between the first semiconductor chip 210 and external components (not shown) to be connected to the external connection terminals 250. In addition, an electrical connection path can be formed through the second chip pad 223P2 of the second semiconductor chip 220, the second vertical interconnect 227, the third package redistribution conductive layer 245, and the external connection terminal 250 connected to the third package redistribution conductive layer 245. That is, signals and / or power can be transmitted only between the second semiconductor chip 220 and external components (not shown) to be connected to the external connection terminals 250.

[0074] Although not shown, the carrier substrate 200 may be removed in a subsequent process. The carrier substrate 200 may be removed at any time after the molding layer 230 is formed.

[0075] Through the above process, it is possible to manufacture as shown in Figure 4A and Figure 4BThe semiconductor package shown. The components of the semiconductor package have been described in the description of the manufacturing method, and thus a detailed description thereof will be omitted.

[0076] According to the semiconductor package and its manufacturing method of the present embodiment, the following effects can be obtained.

[0077] First, by forming a semiconductor package including a first semiconductor chip 210 and a second semiconductor chip 220, the demand for high-performance and large-capacity data processing can be satisfied, and a semiconductor package with a thin thickness can be realized by using a package redistribution layer 240 and vertical interconnects 226, 217, and 227 instead of using a conventional substrate to form a fan-out package.

[0078] In addition, compared with a comparative example in which all chip pads of the first semiconductor chip and the second semiconductor chip are connected to the vertical interconnects, chip pads 213P and 223P to which signals or power commonly used by the first semiconductor chip 210 and the second semiconductor chip 220 are applied can be connected to each other through a horizontal common interconnect 216. Therefore, the number of vertical interconnects 226, 217, and 227 can be reduced, and the space between the vertical interconnects 226, 217, and 227 can be increased. That is, in the semiconductor package of the present embodiment, the density of the vertical interconnects 226, 217, and 227 can be reduced. In this case, compared with the comparative example, crosstalk between the vertical interconnects 226, 217, and 227 can be reduced, and the use of metal materials for forming wirings can be reduced, thereby reducing costs. In addition, compared with the comparative example, the design freedom of the package redistribution layer 240 can be increased. Specifically, since the sizes of the first redistribution pad 243L to the third redistribution pad 245L can be increased, misalignment between the first redistribution pad 243L to the third redistribution pad 245L caused by the sweep of the vertical interconnects 226, 217, and 227 and the resulting defects can also be reduced.

[0079] For reference, hereinafter, reference will be made to Figure 5 Describe the sweep phenomenon of the vertical bonding wirings serving as the vertical interconnects 226, 217, and 227.

[0080] Figure 5 is a diagram illustrating the sweep phenomenon of the vertical bonding wirings.

[0081] Referring to Figure 5 , the vertical bonding wiring VW may have one end E1 attached to the chip pad and the other end E2 located on the opposite side thereof.

[0082] The left side of the arrow shows the state immediately after the formation of the vertical junction wiring VW. As long as no external force is applied, the vertical junction wiring VW can maintain a state of being approximately 90 degrees vertical.

[0083] The right side of the arrow shows the state after an external force such as pressure is applied to the vertical junction wiring VW due to the flow of the molding material during the molding process. When pressure is applied, since one end E1 of the vertical junction wiring VW is fixed to the chip pad, that end E1 does not move. However, since the other end E2 of the vertical junction wiring VW is not fixed and moves according to the direction of the applied pressure, sweeping of the vertical junction wiring VW may occur. That is, the vertical junction wiring VW may bend. As a result of the sweeping, the other end E2 of the vertical junction wiring VW can shift to a random position within the range of the circle shown, for example. Figure 5 The displacement of the other end E2 of the vertical junction wiring VW can be changed by the eddy current of the molding material, which is caused by the injection direction and pressure of the molding material and the surrounding structure. The longer the length of the vertical junction wiring VW, the more severe the sweeping. In the case of the sweeping of the vertical junction wiring VW, problems such as short - circuit between adjacent vertical junction wirings and disconnection of the connection between the vertical junction wiring VW and the chip pad may occur. Additionally, since the position of the other end E2 of the vertical junction wiring VW changes, components to be connected to the other end E2 of the vertical junction wiring VW, for example, the solder pads of the package redistribution conductive layer (refer to Figure 4A 243L, 244L, and 245L in it) may be misaligned with the other end E2 of the vertical line VW. As a result, a connection failure between the vertical junction wiring VW and the package redistribution conductive layer may occur.

[0084] Returning to the description of the effects of this embodiment, a reduction in the number / density of the vertical interconnects 226, 217, and 227 can mean a reduction in the number / density of the solder pads 243L, 244L, and 245L to be connected to the vertical interconnects 226, 217, and 227. Therefore, the sizes of the solder pads 243L, 244L, 245L can be increased, so that even if sweeping of the vertical interconnects 226, 217, and 227 occurs, the misalignment between the vertical interconnects 226, 217, and 227 and the solder pads 243L, 244L, and 245L can be reduced.

[0085] Specifically, in the first vertical interconnector 217 that is connected to the lowermost first semiconductor chip 210 and has a relatively long length, the sweeping phenomenon may be more problematic. However, the number / density of the first vertical interconnectors 217 can be less than the number / density of the vertical common interconnector 226 and the second vertical interconnector 227 that are connected to the second semiconductor chip 220. Therefore, even if the size of the second redistribution pad 244L connected to the first vertical interconnector 217 increases, a short circuit between adjacent second redistribution pads 244L may not occur. Moreover, as the size of the second redistribution pad 244L increases, the degree of misalignment between the first vertical interconnector 217 and the second redistribution pad 244L can be further reduced.

[0086] The planar sizes of the first redistribution pad 243L to the third redistribution pad 245L can each have a value equal to or greater than the displacement of the other end of the vertical common interconnector 226, the displacement of the other end of the first vertical interconnector 217, and the displacement of the other end of the second vertical interconnector 227.

[0087] In addition, in the Figures 3A to 4C embodiment described above, the case where the two semiconductor chips 210 and 220 are stacked with an offset in a predetermined direction has been described. However, in another embodiment, three or more semiconductor chips can be stacked with an offset in a predetermined direction. For example, the following will refer to Figures 6A to 6C for a description thereof.

[0088] Figures 6A to 6C is a diagram illustrating a semiconductor package and a method of manufacturing the same according to another embodiment of the present disclosure. For example, Figure 6A is a plan view of a semiconductor package according to another embodiment of the present disclosure as viewed from the active surface direction. Figure 6B is a cross-sectional view taken along the line Figure 6A B1 - B1'. Figure is a cross-sectional view taken along the line ​ B2 - B2'. A detailed description of components that are substantially the same as those described previously in ​ will be omitted.

[0089] Referring to ​, the first semiconductor chip 310, the second semiconductor chip 320, the third semiconductor chip 330, and the fourth semiconductor chip 340 can be vertically stacked above the surface 301 of the carrier substrate 300. The first semiconductor chip 310 can include chip pads 313P disposed on the active surface 311. The chip pads 313P can be arranged in two columns in a first direction in an edge region of the first semiconductor chip 310 adjacent to the first side surface 315, and include a first column of first chip pads 313P1 and a second column of second chip pads 313P2. The first chip pad 313P1 and the second chip pad 313P2 adjacent to each other in a second direction (i.e., a pair of the first chip pad 313P1 and the second chip pad 313P2) can be electrically connected to each other. Similarly, the second semiconductor chip 320 can include chip pads 323P disposed on the active surface 321. The chip pads 323P can be arranged in two columns in a first direction in an edge region of the second semiconductor chip 320 adjacent to the first side surface 325, and can include a first column of first chip pads 323P1 and a second column of second chip pads 323P2. A pair of the first chip pad 323P1 and the second chip pad 323P2 can be electrically connected to each other. Similarly, the third semiconductor chip 330 can include chip pads 333P disposed on the active surface 331. The chip pads 333P can be arranged in two columns in a first direction in an edge region of the third semiconductor chip 330 adjacent to the first side surface 335, and can include a first column of first chip pads 333P1 and a second column of second chip pads 333P2. A pair of the first chip pad 333P1 and the second chip pad 333P2 can be electrically connected to each other. Similarly, the fourth semiconductor chip 340 can include chip pads 343P disposed on the active surface 341. The chip pads 343P can be arranged in two columns in a first direction in an edge region of the fourth semiconductor chip 340 adjacent to the first side surface 345, and can include a first column of first chip pads 343P1 and a second column of second chip pads 343P2. A pair of the first chip pad 343P1 and the second chip pad 343P2 can be electrically connected to each other.

[0090] Here, the first semiconductor chip 310 to the fourth semiconductor chip 340 can be stacked above the carrier substrate 300 in a state where the active surfaces 311, 321, 331, and 341 face upward instead of facing the surface 301 of the carrier substrate 300 (i.e., in a face-up type).

[0091] In addition, in a state where the first side surfaces 315, 325, 335, and 345 are parallel to each other and are arranged to face the same side (e.g., the left side in the second direction), the first semiconductor chip 310 to the fourth semiconductor chip 340 may be stacked with an offset in a predetermined direction to expose the edge regions adjacent to the first side surfaces 315, 325, 335, and 345, that is, the chip pads 313P, 323P, 333P, and 343P. Here, the predetermined direction may be a direction away from the first side surfaces 315, 325, 335, and 345, for example, the right direction in the second direction.

[0092] Subsequently, the interconnectors 316, 326, 336, 346, 317, 327, 337, and 347 connected to the chip pads 313P, 323P, 333P, and 343P may be formed.

[0093] Among the interconnectors 316, 326, 336, 346, 317, 327, 337, and 347, the common interconnectors 316, 326, 336, and 346 may be connected to the chip pads 313P, 323P, 333P, and 343P to which a common signal or common power is applied. Reference will be made to ​ and ​ to describe the common interconnectors 316, 326, 336, and 346. The common interconnectors 316, 326, 336, and 346 may include: a first horizontal common interconnector 316 that connects the chip pad 313P of the first semiconductor chip 310 and the chip pad 323P of the second semiconductor chip 320 to each other; a second horizontal common interconnector 326 that connects the chip pad 323P of the second semiconductor chip 320 and the chip pad 333P of the third semiconductor chip 330 to each other; a third horizontal common interconnector 336 that connects the chip pad 333P of the third semiconductor chip 330 and the chip pad 343P of the fourth semiconductor chip 340 to each other; and a vertical common interconnector 346 that is electrically connected to the chip pad 343P of the fourth semiconductor chip 340 and extends in the vertical direction.

[0094] As an example, one end and the other end of the first horizontal common interconnector 316 can be connected to the second chip pad 313P2 of the first semiconductor chip 310 and the first chip pad 323P1 of the second semiconductor chip 320, respectively. One end and the other end of the second horizontal common interconnector 326 can be connected to the second chip pad 323P2 of the second semiconductor chip 320 and the first chip pad 333P1 of the third semiconductor chip 330, respectively. One end and the other end of the third horizontal common interconnector 336 can be connected to the second chip pad 333P2 of the third semiconductor chip 330 and the first chip pad 343P1 of the fourth semiconductor chip 340, respectively. The chip pads 313P2, 323P1, 323P2, 333P1, 333P2, and 343P1 connected to the first horizontal common interconnector 316 to the third horizontal common interconnector 336 can be arranged adjacent to each other in a straight line in the second direction. The first horizontal common interconnector 316 to the third horizontal common interconnector 336 can be bonding wirings.

[0095] In addition, as an example, the vertical common interconnector 346 can extend in the vertical direction while being connected to the second chip pad 343P2 of the fourth semiconductor chip 340 at one end. Here, the second chip pad 343P2 of the fourth semiconductor chip 340 connected to the vertical common interconnector 346 can be electrically connected to the first chip pad 343P1 of the fourth semiconductor chip 340 connected to the third horizontal common interconnector 336. The vertical common interconnector 346 can be a vertical bonding wiring.

[0096] Therefore, an electrical connection path can be formed through the second chip pad 313P2 of the first semiconductor chip 310, the first horizontal common interconnector 316, the first chip pad 323P1 of the second semiconductor chip 320 and the second chip pad 323P2 electrically connected to the first chip pad 323P1, the second horizontal common interconnector 326, the first chip pad 333P1 of the third semiconductor chip 330 and the second chip pad 333P2 electrically connected to the first chip pad 333P1, the third horizontal common interconnector 336, the first chip pad 343P1 of the fourth semiconductor chip 340 and the second chip pad 343P2 electrically connected to the first chip pad 343P1, and the vertical common interconnector 346. That is, a path for transmitting signals and / or power common to the first semiconductor chip 310 to the fourth semiconductor chip 340 can be formed.

[0097] On the other hand, among the interconnectors 316, 326, 336, 346, 317, 327, 337, and 347, the first vertical interconnector 317 to the fourth vertical interconnector 347 can be connected to the chip pads 313P, 323P, 333P, and 343P to which a single signal or a single power is applied. Reference will be made to ​ and​ Describe the first vertical interconnect 317 to the fourth vertical interconnect 347.

[0098] As an example, the first vertical interconnect 317 can be connected to chip pads 313P other than the second chip pad 313P2 that is connected to the first horizontal common interconnect 316. In addition, the first vertical interconnect 317 can be connected to chip pads 313P such as the second chip pad 313P2 on which probe testing is not performed. Similarly, the second vertical interconnect 327 can be connected to chip pads 323P other than the chip pads 323P that are connected to the first horizontal common interconnect 316 and the second horizontal common interconnect 326. In addition, the second vertical interconnect 327 can be connected to chip pads 323P such as the second chip pad 323P2 on which probe testing is not performed. Similarly, the third vertical interconnect 337 can be connected to chip pads 333P other than the chip pads 333P that are connected to the second horizontal common interconnect 326 and the third horizontal common interconnect 336. In addition, the third vertical interconnect 337 can be connected to chip pads 333P such as the second chip pad 333P2 on which probe testing is not performed. Similarly, the fourth vertical interconnect 347 can be connected to chip pads 343P other than the chip pads 343P that are connected to the third horizontal common interconnect 336 and the vertical common interconnect 346. In addition, the fourth vertical interconnect 347 can be connected to chip pads 343P such as the second chip pad 343P2 on which probe testing is not performed.

[0099] The electrical connection paths passing through the chip pads 313P of the first semiconductor chip 310 and the first vertical interconnect 317, the electrical connection paths passing through the chip pads 323P of the second semiconductor chip 320 and the second vertical interconnect 327, the electrical connection paths passing through the chip pads 333P of the third semiconductor chip 330 and the third vertical interconnect 337, and the electrical connection paths passing through the chip pads 343P of the fourth semiconductor chip 340 and the fourth vertical interconnect 347 can be separated from each other. That is, the paths for transmitting signals and / or power to the first semiconductor chip 310, the paths for transmitting signals and / or power to the second semiconductor chip 320, the paths for transmitting signals and / or power to the third semiconductor chip 330, and the paths for transmitting signals and / or power to the fourth semiconductor chip 340 can be separated from each other.

[0100] In addition, although not shown, the vertical interconnects (i.e., the vertical common interconnect 346 and the fourth vertical interconnect 347) connected to the uppermost fourth semiconductor chip 340 can be different types of connectors rather than bonding wirings. As an example, the vertical common interconnect 346 and the fourth vertical interconnect 347 can include metal bumps.

[0101] Although not shown, a molding layer and an encapsulation redistribution layer may be formed over the resultant structure of ​ . The landing pads of the encapsulation redistribution conductive layers may overlap and connect to the other ends of each of the vertical common interconnect 346 and the first vertical interconnect 317 to the fourth vertical interconnect 347, respectively.

[0102] Even in the case of the present embodiment, all the effects of the above-described embodiments can be achieved. Specifically, compared with the number / density of the vertical interconnects 346 and 347 connected to the fourth semiconductor chip 340 located at the uppermost part, the number / density of the vertical interconnects 317 connected to the first semiconductor chip 310, the number / density of the vertical interconnects 327 connected to the second semiconductor chip 320, and the number / density of the vertical interconnects 337 connected to the third semiconductor chip 330 can be smaller. That is, since the number / density of the relatively long vertical interconnects 317, 327, and 337 having a sweep problem is small, the size of the landing pads connected to the vertical interconnects 317, 327, and 337 can be increased. As a result, the misalignment between the vertical interconnects 317, 327, and 337 and the landing pads can be reduced.

[0103] In addition, compared with the above-described embodiments, since the number of semiconductor chips included in one semiconductor package is increased, the large-capacity data processing / high performance of the semiconductor package can be further satisfied.

[0104] In addition, in the above ​ embodiment, the case where a plurality of semiconductor chips are stacked in an offset manner in one direction has been described. In this case, the plurality of semiconductor chips can be recognized as one semiconductor chip as a whole. That is, a single-channel semiconductor package can be realized. However, in other embodiments, a semiconductor package having two or more channels can be realized. For example, this will be described below with reference to ​ this.

[0105] ​ is a diagram illustrating a semiconductor package and a method of manufacturing the same according to another embodiment of the present disclosure. Specifically, ​ is a plan view of a semiconductor package according to another embodiment of the present disclosure as viewed from the active surface direction. ​ is a cross-sectional view taken along the line C1-C1' of ​ . ​ is a cross-sectional view taken along the line C2-C2' of ​ . A detailed description of the components that are substantially the same as those described previously in ​ and ​ will be omitted.

[0106] Referring to​ , the first semiconductor chip 410, the second semiconductor chip 420, the third semiconductor chip 430, and the fourth semiconductor chip 440 can be vertically stacked above the surface 401 of the carrier substrate 400. The first semiconductor chip 410 may include chip pads 413P disposed on the active surface 411. The chip pads 413P may be arranged in two columns in the first direction in an edge region of the first semiconductor chip 410 adjacent to the first side surface 415, and include a first column of first chip pads 413P1 and a second column of second chip pads 413P2. The first chip pad 413P1 and the second chip pad 413P2 adjacent to each other in the second direction (i.e., a pair of the first chip pad 413P1 and the second chip pad 413P2) may be electrically connected to each other. Similarly, the second semiconductor chip 420 may include chip pads 423P disposed on the active surface 421. The chip pads 423P may be arranged in two columns in the first direction in an edge region of the second semiconductor chip 420 adjacent to the first side surface 425, and may include a first column of first chip pads 423P1 and a second column of second chip pads 423P2. A pair of the first chip pad 423P1 and the second chip pad 423P2 may be electrically connected to each other. Similarly, the third semiconductor chip 430 may include chip pads 433P disposed on the active surface 431. The chip pads 433P may be arranged in two columns in the first direction in an edge region of the third semiconductor chip 430 adjacent to the first side surface 435, and may include a first column of first chip pads 433P1 and a second column of second chip pads 433P2. A pair of the first chip pad 433P1 and the second chip pad 433P2 may be electrically connected to each other. Similarly, the fourth semiconductor chip 440 may include chip pads 443P disposed on the active surface 441. The chip pads 443P may be arranged in two columns in the first direction in an edge region of the fourth semiconductor chip 440 adjacent to the first side surface 445, and may include a first column of first chip pads 443P1 and a second column of second chip pads 443P2. A pair of the first chip pad 443P1 and the second chip pad 443P2 may be electrically connected to each other.

[0107] Here, the first semiconductor chip 410 to the fourth semiconductor chip 440 may be stacked above the carrier substrate 400 in a state where the active surfaces 411, 421, 431, and 441 face upward instead of facing the surface 401 of the carrier substrate 400 (i.e., the face-up type).

[0108] In addition, in a state where the first side surfaces 415 and 425 are parallel to each other and are arranged to face the same side (e.g., the left side in the second direction), the first semiconductor chip 410 and the second semiconductor chip 420 may be offset and stacked in a predetermined direction to expose an edge region adjacent to the first side surface 415 of the first semiconductor chip 410, that is, the chip pad 413P of the first semiconductor chip 410. Here, the predetermined direction may be a direction away from the first side surface 415, for example, the right direction in the second direction. On the other hand, in a state where the first side surfaces 435 and 445 are parallel to each other and are arranged to face the same side (the same side is opposite to the first side surfaces 415 and 425 of the first semiconductor chip 410 and the second semiconductor chip 420, e.g., the right side in the second direction), the third semiconductor chip 430 and the fourth semiconductor chip 440 may be offset and stacked in a predetermined direction to expose an edge region adjacent to the first side surface 435 of the third semiconductor chip 430, that is, the chip pad 433P of the third semiconductor chip 430. Here, the predetermined direction may be a direction opposite to the offset stacking direction of the first semiconductor chip 410 and the second semiconductor chip 420, for example, the left direction in the second direction. Since the fourth semiconductor chip 440 is located at the uppermost part, the chip pad 443P of the fourth semiconductor chip 440 may be exposed. In addition, the third semiconductor chip 430 and the fourth semiconductor chip 440 may be stacked to expose the chip pad 423P of the second semiconductor chip 420.

[0109] The first chip stack ST1 including the first semiconductor chip 410 and the second semiconductor chip 420 offset and stacked in one direction may be recognized as one semiconductor chip, and the second chip stack ST2 including the third semiconductor chip 430 and the fourth semiconductor chip 440 offset and stacked in the opposite direction may be recognized as another semiconductor chip different from the first chip stack ST1. The signal / power path through the first chip stack ST1 may be electrically separated from the signal / power path through the second chip stack ST2. In addition, the signal / power path through the first chip stack ST1 may be separately recognized from the signal / power path through the second chip stack ST2. Therefore, hereinafter, the first chip stack ST1 and the second chip stack ST2 will be described separately.

[0110] The first chip stack ST1 and the interconnectors 416, 426, 417, and 427 electrically connected thereto may be substantially the same as the above ​ structure.

[0111] Specifically, among the interconnects 416, 426, 417, and 427, the common interconnects 416 and 426 can be connected to the chip pads 413P and 423P to which a common signal or common power is applied. The common interconnects 416 and 426 can include a horizontal common interconnect 416 and a vertical common interconnect 426. One end and the other end of the horizontal common interconnect 416 can be connected to the second chip pad 413P2 of the first semiconductor chip 410 and the first chip pad 423P1 of the second semiconductor chip 420, respectively. The vertical common interconnect 426 can extend in the vertical direction while being connected to the second chip pad 423P2 of the second semiconductor chip 420 at one end.

[0112] In addition, among the interconnects 416, 426, 417, and 427, the first vertical interconnect 417 and the second vertical interconnect 427 can be connected to the chip pads 413P and 423P to which a separate signal or separate power is applied. The first vertical interconnect 417 can be connected to the chip pad 413P other than the second chip pad 413P2 connected to the horizontal common interconnect 416 and the first chip pad 413P1 electrically connected to the second chip pad 413P2. In addition, the first vertical interconnect 417 can be connected to a chip pad 413P such as the second chip pad 413P2 on which a probe test is not performed. The second vertical interconnect 427 can be connected to the chip pad 423P other than the first chip pad 423P1 connected to the horizontal common interconnect 416 and the second chip pad 423P2 connected to the vertical common interconnect 426. In addition, the second vertical interconnect 427 can be connected to a chip pad 423P such as the second chip pad 423P2 on which a probe test is not performed.

[0113] The interconnects 436, 446, 437, and 447 electrically connected to the second chip stack ST2 will be described below.

[0114] For example, among the interconnects 436, 446, 437, and 447, the common interconnects 436 and 446 can be connected to the chip pads 433P and 443P to which a common signal or common power is applied. The common interconnects 436 and 446 can include a horizontal common interconnect 436 and a vertical common interconnect 446. One end and the other end of the horizontal common interconnect 446 can be connected to the second chip pad 443P2 of the third semiconductor chip 430 and the first chip pad 443P1 of the fourth semiconductor chip 440, respectively. The vertical common interconnect 446 can extend in the vertical direction while being connected to the second chip pad 443P2 of the fourth semiconductor chip 440 at one end.

[0115] In addition, among the interconnects 436, 446, 437, and 447, the third vertical interconnect 437 and the fourth vertical interconnect 447 can be connected to the chip pads 433P and 443P to which a separate signal or separate power is applied. The third vertical interconnect 437 can be connected to the chip pad 433P other than the second chip pad 433P2 connected to the horizontal common interconnect 436 and the first chip pad 433P1 electrically connected to the second chip pad 433P2. In addition, the third vertical interconnect 437 can be connected to a chip pad 433P such as the second chip pad 433P2 on which a probe test is not performed. The fourth vertical interconnect 447 can be connected to the chip pad 443P other than the first chip pad 443P1 connected to the horizontal common interconnect 436 and the second chip pad 443P2 connected to the vertical common interconnect 446. In addition, the fourth vertical interconnect 447 can be connected to a chip pad 443P such as the second chip pad 443P2 on which a probe test is not performed.

[0116] The second chip stack ST2 and the interconnects 436, 446, 437, and 437 electrically connected to the second chip stack ST2 can be substantially the same as the state in which the first chip stack ST1 and the interconnects 416, 426, 417, and 427 electrically connected to the first chip stack ST1 are rotated 180 degrees about an axis in the vertical direction.

[0117] In addition, although not shown, the vertical interconnects (i.e., the vertical common interconnect 446 and the fourth vertical interconnect 447) connected to the uppermost fourth semiconductor chip 440 can be different types of connectors rather than bonding wirings. As an example, the vertical common interconnect 446 and the fourth vertical interconnect 447 can include metal bumps.

[0118] Although not shown, a molding layer and a package redistribution layer can be formed above the ​ resulting structure. The solder pads of the package redistribution conductive layer can overlap and be connected to the other ends of each of the vertical common interconnects 426 and 446 and the first vertical interconnect 417 to the fourth vertical interconnect 447, respectively.

[0119] Even in the case of this embodiment, all the effects of the above embodiments can be achieved.

[0120] In addition, compared with the above embodiments, since the number of semiconductor chips included in one semiconductor package is increased, the large-capacity data processing / high performance of the semiconductor package can be further satisfied. In addition, since the first chip stack ST1 and the second chip stack ST2 are recognized as different semiconductor chips, a semiconductor package having a two-channel function can be realized.

[0121] According to the above embodiments of the present disclosure, a semiconductor package having a thin thickness while satisfying the demand for high performance / large capacity can be provided. In addition, a semiconductor package capable of reducing process-induced defects and increasing design freedom can be provided.

[0122] ​ A block diagram illustrating an exemplary electronic system is shown, which includes a memory card 7800 employing at least one of the semiconductor packages according to the embodiments. The memory card 7800 includes a memory 7810 such as a non-volatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 can include at least one of the semiconductor packages according to the described embodiments.

[0123] The memory 7810 can include a non-volatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 can control the memory 7810 to read out the stored data or store data in response to a read / write request from a host 7830.

[0124] ​ A block diagram illustrating an exemplary electronic system 8710 is shown, which includes at least one of the semiconductor packages according to the described embodiments. The electronic system 8710 can include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 can be coupled to each other through a bus 8715 providing a data movement path.

[0125] In an embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 can include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 can include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 can store data and / or commands to be executed by the controller 8711.

[0126] The memory 8713 can include a volatile memory device such as DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory can be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory can constitute a solid state disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

[0127] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0128] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0129] If the electronic system 8710 represents a device capable of performing wireless communication, the electronic system 8710 may be used in a communication system using the following technologies: CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0130] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various variations and modifications can be made without departing from the spirit and scope of the present teachings as defined by the appended claims.

[0131] Cross - reference to related applications

[0132] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0103152, filed on August 18, 2020, the entire content of which is incorporated herein by reference.

Claims

1. A semiconductor package, the semiconductor package comprising: A first semiconductor chip to an Nth semiconductor chip, the first semiconductor chip to the Nth semiconductor chip having a first side surface extending in a first direction, and being offset and stacked toward the opposite side of the first side surface to expose an edge region adjacent to the first side surface, wherein N is a natural number of 2 or more; Chip pads, the chip pads being disposed in each of the edge regions of the first semiconductor chip to the Nth semiconductor chip, the chip pads including a plurality of first chip pads arranged in a first column along the first direction and a plurality of second chip pads arranged in a second column along the first direction, the first column being closer to the first side surface than the second column in a second direction intersecting the first direction, and the first chip pad and the second chip pad adjacent to each other in the second direction being electrically connected to each other; A horizontal common interconnector, one end of the horizontal common interconnector being connected to a second chip pad of a kth semiconductor chip among the first semiconductor chip to the Nth semiconductor chip, and the other end being connected to a first chip pad of a k + 1th semiconductor chip, wherein k is a natural number of 1 or more and N - 1 or less; and A vertical common interconnector, one end of the vertical common interconnector being connected to a second chip pad of the Nth semiconductor chip connected to the first chip pad of the Nth semiconductor chip, the first chip pad of the Nth semiconductor chip being connected to the horizontal common interconnector.

2. The semiconductor package according to claim 1, the semiconductor package further comprising: A first vertical interconnector to an Nth vertical interconnector, the first vertical interconnector to the Nth vertical interconnector being respectively connected to the first semiconductor chip to the Nth semiconductor chip, one end of each of the first vertical interconnector to the Nth vertical interconnector being connected to the first chip pad or the second chip pad not connected to the horizontal common interconnector and the vertical common interconnector.

3. The semiconductor package according to claim 1, wherein, Electric power or signals applied through the vertical common interconnector and the horizontal common interconnector are commonly used in the first semiconductor chip to the Nth semiconductor chip.

4. The semiconductor package according to claim 2, wherein, Electric power or signals applied through the kth vertical interconnector among the first vertical interconnector to the Nth vertical interconnector connected to the kth semiconductor chip are electrically separated from electric power or signals applied through the (k + 1)th vertical interconnector connected to the (k + 1)th semiconductor chip.

5. The semiconductor package according to claim 1, wherein, Each of the vertical common interconnector and the horizontal common interconnector includes bonding wirings.

6. The semiconductor package according to claim 1, wherein, The horizontal common interconnector includes bonding wirings, and The vertical common interconnector includes bumps.

7. The semiconductor package according to claim 2, wherein, Each of the vertical common interconnector, the horizontal common interconnector, and the first vertical interconnector to the Nth vertical interconnector includes bonding wirings.

8. The semiconductor package according to claim 2, wherein, The horizontal common interconnector and each of the first vertical interconnector to the (N - 1)th vertical interconnector include bonding wirings, and Each of the vertical common interconnector and the Nth vertical interconnector includes bumps.

9. The semiconductor package according to claim 2, further comprising: A molding layer that covers the first semiconductor chip to the Nth semiconductor chip and exposes the other ends of each of the vertical common interconnects and the first vertical interconnect to the Nth vertical interconnect; And A package redistribution layer that is formed above the molding layer and electrically connected to the other ends of each of the vertical common interconnects and the first vertical interconnect to the Nth vertical interconnect.

10. The semiconductor package according to claim 9, wherein, The package redistribution layer includes a package redistribution conductive layer having redistribution pads, the redistribution pads being connected to the other ends of each of the vertical common interconnects and the first vertical interconnect to the Nth vertical interconnect, and The planar dimension of the redistribution pads has a value equal to or greater than the displacement of the other ends of each of the vertical common interconnects and the first vertical interconnect to the Nth vertical interconnect.

11. The semiconductor package according to claim 9, wherein, The package redistribution layer includes: A first package redistribution insulating layer that is formed above the molding layer and has openings exposing the other ends of each of the vertical common interconnects and the first vertical interconnect to the Nth vertical interconnect; A package redistribution conductive layer that is formed above the first package redistribution insulating layer and includes redistribution pads filling the openings of the first package redistribution insulating layer; and A second package redistribution insulating layer that covers the first package redistribution insulating layer and the package redistribution conductive layer.

12. The semiconductor package according to claim 11, wherein, The second package redistribution insulating layer includes an opening exposing a part of the package redistribution conductive layer, and Wherein, the semiconductor package further comprises: External connection terminals that are connected to the package redistribution conductive layer through the opening of the second package redistribution insulating layer.

13. The semiconductor package according to claim 1, wherein, Each of the first semiconductor chip to the Nth semiconductor chip includes: A conductive layer; and A protective layer that is formed above the conductive layer and has openings, the openings defining the first chip pads and the second chip pads by exposing multiple portions of the conductive layer, Wherein, the first chip pads and the second chip pads adjacent to each other in the second direction overlap with the conductive layer.

14. The semiconductor package according to claim 2, wherein, The vertical common interconnects and the first vertical interconnect to the Nth vertical interconnect are connected to the first chip pads or the second chip pads whose surfaces have not been deformed due to probing.

15. The semiconductor package according to claim 14, wherein, When the probing deforms the surface of the first chip pads, the vertical common interconnects and the first vertical interconnect to the Nth vertical interconnect are connected to the second chip pads.

16. The semiconductor package according to claim 1, further comprising: The first vertical interconnector to the Nth vertical interconnector, the first vertical interconnector to the Nth vertical interconnector are respectively connected to the first semiconductor chip to the Nth semiconductor chip, and one end of each of the first vertical interconnector to the Nth vertical interconnector is connected to the second chip pad that is not connected to the horizontal common interconnector and the vertical common interconnector.

17. A semiconductor package, the semiconductor package comprising: A first chip stack, the first chip stack includes a first semiconductor chip to an Nth semiconductor chip, the first semiconductor chip to the Nth semiconductor chip have a first side surface extending in a first direction, and are stacked with an offset toward the opposite side of the first side surface of the first semiconductor chip to the Nth semiconductor chip, so as to expose the edge regions adjacent to the first side surface of the first semiconductor chip to the Nth semiconductor chip, wherein, N is a natural number greater than or equal to 2; A second chip stack, the second chip stack is formed above the first chip stack and includes an (N + 1)th semiconductor chip to a Tth semiconductor chip, the (N + 1)th semiconductor chip to the Tth semiconductor chip have a first side surface opposite to the first side surface of the first semiconductor chip to the Nth semiconductor chip, and are stacked with an offset in a direction opposite to the offset stacking direction of the first semiconductor chip to the Nth semiconductor chip, so as to expose the edge regions adjacent to the first side surface of the (N + 1)th semiconductor chip to the Tth semiconductor chip, wherein, T is a natural number greater than or equal to N + 2; Chip pads, the chip pads are disposed in each of the edge regions of the first semiconductor chip to the Tth semiconductor chip, the chip pads include a plurality of first chip pads arranged in a first column along the first direction and a plurality of second chip pads arranged in a second column along the first direction, the first column is closer to the first side surface than the second column in a second direction intersecting the first direction, and the adjacent first chip pad and second chip pad in the second direction are electrically connected to each other; A first horizontal common interconnector, one end of the first horizontal common interconnector is connected to the second chip pad of the kth semiconductor chip among the first semiconductor chip to the Nth semiconductor chip, and the other end thereof is connected to the first chip pad of the (k + 1)th semiconductor chip, wherein, k is a natural number greater than or equal to 1 and less than or equal to N - 1; A second horizontal common interconnector, one end of the second horizontal common interconnector is connected to the second chip pad of the qth semiconductor chip among the (N + 1)th semiconductor chip to the Tth semiconductor chip, and the other end thereof is connected to the first chip pad of the (q + 1)th semiconductor chip, wherein, q is a natural number greater than or equal to N + 1 and less than or equal to T - 1; A first vertical common interconnector, one end of the first vertical common interconnector is connected to a second chip pad of the Nth semiconductor chip that is electrically connected to a first chip pad of the Nth semiconductor chip, and the first chip pad of the Nth semiconductor chip is connected to the first horizontal common interconnector; and A second vertical common interconnector, one end of the second vertical common interconnector is connected to a second chip pad of the Tth semiconductor chip that is electrically connected to a first chip pad of the Tth semiconductor chip, and the first chip pad of the Tth semiconductor chip is connected to the second horizontal common interconnector.

18. The semiconductor package according to claim 17, the semiconductor package further comprising: A first vertical interconnector to a Tth vertical interconnector, the first vertical interconnector to the Tth vertical interconnector are respectively connected to the first semiconductor chip to the Tth semiconductor chip, and one end of each of the first vertical interconnector to the Tth vertical interconnector is connected to a first chip pad or a second chip pad that is not connected to the first horizontal common interconnector, the second horizontal common interconnector, the first vertical common interconnector, and the second vertical common interconnector.

19. The semiconductor package according to claim 17, wherein, The power or signal applied through the first vertical common interconnector and the first horizontal common interconnector is commonly used in the first semiconductor chip to the Nth semiconductor chip, and The power or signal applied through the second vertical common interconnector and the second horizontal common interconnector is commonly used in the (N + 1)th semiconductor chip to the Tth semiconductor chip.

20. The semiconductor package according to claim 18, wherein, The power or signal applied through the kth vertical interconnector among the first vertical interconnector to the Nth vertical interconnector that is connected to the kth semiconductor chip is electrically separated from the power or signal applied through the (k + 1)th vertical interconnector that is connected to the (k + 1)th semiconductor chip, and The power or signal applied through the qth vertical interconnector among the (N + 1)th vertical interconnector to the Tth vertical interconnector that is connected to the qth semiconductor chip is electrically separated from the power or signal applied through the (q + 1)th vertical interconnector that is connected to the (q + 1)th semiconductor chip.

21. The semiconductor package according to claim 17, wherein, Each of the first vertical common interconnector, the second vertical common interconnector, the first horizontal common interconnector, and the second horizontal common interconnector includes bonding wirings.

22. The semiconductor package according to claim 17, wherein, Each of the first horizontal common interconnector, the second horizontal common interconnector, and the first vertical common interconnector includes bonding wirings, and The second vertical common interconnector includes bumps.

23. The semiconductor package according to claim 18, wherein, Each of the first vertical common interconnector, the second vertical common interconnector, the first horizontal common interconnector, the second horizontal common interconnector, and the first vertical interconnector to the Tth vertical interconnector includes bonding wirings.

24. The semiconductor package according to claim 18, wherein, Each of the first horizontal common interconnector, the second horizontal common interconnector, the first vertical common interconnector, and the first vertical interconnector to the (T - 1)th vertical interconnector includes bonding wirings, and Each of the second vertical common interconnector and the Tth vertical interconnector includes bumps.

25. The semiconductor package according to claim 18, further comprising: a molding layer that covers the first semiconductor chip to the T-th semiconductor chip, and exposes the other ends of the first vertical common interconnect, the second vertical common interconnect, and each of the first vertical interconnect to the T-th vertical interconnect; and a package redistribution layer that is formed above the molding layer and electrically connected to the other ends of the first vertical common interconnect, the second vertical common interconnect, and each of the first vertical interconnect to the T-th vertical interconnect.

26. The semiconductor package according to claim 18, wherein, The second chip stack, the second horizontal common interconnect electrically connected to the second chip stack, the second vertical common interconnect, and the (N + 1)-th vertical interconnect to the T-th vertical interconnect are in the same state as the first chip stack, the first horizontal common interconnect electrically connected to the first chip stack, the first vertical common interconnect, and the first vertical interconnect to the N-th vertical interconnect rotated 180 degrees about an axis in the vertical direction.

27. The semiconductor package according to claim 17, wherein, The second chip stack is arranged to expose the edge region of the first side surface of the N-th semiconductor chip.

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