Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof. A method of manufacturing a semiconductor device includes the steps of forming a laminate in which a first material layer and a second material layer are alternately stacked, forming a trench structure that passes through the laminate, forming an opening by removing the first material layer, forming an amorphous barrier layer in the opening, and performing a first heat treatment process to provide deuterium through the opening and to replace hydrogen in the trench structure with deuterium.

Description

TECHNICAL FIELD

[0001] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Recently, as the integration of two-dimensional storage devices including memory cells formed in a single layer on a substrate has reached a point of diminishing return, three-dimensional memory devices including memory cells stacked in a vertical direction on a substrate have been proposed. In addition, in order to improve the operation reliability of memory devices having a three-dimensional structure, various structures and manufacturing methods have been developed. SUMMARY

[0003] Various embodiments of the present disclosure relate to a semiconductor device having a stable structure and improved operation characteristics and a manufacturing method thereof.

[0004] One embodiment of the present disclosure can provide a method of manufacturing a semiconductor device. The method can include forming a stack in which first material layers and second material layers are alternately stacked, forming a channel structure through the stack, forming an opening by removing the first material layers, forming an amorphous barrier layer in the opening, and performing a first heat treatment process to provide deuterium through the opening and to replace hydrogen in the channel structure with deuterium.

[0005] One embodiment of the present disclosure can provide a semiconductor device. The semiconductor device can include a stack of conductive layers and insulating layers alternately stacked. The semiconductor device can further include a channel layer through the stack, the channel layer including deuterium. The semiconductor device can further include a data storage layer between the conductive layer and the channel layer, the data storage layer including deuterium having a higher concentration than a concentration of the deuterium in the channel layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] FIG. 1A And FIG. 1B is a diagram illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0007] FIGS. 2A-2D is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0008] FIGS. 3A-3D is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0009] FIGS. 4A-4D is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0010] FIG. 5is a graph showing a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0011] FIG. 6 is a graph showing a memory system according to one embodiment of the present disclosure.

[0012] FIG. 7 is a graph showing a memory system according to one embodiment of the present disclosure.

[0013] FIG. 8 is a graph showing a memory system according to one embodiment of the present disclosure.

[0014] FIG. 9 is a graph showing a memory system according to one embodiment of the present disclosure.

[0015] FIG. 10 is a graph showing a memory system according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The specific structure and function descriptions of the embodiments are presented in the specification or application for the purpose of enabling. The presented embodiments are not intended to be exhaustive or limiting, and other embodiments are possible.

[0017] FIG. 1A and FIG. 1B is a graph showing a structure of a semiconductor device according to one embodiment of the present disclosure.

[0018] Referring to FIG. 1A , the semiconductor device can include a laminate ST, a channel structure CH, and a barrier pattern 13. The semiconductor device can further include a barrier pattern 14.

[0019] The laminate ST can include conductive layers 11 and insulating layers 12 which are alternately laminated. The conductive layers 11 can be gate electrodes such as memory cells or selection transistors. The conductive layers 11 can include a conductive material such as polysilicon, metal, tungsten, or molybdenum. The insulating layers 12 can function to insulate the laminated conductive layers 11 from each other, and can include an insulating material such as an oxide or a nitride.

[0020] The channel structure CH can pass through the laminate ST in a lamination direction of the conductive layers 11 and the insulating layers 12. The memory cells or the selection transistors can be located in portions where the channel structure CH and the conductive layers 11 intersect each other. The channel structure CH can include a channel layer 18 and a memory layer M, and can further include a gap filling layer 19.

[0021] The memory layer M can include the blocking layer 15, the data storage layer 16, or the tunnel insulating layer 17, or a combination thereof. The memory layer M can be configured such that the tunnel insulating layer 17 covers the sidewall of the channel layer 18, the data storage layer 16 covers the tunnel insulating layer 17, and the blocking layer 15 covers the data storage layer 16.

[0022] The channel layer 18 can include a semiconductor material such as silicon (Si) or germanium (Ge), or can include a nanostructure. The gap filling layer 19 can be formed in the channel layer 18. The gap filling layer 19 can include an insulating material such as an oxide, a nitride, or an air gap. The data storage layer 16 can be interposed between the channel layer 18 and the conductive layer 11. The data storage layer 16 can include a floating gate, a charge trapping material, a polysilicon, a nitride, a variable resistance material, a phase change material, and a nanostructure, etc. The tunnel insulating layer 17 can be interposed between the channel layer 18 and the data storage layer 16. The tunnel insulating layer 17 can include an insulating material such as an oxide. The blocking layer 15 can be interposed between the data storage layer 16 and the conductive layer 11. The blocking layer 15 can include a material having a high dielectric constant (high-k).

[0023] The channel structure CH can include 0.5 at% to 5 at% (atomic percentage) of deuterium. Deuterium is denoted by a letter "D" shown inside a circle in the drawings. The blocking layer 15, the data storage layer 16, the tunnel insulating layer 17, the channel layer 18, and the gap filling layer 19 can contain deuterium at substantially the same concentration or can contain deuterium at different concentrations. Alternatively, certain layers of the channel structure CH can not contain deuterium.

[0024] The deuterium concentration of the data storage layer 16 can be higher than the deuterium concentration of the channel layer 18. The deuterium concentration of the data storage layer 16 can be higher than the deuterium concentration of the tunnel insulating layer 17. The deuterium concentration of the tunnel insulating layer 17 can be higher than the deuterium concentration of the channel layer 18. The deuterium concentration of the tunnel insulating layer 17 can be higher than the deuterium concentration of the blocking layer 15.

[0025] The blocking pattern 13 can be interposed between the blocking layer 15 and the conductive layer 11, and can extend between the conductive layer 11 and the insulating layer 12. As shown, each of the blocking patterns 13 can have a "C" shaped cross-section. The blocking pattern 13 can include a material having a high dielectric constant (high-k). In one embodiment, the blocking pattern 13 can include aluminum oxide. The blocking pattern 13 can have a crystalline state.

[0026] The barrier pattern 13 may include 0.5 at% to 5 at% deuterium. The deuterium concentration of the barrier pattern 13 may be substantially equal to, or lower than, the deuterium concentration of the channel structure CH. The deuterium concentration of the barrier pattern 13 may be lower than the deuterium concentration of the data storage layer 16. The deuterium concentration of the barrier pattern 13 may be lower than the deuterium concentration of the tunnel insulation layer 17. The deuterium concentration of the barrier pattern 13 may be lower than the deuterium concentration of the channel layer 18.

[0027] Barrier pattern 14 can be inserted between barrier pattern 13 and conductive layer 11. Barrier pattern 14 may include tantalum nitride, titanium nitride, tungsten nitride, etc. As shown, each barrier pattern 14 may have a "C" shaped cross-section. Barrier pattern 14 may not include deuterium.

[0028] Reference FIG. 1B The semiconductor device may include a stacked body ST and a channel structure CH. The semiconductor device may also include a second memory pattern M2. The stacked body ST may include alternating layers of conductive layers 11 and insulating layers 12. The channel structure CH may include a channel layer 18 and may also include a first memory layer M1 or a gap-filling layer 19. The first memory layer M1 may include a barrier layer 15, a data storage layer 16, or a tunnel insulating layer 17.

[0029] The second memory pattern M2 can be interposed between the first memory layer M1 and the conductive layer 11, and can extend between the conductive layer 11 and the insulating layer 12. As shown, the second memory pattern M2 can have a "C" shaped cross-section. The second memory pattern M2 may include a barrier layer, a data storage layer, or a tunnel insulating layer, or may include a combination thereof.

[0030] The channel structure CH may include 0.5 at% to 5 at% deuterium. The second memory pattern M2 may include 0.5 at% to 5 at% deuterium. The deuterium concentration of the second memory pattern M2 may be lower than the deuterium concentration of the tunnel insulation layer 17. The deuterium concentration of the second memory pattern M2 may be lower than the deuterium concentration of the channel layer 18.

[0031] According to the above structure, the channel structure CH can include deuterium. In one embodiment, the channel structure CH can have Si-D bonds or ND bonds. Since Si-D bonds or ND bonds have higher bonding energy than Si-H bonds or NH bonds, the channel structure CH with Si-D bonds or ND bonds has greater resistance to electrical stress compared to the channel structure with Si-H bonds or NH bonds. Therefore, the degradation of reliability caused by electrical stress can be mitigated or suppressed. In addition, deuterium can bind to dangling bonds, grain boundaries, and trap sites in the channel structure CH. Therefore, the layer quality of the channel structure CH can be improved, and the breakdown voltage can be increased. Si, N, H, and D represent the chemical symbols for silicon, nitrogen, hydrogen, and deuterium, respectively.

[0032] FIGS. 2A-2D This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Repeated descriptions will be omitted below to avoid redundancy.

[0033] Reference FIG. 2A This forms a stack ST. The stack ST may include alternating layers of a first material layer 21 and a second material layer 22. The first material layer 21 may include a material with high etch selectivity relative to the second material layer 22. In one embodiment, the first material layer 21 may include sacrificial materials such as nitrides and polysilicon, and the second material layer 22 may include an insulating material such as oxides.

[0034] Subsequently, a first opening OP1 is formed through the laminate ST. Then, a channel structure CH is formed in the first opening OP1. First, a memory layer M can be formed in the first opening OP1. A first barrier layer 25, a data storage layer 26, and a tunnel insulation layer 27, or some of them, can be formed in the first opening OP1. Subsequently, a channel layer 28 can be formed in the memory layer M. A gap-filling layer 29 can be formed in the channel layer 28.

[0035] Reference FIG. 2B The first material layer 21 is removed to form the second opening OP2. In one embodiment, after forming a slit SL through the stack ST, the first material layer 21 exposed through the slit SL is selectively etched, thereby forming the second opening OP2. The memory layer M can be exposed through the second opening OP2. A second barrier layer 23 is then formed in the second opening OP2. In one embodiment, the second barrier layer 23 can be formed using a deposition process. The second barrier layer 23 can be conformally deposited along the contours of the slit SL and the second opening OP2. The second barrier layer 23 can be deposited in an amorphous state.

[0036] Subsequently, deuterium is supplied through the second opening OP2, and a heat treatment process is performed. The deuterium supplied through the second opening OP2 can diffuse through the second barrier layer 23 into the first barrier layer 25, the data storage layer 26, the tunnel insulation layer 27, and the channel layer 28, etc. Therefore, hydrogen in the channel structure CH can be replaced by deuterium. The Si-H bonds or NH bonds in the channel structure CH can be changed to Si-D or ND bonds. When the second barrier layer 23 is deposited in an amorphous state, the amorphous second barrier layer 23 can be crystallized through a heat treatment process. The second barrier layer 23 can be partially or completely crystallized.

[0037] In one embodiment, the heat treatment process can be performed at a high temperature of 600°C to 1000°C. Performing the heat treatment process at a high temperature can increase the deuterium substitution rate. The heat treatment process can be performed at a pressure of 0.01 atm to 20 atm. In one embodiment, the heat treatment process can be performed at a lower pressure of 0.1 atm to 5 atm. Compared to performing the heat treatment process at low pressure, performing it at high pressure can increase the deuterium substitution rate, but safety may be reduced due to the risk of explosion, etc. Therefore, by performing the heat treatment process under high temperature and low pressure conditions, the deuterium substitution rate can be safely increased.

[0038] The heat treatment process can be performed over a period of 0.01 Hz to 10 Hz. During the heat treatment process, the flow rate of D2 gas can range from 1 slm to 10 slm. The deuterium replacement rate can be increased by increasing the gas flow rate. Alternatively, the heat treatment process can be performed using a wet oxidation process with D2 and O2 gases. The deuterium replacement rate can be increased by using a wet oxidation process.

[0039] By using a heat treatment process with deuterium gas, the trench structure CH can include 0.5 at% to 5 at% deuterium. The distribution of deuterium in the trench structure CH can be adjusted according to the conditions of the heat treatment process. Under these conditions, the deuterium concentration in the data storage layer 26 can be higher than the deuterium concentration in the tunnel insulation layer 27. The deuterium concentration in the tunnel insulation layer 27 can be higher than the deuterium concentration in the trench layer 28. The deuterium concentration in the trench layer 28 can be higher than the deuterium concentration in the first barrier layer 25. The deuterium concentration in the trench layer 28 can be higher than the deuterium concentration in the second barrier layer 23.

[0040] Reference FIG. 2C A barrier layer 24 is formed. The barrier layer 24 can be formed in the slit SL and the second opening OP2. In one embodiment, a deposition process can be used to form the barrier layer 24. The barrier layer 24 can be deposited conformally along the contour of the second barrier layer 23.

[0041] If a high-temperature process is performed after the barrier layer 24 is formed, the barrier layer 24 may agglomerate or become damaged. In one embodiment of this disclosure, because the barrier layer 24 is formed after a high-temperature heat treatment process, damage to the barrier layer 24 by subsequent processes can be prevented.

[0042] Subsequently, a conductive layer 31 is formed. The conductive layer 31 can be formed in the slit SL and the second opening OP2.

[0043] Reference FIG. 2D The conductive layer 31, barrier layer 24, and second barrier layer 23 are etched. The portions of the conductive layer 31, barrier layer 24, and second barrier layer 23 formed in the slit SL can be etched. This forms individual barrier patterns 23A located in each of the second openings OP2. Barrier pattern 24A and conductive pattern 31A can be located in each barrier pattern 23A.

[0044] According to the manufacturing method described above, hydrogen in the channel structure CH can be replaced by deuterium through the second opening OP2. Because the heat treatment process is performed under high temperature and low pressure conditions, the deuterium replacement rate can be improved.

[0045] FIGS. 3A-3D This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Repeated descriptions will be omitted below to avoid redundancy.

[0046] Reference FIG. 3A A laminate ST is formed. The laminate ST may include alternating layers of first material 41 and second material 42. A first opening OP1 is then formed through the laminate ST. Subsequently, a channel structure CH is formed in the first opening OP1. The channel structure CH may include a memory layer M, which may include a tunnel insulating layer 47, a data storage layer 46, or a first barrier layer 45, or a combination thereof. A channel layer 48 may then be formed in the memory layer M. A gap-filling layer 49 may be formed in the channel layer 48.

[0047] Reference FIG. 3B The first material layer 41 is removed to form a second opening OP2, and an amorphous second barrier layer 43 is formed in the second opening OP2. Thereafter, a first heat treatment process (ANL1) is performed. The first heat treatment process can be used to crystallize the amorphous second barrier layer 43. The first heat treatment process can be performed at 900°C to 1100°C. The amorphous second barrier layer 43 can be partially or completely crystallized by the first heat treatment process. Thus, a second barrier layer 43A that is partially or completely crystalline is formed. Because the amorphous layer is crystallized to form the second barrier layer 43A, the second barrier layer 43A can have a superior layer quality compared to a barrier layer deposited in a crystalline state.

[0048] Reference FIG. 3C Deuterium is supplied through the second opening OP2, and a second heat treatment process (ALN2) is performed. Hydrogen in the channel structure CH can be replaced by deuterium through the second heat treatment process. Hydrogen in the second barrier layer 43A can be replaced by deuterium through the second heat treatment process. Furthermore, when the second barrier layer 43A partially crystallizes in the first heat treatment process, the second barrier layer 43A can be completely crystallized through the second heat treatment process. The second heat treatment process can be performed at a temperature lower than that of the first heat treatment process. If the first heat treatment process, which requires a higher temperature, is performed after the second heat treatment process, the replaced deuterium may be released. Conversely, according to one embodiment of this disclosure, since the second heat treatment process is performed after the first heat treatment process, which requires a higher temperature, the release of the replaced deuterium can be prevented.

[0049] Reference FIG. 3D The second barrier pattern 43B, the barrier pattern 44, and the conductive pattern 51 are formed. After the barrier layer and the conductive layer are formed, the barrier layer, the conductive layer, and the second barrier layer 43A formed in the slit SL can be etched to form the barrier pattern 44, the second barrier pattern 43B, and the conductive pattern 51.

[0050] According to the manufacturing method described above, after the second barrier layer 43 is crystallized by a first heat treatment process, the channel structure is deuterated by a second heat treatment process. Therefore, the release of replaced deuterium due to the high-temperature heat treatment process can be prevented. Furthermore, after performing both the first and second heat treatment processes, a barrier pattern 44 is formed. Therefore, agglomeration or damage to the barrier pattern 44 can be mitigated or prevented.

[0051] FIGS. 4A-4D This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Repeated descriptions will be omitted below to avoid redundancy.

[0052] Reference FIG. 4A A laminate ST is formed. The laminate ST may include alternating layers of first material 61 and second material 62. A first opening OP1 is then formed through the laminate ST. Subsequently, a channel structure CH is formed in the first opening OP1. The channel structure CH may include a first memory layer M1, and the first memory layer M1 may include a tunnel insulating layer 67, a data storage layer 66, or a first barrier layer 65, or a combination thereof. A channel layer 68 may then be formed in the first memory layer M1. A gap-filling layer 69 may be formed in the channel layer 68.

[0053] Reference FIG. 4BThe first material layer 61 is removed to form a second opening OP2, and a second memory layer M2 is formed in the second opening OP2. The second memory layer M2 may include a tunnel insulating layer, a data storage layer, or a second barrier layer, or a combination thereof. The second memory layer M2 may include a layer in an amorphous state.

[0054] Subsequently, a first heat treatment process (ANL1) is performed. This first heat treatment process can be used to crystallize the amorphous layer included in the second memory layer M2. The first heat treatment process can be performed at a temperature of 900°C to 1100°C. Through this process, a second memory layer M2A including a crystalline layer is formed.

[0055] Reference FIG. 4C Deuterium is supplied through the second opening OP2, and a second heat treatment process (ALN2) is performed. Hydrogen in the channel structure CH can be replaced by deuterium through the second heat treatment process. Hydrogen in the second memory layer M2A can also be replaced by deuterium through the second heat treatment process. Furthermore, when the amorphous layer of the second memory layer M2A partially crystallizes during the first heat treatment process, the amorphous layer can be completely crystallized through the second heat treatment process. The second heat treatment process can be performed at a temperature lower than that of the first heat treatment process.

[0056] Reference FIG. 4D A second memory pattern M2B and a conductive pattern 71 are formed in the second memory pattern M2B. A barrier pattern may be further formed between the second memory pattern M2B and the conductive pattern 71.

[0057] FIG. 5 This is a graph illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The x-axis represents the temperature of the heat treatment process (e.g., the second heat treatment process described above), and the y-axis represents the deuterium concentration of the heat-treated layer.

[0058] As described above, by providing deuterium gas and performing a heat treatment process, the Si-H bonds or NH bonds in the layer can be changed into Si-D bonds or ND bonds. FIG. 5 The graph represents the change in deuterium concentration based on variations in temperature and pressure during the heat treatment process. The deuterium concentration on the y-axis is related to the deuterium replacement rate. A high deuterium concentration indicates a high deuterium replacement rate. Conversely, a low deuterium concentration indicates a low deuterium replacement rate.

[0059] Referring to the graph, under the same pressure, the higher the temperature of the heat treatment process, the higher the deuterium concentration. At the same temperature, the higher the pressure of the heat treatment process, the higher the deuterium concentration. Therefore, it can be seen that the higher the temperature and pressure of the heat treatment process, the higher the deuterium replacement rate. Furthermore, the deuterium replacement rate can be increased more effectively by increasing the temperature rather than increasing the pressure. According to embodiments of this disclosure, the deuterium replacement rate of the channel structure CH can be increased by performing the heat treatment process at a high temperature. Furthermore, since the deuterium replacement rate can be sufficiently increased at high temperatures, the pressure can be determined to be low or high considering process safety.

[0060] FIG. 6 This is a diagram illustrating a memory system 1000 according to one embodiment of the present disclosure.

[0061] Reference FIG. 6 The memory system 1000 may include a memory device 1200 configured to store data and a memory controller 1100 configured to communicate between the memory device 1200 and the host 2000.

[0062] The host 2000 can be a device or system configured to store data in or retrieve data from the memory system 1000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, and erase requests for erase operations. The host 2000 can communicate with the memory system 1000 through various interfaces such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0063] The host 2000 may include at least one of a computer, portable digital device, tablet PC, digital camera, digital audio player, television, wireless communication device and cellular phone, but the embodiments disclosed herein are not limited thereto.

[0064] The memory controller 1100 can control the overall operation of the memory system 1000. The memory controller 1100 can control the memory device 1200 according to requests from the host 2000. The memory controller 1100 can control the memory device 1200 to perform programming operations, read operations, and erase operations, etc., according to requests from the host 2000. Alternatively, even without requests from the host 2000, the memory controller 1100 can perform background operations to improve the performance of the memory system 1000.

[0065] The memory controller 1100 can send control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. The control signals and data signals can be sent to the memory device 1200 through different input / output lines. Data signals can include commands, addresses, or data. Control signals can be used to identify portions of the input data signals.

[0066] The memory device 1200 can perform programming, reading, and erasing operations under the control of the memory controller 1100. The memory device 1200 can be a volatile memory device in which data stored therein is lost when power is interrupted, or a non-volatile memory device in which data stored therein is retained even when power is interrupted. The memory device 1200 can be a reference... FIG. 1A and FIG. 1B The semiconductor device described herein. The memory device 1200 can be configured as described by reference to... FIGS. 2A-5 The semiconductor device is manufactured using the described manufacturing method. In one embodiment, the semiconductor device may be a flash memory device.

[0067] When a programming, reading, or erasing operation is requested from the host 2000, the programming, reading, or erasing operation is commanded to the memory device 1200. This method can improve cell performance characteristics and retention characteristics, among other things.

[0068] FIG. 7 This is a diagram illustrating a memory system 30000 according to one embodiment of the present disclosure.

[0069] Reference FIG. 7 The memory system 30000 can be implemented in a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a memory controller 2100 configured to control the operation of the memory device 2200.

[0070] The memory controller 2100 can control the data access operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 2200 under the control of the processor 3100.

[0071] Under the control of the memory controller 2100, the data programmed in the memory device 2200 can be output through the display 3200.

[0072] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed in the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the memory controller 2100 or the display 3200. The memory controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Furthermore, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be used to input control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as an indicator device such as a touchpad and computer mouse, keypad, or keyboard. The processor 3100 can control the operation of the display 3200 so that data output from the memory controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0073] In one embodiment, the memory controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 3100 or as a separate chip from the processor 3100.

[0074] FIG. 8 This is a diagram illustrating a memory system 40000 according to one embodiment of the present disclosure.

[0075] Reference FIG. 8 The 40000 memory system can be implemented in personal computers (PCs), tablets, netbooks, e-readers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, or MP4 players.

[0076] The memory system 40000 may include a memory device 2200 and a memory controller 2100 configured to control data processing operations of the memory device 2200.

[0077] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input from the input device 4200. For example, the input device 4200 can be implemented as an indicator device such as a touchpad or computer mouse, a keypad or keyboard.

[0078] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the memory controller 2100. In one embodiment, the memory controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100.

[0079] FIG. 9 This is a diagram illustrating a memory system 50000 according to one embodiment of the present disclosure.

[0080] Reference FIG. 9 The memory system 50000 can be implemented in, for example, an image processing device such as a digital camera, a mobile phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet computer equipped with a digital camera.

[0081] The memory system 50000 may include a memory device 2200 and a memory controller 2100, the memory controller 2100 being configured to control data processing operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 2200.

[0082] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be sent to the processor 5100 or the memory controller 2100. Under the control of the processor 5100, the converted digital signals can be output to the display 5300, or stored in the memory device 2200 by the memory controller 2100. Data stored in the memory device 2200 can be output to the display 5300 under the control of the processor 5100 or the memory controller 2100.

[0083] In one embodiment, the memory controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 5100 or as a separate chip from the processor 5100.

[0084] FIG. 10 This is a diagram illustrating a memory system 70000 according to one embodiment of the present disclosure.

[0085] Reference FIG. 10The memory system 70000 can be implemented in a memory card or a smart card. The memory system 70000 may include a memory device 2200, a memory controller 2100, and a card interface 7100.

[0086] The memory controller 2100 can control the data exchange between the memory device 2200 and the card interface 7100. In one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but this disclosure is not limited thereto.

[0087] Card interface 7100 can interface for data exchange between host 60000 and memory controller 2100 according to the protocol of host 60000. In one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Here, card interface 7100 can refer to hardware, software installed in the hardware, or signal transmission method that can support the protocol used by host 60000.

[0088] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, tablet computer, digital camera, digital audio player, cellular phone, console video game hardware or digital set-top box, the host interface 6200 can communicate with the memory device 2200 through the card interface 7100 and the memory controller 2100 under the control of the microprocessor 6100.

[0089] It can provide a semiconductor device with stable structure and improved reliability.

[0090] Cross-reference to related applications

[0091] This application claims priority to Korean Patent Application No. 10-2020-0105558, filed on August 21, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminate with alternating layers of the first and second materials; Forming a channel structure through the stacked body; An opening is formed by removing the first material layer; An amorphous barrier layer is formed in the opening; as well as A first heat treatment process is performed to provide deuterium through the opening and to replace hydrogen in the channel structure with the deuterium. The trench structure includes a trench layer, a tunnel insulation layer surrounding the trench layer, a data storage layer surrounding the tunnel insulation layer, and a barrier layer surrounding the data storage layer. The data storage layer includes deuterium at a concentration higher than that in the channel layer.

2. The method according to claim 1, wherein, Through the first heat treatment process, the Si-H bonds in the channel structure are changed to Si-D bonds, and the NH bonds are changed to ND bonds.

3. The method according to claim 1, further comprising the following steps: Before performing the first heat treatment process, a second heat treatment process is performed to crystallize the amorphous barrier layer.

4. The method according to claim 3, wherein, The first heat treatment process is performed at a temperature lower than the temperature at which the second heat treatment process is performed.

5. The method according to claim 3, wherein, The first heat treatment process is performed at a temperature of 600°C to 1000°C; and The second heat treatment process is performed at a temperature of 900°C to 1100°C.

6. The method according to claim 3, wherein, The amorphous barrier layer is partially crystallized through the second heat treatment process; and The partially crystallized barrier layer is crystallized through the first heat treatment process.

7. The method according to claim 1, wherein, The first heat treatment process is performed at a temperature of 600°C to 1000°C.

8. The method according to claim 1, wherein, The first heat treatment process is performed under a pressure of 0.1 atm to 5 atm.

9. The method according to claim 1, wherein, The first heat treatment process is performed from 0.01 Hour to 10 Hour.

10. The method according to claim 1, wherein, The first heat treatment process provides 1 slm to 10 slm of D2 gas.

11. The method according to claim 1, wherein, The first heat treatment process is performed using a wet oxidation process with D2 gas and O2 gas.

12. The method according to claim 1, wherein, Through the first heat treatment process, hydrogen in at least one of the trench layer, the tunnel insulation layer, the data storage layer, and the barrier layer is replaced by deuterium.

13. The method according to claim 1, further comprising the step of: After performing the first heat treatment process, a barrier layer is formed in the opening.

14. The method of claim 13, further comprising the step of: A conductive layer is formed in the barrier layer.

15. A semiconductor device comprising: A laminate comprising alternating layers of conductive and insulating layers; A channel layer, the channel layer extending through the laminate, the channel layer comprising deuterium; and A data storage layer located between the conductive layer and the channel layer, the data storage layer comprising deuterium at a concentration higher than that in the channel layer.

16. The semiconductor device of claim 15, further comprising: A tunnel insulation layer, located between the trench layer and the data storage layer; as well as A barrier layer is located between the data storage layer and the conductive layer. The deuterium concentration in the data storage layer is higher than that in the barrier layer and the tunnel insulation layer.

17. The semiconductor device according to claim 16, wherein, The deuterium concentration in the tunnel insulation layer is higher than that in the barrier layer.

18. The semiconductor device according to claim 16, wherein, The deuterium concentration in the channel layer is higher than that in the barrier layer.

19. The semiconductor device of claim 15, further comprising: A blocking pattern is located between the conductive layer and the data storage layer. The deuterium concentration in the blocking pattern is lower than the deuterium concentration in the data storage layer and the deuterium concentration in the channel layer.

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