Control circuit of power converter and reference voltage adjustment method thereof

Abstract

A control circuit for a power converter includes a first sensing circuit, a reference voltage generating circuit, an error amplifier circuit and a pulse width modulation circuit. The first sensing circuit is coupled to a first output circuit to provide a first current sensing signal. The reference voltage generating circuit is coupled to the first sensing circuit and provides a reference voltage according to the first current sensing signal. The error amplifier circuit is coupled to the reference voltage generating circuit to receive the reference voltage and an output feedback voltage of the power converter to provide an error amplifier signal. The pulse width modulation circuit is coupled between the error amplifier circuit and the first output circuit to receive the error amplifier signal and provide a control signal to control the first output circuit. The reference voltage generating circuit also receives the error amplifier signal and adjusts the reference voltage generated according to the error amplifier signal. The control circuit for the power converter can effectively improve the output stability without affecting the output voltage under long time load.

Description

Technical Field

[0001] This invention relates to power converters, and more particularly to a control circuit for a power converter and a method for adjusting its reference voltage. Background Technology

[0002] In typical power conversion circuits, to reduce the output voltage fluctuation during continuous load unloading, a reference voltage change proportional to the output current is usually specified. This reference voltage is used for feedback control, a process known as Adaptive Voltage Positioning (AVP), and the ratio is called the load line. Since the load line represents the proportional relationship between voltage (reference voltage change) and current (output current), it is expressed as a resistance, denoted as RLL.

[0003] In known dynamic voltage regulation circuits, if a fixed load line setting is used, meaning that the same reference voltage change is provided under the same output current, the rise and fall rate of the output current (inductor current) of the power stage operating at a low input voltage will be slower than that of the power stage operating at a high input voltage. When the load connected to the power converter undergoes unloading behavior, the swing of the total current within a fixed time is smaller, causing the reference voltage change within a fixed time to be lower than the expected change. This overreaction of the control loop results in an excessively large fluctuation in the output voltage of the power converter, making it unable to provide a stable output.

[0004] In other words, directly applying a load line with a high input voltage to a low input voltage situation results in insufficient reference voltage change because the output current cannot keep up with the load change. This causes the control loop to overreact, leading to an increase in the peak-to-peak value of the output voltage and an inability to provide a stable output. This situation needs to be improved. Summary of the Invention

[0005] In view of this, the present invention proposes a control circuit for a power converter and a reference voltage adjustment method thereof, so as to effectively solve the above-mentioned problems encountered in the prior art.

[0006] According to a specific embodiment of the present invention, a control circuit for a power converter is provided. In this embodiment, the control circuit includes a first sensing circuit, a reference voltage generating circuit, an error amplification circuit, and a pulse width modulation circuit. The first sensing circuit is coupled to a first output circuit to provide a first current sensing signal. The reference voltage generating circuit is coupled to the first sensing circuit and provides a reference voltage based on the first current sensing signal. The error amplification circuit is coupled to the reference voltage generating circuit and receives the reference voltage and the output feedback voltage of the power converter to provide an error amplification signal. The pulse width modulation circuit is coupled between the error amplification circuit and the first output circuit, receives the error amplification signal, and provides a control signal to control the first output circuit. The reference voltage generating circuit also receives the error amplification signal and adjusts the reference voltage based on the error amplification signal.

[0007] In one embodiment, the reference voltage generation circuit further includes a comparison circuit coupled to an error amplifier circuit, which compares the error amplifier signal with a threshold value to generate a comparison result.

[0008] In one embodiment, when the load connected to the power converter is deloaded, the reference voltage generation circuit changes the ratio between the reference voltage and the output current provided by the output circuit from a preset value to an adjusted value based on the error amplification signal.

[0009] In one embodiment, when the load connected to the power converter is stable, the reference voltage generation circuit gradually restores the ratio from the adjusted value to the preset value.

[0010] In one embodiment, the adjustment value is related to the input voltage of the power converter.

[0011] In one embodiment, the reference voltage generation circuit includes an adjustment circuit and a voltage generation circuit. The adjustment circuit is coupled to the outputs of the first sensing circuit and the error amplifier circuit, respectively. The voltage generation circuit is coupled to the inputs of the adjustment circuit and the error amplifier circuit, respectively, and generates a reference voltage.

[0012] In one embodiment, the reference voltage generation circuit includes an analog-to-digital converter (ADC) circuit and a digital voltage generation circuit. The ADC circuit is coupled to a first sensing circuit, and the digital voltage generation circuit is coupled between the ADC circuit and an error amplifier circuit. The ADC circuit converts a first current sensing signal into a digital sensed value. The digital voltage generation circuit generates a digital reference value representing a reference voltage based on the digital sensed value.

[0013] In one embodiment, the control circuit is further coupled to the second output circuit and includes a second sensing circuit coupled between the second output circuit and the reference voltage generation circuit, and provides a second current sensing signal to the reference voltage generation circuit. The reference voltage generation circuit generates a reference voltage based on the first current sensing signal and the second current sensing signal.

[0014] According to another specific embodiment of the present invention, a reference voltage adjustment method is provided. In this embodiment, the reference voltage adjustment method is applied to the control circuit of a power converter. The control circuit is coupled to a first output circuit. The reference voltage adjustment method includes the following steps: (a) providing a first current sensing signal; (b) providing a reference voltage based on the first current sensing signal; (c) receiving the reference voltage and an output feedback voltage to provide an error amplification signal; (d) receiving the error amplification signal and providing a control signal to control the first output circuit; and (e) adjusting the reference voltage based on the error amplification signal.

[0015] In one embodiment, when the load connected to the power converter is deloaded, the above method changes the ratio between the load and the output current provided by the output circuit from a preset value to an adjusted value based on the error amplification signal.

[0016] Compared to existing technologies, the control circuit and reference voltage adjustment method of the power converter of the present invention, when load withdrawal occurs, first determines whether the preset load line is sufficient based on the error amplification signal. When the preset reference voltage change is insufficient (i.e., the error amplification signal is greater than the threshold value), the load line value is first increased to increase the reference voltage change, and then the load line is gradually adjusted back to the preset value based on the comparison result between the error amplification signal and the threshold value. It has the following advantages / effects:

[0017] (1) The reference voltage variation can be adjusted appropriately according to the input voltage and load current to reduce the peak-to-peak difference of the output voltage during rapid unloading under different input voltage applications, thus effectively improving the output stability.

[0018] (2) The reference voltage change can gradually return to the preset value after the unloading is completed, without affecting the output voltage after long-term unloading.

[0019] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the control circuit of a power converter according to one embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of the control circuit of a power converter according to another embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of the control circuit for an analog power converter.

[0023] Figure 4 for Figure 3 An embodiment of a bidirectional counting circuit.

[0024] Figure 5This is a schematic diagram of the control circuit for a digital power converter.

[0025] Figure 6 and Figure 7 The following are timing diagrams showing the control circuits of power converters in the prior art and the present invention being continuously pumped for a short period of time.

[0026] Figure 8 and Figure 9 These are timing diagrams of the control circuits of the power converters in the prior art and the present invention, respectively, during long-term unloading.

[0027] Figure 10 This is a flowchart of a reference voltage adjustment method according to another embodiment of the present invention.

[0028] Explanation of key component symbols:

[0029] 1: Control circuit

[0030] 10: Sensing Circuit

[0031] 12: Reference Voltage Generation Circuit

[0032] 14: Error Amplifier Circuit

[0033] 16: Pulse Width Modulation Circuit

[0034] OS: Output Circuit

[0035] R1~R2: Resistors

[0036] D1~D2: Drive circuit

[0037] M1~M2: Power switches

[0038] L: Output inductance

[0039] ROUT: Output resistance

[0040] COUT: Output capacitor

[0041] GND: Ground terminal

[0042] ISEN: Sensing signal

[0043] IPH: Current sensing signal

[0044] VEAP: Reference Voltage

[0045] VFB: Output Feedback Voltage

[0046] VERR: Error Amplification Signal

[0047] VIN: Input voltage

[0048] VOUT: Output voltage

[0049] PWM: Control signal

[0050] 2: Control Circuit

[0051] 201-203: Sensing Circuit

[0052] 22: Reference Voltage Generation Circuit

[0053] 24: Error Amplifier Circuit

[0054] 26: Pulse Width Modulation Circuit

[0055] IPH1~IPH3: Current sensing signals

[0056] VS1~VS3: Sensing signals

[0057] PWM1~PWM3: Control signals

[0058] OS1~OS3: Output Circuit

[0059] L1~L3: Output inductors

[0060] IOUT1~IOUT3: Output current

[0061] ILOAD: Load current

[0062] 3: Control Circuit

[0063] 301-302: Sensing circuit

[0064] 32: Reference Voltage Generation Circuit

[0065] 34: Error Amplifier Circuit

[0066] 36: Pulse Width Modulation Circuit

[0067] 3010, 3020: Amplifiers

[0068] 3012: Current Mirror

[0069] 3022: Current Mirror

[0070] ADJ: Adjustment Circuit

[0071] 320: Comparator Circuit

[0072] 322: Bidirectional counting circuit

[0073] 324: Current Mirror

[0074] 326: Voltage generation circuit

[0075] 340: Error Amplifier

[0076] 362: Comparator Circuit

[0077] 364: Pulse Width Modulation Logic Circuit

[0078] 3260: Current Mirror

[0079] 3262: Voltage Follower

[0080] IM: Current signal

[0081] R: Resistance

[0082] C: Capacitor

[0083] RAMP: Ramp signal

[0084] CAMP: Compensation Signal

[0085] VDAC: Preset voltage

[0086] X:Y: Current ratio

[0087] VTH: Threshold value

[0088] CMP: Comparison Signal

[0089] CT: Counting signal

[0090] CSP1 / CSN1: Sensing signal

[0091] CSP2 / CSN2: Sensing signal

[0092] 3220: Converter

[0093] 3222: Bidirectional Counter

[0094] M: Preset value

[0095] N: Initial adjustment value

[0096] 5: Control Circuit

[0097] 501-503: Sensing Circuits

[0098] 52: Reference Voltage Generation Circuit

[0099] 54: Error Amplifier Circuit

[0100] 56: Pulse Width Modulation Circuit

[0101] 58: Analog-to-digital converter

[0102] 5201~5203: Analog-to-digital converter

[0103] 522: Digital Reference Value Generator

[0104] DISUM: Digital summation current signal

[0105] DEAP: Numerical Reference Value

[0106] DERR: Digital Error Amplification Signal

[0107] DFB: Digital Output Feedback Value

[0108] RLL: Load Line

[0109] VDEC_CEAP: Change in reference voltage

[0110] P1~P2: Output voltage peak-to-peak value

[0111] t1~t4: Time

[0112] S10~S18: Steps Detailed Implementation

[0113] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Elements / components referred to by the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0114] According to a specific embodiment of the present invention, a control circuit for a power converter is provided. In this embodiment, the control circuit can be applied to a single-phase or multi-phase power converter, depending on the actual requirements.

[0115] Please refer to Figure 1 . Figure 1 This is a schematic diagram of the control circuit for a single-phase power converter. (Example:) Figure 1 As shown, control circuit 1 is coupled to output circuit OS. Resistors R1 and R2 are connected in series between output circuit OS and ground GND. Output resistor ROUT and output capacitor COUT are connected in series between output circuit OS and ground GND. Control circuit 1 is also coupled to resistors R1 and R2.

[0116] The output circuit OS includes drive circuits D1-D2, power switches M1-M2, and output inductor L. Drive circuit D1 is coupled between control circuit 1 and the control terminal of power switch M1. Drive circuit D2 is coupled between control circuit 1 and the control terminal of power switch M2. Power switches M1 and M2 are connected in series, with power switch M2 coupled to ground GND. One end of the output inductor L is coupled between power switches M1 and M2. The other end of the output inductor L has an output voltage VOUT and is coupled to resistor R1 and output resistor ROUT (load). Load current ILOAD flows through resistor ROUT.

[0117] The control circuit 1 includes a sensing circuit 10, a reference voltage generation circuit 12, an error amplifier circuit 14, and a pulse width modulation circuit 16. The sensing circuit 10 is coupled to the output inductor L in the output circuit OS. The reference voltage generation circuit 12 is coupled to the sensing circuit 10. The input terminals of the error amplifier circuit 14 are coupled to the reference voltage generation circuit 12 and resistors R1 and R2, respectively, and the output terminals of the error amplifier circuit 14 are coupled to the pulse width modulation circuit 16 and the reference voltage generation circuit 12, respectively. The pulse width modulation circuit 16 is coupled between the error amplifier circuit 14 and the output circuit OS.

[0118] Sensing circuit 10 senses the inductor current flowing through the output inductor L of output circuit OS to obtain a sensing signal ISEN, and provides a current sensing signal IPH to reference voltage generation circuit 12 accordingly. Reference voltage generation circuit 12 provides a reference voltage VEAP to error amplifier circuit 14 based on the current sensing signal IPH. It should be noted that the sensing signal ISEN is usually a voltage signal, which can be obtained by sensing the inductor current flowing through output inductor L through circuits such as DC resistors (DCR) and resistive elements, but is not limited to this.

[0119] When the error amplifier circuit 14 receives the reference voltage VEAP from the reference voltage generation circuit 12 and the output feedback voltage VFB from the resistors R1 and R2 respectively, the error amplifier circuit 14 will generate an error amplification signal VERR based on the reference voltage VEAP and the output feedback voltage VFB, and output it to the pulse width modulation circuit 16 and the reference voltage generation circuit 12.

[0120] When the pulse width modulation circuit 16 receives the error amplification signal VERR, the pulse width modulation circuit 16 will generate a control signal PWM to the output circuit OS according to the error amplification signal VERR, thereby controlling the operation of the output circuit OS.

[0121] When the reference voltage generation circuit 12 receives the error amplification signal VERR, it adjusts the generated reference voltage VEAP according to the error amplification signal VERR. In practical applications, the reference voltage generation circuit 12 can adjust the change in the reference voltage VEAP according to the error amplification signal VERR, for example, by adjusting the change in the reference voltage VEAP accordingly based on the comparison result between the error amplification signal VERR and the threshold value, but this is not a limitation.

[0122] Please refer to Figure 2 . Figure 2 This is a schematic diagram of the control circuit for a multiphase power converter. Figure 1 The only difference in the embodiments is that: (1) the control circuit 2 is coupled to multiple output circuits OS1 to OS3 respectively. The circuit architecture of output circuits OS2 to OS3 is the same as that of output circuit OS1.

[0123] (2) The control circuit 2 includes multiple sensing circuits 201 to 203. Sensing circuits 201 to 203 are respectively coupled to the output inductors L1 to L3 of the output circuits OS1 to OS3. The reference voltage generation circuit 22 is respectively coupled to sensing circuits 201 to 203. Other circuits are... Figure 1 The implementation methods are the same and will not be described again here.

[0124] Sensing circuits 201-203 are used to sense sensing signals VS1-VS3 related to the output currents IOUT1-IOUT3 flowing through the output inductors L1-L3 of the output circuits OS1-OS3, and provide current sensing signals IPH1-IPH3 to the reference voltage generation circuit 22 accordingly. The reference voltage generation circuit 22 provides a reference voltage VEAP to the error amplifier circuit 24 based on the current sensing signals IPH1-IPH3. In this embodiment, the means of obtaining sensing signals VS1-VS3 from the output inductors L1-L3 can be a DC resistance (DCR) sensing circuit, and the sensed signals VS1-VS3 are voltage signals, but this is not a limitation.

[0125] Please refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the control circuit 3 for a multiphase analog power converter. Figure 4 This refers to the bidirectional counting circuit 322 in the reference voltage generation circuit 32. For example... Figure 3 As shown, the control circuit 3 of the multiphase analog power converter obtains sensing signals CSP1~CSP2 / CSN1~CSN2 from the output circuits OS1~OS2. Other external circuits and coupling relationships are as follows. Figure 2 Since they are the same, they will not be elaborated further.

[0126] The control circuit 3 includes sensing circuits 301-302, a reference voltage generation circuit 32, an error amplifier circuit 34, and a pulse width modulation circuit 36. Sensing circuits 301-302 are coupled to output circuits OS1-OS2, respectively. The reference voltage generation circuit 32 is coupled to sensing circuits 301-302. The input terminals of the error amplifier circuit 34 are coupled to the reference voltage generation circuit 32 and resistors R1 and R2, respectively, and the output terminals of the error amplifier circuit 34 are coupled to the pulse width modulation circuit 36 ​​and the reference voltage generation circuit 32, respectively. The pulse width modulation circuit 36 ​​is coupled between the error amplifier circuit 34 and the output circuits OS1-OS2.

[0127] The sensing circuit 301 includes an amplifier 3010 and a current mirror 3012. The two input terminals of the amplifier 3010 receive the sensing signal CSP1 / CSN1 related to the output current IOUT1 of the output circuit OS1 and output the comparison result to control the current mirror 3012 (1:1) to generate a current sensing signal IPH1 to the reference voltage generation circuit 32.

[0128] Similarly, the sensing circuit 302 includes an amplifier 3020 and a current mirror 3022. The two input terminals of the comparator 3020 receive the sensing signal CSP2 / CSN2 related to the output current IOUT2 ​​of the output circuit OS2 and output the comparison result to control the current mirror 3022 (1:1) to generate a current sensing signal IPH2 to the reference voltage generation circuit 32. It should be noted that in this embodiment, the sensing circuits 301 to 302 obtain the sensing signal CSP / CSN through an external DC resistor (DCR) sensing circuit (not shown), but this is not a limitation.

[0129] The reference voltage generation circuit 32 includes a comparator circuit 320, a bidirectional counting circuit 322, a current mirror 324, and a voltage generation circuit 326. The input terminals of the comparator circuit 320 are coupled to the output terminal of the error amplifier circuit 34 and the threshold value VTH. The bidirectional counting circuit 322 is coupled between the comparator circuit 320 and the current mirror 324. The current mirror 324 is coupled to sensing circuits 301-302, the bidirectional counting circuit 322, and the voltage generation circuit 326. The voltage generation circuit 326 is coupled to the input terminals of the current mirror 324 and the error amplifier circuit 34. The comparator circuit 320, the bidirectional counting circuit 322, and the current mirror 324 can also be collectively referred to as the adjustment circuit ADJ, but this is not a limitation.

[0130] like Figure 4 As shown, the bidirectional counting circuit 322 includes a converter 3220 and a bidirectional counter 3222. The converter 3220 is coupled to the bidirectional counter 3222. The converter 3220 generates an initial adjustment value N for the ratio (hereinafter referred to as the load line (RLL)) between the change in the reference voltage VEAP and the output current (IOUT1+IOUT2) received by the output circuits OS1 to OS2. The bidirectional counter 3222 receives the initial adjustment value N, the preset value M of the load line (RLL), and the comparison signal CMP provided by the comparison circuit 320, and generates a counting signal CT to the current mirror 324 accordingly.

[0131] For example, when the comparison result of the comparator circuit 320 is that the error amplification signal VERR is higher than the threshold value VTH, it indicates that the load connected to the power converter has been de-loaded. At this time, the bidirectional counter 3222 will change the load line (RLL) from the original preset value M to the adjustment value (M+N) according to the comparison signal CMP. In other words, the adjustment value (M+N) is the preset value M plus the initial adjustment value N, but it is not limited to this.

[0132] In fact, the initial adjustment value N is related not only to the input voltage VIN, but also to the on-time TON and minimum off-time TOFF (min) in the control signals PWM1 to PWM2 generated by the pulse width modulation logic circuit 364, but is not limited to this.

[0133] After a period of time, when the comparison result of the comparison circuit 320 comparing the error amplification signal VERR with the threshold value VTH begins to change to the error amplification signal VERR being lower than the threshold value VTH, it indicates that the load connected to the power converter is stabilizing. At this time, the bidirectional counter 3222 will gradually restore the load line (RLL) from the adjustment value (M+N) to the preset value M according to the comparison signal CMP.

[0134] When the current mirror 324 receives the current sensing signals IPH1 to IPH2 provided by the sensing circuits 301 to 302, the current mirror 324 generates a current signal IM corresponding to the current sensing signals IPH1 to IPH2 according to the current ratio X:Y and sends it to the voltage generation circuit 326. In this example, the magnification of the current mirror 324 is the value of the load line (RLL).

[0135] The voltage generation circuit 326 includes a current mirror 3260, a voltage follower 3262, and a resistor R. The current mirror 3260 is coupled to the current mirror 324 of the reference voltage generation circuit 32 and the resistor R. The output of the voltage follower 3262 is coupled between the current mirror 3260 and the resistor R. One input terminal + of the voltage follower 3262 is coupled to a preset voltage VDAC, and the other input terminal - is coupled to its output terminal.

[0136] When the current mirror 3260 receives the current signal IM provided by the current mirror 324 of the reference voltage generation circuit 32, the current mirror 3260 transmits the current signal IM to the resistor R according to a 1:1 current ratio. Since the voltage follower 3262 limits the voltage at one end of the resistor R to a preset voltage VDAC, when the current signal IM flows through the resistor R, the voltage at the other end of the resistor R is equal to VDAC - (IM * R) and is provided to the error amplifier circuit 34 as the reference voltage VEAP. In other words, once the current signal IM provided by the current mirror 324 of the reference voltage generation circuit 32 is changed, the reference voltage VEAP will also change accordingly.

[0137] The error amplifier circuit 34 includes an error amplifier 340. When one input terminal of the error amplifier 340 receives a reference voltage VEAP provided by the reference voltage generation circuit 32 and its other input terminal receives an output feedback voltage VFB related to the output voltage VOUT, the error amplifier circuit 34 generates an error amplification signal VERR based on the reference voltage VEAP and the output feedback voltage VFB.

[0138] The pulse width modulation circuit 36 ​​includes a resistor R, a capacitor C, a comparator circuit 362, and a pulse width modulation logic circuit 364. The resistor R and the capacitor C are connected in series between one input terminal of the comparator circuit 362 and the ground terminal GND, and are used as a low-pass filter (LPF) to filter the error amplification signal VERR provided by the error amplification circuit 34 to generate a compensation signal COMP.

[0139] Comparator circuit 362 compares the compensation signal COMP with the ramp signal RAMP and provides a comparison signal to pulse width modulation logic circuit 364 based on the comparison result. Pulse width modulation logic circuit 364 generates control signals PWM1 to PWM2 based on the comparison signal and sends them to output circuits OS1 to OS2 to control the operation of output circuits OS1 to OS2.

[0140] In other words, the analog control circuit 3 can effectively change the load line (RLL) by dynamically adjusting the current ratio X:Y of the current mirror 324, and adjust the change in the reference voltage (i.e., the preset voltage VDAC - reference voltage VEAP) through the current signal IM generated by it, thus achieving the effect of dynamically adjusting the reference voltage VEAP.

[0141] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a multiphase digital power converter. Figure 5 and Figure 3 The only difference is that control circuit 5 also includes an analog-to-digital converter 58, and its reference voltage generation circuit 52 is digital, providing a digital value representing the reference voltage. The analog-to-digital converter 58 is coupled to the error amplifier circuit 54 and resistors R1 and R2, respectively; the rest are connected to... Figure 3 Since they are the same, they will not be elaborated further.

[0142] The reference voltage generation circuit 52 includes analog-to-digital converters 5201-5203 and a digital reference voltage generator 522. The analog-to-digital converters 5201-5203 are respectively coupled between the sensing circuits 501-503 and the digital reference voltage generator 522. The digital reference voltage generator 522 is also coupled to the error amplifier circuit 54.

[0143] Analog-to-digital converters 5201-5203 convert the current sensing signals IPH1-IPH3 provided by sensing circuits 501-503 into digital sensing values ​​and output a digital summed current signal DISUM to a digital reference voltage generator 522. The digital reference voltage generator 522 generates a digital reference value DEAP representing the reference voltage based on the digital summed current signal DISUM and outputs it to the error amplifier circuit 54. Analog-to-digital converter 58 converts the output feedback voltage VFB between resistors R1 and R2 into a digital output feedback value DFB and outputs it to the error amplifier circuit 54.

[0144] When the error amplifier circuit 54 receives the digital reference value DEAP and the digital output feedback value DFB, respectively, it generates a digital error amplification signal DERR based on these values ​​and provides it to the pulse width modulation circuit 56 and the digital reference voltage generator 522. The digital reference voltage generator 522 determines whether to increase the change in the digital reference value DEAP from the original preset value M to the adjusted value (M+N) based on whether the digital error amplification signal DERR is higher than the threshold value DTH.

[0145] In practical applications, the digital control circuit 5 can convert the error amplification signal into an adjustment value through a look-up table to directly generate a new digital reference value DEAP, but it is not limited to this.

[0146] Please refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 The following are timing diagrams of the control circuits of the power converters of the prior art and the present invention, respectively, under short-term continuous loading. The simulation conditions are: input voltage VIN = 6V, and the preset value of load line RLL M = 2mΩ (applicable to 12V), but not limited to these conditions.

[0147] like Figure 6 As shown, since existing technologies do not have a reference voltage adjustment mechanism like that of this invention, the load line RLL remains unchanged at the preset value M = 2mΩ regardless of whether the load is unloaded or not. The reference voltage VEAP and the output current IOUT change proportionally, and the peak-to-peak value P1 of the output voltage VOUT is 300mV.

[0148] like Figure 7As shown, at time t1, the load begins to withdraw the load current ILOAD, and the output current IOUT changes from a low level to a high level due to the withdrawal. At this time, the output voltage VOUT begins to drop due to the withdrawal, and the reference voltage VEAP responds to the drop mechanism and drops to a preset voltage value according to the preset value M = 2mΩ of the load line RLL. At this time, because the drop in output voltage VOUT is large, the difference between the reference voltage VEAP and the output feedback voltage VFB (related to the output voltage VOUT) increases (i.e., the error amplification signal VERR), causing the error amplification signal VERR to increase and exceed the threshold value VTH. Therefore, the load line RLL will increase from the original preset value M to the adjustment value (M+N) = 2.2mΩ, thereby causing the reference voltage VEAP to drop even lower.

[0149] At time t2, the load is unloaded, and the output current IOUT changes from a high level to a low level due to the unloading. The power supply during the unloading period causes the previously decreasing output voltage VOUT to start rising again, making the difference between the reference voltage VEAP and the output feedback voltage VFB (related to the output voltage VOUT) (i.e., the error amplification signal VERR) smaller and less than 0. At this time, if the error amplification signal VERR is less than the threshold value VTH, the load line RLL will decrease by 1 unit from the adjustment value (M+N) = 2.2mΩ, instead of dropping directly back to the preset value M.

[0150] At time t3, the load is emptied again, and the load current ILOAD is emptied. The output current IOUT changes from a low level to a high level due to the emptying. At this time, the output voltage VOUT begins to drop due to the emptying. However, the difference between the reference voltage VEAP and the output feedback voltage VFB (which is related to the output voltage VOUT) (i.e., the error amplification signal VERR) has not yet returned to 0. Therefore, the error amplification signal VERR is still less than the threshold value VTH, and the load line RLL will drop by 1 unit again.

[0151] At time t4, the output voltage VOUT continues to decrease due to load withdrawal, causing the difference between the reference voltage VEAP and the output feedback voltage VFB (related to the output voltage VOUT) (i.e., the error amplification signal VERR) to increase and exceed the threshold value VTH. Therefore, the load line RLL increases to the adjustment value (M+N) = 2.2mΩ. This means that the reference voltage VEAP will be adaptively adjusted due to the change in its ratio with the output current IOUT, and the peak-to-peak value of the output voltage VOUT P2 is 230mV.

[0152] It should be noted that the comparison Figure 6 and Figure 7 It can be seen that: due to Figure 7 The load line RLL shown is raised during deloading, resulting in a smaller error amplification signal VERR and a lower peak-to-peak output voltage P2 (230mV). Figure 6The peak-to-peak output voltage P1 (300mV) is shown. In other words, compared with the prior art, the control circuit of the power converter proposed in this invention can effectively reduce the peak-to-peak output voltage VOUT during continuous load unloading by dynamically adjusting the reference voltage VEAP, thereby providing a more stable output.

[0153] Please refer to Figure 8 and Figure 9 , Figure 8 and Figure 9 These are timing diagrams of the control circuits of the power converters in the prior art and the present invention, respectively, under long-term load conditions.

[0154] like Figure 8 As shown, since the prior art does not have a reference voltage adjustment mechanism like the present invention, when the control circuit of the prior art power converter is deloaded for a long time, the load line RLL will remain unchanged at the preset value M = 2mΩ.

[0155] like Figure 9 As shown, at time t1, when the load just starts to draw the load current ILOAD, the load line RLL will increase from the original preset value M to the adjusted value (M+N). Then, under long-term drawdown, the load line RLL will gradually return to the preset value M as the system enters a steady state. Therefore, the control circuit of the power converter of the prior art and the present invention performs similarly under long-term drawdown.

[0156] According to another specific embodiment of the present invention, a reference voltage adjustment method is provided. In this embodiment, the reference voltage adjustment method is applied to the control circuit of a power converter. The control circuit is coupled to a first output circuit.

[0157] Please refer to Figure 10 , Figure 10 A flowchart of the reference voltage adjustment method in this embodiment is provided. Figure 10 As shown, the reference voltage adjustment method includes the following steps:

[0158] Step S10: Provide a first current sensing signal;

[0159] Step S12: Provide a reference voltage based on the first current sensing signal;

[0160] Step S14: Receive the reference voltage and the output feedback voltage to provide an error amplification signal;

[0161] Step S16: Receive the error amplification signal and provide a control signal to control the first output circuit; and

[0162] Step S18: Adjust the reference voltage according to the error amplification signal.

[0163] In analog applications, step S18 adjusts the scaling factor of the sensed current (load line RLL) to change the amount of change in the reference voltage, thereby adjusting the reference voltage, but it is not limited to this. When the load connected to the power converter is de-loaded, step S18 increases the scaling factor of the sensed current according to the error amplification signal, changing the scaling factor from the preset value M to the adjusted value (M+N). When the load connected to the power converter stabilizes, the reference voltage adjustment method gradually restores the scaling factor from the adjusted value (M+N) back to the preset value (M).

[0164] In one embodiment, step S10 further includes providing a second current sensing signal IPH2, and step S12 further includes generating a reference voltage based on the first current sensing signal and the second current sensing signal, but is not limited thereto.

[0165] If the control circuit of the power converter is digital, the reference voltage adjustment method further includes: converting the first current sensing signal into a digital sensing value, and generating a digital reference value representing the reference voltage based on the digital sensing value; and selectively changing the ratio of the change in the digital reference value to the output current (load line RLL) from a preset value to an adjusted value based on whether the error amplification signal is higher than a threshold value, and generating a digital reference value based on the relationship that the change in the digital reference value = output current * load line.

[0166] Compared to existing technologies, the control circuit of the power converter and its reference voltage adjustment method of the present invention, when load withdrawal occurs, first determines whether the preset reference voltage change is sufficient based on the error amplification signal. If the preset reference voltage change is insufficient (i.e., the error amplification signal is greater than the threshold value), the reference voltage change is first increased, and then gradually adjusted back to the preset reference voltage change based on the comparison result between the error amplification signal and the threshold value. It has the following advantages / effects:

[0167] (1) The reference voltage variation can be adjusted appropriately according to the input voltage and load current to reduce the peak-to-peak difference of the output voltage during rapid unloading under different input voltage applications, thus effectively improving the output stability.

[0168] (2) The reference voltage change can gradually return to the preset value after the unloading is completed, without affecting the output voltage after long-term unloading.

Claims

1. A control circuit of a power converter coupled to a first output circuit, characterized by, The control circuit comprises: a first sensing circuit coupled to the first output circuit to provide a first current sensing signal; a reference voltage generating circuit coupled to the first sensing circuit and configured to provide a reference voltage according to the first current sensing signal; an error amplifier circuit coupled to the reference voltage generating circuit and configured to receive the reference voltage and an output feedback voltage of the power converter to provide an error amplifier signal; and a pulse width modulation circuit coupled between the error amplifier circuit and the first output circuit, configured to receive the error amplifier signal and provide a control signal to control the first output circuit, wherein the reference voltage generating circuit is further configured to receive the error amplifier signal and adjust the reference voltage according to the error amplifier signal, and when a load connected to the power converter is subjected to a load transient, the reference voltage generating circuit is configured to change a ratio between a variation of the reference voltage and an output current provided by the output circuit from a preset value to an adjusted value according to the error amplifier signal.

2. The control circuit of claim 1, wherein, The reference voltage generating circuit further comprises a comparison circuit coupled to the error amplifier circuit and configured to compare the error amplifier signal with a threshold value to generate a comparison result.

3. The control circuit of claim 1, wherein, When the load connected to the power converter is stable, the reference voltage generating circuit is configured to gradually change the ratio from the adjusted value back to the preset value.

4. The control circuit of claim 1, wherein, The adjusted value is related to an input voltage of the power converter.

5. The control circuit of claim 1, wherein, The reference voltage generating circuit comprises an adjustment circuit and a voltage generating circuit, the adjustment circuit is coupled to an output terminal of the first sensing circuit and an output terminal of the error amplifier circuit, and the voltage generating circuit is coupled to an input terminal of the adjustment circuit and an input terminal of the error amplifier circuit and configured to generate the reference voltage.

6. The control circuit of claim 5, wherein, The adjustment circuit comprises a comparison circuit and a bidirectional counting circuit, the comparison circuit is coupled to the output terminal of the error amplifier circuit, the bidirectional counting circuit is coupled to an output terminal of the comparison circuit, and configured to determine and adjust a variation of the reference voltage according to a comparison signal provided by the comparison circuit.

7. The control circuit of claim 1, wherein, The reference voltage generating circuit comprises an analog-digital conversion circuit and a digital voltage generating circuit, the analog-digital conversion circuit is coupled to the first sensing circuit, and the digital voltage generating circuit is coupled between the analog-digital conversion circuit and the error amplifier circuit, the analog-digital conversion circuit is configured to convert the first current sensing signal into a digital sensing value, and the digital voltage generating circuit is configured to generate a digital reference value representing the reference voltage according to the digital sensing value.

8. The control circuit of claim 7, wherein, The digital voltage generating circuit is configured to selectively change the ratio between the variation of the digital reference value and the output current from the preset value to the adjusted value according to whether the error amplifier signal is higher than a threshold value.

9. The control circuit of claim 1, wherein, The control circuit is further coupled to a second output circuit, and the control circuit further comprises: a second sensing circuit coupled between the second output circuit and the reference voltage generating circuit, and configured to provide a second current sensing signal to the reference voltage generating circuit, and the reference voltage generating circuit is configured to generate the reference voltage according to the first current sensing signal and the second current sensing signal.

10. A reference voltage adjustment method, characterized by, The reference voltage adjustment method is applied to a control circuit of a power converter, the control circuit is coupled to a first output circuit, the reference voltage adjustment method comprises the following steps: (a) providing a first current sensing signal; (b) providing a reference voltage according to the first current sensing signal; (c) receiving the reference voltage and an output feedback voltage to provide an error amplification signal; (d) receiving the error amplification signal and providing a control signal to control the first output circuit; and (e) adjusting the reference voltage according to the error amplification signal, wherein when a load connected to the power converter is in a load-drawing state, the reference voltage adjustment method changes a ratio between a variation amount of the reference voltage and an output current provided by the output circuit according to the error amplification signal from a preset value to an adjustment value.

11. The reference voltage adjustment method of claim 10, further comprising the following step: (f) comparing the error amplification signal with a threshold value to generate a comparison result.

12. The reference voltage adjusting method of claim 10, wherein, When the load connected to the power converter is stable, the reference voltage adjustment method gradually returns the ratio between the variation amount of the reference voltage and the output current from the adjustment value to the preset value.

13. The reference voltage adjusting method of claim 10, wherein, The adjustment value is related to an input voltage.

14. The reference voltage adjusting method of claim 10, wherein, The reference voltage adjustment method further comprises: converting the first current sensing signal into a digital sensing value, and generating a digital reference value representing the reference voltage according to the digital sensing value.

15. The reference voltage adjusting method of claim 14, wherein, The reference voltage adjustment method further comprises: selectively changing the ratio between the variation amount of the digital reference value and the output current from a preset value to an adjustment value according to whether the error amplification signal is higher than a threshold value.

16. The reference voltage adjusting method of claim 10, wherein, Step (a) further comprises providing a second current sensing signal and step (b) further comprises generating the reference voltage according to the first current sensing signal and the second current sensing signal.

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