Semiconductor chip testing device and testing method

Abstract

The present invention provides a test device and a test method for semiconductor chips, which minimize the maintenance of contact probes and measuring tables when damage to semiconductor chips occurs. If the device to be measured is turned on, its drain-source voltage Vds decreases and the drain current Id increases. Next, if the device to be measured is turned off, its drain-source voltage Vds increases sharply and the drain current Id decreases. If there is a sharp change in the drain current Id during the period when the drain current Id decreases, the device to be measured is judged to be damaged. The energy applied to the damaged device to be measured is calculated. Only when the applied energy exceeds the set value, the test device is stopped and an instruction is given to replace the contact probe or the measuring table, or replace both of them. Thereby, maintenance costs are suppressed.

Description

Technical Field

[0001] The invention relates to a testing device and a testing method for semiconductor chips. Background Art

[0002] Power devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and / or IGBT (Insulated Gate Bipolar Transistor) are subjected to dynamic characteristic tests in the state of semiconductor wafers or semiconductor chips.

[0003] Fig.12 is a diagram showing a measurement mechanism used in conventional semiconductor chip tests. Fig.13 This is a diagram showing a state in which deposits are generated on contact probes due to energy applied to a semiconductor chip after the semiconductor chip is damaged by a test.

[0004] like Fig.12 As shown, a device under test 100, which is a semiconductor chip, is tested using a tester 101, a contact probe 102, a contact block 103 for holding the contact probe 102, and a test table 104. At this time, the device under test 100 is electrically connected to the tester 101 through the contact probe 102 and the test table 104, and is subjected to a short-term electrical stress from the tester 101 to perform good / bad product sorting.

[0005] The tester 101 is provided with a semiconductor switch between a power source and the device under test 100. If the device under test 100 is damaged during the test, the semiconductor switch is turned off to cut off the current flowing in the device under test 100. In the semiconductor switch, a discharge-blocking snubber circuit is used as a snubber circuit for absorbing the surge voltage generated when the semiconductor switch is turned off (for example, refer to Patent Document 1). Therefore, the current that continues to flow after the semiconductor switch is turned off can be reduced, and the expansion of the damage to the device under test 100 and the damage to the contact probe 102 and the measuring table 104 are suppressed, so that the maintenance cost is reduced.

[0006] In addition, when testing the device under test 100, if Fig.13As shown, a dynamic characteristic test is performed by bringing a contact probe 102 into contact with an electrode of the device under test 100 while applying a load to the electrode of the device under test 100. Here, if a current that may damage the device under test 100 flows during the test, a foreign object 105 obtained by melting a component of the device under test 100 (silicon in the case of a silicon device) may adhere to the contact probe 102. Such a foreign object 105 may adhere not only to the contact probe 102 but also to the measurement table 104.

[0007] If foreign matter 105 is attached to the contact probe 102 and the measuring table 104, the foreign matter 105 not only physically damages the device under test 100 to be tested next, but also prevents normal testing due to the presence of the foreign matter 105 in the test circuit. Therefore, when the device under test 100 is damaged, the test of the tester 101 needs to be interrupted and the contact probe 102 and the measuring table 104 need to be inspected.

[0008] In response to this, a technology for automating the inspection when a device is damaged has been proposed (for example, refer to Patent Document 2). According to the technology of Patent Document 2, when a semiconductor chip is damaged, first, the distance between the damage mark formed on the upper electrode of the semiconductor chip and the crimping mark of the contact probe is measured based on the image information of the semiconductor chip. Then, it is determined whether the distance is below a determination reference distance (for example, 0.5 mm), and the contact probe is maintained only when it is below the determination reference distance. As a result, compared with the case where the contact probe is maintained every time a semiconductor chip is damaged, the downtime of the test device can be shortened and the maintenance cost can be reduced.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Publication No. 2013-92534

[0012] Patent Document 2: Japanese Patent Application Publication No. 2010-276477 Summary of the invention

[0013] Technical issues

[0014] However, even when a discharge-blocking snubber circuit is used as a snubber circuit for absorbing surge voltage generated when a semiconductor switch is turned off, damage caused by current that continues to flow after damage cannot be completely suppressed. In addition, in the technology of determining whether maintenance of the contact probe is required by image processing of the semiconductor chip, there is a problem that the system becomes complicated.

[0015] The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor chip testing apparatus and a testing method that minimize the maintenance of contact probes and a measuring table when damage to the semiconductor chip occurs.

[0016] Technical Solution

[0017] In order to solve the above-mentioned problem, in one aspect, the present invention provides a semiconductor chip test device for a screening test of a semiconductor chip of a power device that may cause chip damage. The semiconductor chip test device stops the test device when the applied energy applied to the semiconductor chip that may cause chip damage due to the screening test exceeds a set value.

[0018] In addition, the present invention provides a semiconductor chip testing method for a screening test that may cause chip damage to a semiconductor chip of a power device. The semiconductor chip testing method includes the steps of determining that the semiconductor chip is defective when chip damage occurs in the semiconductor chip due to the screening test, and calculating the applied energy applied to the semiconductor chip; determining whether the value of the applied energy is greater than a set value; and instructing the test device to stop when it is determined that the value of the applied energy is greater than the set value.

[0019] Technical Effects

[0020] The semiconductor chip testing apparatus and testing method having the above-described structure can reduce maintenance after chip damage, thereby having the advantages of shortening the device downtime for maintenance and reducing the manufacturing cost associated with the device downtime. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a diagram illustrating a test device for an inductive load avalanche withstand test according to an embodiment of the present invention.

[0022] Figure 2 This is a block diagram showing a configuration example of a tester.

[0023] Figure 3 The figure shows an example of a handler for conveying semiconductor chips.

[0024] Figure 4 This is a flowchart illustrating the flow of operation of the test device.

[0025] Figure 5 This is a diagram showing the time-dependent changes in the drain-source voltage and drain current of the device under test measured during the test.

[0026] Figure 6 This is a graph showing the relationship between the post-damage energy and the damage to the measuring table and the contact probe.

[0027] Figure 7 1 and 10 are schematic diagrams of a power device, wherein (a) is a plan view showing a main portion of a semiconductor chip, (b) is a cross-sectional view taken along the line AA of (a), and (c) is a diagram showing a main portion of a finished product in which the device under test is assembled.

[0028] Figure 8 This is a diagram showing the temperature change of the device under test with respect to the energy applied for the avalanche test.

[0029] Fig. 9 This is a graph showing the relationship between the device's inherent avalanche withstand capability and temperature.

[0030] Fig.10 This is a diagram for explaining the timing of sampling the temperature sensing voltage of the temperature sensing diode.

[0031] Fig.11 This is a diagram for explaining current correction due to the difference in thermal resistance of applied energy.

[0032] Fig.12 This is a diagram showing a measurement mechanism used in conventional semiconductor chip tests.

[0033] Fig.13 This is a diagram showing a state in which deposits are generated on contact probes due to energy applied to a semiconductor chip after the semiconductor chip is damaged by a test.

[0034] Explanation of symbols

[0035] 1: Device under test; 2: Semiconductor chip; 2a: Semiconductor substrate; 2b: Drain electrode; 2c: Source electrode; 2g: Gate electrode; 2h: Anode electrode; 2i: Cathode electrode; 2j: Protective film; 3: Temperature sensing diode; 5: Insulating substrate; 6: Wiring; 7: Solder; 8: Wire; 11: Gate drive unit; 12: Ammeter; 13: Inductor; 14: Power supply; 15: Capacitor; 16: Voltmeter; 17: Current source; 18: Voltmeter; 19 : Tester; 20: Input unit; 20a: Acquisition unit; 21: Storage unit; 22: Digital converter; 23: Output unit; 24: Display unit; 25: Processor; 26: Transport unit; 27: Measuring unit; 28: Adsorption chuck; 29: Chip tray; 30: Measuring table; 31: Adsorption chuck; 32, 33: Chip tray; 41: Calculation unit; 41a: Damage determination unit; 41b: Energy calculation unit; 41c: Replacement determination unit; 41d: Correction value calculation unit DETAILED DESCRIPTION

[0036] Hereinafter, the embodiment of the present invention will be described in detail with reference to the accompanying drawings, taking the case where the embodiment of the present invention is applied to an inductive load avalanche withstand test as a screening test for semiconductor chips of power devices that may cause chip damage as an example. It should be noted that the parts denoted by the same symbols in the drawings represent the same components.

[0037] Figure 1 FIG. 1 is a diagram illustrating a test device for an inductive load avalanche withstand test according to an embodiment of the present invention. Figure 2 is a block diagram showing an example of the configuration of a tester. Figure 3 The figure shows an example of a handler for conveying semiconductor chips.

[0038] Figure 1 The test device shown is a device for performing an inductive load avalanche withstand test on a power device as a device under test 1. It should be noted that the device under test 1 shown in the figure has a temperature sensing diode 3 for temperature detection built into a semiconductor chip 2 of a MOSFET, and has a gate terminal G, a drain terminal D, a source terminal S, an anode terminal A, and a cathode terminal K.

[0039] In the present embodiment, the temperature sensing diode 3 as the temperature detection element is built into the semiconductor chip 2, but it is not necessary to be built into the semiconductor chip 2. In addition, the temperature detection element may be arranged in a test device instead of the device under test 1.

[0040] Tester 19 Figure 2 As shown, there are a digital converter 22, an ammeter 12, an inductor 13, a power supply 14, a capacitor 15, a voltmeter 16, a current source 17, a voltmeter 18 and a gate drive unit (GDU) 11.

[0041] The gate terminal G of the device under test 1 is connected to the output terminal of the gate driving unit 11, and the low potential terminal of the gate driving unit 11 is connected to the source terminal S of the device under test 1. The drain terminal D of the device under test 1 is connected to the negative terminal of the ammeter 12, the positive terminal of the ammeter 12 is connected to one terminal of the inductor 13 as an inductive load, and the other terminal of the inductor 13 is connected to the positive terminal of the variable voltage power supply 14 and the positive terminal of the capacitor 15. In addition, the drain terminal D of the device under test 1 is connected to the positive terminal of the voltmeter 16, and the negative terminal of the voltmeter 16 is connected to the source terminal S of the device under test 1. The anode terminal A of the device under test 1 is connected to the output terminal of the current source 17 and the positive terminal of the voltmeter 18, and the other terminal of the current source 17 and the negative terminal of the voltmeter 18 are connected to the cathode terminal K of the device under test 1.

[0042] The ammeter 12 measures the drain current Id of the device under test 1, and the measurement result is transmitted to the digital converter 22. The voltmeter 16 measures the drain-source voltage Vds of the device under test 1, and the measurement result is transmitted to the digital converter 22. The voltmeter 18 measures the forward voltage of the temperature sensing diode 3 driven by the current source 17, that is, the temperature sensing voltage VF, and the measurement result is transmitted to the digital converter 22. The temperature sensing diode 3 has a temperature coefficient, and the measured temperature sensing voltage VF becomes the temperature information of the device under test 1.

[0043] It should be noted that in this test apparatus, the electrical connection between the drain terminal D of the device under test 1 and the ammeter 12 is made through the test table. In addition, the electrical connection between the gate terminal G of the device under test 1 and the gate drive unit 11, the electrical connection between the source terminal S of the device under test 1 and the power supply 14, and the electrical connection between the anode terminal A and the cathode terminal K of the device under test 1 and the current source 17 and the voltmeter 18 are respectively made by contact probes. Fig.12 Likewise, the contact probes are held by the contact blocks.

[0044] The digital converter 22 is as follows Figure 2 As shown, the apparatus includes an input unit 20, a storage unit 21, a computing unit 41, an output unit 23, and a display unit 24. The input unit 20 includes an acquisition unit 20a, and the computing unit 41 includes a damage determination unit 41a, an energy calculation unit 41b, a replacement determination unit 41c, and a correction value calculation unit 41d. The correction value calculation unit 41d is provided as needed. In the case where the correction value calculation unit 41d is not provided, when the correction value is used, the correction value calculated outside the apparatus is input from the input unit 20 and stored in the storage unit 21.

[0045] In the input unit 20, the acquisition unit 20a acquires the current value (drain current Id) from the ammeter 12, the voltage value (drain-source voltage Vds) from the voltmeter 16, and the voltage value (temperature sensing voltage VF of the temperature sensing diode 3) from the voltmeter 18. In addition, the avalanche energy and thermal resistance Rth obtained by preliminarily analyzing the finished product in which the device under test 1 is assembled are input to the acquisition unit 20a of the input unit 20. In the case where the correction value calculation unit 41d is not provided, it does not need to be input.

[0046] The storage unit 21 stores each measured value, a set value used in the replacement necessity determination unit 22 c , and, if necessary, a temperature and avalanche energy acquired in advance for calculating a correction value due to a difference in thermal resistance.

[0047] The damage determination unit 41a of the calculation unit 41 determines that the device under test 1 is damaged when the acquired current value (drain current Id) changes suddenly. The energy calculation unit 41b calculates the energy applied to the device under test 1 after the test is completed when it is determined to be damaged. The replacement determination unit 41c determines whether the energy calculated by the energy calculation unit 41b is a set value that requires replacement of the measurement table and the contact probe. The correction value calculation unit 41d calculates the correction value that is circulated in the device under test 1 in order to make the conditions of the measurement system consistent with the conditions of the finished product.

[0048] The output unit 23 is connected to the processor 25, and instructs the sorting of the device under test 1 or outputs the end of measurement according to the determination result of the damage determination unit 41a. The output unit 23 also corrects the current value or voltage value applied to the device under test 1 by the gate drive unit 11 or the power supply 14 according to the calculation result of the correction value calculation unit 41d. The display unit 24 displays the operating status of the digital converter 22 including the alarm notification when the damage of the device under test 1 occurs.

[0049] Processor 25 Figure 3 As shown, the conveying unit 26 and the measuring unit 27 are provided. In the conveying unit 26, the suction chuck 28 takes out the device under test 1 stored in the chip tray 29 and conveys it to the measuring table 30 of the measuring unit 27. The conveying unit 26 also picks up the device under test 1 after the measurement by the suction chuck 31, and conveys the device under test 1 to the chip tray 32 for good products or the chip tray 33 for defective products according to the measurement result.

[0050] Next, use Figure 1 The test apparatus shown in the figure will be used to explain the procedure of performing the inductive load avalanche withstand test of the device under test 1.

[0051] Figure 4 is a flow chart illustrating the working flow of the test device. Figure 5 is a graph showing the time-dependent changes in the drain-source voltage and drain current of the device under test measured during the test. Figure 6 This is a graph showing the relationship between the post-damage energy and the damage to the measuring table and the contact probe.

[0052] First, for the inductive load avalanche withstand test of the device under test 1 , the device under test 1 is transferred from the chip tray 29 to the measuring table 30 of the measuring section 27 in the handler 25 (step S1 ), and a contact probe is brought into contact with the device under test 1 (step S2 ).

[0053] Next, the voltage of the power supply 14 is increased to a predetermined voltage, and the voltage is applied to the device under test 1 (step S3). Figure 5As shown, a drain-source voltage Vds is applied to the drain terminal D and the source terminal S of the device under test 1 , and the drain current Id is 0 ampere (A) because the device under test 1 is turned off.

[0054] Next, a pulse signal is outputted by the gate driving unit 11 and applied to the gate terminal G of the device under test 1, thereby starting the switching of the device under test 1 (step S4). If the device under test 1 is turned on, the drain-source voltage Vds decreases to a value close to 0 volts (V), and the drain current Id gradually increases due to the inductor 13. At this time, energy is accumulated in the inductor 13. Then, if the device under test 1 is turned off, the energy accumulated in the inductor 13 suddenly flows into the drain and source of the device under test 1, so the drain-source voltage Vds jumps up and the drain current Id gradually decreases.

[0055] Then, the drain current Id measured by the ammeter 12 and the drain-source voltage Vds measured by the voltmeter 16 are acquired by the digital converter 22 and stored in the storage unit 21 (step S5 ).

[0056] Next, the damage determination unit 41a of the calculation unit 41 analyzes the waveform of the drain current Id sampled after the device under test 1 is turned off, and determines whether the device under test 1 is damaged (step S6). The damage determination unit 41a determines that the inductive load avalanche withstand test of the device under test 1 is qualified when the drain current Id gradually decreases to 0A after the device under test 1 is turned off. Figure 5 When the voltage increases sharply as shown, the damage determination unit 41a determines that the device under test 1 is damaged.

[0057] Next, it is determined whether the device under test 1 is defective as a result of the determination by the damage determination unit 41a (step S7). The device under test 1 determined to be damaged by the damage determination unit 41a is defective. If the device under test 1 is defective, the process proceeds to step S8, and if the device under test 1 is not defective, the process proceeds to step S12.

[0058] If the device under test 1 is determined to be defective, the energy calculation unit 41b of the operation unit 41 performs energy analysis after the failure (step S8). Figure 5 As shown, the calculation is performed from after damage (hereinafter also referred to as the time point when the drain current Id increases instantaneously) to when the drain current Id drops to almost 0 A in a vibration-like manner, and the applied energy after damage is calculated by the time integral of the product of the drain-source voltage Vds and the drain current Id. Although it is desirable that the start time point of calculating the applied energy is after damage, it may be started from the time point when the pulse signal starts to be applied to the gate terminal G of the semiconductor chip 2 instead of after damage.

[0059] Next, the replacement necessity determination unit 41c of the calculation unit 41 determines whether the energy applied to the device under test 1 after the damage of the device under test 1 is greater than the set value (step S9). Here, the set value is based on the relationship between the post-damage energy and the device damage (damage mark depth and damage mark width) in the measurement system used. Figure 6 The energy after damage is determined by the certain relationship shown in FIG. That is, the relationship between the energy after damage and the device damage is analyzed in advance, and the energy after damage when the device damage begins to occur is set as the set value. Therefore, if the energy after damage is above the set value, it is determined that there is damage to the measuring table 30 and the contact probe caused by the damage of the device under test 1, and the processing enters step S10. In addition, if the energy after damage is less than the set value, even if the device under test 1 is damaged, it is determined that there is no damage to the measuring table 30 and the contact probe caused by this, and the processing enters step S12.

[0060] It should be noted that, in fact, in most cases, the post-damage energies when the measuring table 30 and the contact probe are damaged due to damage to the measured device 1 are different. Generally speaking, the set value for determining whether the contact probe needs to be replaced is smaller than the set value for determining whether the measuring table 30 needs to be replaced. Therefore, a first set value for the contact probe and a second set value for the measuring table 30 are prepared, and when the calculated post-damage energy is greater than the first set value and less than the second set value, it can be instructed to replace only the contact probe. In addition, when the calculated post-damage energy becomes greater than the second set value, it can be instructed to replace the measuring table 30 and the contact probe. Rarely, depending on the type of damage, there are also cases where only the measuring table 30 can be replaced.

[0061] Next, when the digitizer 22 determines that the measuring table 30 and the contact probes are damaged due to the damage of the device under test 1, the processor 25 is instructed to transport the damaged device under test 1 to the chip tray 33 for defective products (step S10). In this example, the chip tray 33 for defective products is used, but the chip tray may not be used.

[0062] Next, the digitizer 22 issues an apparatus alarm notification and instructs the processor 25 to replace the measuring table 30 and the contact probe (step S11 ), and then the process returns to step S1 .

[0063] When it is determined in step S7 that the device under test 1 is not defective, or when it is determined in step S9 that the energy applied to the device under test 1 is not greater than the set value, the device under test 1 after the test is completed is transported to the chip tray 32 or 33 (step S12), and then the process returns to step S1.

[0064] The test apparatus determines whether the measuring table 30 and the contact probes need to be replaced based on the amount of energy applied after the damage to the device under test 1. Therefore, when the damage to the device is small, the maintenance man-hours can be reduced, thereby increasing the throughput of chip manufacturing and reducing the manufacturing cost.

[0065] Next, in the screening test that may cause damage to the device under test 1, a test adapted to the actual use of the device under test 1 is discussed. That is, when the device under test 1 is tested in a chip state and when the device under test 1 is tested in an assembled finished product state, the test results may be different even if the tests are performed under the same temperature conditions.

[0066] Figure 7 The schematic diagram of the power device, wherein (a) is a top view showing the main part of the semiconductor chip, (b) is a cross-sectional view taken along the line AA of (a), and (c) is a diagram showing the main part of the finished product in which the device to be measured is assembled.

[0067] like Figure 7 (a) and Figure 7 As shown in (b), the semiconductor chip 2 has a drain electrode 2b on one side of the semiconductor substrate 2a and a source electrode 2c on the other side. In addition, a gate electrode 2g, an anode electrode 2h, and a cathode electrode 2i are arranged on the other side. The temperature sensing diode 3 is arranged under the protective film 2j and in an insulating film (not shown) on the semiconductor substrate 2a. Figure 7 As shown in (c), the finished product is a wiring 6 provided on an insulating substrate 5 and electrically connected to the drain electrode 2b of the semiconductor chip 2 by a solder 7. The source electrode 2c of the semiconductor chip 2 and the like are bonded to the wire 8 by wire bonding. In consideration of the bondability with the solder 7, the drain electrode 2b of the semiconductor chip 2 can be configured with a stacked layer of a layer containing Ni as a main component and an Au layer on the outermost surface. The source electrode 2c of the semiconductor chip 2 can be configured with a layer containing Al as a main component on the outermost surface. In addition, the same layer as the drain electrode 2b can also be configured on the outermost surface. In the case where a stacked layer of a layer containing Ni as a main component and an Au layer is configured on the outermost surface of the source electrode 2c, the source electrode 2c can also be electrically connected to a lead frame and the like by solder.

[0068] Figure 8 is a diagram showing the temperature change of the device under test with respect to the energy applied for the avalanche test. Fig. 9 This is a graph showing the relationship between the device's inherent avalanche withstand capability and temperature.

[0069] According to the Figure 8, indicating that the temperature of the device under test 1 during the avalanche test is lower in the state of the finished product in which the device under test 1 is assembled than in the state of the chip. This is probably because, in the state of the chip, the contact resistance between the device under test 1 and the test table 30 and the contact probe is large, the heat dissipation through the test table 30 and the contact probe is poor, and the thermal resistance is large. On the other hand, in the state of the finished product in which the device under test 1 is assembled, the electrical connection between the device under test 1 and the bonding wire and the printed circuit board is mainly performed through solder, so the contact resistance is small, the heat dissipation is good, and therefore the thermal resistance is small.

[0070] In addition, the device under test 1 is Fig. 9 As shown in FIG. 1 , the avalanche withstand capacity increases as the temperature is low, and tends to decrease as the temperature increases. This indicates that in an avalanche test, if the temperature of the device under test 1 changes, the avalanche withstand capacity also changes.

[0071] Thus, since the avalanche withstand test in the chip state is also affected by thermal resistance, if the heat dissipation characteristics change due to the material of the test table 30, the design of the adsorption holes, the material, layout and / or load of the contact probe on the upper surface, the target energy amount of the finished product will deviate. Figure 8 As shown in FIG. 1 , although the measurement condition aims to apply an energy of 1.0 J, the temperature rise in the chip state is actually large, and the test is performed under conditions corresponding to applying an energy of more than 1.0 J. However, the avalanche withstand capacity against temperature rise depends on the device of the device under test 1, so it is necessary to optimize the conditions corresponding to the thermal resistance of the measurement system.

[0072] Therefore, in this test apparatus, in order to measure the temperature of the device under test in the measuring section, a current source 17 and a voltmeter 18 are provided. Thus, the thermal resistance of the semiconductor chip 2 in the avalanche withstand test can be obtained.

[0073] A specific method for calculating the thermal resistance will be described below.

[0074] First, using the device under test 1 assembled into a finished product, the following analysis is performed in advance: Fig. 9 The temperature dependence of the avalanche resistance corresponding to the device is shown. Based on the target avalanche resistance of the finished product obtained thereby, an avalanche resistance test is performed on a plurality of devices under test 1, the temperature of the device under test 1 at that time and the avalanche energy applied are obtained, and the thermal resistance is calculated.

[0075] Next, with regard to the thermal resistance based on the measurement system, an avalanche withstand test is performed on multiple devices 1 under test in a chip state based on an applied voltage and pulse signal that are the same as the avalanche energy applied through the avalanche withstand test of the finished product, and the drain current Id measured by the ammeter 12, the drain-source voltage Vds measured by the voltmeter 16, and the temperature sensing voltage VF of the temperature sensing diode 3 measured by the voltmeter 18 are obtained, and the thermal resistance is calculated based on the temperature and the applied avalanche energy.

[0076] Fig.10 is a diagram illustrating the timing of sampling the temperature sensing voltage of the temperature sensing diode, Fig.11 This is a diagram for explaining current correction due to the difference in thermal resistance of applied energy.

[0077] In order to find the thermal resistance based on the measurement system, Fig.10 As shown, first, the temperature sensing voltage VF1[V] before the avalanche test and the temperature sensing voltage VF2[V] after the avalanche test are obtained, and their difference is calculated. Next, while obtaining the temperature sensing voltage VF2[V], the product of the drain-source voltage Vds[V] and the drain current Id[A] is taken as P[W] to calculate the thermal resistance Rth[℃ / W]=(VF1-VF2) / P.

[0078] Next, calculation of the correction value for optimal adjustment of the conditions corresponding to the thermal resistance of the measurement system will be described. The relationship between the avalanche withstand capability and the thermal resistance of the device under test 1 is as follows: Fig.11 The relationship shown by the dotted line in the middle can set the avalanche tolerance to be larger as the thermal resistance Rth is smaller. Here, because the avalanche tolerance and thermal resistance of the finished product are measured in advance, the avalanche tolerance under the same temperature conditions as the finished product can be known. From the relationship between the avalanche tolerance and thermal resistance of the device under test 1 at this time, the avalanche tolerance equivalent to the previously calculated thermal resistance is obtained as the chip condition, and the correction value for the test condition of the measurement system based on the chip state is obtained in a manner equivalent to the avalanche tolerance at that time. The correction value can be stored in the storage unit 21, for example. The correction value can be a current value or a voltage value.

[0079] The calculation of the correction value can be performed by the correction value calculation unit 41d. In this case, for example, the applied avalanche energy and thermal resistance derived from the target avalanche tolerance of the finished product are input to the digital converter 22. As the avalanche energy, the test conditions of the voltage and pulse signal width applied to the device under test 1 can also be set. In addition, the thermal resistance of the chip state is calculated as described above, and the correction value is calculated by the correction value calculation unit 41d. In the case where the correction value is a current value, it is transmitted to the gate drive unit 11 to shorten the width of the pulse signal. In the case where the correction value is a voltage value, it is transmitted to the power supply 14, and the power supply 14 reduces the voltage applied between the drain and the source. Therefore, since the device under test 1 is subjected to an avalanche test under chip conditions with a low correction value corresponding to the target value of the finished product, no excessive energy is applied.

[0080] It should be noted that when the correction value calculation unit 41d is not set, the applied avalanche energy of the finished product is input into the digital converter 22, the thermal resistance in the measuring system is calculated and output, the correction value is calculated based on the thermal resistance of the finished product and the thermal resistance of the measuring system, and the correction value or the applied avalanche energy in the measuring system is input into the digital converter 22.

[0081] Thus, since the energy applied when performing the test under the same temperature conditions as the state of the finished product in which the device under test 1 is assembled can be reduced, excessive energy can be avoided as a screening test, and the occurrence rate of defective products can be reduced accordingly.

[0082] In addition, in this embodiment, the case where the singulated semiconductor chips are used as the devices to be measured 1 is described. However, the screening test of the semiconductor chips may be performed in the state of the semiconductor wafer before singulation.

Claims

1. A semiconductor chip testing device, characterized in that: In a test apparatus for screening a semiconductor chip of a power device that may cause chip damage, the following is provided: a damage determination unit configured to determine whether the chip damage occurs in the semiconductor chip due to the screening test; an energy calculation unit that receives the information that the chip is determined to be damaged by the damage determination unit and calculates the applied energy applied to the semiconductor chip; a determination unit configured to determine whether the value of the applied energy calculated by the energy calculation unit is greater than a set value; as well as A correction value calculation unit calculates a correction value of the avalanche energy in the measuring system that is corrected to be equivalent to the avalanche energy of the finished product based on the thermal resistance of the finished product in which the semiconductor chip is assembled in an avalanche withstand test and the thermal resistance of the measuring system when the semiconductor chip is tested in the test device with the avalanche energy in the avalanche withstand test of the finished product.

2. The semiconductor chip testing device according to claim 1, characterized in that: The test apparatus further includes a stop instructing unit for instructing the test apparatus to stop in order to replace a contact probe electrically contacting the semiconductor chip when the value of the applied energy is equal to or greater than the set value.

3. The semiconductor chip testing device according to claim 1, characterized in that: The test apparatus further includes a stop instructing unit for instructing the test apparatus to stop in order to replace a measuring table that is in electrical contact with the semiconductor chip when the value of the applied energy is equal to or greater than the set value.

4. The semiconductor chip testing device according to claim 1, characterized in that: The energy calculation unit calculates the value of the applied energy based on a time integral of a product of a voltage and a current applied to the semiconductor chip.

5. The semiconductor chip testing device according to any one of claims 1 to 4, characterized in that: The calculation of the applied energy is to calculate the post-damage applied energy applied to the semiconductor chip from the time when the chip damage occurs.

6. The semiconductor chip testing device according to claim 5, characterized in that: The set value is a value determined based on a previously analyzed relationship between damage to the semiconductor chip and the amount of energy applied after damage.

7. The semiconductor chip testing device according to claim 1, characterized in that: A handler is provided for conveying the semiconductor chips to a measuring section during the screening test and conveying the semiconductor chips of the measuring section to a good product tray according to a determination result of the damage determination section after the screening test is completed.

8. A method for testing a semiconductor chip, characterized in that: In a test method for semiconductor chips used for screening tests that may cause chip damage to semiconductor chips of power devices, including: When the semiconductor chip is damaged due to the screening test, the semiconductor chip is judged as defective and an applied energy to the semiconductor chip is calculated; A step of determining whether the value of the applied energy is above a set value; When it is determined that the value of the applied energy is greater than the set value, instructing the test device to stop; and The step of calculating a correction value of the avalanche energy in the measuring system that is corrected to be equivalent to the avalanche energy of the finished product based on the thermal resistance of the finished product in the avalanche withstand test of the finished product in which the semiconductor chip is assembled and the thermal resistance in the measuring system when the semiconductor chip is tested in the testing device with the avalanche energy in the avalanche withstand test of the finished product.

9. The semiconductor chip testing method according to claim 8, characterized in that: The method also includes the steps of replacing the contact probe and restarting the test after the test device stops.

10. The semiconductor chip testing method according to claim 8, characterized in that: The method further includes the steps of replacing the measuring table and restarting the test after the test device stops.

11. The semiconductor chip testing method according to any one of claims 8 to 10, characterized in that: The applied energy is calculated based on the time integral of the product of the voltage and the current applied to the semiconductor chip.

12. The semiconductor chip testing method according to claim 8, characterized in that: The calculation of the applied energy is to calculate the post-damage applied energy applied to the semiconductor chip from the time when the chip damage occurs.

13. The semiconductor chip testing method according to claim 12, characterized in that: The set value is a value determined based on a previously analyzed relationship between damage to the semiconductor chip and the amount of energy applied after damage.

14. A method for testing a semiconductor chip, characterized in that: In a test method for semiconductor chips used for screening tests that may cause chip damage to semiconductor chips of power devices, including: When the semiconductor chip is damaged due to the screening test, the semiconductor chip is judged as defective and an applied energy to the semiconductor chip is calculated; A step of determining whether the value of the applied energy is above a set value; When it is determined that the value of the applied energy is greater than the set value, instructing the test device to stop; and A step of calculating the avalanche energy in the measuring system equivalent to the avalanche energy of the finished product based on the thermal resistance of the finished product in which the semiconductor chip is assembled in an avalanche withstand test and the thermal resistance in the measuring system when the semiconductor chip is tested in the test device with the avalanche energy in the avalanche withstand test of the finished product.

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