Network topology design method and device, electronic equipment and storage medium

Abstract

A network topology design method and device of an integrated circuit, an electronic device, and a computer readable storage medium. The network topology design method of the integrated circuit comprises: obtaining at least one network structure model, each network structure model being generated by packaging a network structure of a preset area, the network structure of the preset area being part of the integrated circuit, and each network structure model comprising a plurality of attributes; performing at least one assignment on the plurality of attributes in each network structure model to obtain a plurality of instantiated models; splicing the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit; and converting the overall network model into a simulation netlist of the integrated circuit, the simulation netlist comprising a plurality of physical devices. The method can improve the efficiency of verifying a complex topology of a single logical network, shorten the verification period, and is suitable for fast iteration verification.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a network topology design method, apparatus, electronic device and computer readable storage medium of an integrated circuit. BACKGROUND

[0002] After the chip manufacturing process enters the deep sub-micron level, the design target is continuously improved under the premise of low delay characteristics brought by advanced processes, such as gradually increasing the clock frequency. Therefore, the physical design has also made many improvements to achieve the design target. For example, low delay is achieved by using a complex topology of a single logic (e.g., a mesh network topology). SUMMARY

[0003] At least one embodiment of the present disclosure provides a network topology design method of an integrated circuit, comprising: obtaining at least one network structure model, each network structure model being generated for a network structure package of a preset region, the network structure of the preset region being part of the integrated circuit, each network structure model comprising a plurality of attributes; performing at least one assignment on the plurality of attributes in each network structure model to obtain a plurality of instantiated models; splicing the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit; and converting the overall network model into a simulation netlist of the integrated circuit, the simulation netlist comprising a plurality of physical devices.

[0004] For example, in the network topology design method provided by an embodiment of the present disclosure, obtaining at least one network structure model comprises: obtaining electrical characteristics required by the integrated circuit; and determining at least one network structure model according to the electrical characteristics.

[0005] For example, in the network topology design method provided by an embodiment of the present disclosure, each network structure model comprises: a module vertex sub-model and a boundary routing sub-model, the module vertex sub-model indicating attributes of feature points of the preset region, and the boundary routing sub-model indicating attributes of routing used to connect the plurality of feature points.

[0006] For example, in the network topology design method provided by an embodiment of the present disclosure, the attributes of the feature points comprise: feature point identifiers and coordinate information; and the attributes of the routing comprise: routing identifiers, start points and end points.

[0007] For example, in the network topology design method provided by an embodiment of the present disclosure, splicing the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit comprises: splicing the plurality of instantiated models according to the coordinate information of the feature points to obtain an overall network model corresponding to the integrated circuit.

[0008] For example, in the network topology structure design method provided by an embodiment of the present disclosure, for two adjacent instantiation models, there is at least one overlapping edge after the two instantiation models are spliced, and there is no gap region in the overall network model.

[0009] For example, in the network topology structure design method provided by an embodiment of the present disclosure, converting the overall network model into a simulation netlist of the integrated circuit includes: for each instantiation model in the plurality of instantiation models, obtaining an attribute value of a target attribute in the plurality of attributes in the each instantiation model; determining a physical characteristic associated with the target attribute; determining a physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and for each instantiation model in the overall network model, representing the corresponding instantiation model with the physical device to obtain the simulation netlist of the integrated circuit.

[0010] For example, in the network topology structure design method provided by an embodiment of the present disclosure, the target attribute includes a wire length, the physical characteristic associated with the wire length includes a resistance value of the wire in a unit length, and determining the physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute includes: determining a target resistance based on the wire length and the resistance value of the wire in the unit length.

[0011] For example, in the network topology structure design method provided by an embodiment of the present disclosure, each network structure model includes: a clock network structure model or a power supply network structure model, the clock network structure model includes a clock network topology structure, and the power supply network structure model includes a power supply network topology structure.

[0012] For example, in the network topology structure design method provided by an embodiment of the present disclosure, further including: verifying, by using the simulation netlist, whether the network topology structure of the integrated circuit meets the evaluation index.

[0013] An embodiment of the present disclosure provides a network topology structure design apparatus of an integrated circuit, including: an obtaining unit configured to obtain at least one network structure model, each network structure model being generated by packaging a network structure of a preset region, the network structure of the preset region being a part of the integrated circuit, and each network structure model including a plurality of attributes; an instantiation unit configured to perform at least one assignment on the plurality of attributes in each network structure model to obtain a plurality of instantiation models; a splicing unit configured to splice the plurality of instantiation models to obtain an overall network model corresponding to the integrated circuit; and a netlist generation unit configured to convert the overall network model into a simulation netlist of the integrated circuit, the simulation netlist including a plurality of physical devices.

[0014] For example, in the network topology structure design apparatus provided by an embodiment of the present disclosure, the obtaining unit comprises: an electrical characteristic obtaining subunit configured to obtain electrical characteristics required by the integrated circuit; and a model determining subunit configured to determine at least one network structure model according to the electrical characteristics.

[0015] For example, in the network topology structure design apparatus provided by an embodiment of the present disclosure, each network structure model comprises: a module vertex submodel and a boundary routing submodel, the module vertex submodel indicating attributes of feature points of a preset region, and the boundary routing submodel indicating attributes of routing used to connect the feature points.

[0016] For example, in the network topology structure design apparatus provided by an embodiment of the present disclosure, the attributes of the feature points comprise: feature point identifiers and coordinate information, and the attributes of the routing comprise: routing identifiers, start points and end points.

[0017] For example, in the network topology structure design apparatus provided by an embodiment of the present disclosure, the splicing unit comprises a splicing subunit configured to splice the plurality of instantiated models according to the coordinate information of the feature points to obtain the overall network model corresponding to the integrated circuit.

[0018] For example, in the network topology structure design apparatus provided by an embodiment of the present disclosure, for two adjacent instantiated models, there is at least one overlapping edge after the two instantiated models are spliced, and there is no gap region in the overall network model.

[0019] For example, in the network topology structure design apparatus provided by an embodiment of the present disclosure, the netlist generating unit comprises: an attribute value obtaining subunit configured to obtain, for each of the plurality of instantiated models, an attribute value of a target attribute in a plurality of attributes in each instantiated model; a physical characteristic determining subunit configured to determine a physical characteristic associated with the target attribute; a physical device determining subunit configured to determine a physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and a simulation netlist generating subunit configured to represent, for each instantiated model in the overall network model, the corresponding instantiated model with the physical device to obtain a simulation netlist of the integrated circuit.

[0020] For example, in the network topology structure design apparatus provided by an embodiment of the present disclosure, the target attribute comprises a routing length, the physical characteristic associated with the routing length comprises a resistance value of the routing per unit length, and the physical device determining subunit comprises a resistance determining subunit configured to determine a target resistance based on the routing length and the resistance value of the routing per unit length.

[0021] For example, in the network topology design apparatus provided by an embodiment of the present disclosure, each network structure model comprises a clock network structure model or a power supply network structure model, the clock network structure model comprises a clock network topology structure, and the power supply network structure model comprises a power supply network topology structure.

[0022] For example, in the network topology design apparatus provided by an embodiment of the present disclosure, the apparatus further comprises a simulation unit configured to verify whether the network topology structure of the integrated circuit meets the evaluation index by using a simulation netlist.

[0023] For example, in some embodiments of the present disclosure, the apparatus further comprises an adjustment unit configured to re-adjust at least one network structure model in response to the network topology structure of the integrated circuit not meeting the evaluation index.

[0024] An electronic device is provided in at least one embodiment of the present disclosure, comprising a processor, a memory comprising one or more computer program modules, and one or more computer program modules stored in the memory and configured to be executed by the processor, wherein the one or more computer program modules comprise instructions for implementing the network topology design method of the integrated circuit provided by any embodiment of the present disclosure.

[0025] A computer readable storage medium is provided in at least one embodiment of the present disclosure, for storing non-transitory computer readable instructions, which, when executed by a computer, can implement the network topology design method of the integrated circuit provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0027] Figure 1 A flowchart of a network topology design method of an integrated circuit provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 2A A schematic diagram of a network structure model 200 provided by at least one embodiment of the present disclosure is shown.

[0029] Figure 2B A model structure 210 of the network structure model 200 provided by at least one embodiment of the present disclosure is shown.

[0030] Figure 2C A mapping relationship between the model structure 210 and a layout 220 provided by at least one embodiment of the present disclosure is shown.

[0031] Figure 3AThe schematic diagram of the integrated circuit provided by at least one embodiment of the present disclosure is shown. Figure 1 The method flowchart of step S10 in the embodiment is shown.

[0032] Figure 3B The schematic diagram of at least one network structure model of the integrated circuit provided by at least one embodiment of the present disclosure is shown.

[0033] Figure 3C The schematic diagram of the integrated circuit provided by at least one embodiment of the present disclosure is shown. Figure 3B The instantiation model of the network structure model A and the network structure model B is shown.

[0034] Figure 3D The schematic diagram of the integrated circuit provided by at least one embodiment of the present disclosure is shown. Figure 3C The schematic diagram of the integrated circuit provided by at least one embodiment of the present disclosure is shown.

[0035] Figure 4 The method flowchart of step S40 in the embodiment is shown.

[0036] Figure 5 The schematic diagram of the simulation netlist 500 obtained by representing one instantiation model with physical devices is shown.

[0037] Figure 6 The flowchart of another network topology design method provided by at least one embodiment of the present disclosure is shown.

[0038] Figure 7 The schematic block diagram of the network topology design apparatus of an integrated circuit provided by at least one embodiment of the present disclosure is shown.

[0039] Figure 8A The schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0040] Figure 8B The schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure is shown.

[0041] Figure 9 The schematic diagram of a computer readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0042] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative work belong to the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0044] Currently, for complex topologies of a single logical network, a complete verification process requires the use of multiple electronic design automation (EDA) tools, resulting in long verification cycles. Furthermore, each EDA tool has high detail requirements, necessitating the actual placement and accurate connection of units within the network topology. This approach is unsuitable for rapid verification iterations and cannot efficiently manage complex topologies.

[0045] Therefore, at least one embodiment of this disclosure provides a network topology design method, a network topology design apparatus, an electronic device, and a computer-readable storage medium for integrated circuits. The network topology design method for integrated circuits includes: obtaining at least one network structure model, each network structure model being generated by encapsulating the network structure of a preset region, the network structure of the preset region being part of the integrated circuit, and each network structure model including multiple attributes; assigning values ​​to the multiple attributes in each network structure model at least once to obtain multiple instantiated models; concatenating the multiple instantiated models to obtain an overall network model corresponding to the integrated circuit; and converting the overall network model into a simulation netlist of the integrated circuit, the simulation netlist including multiple physical devices. This network topology design method for integrated circuits can improve the efficiency of verifying complex topologies of a single logic network, shorten the verification cycle, and is suitable for rapid iteration verification.

[0046] Figure 1 A flowchart is shown of a network topology design method for an integrated circuit provided in at least one embodiment of the present disclosure.

[0047] like Figure 1 As shown, the method may include steps S10 to S40.

[0048] Step S10: obtaining at least one network structure model, each network structure model being generated by encapsulating a network structure of a preset region, the network structure being integrated into a circuit, and each network structure model including a plurality of attributes.

[0049] Step S20: performing at least one assignment to the plurality of attributes in each network structure model to obtain a plurality of instantiated models.

[0050] Step S30: splicing the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit.

[0051] Step S40: converting the overall network model into a simulation netlist of the integrated circuit, the simulation netlist including a plurality of physical devices.

[0052] In some embodiments of the present disclosure, the plurality of instantiated models are spliced to obtain an overall network model of the integrated circuit, and a simulation netlist is generated using the overall network model to verify the network topology using the simulation netlist. Since the overall network model is obtained by splicing the plurality of instantiated models, when the verification result of the verification does not meet the evaluation index of the integrated circuit, only one or more instantiated models need to be modified or the network structure model corresponding to the instantiated model needs to be modified, without the need to redesign the integrated circuit, without the need to actually place and accurately connect the units in each network topology, so that the method is easy to quickly adjust the network topology of the integrated circuit, shortens the verification period, and facilitates rapid iteration. The method can be applied, for example, to the early trial design stage of chip design.

[0053] For example, for step S10, at least one network structure model can be read from a model library.

[0054] For example, the at least one network structure model is designed by a designer according to the index requirements of the integrated circuit and is stored in the model library. For example, when the method is used to design a clock network topology, the at least one network structure model can be designed according to the clock index requirements of the integrated circuit.

[0055] For example, the at least one network structure model can also be generated according to input instructions or input operations of the designer. The input instructions or input operations include parameters such as the size, area, etc. of the network structure model.

[0056] In some embodiments of the present disclosure, each network structure model can include a boundary routing sub-model and a module vertex sub-model, the module vertex sub-model indicating the attributes of feature points of the preset region, and the boundary routing sub-model indicating the attributes of routing used to connect the plurality of feature points.

[0057] Figure 2AA schematic diagram of the network structure model 200 is shown.

[0058] Figure 2B A model structure 210 of the network structure model 200 is shown.

[0059] In some embodiments of the present disclosure, the network structure model 200 is encapsulated from the model structure 210 to facilitate the stitching operation in the subsequent step S30.

[0060] In some embodiments of the present disclosure, the model structure 210 can represent a layout of the preset region. For example, the model structure 210 is obtained by mapping the layout of the preset region. For example, a metal line in the layout is mapped as a straight line, and two metal nodes connected by the metal line are mapped as a circle. The metal node is, for example, used to connect different physical devices in an integrated circuit, for example, the metal node can be a via, used to connect physical devices located at different layers, etc. The mapping relationship between the model structure 210 and the layout of the preset region will be described below in conjunction with Figure 2C The mapping relationship between the model structure 210 and the layout of the preset region will be described below in conjunction with

[0061] As shown in Figure 2A , the network structure model 200 can include a module vertex sub-model 206 and a boundary routing sub-model 207, etc. The network structure model 200 can also include a driving unit vertex sub-model 208.

[0062] The module vertex sub-model 206 indicates the attributes of the feature points of the preset region. For example, the feature points of the preset region can be the vertices of the preset region, which are the vertices of the corresponding network structure model 200 of the preset region. For example, the four vertices of the preset region in the form of a rectangle can be the vertices of the network structure model 200.

[0063] The boundary routing sub-model 207 indicates the attributes of the routing for connecting a plurality of feature points, for example, indicates the attributes of the boundary routing of the preset region. For example, the four sides of the preset region in the form of a rectangle can be the boundary routing of the preset region.

[0064] The driving unit vertex sub-model 208 is used to represent the vertices of the driving unit.

[0065] As shown in Figure 2B , in addition to the module vertex sub-model 206, the boundary routing sub-model 207, and the driving unit vertex sub-model 208, the network structure model 200 can also include a driving unit sub-model 201, a load unit sub-model 202, a routing sub-model 203, and a node sub-model 204. Although the driving unit sub-model 201, the load unit sub-model 202, the routing sub-model 203, and the node sub-model 204 are not shown in the network structure model 200 of Figure 2A , sinceFigure 2A Network structure model 200 is based on the network structure model 200. Figure 2B The model structure 200 is obtained by encapsulating the model structure 210. Therefore, the network structure model 200 naturally includes the driving unit sub-model 201, the load unit sub-model 202, the winding sub-model 203, and the node sub-model 204.

[0066] For example, driver cell sub-model 201 represents a driver cell in a preset region of an integrated circuit. Driver cell sub-model 201 may include driver attributes, such as driver power consumption and driver size. Designers may set the driver attributes of driver cell sub-model 201 or not.

[0067] For example, load cell sub-model 202 represents a load in a preset area of ​​an integrated circuit. Load cell sub-model 202 may include load attributes, such as the electrical characteristics of the load. Designers may set the load attributes of load cell sub-model 202, or they may choose not to set the load attributes of load cell sub-model 202.

[0068] For example, node sub-model 204 represents a node in a predetermined region of an integrated circuit, such as a metal node. Nodes are used to connect different devices in an integrated circuit.

[0069] For example, a node's attributes can include a node identifier and coordinate information. The node identifier can be, for example, the node's name. The coordinate information can include, for example, the node's coordinates in a two-dimensional or three-dimensional coordinate system. In addition to the node identifier and coordinate information, node attributes can also include, for example, the node's name in the instantiated model, the node type, and custom attributes. The node identifier is used to distinguish different nodes.

[0070] In some embodiments of this disclosure, the attributes of a node can be represented by a set T, for example, set T = {id, locX, locY, node type, grid id, ...}, where id represents the name of the node, locX represents the X-axis coordinate of the node, locY represents the Y-axis coordinate of the node, node type represents the type of the node, and grid id represents the name of the node in the instantiated model after it is instantiated.

[0071] The module vertex sub-model 206 in the network structure model 200 can be a node located at a vertex in a preset region in the node sub-model 204. Therefore, the module vertex sub-model 206 includes feature point identifiers and coordinate information. The feature point identifiers are used to distinguish different vertices in the network structure model 200.

[0072] For example, the winding sub-model 203 represents a winding in a preset region of an integrated circuit, used to connect multiple nodes. The winding sub-model 203 includes attributes of the winding, such as winding identifier, start point, and end point. The winding identifier is used to distinguish different windings in the network structure model 200. In addition to the winding identifier, start point, and end point, the attributes of the winding may also include the winding length, winding type, name in the instantiated model after instantiation, detour mode, and custom attributes. For example, windings can be divided into multiple types according to their function. For example, windings connecting physical devices on the same layer are of type one, windings connecting physical devices on two adjacent layers are of type two, etc. The detour mode can refer to the straightness or curvature of the winding.

[0073] In some embodiments of this disclosure, the attributes of the winding are represented by a set S, for example, S = {from, to, label, net length, net type, grid id, detour mode, user attribute, ...}, where from represents the starting point, to represents the ending point, label represents the name of the winding, net length represents the winding length, net type represents the winding type, gridid ​​represents the name in the instantiated model after instantiation, detour mode represents the detour mode, and user attribute represents a custom attribute.

[0074] In this document, custom attributes refer to the attributes of sub-models defined by designers according to actual needs. In the embodiments of this disclosure, the attributes of each sub-model are not limited to the attributes mentioned above. Compared to the attributes of each sub-model mentioned above, each sub-model in actual applications may contain more or fewer attributes, and designers can set the attributes of each sub-model according to actual needs.

[0075] Figure 2C The mapping relationship between the model structure 210 provided in at least one embodiment of this disclosure and the layout 220 of the preset region is shown.

[0076] like Figure 2C As shown, the load in layout 220 is mapped to the load in model structure 210. For example, Figure 2C The loads 302 located on both sides of the via 301 are mapped to two stacked load cell sub-models 202 in the model structure 210.

[0077] like Figure 2C As shown, the metal node 306, which serves as the vertex of the preset region in layout 220, can be mapped to the module vertex sub-model 206 in model structure 210.

[0078] like Figure 2CAs shown, the metal line 303 in the layout 220 is mapped to the wire sub-model 203 in the model structure 210.

[0079] As shown, the metal node 304 in the layout 220, except for the boundary vertex, can be mapped to the node sub-model 204 in the model structure 210. Figure 2C

[0080] As shown, the drive 305 in the layout 220 can be mapped to the drive cell sub-model 201 in the model structure 210. Figure 2C It should be understood that the mapping relationship shown is only shown for the convenience of understanding the embodiments of the present disclosure, and in actual design, the designer can define the mapping relationship by himself, and is not limited to the embodiments shown.

[0081] In addition, in actual design, the layout 220 can not exist, that is, the designer does not need to design the layout in advance, and the designer only needs to determine the mapping relationship to obtain the network structure model. Figure 2C It is only shown for the convenience of understanding the embodiments of the present disclosure. Figure 2C Figure 2C A method flowchart of step S10 in the method is shown.

[0082] Figure 3A As shown, step S10 can include step S11 and step S12. Figure 1 Step S11: Obtain the electrical characteristics required by the integrated circuit.

[0083] Figure 3A Step S12: Determine at least one network structure model according to the electrical characteristics.

[0084] For step S11, the electrical characteristics may, for example, include capacitance value, resistance value, output waveform, etc.

[0085] In some embodiments of the present disclosure, the electrical characteristics required by the integrated circuit can be realized through the metal grid interconnection of the network topology structure of the integrated circuit. For example, the resistance value of the resistance obtained by the metal grid interconnection.

[0086] For step S12, for example, a plurality of different electrical characteristics required by the integrated circuit are determined, for each electrical characteristic, a network structure is generated, so that the network structure has the electrical characteristic. The network structure is the network structure of the preset region in the integrated circuit, and the network structure is encapsulated to generate a network structure model.

[0087]

[0088]

[0089] Figure 3B ​​​​​A schematic diagram of at least one network structure model of an integrated circuit is shown.

[0090] As shown in Figure 3B , the integrated circuit includes two network structure models, namely network structure model A and network structure model B.

[0091] The network structure model A and the network structure model B have different attributes, for example, the length of the network structure model A and the network structure model B are different.

[0092] It can be understood that the network structure model A and the network structure model B are only schematic representations of at least one network structure model of an integrated circuit, and do not limit the present disclosure. For example, the integrated circuit can have more (3, 4, …) network structure models.

[0093] For step S20: the plurality of attributes in each network structure model can be assigned once or multiple times, or not assigned. Each time the plurality of attributes in the network structure model is assigned, an instantiated model is obtained.

[0094] For example, assigning each attribute in the set T once and assigning each attribute in the set S once obtains an instantiated model.

[0095] In an embodiment of the present disclosure, the number of times of assigning different network structure models can be different.

[0096] Figure 3C A schematic diagram of the instantiated models of the network structure model A and the network structure model B in Figure 3B is shown.

[0097] As shown in Figure 3C , for example, the network structure model A is assigned twice to obtain two instantiated models of the network structure model A, namely instantiated model A1 and instantiated model A2. The network structure model B is assigned four times to obtain four instantiated models of the network structure model B, namely instantiated model B1, instantiated model B2, instantiated model B3 and instantiated model B4.

[0098] For step S30: for example, according to the coordinate information of the feature points, the plurality of instantiated models are spliced to obtain the overall network model corresponding to the integrated circuit. In this embodiment, the coordinate information of the feature points is directly included in the instantiated models, so that the plurality of instantiated models can be directly spliced according to the coordinate information. The splicing method in this embodiment is simple and easy to implement.

[0099] Figure 3D A schematic diagram of the overall network model of the integrated circuit is shown. Figure 3CA schematic diagram of the overall network model obtained by splicing the plurality of instantiated models.

[0100] As shown in Figure 3C and 3D The instantiated model A1 includes the coordinate information of the module vertex sub-models A11, A12, A13 and A14, and the instantiated model A2 includes the coordinate information of the module vertex sub-models A21, A22, A23 and A24. The coordinate information of the vertex A13 and the coordinate information of the vertex A12 are the same as the coordinate information of the vertex A21 and the coordinate information of the vertex A22, respectively. Therefore, in step S30, the vertex A13 and the vertex A21 are overlapped into one point, and the vertex A12 and the vertex A22 are overlapped into one point, so as to splice A1 and A2.

[0101] The splicing method between the instantiated model B1, the instantiated model B2, the instantiated model B3 and the instantiated model B4 and the instantiated model A1 and the instantiated model A2 is similar to the splicing method between the instantiated model A1 and the instantiated model A2, which will not be described here.

[0102] The overall network model shown in Figure 3D is obtained by splicing a plurality of instantiated models. As shown in Figure 3D In some embodiments of the present disclosure, for two adjacent instantiated models, there is at least one overlapping edge after the two instantiated models are spliced, and there is no gap region in the overall network model.

[0103] In some embodiments of the present disclosure, the splicing of the plurality of instantiated models is not limited to planar splicing, but also includes three-dimensional splicing, which can represent the interconnection relationship between different metal layers.

[0104] Figure 4 A method flowchart of step S40 provided by at least one embodiment of the present disclosure is shown.

[0105] As shown in Figure 4 The method can include steps S41-S44.

[0106] Step S41: For each of the plurality of instantiated models, obtain the attribute value of the target attribute in the plurality of attributes in each instantiated model.

[0107] Step S42: Determine the physical characteristic associated with the target attribute.

[0108] Step S43: Determine the physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute.

[0109] Step S44: For each instantiated model in the overall network model, represent the corresponding instantiated model with the physical device to obtain the simulation netlist of the integrated circuit.

[0110] For step S41, the target attribute can be at least one attribute of a plurality of attributes that has an influence on the selection of the physical device in the simulation netlist. For example, a resistance is included in the simulation netlist, and the wire length has an influence on the resistance value in the simulation netlist, and thus the target attribute can include the wire length. For another example, a parasitic capacitance is included in the simulation netlist, and the distance between two loads that generate the parasitic capacitance has an influence on the parasitic capacitance, and thus the target attribute can include the coordinate information of the two loads respectively.

[0111] In some embodiments of the present disclosure, the target attribute can be determined according to the input or selection operation of the user, and thus the attribute value of the target attribute is read from the network structure model. In other embodiments of the present disclosure, the target attribute can be preset.

[0112] For step S42, the physical characteristic associated with the target attribute can be a physical characteristic that acts together with the target attribute to determine the physical device in the simulation netlist.

[0113] For example, the wire length and the resistance value of the wire per unit length determine the resistance value generated by the wire in the integrated circuit, and thus the physical characteristic associated with the wire length includes the resistance value of the wire per unit length.

[0114] For step S43, the physical device is determined according to the calculation relationship between the attribute value of the target attribute, the physical characteristic associated with the target attribute, and the physical parameter of the physical device, for example. For example, the target resistance is determined according to the wire length and the resistance value of the wire per unit length. For another example, the parasitic capacitance is determined according to the dielectric constant of the medium between the two plates, the distance between the two loads, and the facing area of the two loads.

[0115] For step S44, for example, for each instantiated model, the physical device is substituted into the instantiated model to obtain the simulation netlist of the integrated circuit. The physical device can include a resistor-capacitance (RC), a load, a driver, and the like, for example. Figure 3D The overall network model shown in FIG. 5 shows the simulation netlist 500 obtained by substituting the physical device into the instantiated model A1.

[0116] Figure 5 FIG. 5 shows a schematic diagram of the simulation netlist 500 obtained by substituting the physical device into the instantiated model according to at least one embodiment of the present disclosure.

[0117] For example, the simulation netlist 500 shown in FIG. 5 is obtained by substituting the resistor-capacitance (RC), the load, the driver, and the like into the instantiated model A1. Figure 5 The simulation netlist 500 shown in FIG. 5 is obtained by substituting the resistor-capacitance (RC), the load, the driver, and the like into the instantiated model A1.

[0118] As shown in FIG. 5, the simulation netlist 500 includes a plurality of nodes, and each node can be connected to at least one other node. Figure 5As shown, the simulation netlist 500 includes at least one driver 501, a wire 502, and a load 503.

[0119] In Figure 5 In the embodiment shown, since the wire has resistance, in Figure 5 the wire is represented by a physical device resistance, and the resistance value representing the resistance of the wire is determined according to the method of step S43 described above, i.e., according to the wire length and the resistance value of the wire per unit length.

[0120] As shown, the load 503 can include a capacitor, a transistor, a light-emitting element, etc., and a person skilled in the art can set the load according to actual needs. Figure 5

[0121] In some embodiments of the present disclosure, the network topology design method described in any of the above embodiments can be applied to the design of a clock network topology or the design of a power supply network topology. When the network topology design method is applied to the design of a clock network topology, each network structure model is a clock network structure model; or, when the network topology design method is applied to the design of a power supply network topology, each network structure model is a power supply network structure model. When the network topology design method is applied to the design of a clock network topology, the driving unit can be a clock signal; or, when the network topology design method is applied to the design of a power supply network topology, the driving unit can be a power supply.

[0122] Figure 6 A flowchart of another network topology design method provided by at least one embodiment of the present disclosure is shown.

[0123] As shown, the method can include steps S10-S40 shown in Figure 6 Figure 1 In addition to steps S10-S40 shown in

[0124] In step S50, the network topology of the integrated circuit is verified using the simulation netlist to determine whether the evaluation index is met.

[0125] For example, when the network topology design method is applied to the design of a clock network topology, the evaluation index can include clock demand indexes such as setup time and hold time, etc.

[0126] For example, the simulation netlist is simulated to verify whether the clock network topology meets the demand for setup time and hold time.

[0127] ​​For example, EDA tools can be used to verify the network topology of integrated circuits to determine whether the network topology of integrated circuits meets the evaluation criteria.

[0128] If the network topology meets the evaluation criteria, the network can be laid out and routed according to the simulated netlist and then proceed to the actual production process.

[0129] Continue to refer to Figure 6 In other embodiments of this disclosure, the network topology design method for integrated circuits includes, in addition to, Figure 1 In addition to steps S10 to S50 shown, step S60 may also be included.

[0130] Step S60: In response to the network topology of the integrated circuit not meeting the evaluation criteria, at least one network structure model is readjusted.

[0131] If the network topology does not meet the evaluation criteria, one or more network structure models can be adjusted, and a simulation netlist can be obtained based on at least one adjusted network structure model. The simulation can then be repeated until a network topology that meets the evaluation criteria is obtained.

[0132] For example, the properties of some or all of the network structure models in a network structure model are adjusted to readjust at least one network structure model. That is, at least one network structure model is adjusted based on the verification results of the overall network topology of the integrated circuit obtained by splicing together at least one network structure model.

[0133] In other embodiments of this disclosure, if the network topology does not meet the evaluation criteria, one or more instantiated models can be adjusted, and a simulation netlist can be obtained again for simulation.

[0134] In the above embodiments of this disclosure, when the verification results do not meet the evaluation indicators of the integrated circuit, it is only necessary to modify one or more instantiated models or the network structure model corresponding to the instantiated model, without redesigning the integrated circuit or actually placing and accurately connecting the units in each network topology. Therefore, this method is easy to quickly adjust the network topology of the integrated circuit, shortens the verification cycle, and facilitates rapid iteration.

[0135] Figure 7 A schematic block diagram of a network topology design apparatus 700 for an integrated circuit provided in at least one embodiment of the present disclosure is shown.

[0136] For example, such as Figure 7 As shown, the network topology design device 700 of the integrated circuit includes an acquisition unit 710, an instantiation unit 720, a splicing unit 730, and a netlist generation unit 740.

[0137] The obtaining unit 710 is configured to obtain at least one network structure model, each network structure model being generated by encapsulating a network structure of a preset region, the network structure of the preset region being part of an integrated circuit, and each network structure model including a plurality of attributes.

[0138] The obtaining unit 710 may, for example, perform the step S10 described above. Figure 1

[0139] The instantiation unit 720 is configured to perform at least one assignment to the plurality of attributes in each network structure model to obtain a plurality of instantiated models.

[0140] The instantiation unit 720 may, for example, perform the step S20 described above. Figure 1

[0141] The splicing unit 730 is configured to splice the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit.

[0142] The splicing unit 730 may, for example, perform the step S30 described above. Figure 1

[0143] The netlist generation unit 740 is configured to convert the overall network model into a simulation netlist of the integrated circuit, the simulation netlist including a plurality of physical devices.

[0144] The netlist generation unit 740 may, for example, perform the step S40 described above. Figure 1

[0145] For example, in some embodiments of the present disclosure, the obtaining unit includes an electrical characteristic obtaining subunit configured to obtain electrical characteristics of a plurality of physical devices in the integrated circuit, and a model determining subunit configured to determine at least one network structure model according to the electrical characteristics of the plurality of physical devices.

[0146] For example, in some embodiments of the present disclosure, each network structure model includes a module vertex submodel and a boundary routing submodel, the module vertex submodel indicating attributes of feature points of the preset region, and the boundary routing submodel indicating attributes of routing used to connect the plurality of feature points.

[0147] For example, in some embodiments of the present disclosure, the attributes of the feature points include feature point identifiers and coordinate information, and the attributes of the routing include routing identifiers, start points, and end points.

[0148] For example, in some embodiments of the present disclosure, the splicing unit includes a splicing subunit configured to splice the plurality of instantiated models according to the coordinate information of the feature points to obtain the overall network model corresponding to the integrated circuit. ​​​​

[0149] For example, in some embodiments of the present disclosure, for two adjacent instantiated models, there is at least one overlapping edge after the two instantiated models are spliced, and there is no gap area in the overall network model.

[0150] For example, in some embodiments of the present disclosure, the netlist generation unit comprises: an attribute value acquisition subunit configured to, for each instantiated model in the plurality of instantiated models, acquire an attribute value of a target attribute in the plurality of attributes in each instantiated model; a physical characteristic determination subunit configured to determine a physical characteristic associated with the target attribute; a physical device determination subunit configured to determine a physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and a simulation netlist generation subunit configured to, for each instantiated model in the overall network model, represent the corresponding instantiated model with the physical device to obtain a simulation netlist of the integrated circuit.

[0151] For example, in some embodiments of the present disclosure, the target attribute comprises a wire length, the physical characteristic associated with the wire length comprises a resistance value of the wire within a unit length, and the physical device determination subunit comprises a resistance determination subunit configured to determine a target resistance based on the wire length and the resistance value of the wire within the unit length.

[0152] For example, in some embodiments of the present disclosure, each network structure model comprises a clock network structure model or a power supply network structure model, the clock network structure model comprises a clock network topology, and the power supply network structure model comprises a power supply network topology.

[0153] For example, in some embodiments of the present disclosure, further comprising a simulation unit configured to verify whether the network topology of the integrated circuit meets the evaluation index by using the simulation netlist.

[0154] For example, in some embodiments of the present disclosure, further comprising an adjustment unit configured to, in response to the network topology of the integrated circuit not meeting the evaluation index, readjust at least one network structure model.

[0155] For example, the acquisition unit 710, the instantiation unit 720, the splicing unit 730, and the netlist generation unit 740 can be hardware, software, firmware, and any feasible combination thereof. For example, the acquisition unit 710, the instantiation unit 720, the splicing unit 730, and the netlist generation unit 740 can be special-purpose or general-purpose circuits, chips, or devices, etc., or can be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above-mentioned units.

[0156] It should be noted that in the embodiments of this disclosure, each unit of the network topology design device 700 corresponds to each step of the aforementioned network topology design method. For the specific functions of the network topology design device 700, please refer to the relevant description of the network topology design method, which will not be repeated here. Figure 7 The components and structures of the network topology design device 700 shown are merely exemplary and not limiting. The network topology design device 700 may also include other components and structures as needed.

[0157] At least one embodiment of this disclosure also provides an electronic device including a processor and a memory, the memory including one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the network topology design method described above. This electronic device can improve the efficiency of verifying complex topologies of a single logical network, shorten the verification cycle, and is suitable for verifying rapid iterations.

[0158] Figure 8A This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. For example... Figure 8A As shown, the electronic device 800 includes a processor 810 and a memory 820. The memory 820 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 810 executes the non-transitory computer-readable instructions, which, when executed by the processor 810, can perform one or more steps in the network topology design method described above. The memory 820 and the processor 810 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0159] For example, processor 810 may be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing and / or program execution capabilities. For example, the central processing unit (CPU) may be an x86 or ARM architecture. Processor 810 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 800 to perform desired functions.

[0160] For example, the memory 820 can include any combination of one or more computer program products, which can include various forms of computer-readable storage media, for example, volatile and / or non-volatile memory. Volatile memory, for example, can include random access memory (RAM), and / or a cache, etc. Non-volatile memory, for example, can include read-only memory (ROM), hard disks, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules can be stored on the computer-readable storage media, and the processor 810 can execute the one or more computer program modules to implement various functions of the electronic device 800. Various application programs and various data used and / or generated by the application programs, etc. can also be stored in the computer-readable storage media.

[0161] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 800 can refer to the description of the network topology design method in the foregoing description, and will not be described here.

[0162] Figure 8B Another schematic block diagram of an electronic device is provided for some embodiments of the present disclosure. The electronic device 900 is suitable for implementing the network topology design method provided by the embodiments of the present disclosure, for example. The electronic device 900 can be a terminal device, etc. It should be noted that, Figure 8B The electronic device 900 shown is only an example, which does not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0163] As Figure 8B shown, the electronic device 900 can include a processing device (such as a central processor, a graphics processor, etc.) 910, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 920 or programs loaded from a storage device 980 to a random access memory (RAM) 930. Various programs and data required for the operation of the electronic device 900 are also stored in the RAM 930. The processing device 910, the ROM 920, and the RAM 930 are connected to each other through a bus 940. An input / output (I / O) interface 950 is also connected to the bus 940.

[0164] Typically, the following devices can be connected to I / O interface 950: input devices 960 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 970 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 980 including, for example, magnetic tapes, hard disks, etc.; and communication devices 990. Communication device 990 allows electronic device 900 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 8B An electronic device 900 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 900 may alternatively implement or have more or fewer devices.

[0165] For example, according to embodiments of this disclosure, the network topology design method described above can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for executing the network topology design method described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 990, or installed from a storage device 980, or installed from a ROM 920. When the computer program is executed by a processing device 910, the functions defined in the network topology design method provided by embodiments of this disclosure can be implemented.

[0166] At least one embodiment of this disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, can implement the network topology design method described above. Using this computer-readable storage medium can improve the efficiency of verifying complex topologies of a single logical network, shorten the verification cycle, and is suitable for rapid iteration verification.

[0167] Figure 9 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. For example... Figure 9 As shown, the storage medium 1000 is used to store non-transitory computer-readable instructions 1010. For example, when the non-transitory computer-readable instructions 1010 are executed by a computer, one or more steps in the network topology design method described above can be performed.

[0168] For example, the storage medium 1000 can be used in the aforementioned electronic device 800. For example, the storage medium 1000 can be... Figure 8A The memory 820 in the illustrated electronic device 800. For example, a description of the storage medium 1000 can be found here. Figure 8AThe corresponding description of the memory 820 in the electronic device 800 shown here will not be repeated.

[0169] The following points need to be explained:

[0170] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0171] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0172] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for designing a network topology of an integrated circuit, comprising: obtaining at least one network structure model, wherein each network structure model is generated from a network structure encapsulating a preset region as a part of the integrated circuit, and each network structure model comprises a plurality of attributes; performing at least one assignment to the plurality of attributes in each network structure model to obtain a plurality of instantiated models; stitching the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit; converting the overall network model into a simulation netlist of the integrated circuit, wherein the simulation netlist comprises a plurality of physical devices; and verifying whether the network topology of the integrated circuit satisfies evaluation indexes by using the simulation netlist; wherein the obtaining of the at least one network structure model comprises: obtaining electrical characteristics required by the integrated circuit; and determining the at least one network structure model according to the electrical characteristics; wherein each network structure model comprises a module vertex sub-model and a boundary routing sub-model, the module vertex sub-model indicates attributes of feature points of the preset region, and the boundary routing sub-model indicates attributes of routings for connecting the feature points; the attributes of the feature points comprise feature point identifiers and coordinate information; and the attributes of the routings comprise routing identifiers, start points and end points; the stitching of the plurality of instantiated models to obtain the overall network model corresponding to the integrated circuit comprises: stitching the plurality of instantiated models according to the coordinate information of the feature points to obtain the overall network model corresponding to the integrated circuit; for two adjacent instantiated models, there is at least one overlapping edge after the two instantiated models are stitched; and there is no gap region in the overall network model; the converting of the overall network model into the simulation netlist of the integrated circuit comprises: obtaining an attribute value of a target attribute in the plurality of attributes in each instantiated model in the plurality of instantiated models; determining a physical characteristic associated with the target attribute; determining the physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and representing the corresponding instantiated model by the physical device for each instantiated model in the overall network model to obtain the simulation netlist of the integrated circuit; the target attribute comprises a routing length, and the physical characteristic associated with the routing length comprises a resistance value of a routing in a unit length; the determining of the physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute comprises: determining a target resistance based on the routing length and the resistance value of the routing in the unit length; each network structure model comprises a clock network structure model or a power supply network structure model, the clock network structure model comprises a clock network topology, and the power supply network structure model comprises a power supply network topology; and the method further comprises: obtaining a plurality of network structure models, wherein each network structure model is generated from a network structure encapsulating a preset region as a part of the integrated circuit, and each network structure model comprises a plurality of attributes; performing at least one assignment to the plurality of attributes in each network structure model to obtain a plurality of instantiated models; stitching the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit; converting the overall network model into a simulation netlist of the integrated circuit, wherein the simulation netlist comprises a plurality of physical devices; and verifying whether the network topology of the integrated circuit satisfies evaluation indexes by using the simulation netlist. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The method of claim 1, wherein, ​ ​ 3. The method of claim 1, wherein, ​ ​ 4. The method of claim 1, wherein, ​ ​ ​ ​ ​ 5. The method of claim 4, wherein, ​ ​ ​ 6. The method according to any one of claims 1 to 5, wherein, ​ ​ ​ In response to the network topology of the integrated circuit not satisfying the evaluation index, readjusting the at least one network structure model.

8. An apparatus for designing a network topology of an integrated circuit, comprising: an obtaining unit configured to obtain at least one network structure model, wherein each network structure model is generated for a network structure package of a preset region, the network structure of the preset region being a part of the integrated circuit, and the each network structure model comprising a plurality of attributes; an instantiating unit configured to perform at least one assignment to the plurality of attributes in the each network structure model to obtain a plurality of instantiated models; a splicing unit configured to splice the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit; a netlist generating unit configured to convert the overall network model into a simulation netlist of the integrated circuit, wherein the simulation netlist comprises a plurality of physical devices; and a simulation unit configured to verify whether the network topology of the integrated circuit satisfies an evaluation index by using the simulation netlist. The obtaining unit comprises: an electrical characteristic obtaining subunit configured to obtain electrical characteristics required by the integrated circuit; and a model determining subunit configured to determine the at least one network structure model according to the electrical characteristics. The each network structure model comprises a module vertex submodel and a boundary routing submodel, the module vertex submodel indicating attributes of feature points of the preset region, and the boundary routing submodel indicating attributes of routing used to connect the feature points; the attributes of the feature points comprising feature point identifiers and coordinate information; the attributes of the routing comprising routing identifiers, start points, and end points.

9. The apparatus of claim 8, wherein, The netlist generating unit comprises: an attribute value obtaining subunit configured to obtain, for each of the plurality of instantiated models, an attribute value of a target attribute in the plurality of attributes in the each instantiated model; a physical characteristic determining subunit configured to determine a physical characteristic associated with the target attribute; a physical device determining subunit configured to determine the physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and a simulation netlist generating subunit configured to represent, for each of the instantiated models in the overall network model, the corresponding instantiated model by the physical device to obtain the simulation netlist of the integrated circuit.

10. An electronic device, comprising: a processor; a memory comprising one or more computer program instructions; wherein the one or more computer program instructions are stored in the memory and implemented by the processor to realize instructions of the network topology design method of the integrated circuit according to any one of claims 1-7.

11. A computer-readable storage medium having non-transitorily stored thereon computer-readable instructions, wherein, The computer readable instructions, when executed by the processor, realize the network topology design method of the integrated circuit according to any one of claims 1-7.

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