A common-mode noise suppression filter based on through-silicon vias

Abstract

The present invention discloses a common mode noise suppression filter based on through silicon via, comprising eight top double-layer interdigital capacitors, wherein the eight top double-layer interdigital capacitors are connected to eight bottom double-layer interdigital capacitors through thirteen TSV inductors. The present invention can achieve broadband suppression of common mode noise while maintaining the integrity of differential signals, and has a compact overall structure and high integration.

Description

Technical Field

[0001] The invention belongs to the technical field of three-dimensional integrated circuits and relates to a common-mode noise suppression filter based on through-silicon vias. Background Art

[0002] Differential or balanced signaling has become a popular technology in high-speed systems due to its good immunity to external noise, small crosstalk between adjacent pairs, and signal integrity. Therefore, this transmission technology is often used in advanced transition interfaces such as universal serial bus, peripheral component rapid interconnection, and high-definition multimedia interface. However, in a real differential signal structure, there is a certain common mode (CM) noise, which is another basic mode of the structure and is inevitable.

[0003] This noise is caused by the unbalanced output of the signal transmitting device, the asymmetry of the two signal paths, or the crosstalk from the adjacent signal pairs. A well-designed device should meet three characteristics: broadband CM noise suppression; good differential signal integrity; compact size. In previous studies, a different concept of using an improved T-type circuit was proposed to minimize the circuit size and achieve broadband CM noise suppression. However, in order to maintain the good performance of the design, the improved T-type circuit is evenly divided into several smaller circuits to make the group delay milder. This intuitive method is to make the signal complete at the expense of increasing the circuit area, but this method needs to be improved.

[0004] For periodic complex circuit topology networks, inductor devices are realized through TSV technology, and passive devices are integrated through three-dimensional integration technology in complex circuit topology structures, which can achieve compact structure and higher integration. Broadband common-mode noise suppression is achieved while maintaining differential signal integrity. Summary of the invention

[0005] The object of the present invention is to provide a common-mode noise suppression filter based on through-silicon vias, which can achieve broadband suppression of common-mode noise while maintaining the integrity of differential signals, and has a compact overall structure and high integration.

[0006] The technical solution adopted by the present invention is a common mode noise suppression filter based on silicon vias, including eight top double-layer interdigital capacitors, and the eight top double-layer interdigital capacitors are connected to eight bottom double-layer interdigital capacitors through thirteen TSV inductors.

[0007] The present invention is also characterized in that:

[0008] The eight top double-layer interdigital capacitors include a double-layer interdigital capacitor C1, a double-layer interdigital capacitor C2, a double-layer interdigital capacitor C3, a double-layer interdigital capacitor C4, a double-layer interdigital capacitor C5, a double-layer interdigital capacitor C6, a double-layer interdigital capacitor C7 and a double-layer interdigital capacitor C8;

[0009] The eight bottom double-layer interdigital capacitors include a double-layer interdigital capacitor C9, a double-layer interdigital capacitor C10, a double-layer interdigital capacitor C11, a double-layer interdigital capacitor C12, a double-layer interdigital capacitor C13, a double-layer interdigital capacitor C14, a double-layer interdigital capacitor C15 and a double-layer interdigital capacitor C16;

[0010] The double-layer interdigital capacitor C1, the double-layer interdigital capacitor C2, the double-layer interdigital capacitor C3, the double-layer interdigital capacitor C4, the double-layer interdigital capacitor C5, the double-layer interdigital capacitor C6, the double-layer interdigital capacitor C7, the double-layer interdigital capacitor C8, the double-layer interdigital capacitor C9, the double-layer interdigital capacitor C10, the double-layer interdigital capacitor C11, the double-layer interdigital capacitor C12, the double-layer interdigital capacitor C13, the double-layer interdigital capacitor C14, the double-layer interdigital capacitor C15 and the double-layer interdigital capacitor C16 have the same structure, and all include capacitor plate Plate1, capacitor plate Plate2, capacitor plate Plate3 and capacitor plate Plate4;

[0011] The capacitor plate Plate1 and the capacitor plate Plate3 form an interdigital capacitor between the same layer; the capacitor plate Plate2 and the capacitor plate Plate4 form an interdigital capacitor between the same layer;

[0012] The capacitor plate Plate1 is connected to the capacitor plate Plate4, and the capacitor plate Plate2 is connected to the capacitor plate Plate3.

[0013] The thirteen TSV inductors include TSV inductor L1, TSV inductor L2, TSV inductor L3, TSV inductor L4, TSV inductor L5, TSV inductor L6, TSV inductor L7, TSV inductor L8, TSV inductor L9, TSV inductor L10, TSV inductor L11, TSV inductor L12 and TSV inductor L13;

[0014] TSV inductor L1, TSV inductor L2, TSV inductor L3, TSV inductor L4, TSV inductor L5, TSV inductor L6, TSV inductor L7, TSV inductor L8, TSV inductor L9, TSV inductor L10, TSV inductor L11, TSV inductor L12 and TSV inductor L13 are all formed by spirally winding a plurality of TSVs, and the TSVs are connected end to end in sequence through RDL layers.

[0015] The spiral winding direction of each TSV in the TSV inductor L1 is opposite to the spiral winding direction of each TSV in the TSV inductor L2 .

[0016] The starting end port1 of the TSV inductor L1 is connected to the capacitor plate plate2 of the double-layer interdigital capacitor C1;

[0017] The end port2 of the TSV inductor L1 is connected to the end port2 of the TSV inductor L2 and the capacitor plate plate2 of the double-layer interdigital capacitor C2 respectively;

[0018] The starting end port1 of the TSV inductor L2 is respectively connected to the capacitor plate plate4 of the double-layer interdigital capacitor C1, the capacitor plate plate2 of the double-layer interdigital capacitor C3, and the starting end port1 of the TSV inductor L3;

[0019] The capacitor plate plate 4 of the double-layer interdigital capacitor C3 is connected to the capacitor plate plate 2 of the double-layer interdigital capacitor C5 and the capacitor plate plate 2 of the double-layer interdigital capacitor C4 respectively;

[0020] The capacitor plate plate4 of the double-layer interdigital capacitor C4 is respectively connected to the end port2 of the TSV inductor L3, the starting end port1 of the TSV inductor L4, and the capacitor plate plate2 of the double-layer interdigital capacitor C6;

[0021] The capacitor plate plate 4 of the double-layer interdigital capacitor C6 is connected to the capacitor plate plate 2 of the double-layer interdigital capacitor C7 and the capacitor plate plate 2 of the double-layer interdigital capacitor C8 respectively;

[0022] The capacitor plate plate 4 of the double-layer interdigital capacitor C7 is connected to the end port 2 of the TSV inductor L4;

[0023] The capacitor plate plate4 of the double-layer interdigital capacitor C5 is connected to the starting end port1 of the TSV inductor L5;

[0024] The capacitor plate plate 4 of the double-layer interdigital capacitor C8 is connected to the end port 2 of the TSV inductor L6;

[0025] The starting end port1 of the TSV inductor L8 is connected to the capacitor plate plate1 of the double-layer interdigital capacitor C9, the end port2 of the TSV inductor L9, and the capacitor plate plate1 of the double-layer interdigital capacitor C10 respectively;

[0026] The starting end port1 of the TSV inductor L9 is respectively connected to the capacitor plate plate3 of the double-layer interdigital capacitor C9, the capacitor plate plate1 of the double-layer interdigital capacitor C11, and the starting end port1 of the TSV inductor L10;

[0027] The capacitor plate plate 3 of the double-layer interdigital capacitor C11 is connected to the capacitor plate plate 1 of the capacitor plate C13 and the capacitor plate plate 1 of the double-layer interdigital capacitor C12 respectively;

[0028] The capacitor plate plate3 of the double-layer interdigital capacitor C12 is connected to the end port2 of the TSV inductor L10, the starting end port1 of the TSV inductor L11, and the capacitor plate plate1 of the double-layer interdigital capacitor C14 respectively;

[0029] The capacitor plate plate 3 of the double-layer interdigital capacitor C14 is connected to the capacitor plate plate 1 of the double-layer interdigital capacitor C15 and the capacitor plate plate 1 of the double-layer interdigital capacitor C8 respectively;

[0030] The capacitor plate plate 3 of the double-layer interdigital capacitor C15 is connected to the end port 2 of the TSV inductor L11;

[0031] The capacitor plate plate3 of the double-layer interdigital capacitor C13 is connected to the starting end port1 of the TSV inductor L12;

[0032] The capacitor plate plate 3 of the double-layer interdigital capacitor C16 is connected to the end port 2 of the TSV inductor L13;

[0033] The capacitor plate plate4 of the double-layer interdigital capacitor C2, the capacitor plate plate4 of the double-layer interdigital capacitor C10, the end port2 of the TSV inductor L5, the end port2 of the TSV inductor L12, the starting end port1 of the TSV inductor L6, and the starting end port1 of the TSV inductor L13 are all connected to the end port2 of the TSV inductor L7.

[0034] The beneficial effects of the present invention are as follows:

[0035] 1. Adopt TSV structure, TSV is located in the silicon substrate, and is compatible with existing common silicon process products;

[0036] 2. The use of double-layer interdigital capacitors can achieve a larger capacitance without increasing the area;

[0037] 3. TSV technology is used to realize inductor devices, with compact structure and high integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the three-dimensional structure of a common-mode noise suppression filter based on through-silicon vias of the present invention;

[0039] Figure 2 It is a schematic structural diagram of a common mode noise suppression filter based on through silicon vias of the present invention after removing eight top double-layer interdigital capacitors;

[0040] Figure 3 It is a schematic structural diagram of the connection between the bottom double-layer interdigital capacitor and the TSV inductor in a common-mode noise suppression filter based on through silicon vias of the present invention;

[0041] Figure 4 It is a schematic structural diagram of a bottom double-layer interdigital capacitor in a common-mode noise suppression filter based on through-silicon vias of the present invention;

[0042] Figure 5 It is a schematic structural diagram of a single TSV in a common-mode noise suppression filter based on through silicon vias of the present invention;

[0043] 6(a) to (m) are top views of TSV inductors in a common-mode noise suppression filter based on through silicon vias according to the present invention;

[0044] Figure 7 It is a front view of a single double-layer interdigital capacitor in a common-mode noise suppression filter based on through-silicon vias of the present invention;

[0045] Figure 8 It is a schematic diagram of the three-dimensional structure of a single double-layer interdigital capacitor in a common-mode noise suppression filter based on through-silicon vias of the present invention;

[0046] Fig. 9 It is a schematic structural diagram between capacitor plate plate 2 and capacitor plate 4 in a single double-layer interdigital capacitor in a common-mode noise suppression filter based on through silicon vias of the present invention;

[0047] Fig.10 It is a circuit diagram of a common mode noise suppression filter based on through silicon vias of the present invention;

[0048] Fig.11 This is a simulation curve diagram of a common-mode noise suppression filter model based on through silicon vias of the present invention.

[0049] In the figure, 1. copper pillar, 2. silicon dioxide layer, 3. silicon-based substrate layer, 4. upper RDL, 5. lower RDL, 6. interconnection bond, 7. interconnection layer. DETAILED DESCRIPTION

[0050] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] The present invention discloses a common mode noise suppression filter based on through silicon via, which adopts TSV inductor and double-layer interdigital capacitor in structural model implementation. Figure 1 As shown, the entire structure from top to bottom is eight top double-layer interdigital capacitors, interconnection key 6, interconnection layer 7, interconnection key 6, thirteen TSV inductors, interconnection key 6, interconnection layer 7, interconnection key 6 and eight bottom double-layer interdigital capacitors.

[0052] like Figures 2 to 4As shown, the eight top double-layer interdigital capacitors include double-layer interdigital capacitor C1, double-layer interdigital capacitor C2, double-layer interdigital capacitor C3, double-layer interdigital capacitor C4, double-layer interdigital capacitor C5, double-layer interdigital capacitor C6, double-layer interdigital capacitor C7 and double-layer interdigital capacitor C8;

[0053] The eight bottom double-layer interdigital capacitors include a double-layer interdigital capacitor C9, a double-layer interdigital capacitor C10, a double-layer interdigital capacitor C11, a double-layer interdigital capacitor C12, a double-layer interdigital capacitor C13, a double-layer interdigital capacitor C14, a double-layer interdigital capacitor C15, and a double-layer interdigital capacitor C16;

[0054] The structures of double-layer interdigital capacitor C1, double-layer interdigital capacitor C2, double-layer interdigital capacitor C3, double-layer interdigital capacitor C4, double-layer interdigital capacitor C5, double-layer interdigital capacitor C6, double-layer interdigital capacitor C7, double-layer interdigital capacitor C8, double-layer interdigital capacitor C9, double-layer interdigital capacitor C10, double-layer interdigital capacitor C11, double-layer interdigital capacitor C12, double-layer interdigital capacitor C13, double-layer interdigital capacitor C14, double-layer interdigital capacitor C15 and double-layer interdigital capacitor C16 are the same, such as Figure 7 As shown, they all include capacitor plate Plate1, capacitor plate Plate2, capacitor plate Plate3, and capacitor plate Plate4;

[0055] The capacitor plate Plate1 and the capacitor plate Plate3 form an interdigital capacitor between the same layer; the capacitor plate Plate2 and the capacitor plate Plate4 form an interdigital capacitor between the same layer;

[0056] The capacitor plate Plate1 is connected to the capacitor plate Plate4, and the capacitor plate Plate2 is connected to the capacitor plate Plate3.

[0057] Each TSV inductor and each double-layer interdigital capacitor are connected by interconnection layer 7;

[0058] Each TSV inductor is connected to each double-layer interdigital capacitor by connecting in the following order: interconnection key 6 , interconnection layer 7 , and interconnection key 6 from top to bottom.

[0059] The capacitor plates Plate1 and Plate2, the capacitor plates Plate3 and Plate4 respectively form a metal (Cu)-oxide (silicon dioxide)-metal (Cu) (MIM) capacitor;

[0060] like Figure 8 , 9As shown, capacitor plate Plate1 is connected to capacitor plate Plate4 (one end of copper block Net2 is connected to the inner side of capacitor plate plate1, the other end of copper block Net2 is connected to copper block Net3; copper block Net5 connects copper block Net3 to the inner side of capacitor plate plate4);

[0061] The capacitor plate Plate2 is connected to the capacitor plate Plate3 (the copper block Net1 on the same layer connected to the capacitor plate Plate2 is connected to the capacitor plate Plate3 on the upper layer through the copper block Net4).

[0062] Each double-layer interdigital capacitor has the same structure, and each RDL (copper block Net1, copper block Net2, copper block Net3, copper block Net4, copper block Net5 are RDLs that connect the plate metal plates) is 10um wide, 10um high, 2um apart, 2um apart between the upper and lower layers, and 2um apart from the finger to the plate. The capacitor medium is silicon dioxide.

[0063] The index and finger length aw of each capacitor are different. The finger length of double-layer interdigital capacitor C3, double-layer interdigital capacitor C4, double-layer interdigital capacitor C11, and double-layer interdigital capacitor C12 (0.150PF) is 73.5um and the index is 3;

[0064] The finger length of double-layer interdigital capacitor C1 and double-layer interdigital capacitor C9 (0.071PF) is 40.5um, index 2; the finger length of double-layer interdigital capacitor C2 and double-layer interdigital capacitor C10 (0.784PF) is 92.2um, index 13; the finger length of double-layer interdigital capacitor C5 and double-layer interdigital capacitor C13 (0.122PF) is 53.8um, index 3; the finger length of double-layer interdigital capacitor C6, double-layer interdigital capacitor C7, double-layer interdigital capacitor C14 and double-layer interdigital capacitor C15 (0.190PF) is 69um, index 4; the finger length of double-layer interdigital capacitor C8 and double-layer interdigital capacitor C16 (0.0984PF) is 71um, index 2. Single-layer interdigital capacitors can also be used to achieve this function. Compared with single-layer capacitors, double-layer capacitors have great advantages in the area occupied.

[0065] The thirteen TSV inductors include TSV inductor L1, TSV inductor L2, TSV inductor L3, TSV inductor L4, TSV inductor L5, TSV inductor L6, TSV inductor L7, TSV inductor L8, TSV inductor L9, TSV inductor L10, TSV inductor L11, TSV inductor L12 and TSV inductor L13;

[0066] TSV inductor L1, TSV inductor L2, TSV inductor L3, TSV inductor L4, TSV inductor L5, TSV inductor L6, TSV inductor L7, TSV inductor L8, TSV inductor L9, TSV inductor L10, TSV inductor L11, TSV inductor L12 and TSV inductor L13 are all formed by spirally winding a plurality of TSVs, and the TSVs are connected end to end in sequence through RDL layers.

[0067] The spiral winding direction of each TSV in the TSV inductor L1 is opposite to the spiral winding direction of each TSV in the TSV inductor L2 .

[0068] The inductor part is formed by combining TSV with upper and lower RDL;

[0069] like Figure 5 As shown, each TSV (through silicon via) includes a copper pillar 1, and the outside of the copper pillar 1 is coaxially wrapped with a silicon dioxide layer 2 and a silicon-based substrate layer 3 in sequence; the diameter of the copper pillar 1 is 10um, the height of the copper pillar 1 is 96um, and a thin layer of 0.3um silicon dioxide layer 2 is wrapped around the outer periphery of the copper pillar 1. In each inductor part formed by TSV, the lateral center distance of TSV is 20um, the RDL width is 10um, and the thickness is 3um.

[0070] As shown in Figure 6(a), the winding structure of the TSV inductor L1 is a top view, wherein the TSV inductor L1 is formed by spirally winding with 6 TSVs connected in sequence; the upper end of each TSV in the TSV inductor L1 is connected to the upper layer RDL4, and the lower end of each TSV in the TSV inductor L1 is connected to the lower layer RDL5; in the TSV inductor L1, the length of the lower layer RDL5 is 64um, and the length of the upper layer RDL4 is 32um, 61.5um, 61.5um, and 32um from the starting end port1 of the TSV inductor L1 to the end port2 of the TSV inductor L1.

[0071] FIG6(b) is a top view of the winding structure of the TSV inductor L2; the TSV inductor L2 is formed by winding six TSVs in sequence in a spiral shape; the upper end of each TSV in the TSV inductor L2 is connected to the upper layer RDL4, and the lower end of each TSV is connected to the lower layer RDL5; the TSV inductor L2 and the TSV inductor L1 have the same size, but the winding method is exactly opposite;

[0072] FIG6(c) is a top view of the winding of the TSV inductor L3; wherein the TSV inductor L3 is formed by winding four TSVs in sequence in a spiral shape; the upper end of each TSV in the TSV inductor L3 is connected to the upper layer RDL4, and the lower end of each TSV in the TSV inductor L3 is connected to the lower layer RDL5;

[0073] In the TSV inductor L3, the length of the lower layer RDL5 is 30um, and the length of the upper layer RDL4 is 20um, 40um, and 20um from the starting end port1 of the TSV inductor L3 to the end port2 of the TSV inductor L3;

[0074] FIG6(d) is a top view of the winding of the TSV inductor L4; wherein the TSV inductor L4 is formed by winding four TSVs in sequence in a spiral shape; the upper end of each TSV in the TSV inductor L4 is connected to the upper layer RDL4, and the lower end of each TSV in the TSV inductor L4 is connected to the lower layer RDL5;

[0075] In the TSV inductor L4, the length of the lower layer RDL5 is 30um, and the length of the upper layer RDL4 is 17um, 40um, and 10um from the starting end port1 of the TSV inductor L4 to the end port2 of the TSV inductor L4;

[0076] FIG6(e) is a top view of the winding of the TSV inductor L5; wherein the TSV inductor L5 is formed by winding four TSVs in sequence in a spiral shape; the upper end of each TSV in the TSV inductor L5 is connected to the upper layer RDL4, and the lower end of each TSV in the TSV inductor L5 is connected to the lower layer RDL5;

[0077] In the TSV inductor L5, the length of the lower layer RDL5 is 30um, and the length of the upper layer RDL4 is 16um, 40um, and 16um from the starting end port1 of the TSV inductor L5 to the end port2 of the TSV inductor L5;

[0078] FIG6(f) is a top view of the winding of the TSV inductor L6; wherein the TSV inductor L6 is formed by winding four TSVs in sequence in a spiral shape; the upper end of each TSV in the TSV inductor L6 is connected to the upper layer RDL4, and the lower end of each TSV in the TSV inductor L6 is connected to the lower layer RDL5;

[0079] In the TSV inductor L6, the length of the lower layer RDL5 is 32 um, and the length of the upper layer RDL4 from the starting end port1 of the TSV inductor L6 to the end port2 of the TSV inductor L6 is 22 um, 41 um, and 22 um respectively.

[0080] FIG6(g) is a top view of the winding of the TSV inductor L7; wherein the TSV inductor L7 is formed by winding six TSVs in sequence in a spiral shape; the upper end of each TSV in the TSV inductor L7 is connected to the upper layer RDL4, and the lower end of each TSV in the TSV inductor L7 is connected to the lower layer RDL5;

[0081] In the TSV inductor L6 , the length of the lower layer RDL5 is 32 um, and the length of the upper layer RDL4 is 22 um, 41 um, and 22 um from the starting end port1 of the TSV inductor L6 to the end port2 of the TSV inductor L6 .

[0082] In the TSV inductor L7, the length of the lower layer RDL5 is 50um, and the length of the upper layer RDL4 is 30um, 56.5um, 56.5um, 30um, and 150um from the starting end port1 of the TSV inductor L7 to the end port2 of the TSV inductor L7;

[0083] Fig.10 The circuit diagram of a common mode noise suppression filter based on through silicon vias is shown in FIG. The inductor size and structure of the lower half of the circuit are the same as those of the upper half, but the difference is that the inductor of the lower half is in a mirror image relationship with the inductor of the upper half, that is, the upper RDL of the L8-L13 inductor structure is located at the lower RDL5 of the TSV inductor L1-L7. It can be adjusted according to the required value or structure.

[0084] FIG6(h) is a top view of the TSV inductor L8, where the TSV inductor L8 and the TSV inductor L1 are mirror images of the TSV inductor L7;

[0085] FIG6(i) is a top view of the TSV inductor L9, where the TSV inductor L9 and the TSV inductor L2 are mirror images of the TSV inductor L7;

[0086] FIG6( j ) is a top view of the TSV inductor L10 , where the TSV inductor L10 and the TSV inductor L3 are mirror images of the TSV inductor L7 ;

[0087] FIG6( k ) is a top view of the TSV inductor L11 , where the TSV inductor L11 and the TSV inductor L4 are mirror images of the TSV inductor L7 ;

[0088] FIG6( l ) is a top view of the TSV inductor L12 , where the TSV inductor L12 and the TSV inductor L5 are mirror images of the TSV inductor L7 ;

[0089] FIG6( m ) is a top view of the TSV inductor L13 , where the TSV inductor L13 and the TSV inductor L6 are mirror images of the TSV inductor L7 ;

[0090] The starting end port1 of the TSV inductor L1 is connected to the capacitor plate plate2 of the double-layer interdigital capacitor C1;

[0091] The end port2 of the TSV inductor L1 is connected to the end port2 of the TSV inductor L2 and the capacitor plate plate2 of the double-layer interdigital capacitor C2 respectively;

[0092] The starting end port1 of the TSV inductor L2 is respectively connected to the capacitor plate plate4 of the double-layer interdigital capacitor C1, the capacitor plate plate2 of the double-layer interdigital capacitor C3, and the starting end port1 of the TSV inductor L3;

[0093] The capacitor plate plate 4 of the double-layer interdigital capacitor C3 is connected to the capacitor plate plate 2 of the double-layer interdigital capacitor C5 and the capacitor plate plate 2 of the double-layer interdigital capacitor C4 respectively;

[0094] The capacitor plate plate4 of the double-layer interdigital capacitor C4 is respectively connected to the end port2 of the TSV inductor L3, the starting end port1 of the TSV inductor L4, and the capacitor plate plate2 of the double-layer interdigital capacitor C6;

[0095] The capacitor plate plate 4 of the double-layer interdigital capacitor C6 is connected to the capacitor plate plate 2 of the double-layer interdigital capacitor C7 and the capacitor plate plate 2 of the double-layer interdigital capacitor C8 respectively;

[0096] The capacitor plate plate 4 of the double-layer interdigital capacitor C7 is connected to the end port 2 of the TSV inductor L4;

[0097] The capacitor plate plate4 of the double-layer interdigital capacitor C5 is connected to the starting end port1 of the TSV inductor L5;

[0098] The capacitor plate plate 4 of the double-layer interdigital capacitor C8 is connected to the end port 2 of the TSV inductor L6;

[0099] The starting end port1 of the TSV inductor L8 is connected to the capacitor plate plate1 of the double-layer interdigital capacitor C9, the end port2 of the TSV inductor L9, and the capacitor plate plate1 of the double-layer interdigital capacitor C10 respectively;

[0100] The starting end port1 of the TSV inductor L9 is respectively connected to the capacitor plate plate3 of the double-layer interdigital capacitor C9, the capacitor plate plate1 of the double-layer interdigital capacitor C11, and the starting end port1 of the TSV inductor L10;

[0101] The capacitor plate plate 3 of the double-layer interdigital capacitor C11 is connected to the capacitor plate plate 1 of the capacitor plate C13 and the capacitor plate plate 1 of the double-layer interdigital capacitor C12 respectively;

[0102] The capacitor plate plate3 of the double-layer interdigital capacitor C12 is connected to the end port2 of the TSV inductor L10, the starting end port1 of the TSV inductor L11, and the capacitor plate plate1 of the double-layer interdigital capacitor C14 respectively;

[0103] The capacitor plate plate 3 of the double-layer interdigital capacitor C14 is connected to the capacitor plate plate 1 of the double-layer interdigital capacitor C15 and the capacitor plate plate 1 of the double-layer interdigital capacitor C8 respectively;

[0104] The capacitor plate plate 3 of the double-layer interdigital capacitor C15 is connected to the end port 2 of the TSV inductor L11;

[0105] The capacitor plate plate3 of the double-layer interdigital capacitor C13 is connected to the starting end port1 of the TSV inductor L12;

[0106] The capacitor plate plate 3 of the double-layer interdigital capacitor C16 is connected to the end port 2 of the TSV inductor L13;

[0107] The capacitor plate plate4 of the double-layer interdigital capacitor C2, the capacitor plate plate4 of the double-layer interdigital capacitor C10, the end port2 of the TSV inductor L5, the end port2 of the TSV inductor L12, the starting end port1 of the TSV inductor L6, and the starting end port1 of the TSV inductor L13 are all connected to the end port2 of the TSV inductor L7.

[0108] Plate 1 and plate 3, plate 2 and plate 4 are metal plates connecting the fingers of each layer in each double-layer interdigital capacitor.

[0109] Net1, Net2, Net3, Net4, and Net5 are RDLs that connect the plate metal plates. The materials of plate and Net are both metal Cu. The finger length aw is to be designed, and the distance d from the finger to the plate is 2um.

[0110] There is mutual inductance between the TSV inductor L1 and the TSV inductor L2 , and between the TSV inductor L8 and the TSV inductor L9 , and the coupling coefficient k is 0.314.

[0111] Coupling coefficient:

[0112]

[0113] Table 1 below shows the values ​​of various components of a common mode noise suppression filter based on through silicon vias of the present invention:

[0114] Table 1

[0115]

[0116]

[0117] Fig.11 This is the simulation result diagram. Fig.11It can be seen that when the differential signal loss is less than 3dB in the 0-8.6GHZ frequency band, the common mode noise is suppressed by more than 10dB in the 3.8-8.6GHZ frequency band, and the noise is suppressed by more than 20dB in the 4.45-7.85GHZ frequency band, with a relative bandwidth of 80%. In addition to maintaining the good basic performance of the filter, compared with the fourth-order circuit topology realized by the IPD process, the suppression bandwidth is wider and the structure is more compact.

Claims

1. A common mode noise suppression filter based on through silicon vias, characterized in that: The eight top double-layer interdigital capacitors are connected to the eight bottom double-layer interdigital capacitors through thirteen TSV inductors respectively; The eight top double-layer interdigital capacitors include a double-layer interdigital capacitor C1, a double-layer interdigital capacitor C2, a double-layer interdigital capacitor C3, a double-layer interdigital capacitor C4, a double-layer interdigital capacitor C5, a double-layer interdigital capacitor C6, a double-layer interdigital capacitor C7 and a double-layer interdigital capacitor C8; The eight bottom double-layer interdigital capacitors include a double-layer interdigital capacitor C9, a double-layer interdigital capacitor C10, a double-layer interdigital capacitor C11, a double-layer interdigital capacitor C12, a double-layer interdigital capacitor C13, a double-layer interdigital capacitor C14, a double-layer interdigital capacitor C15 and a double-layer interdigital capacitor C16; The double-layer interdigital capacitor C1, the double-layer interdigital capacitor C2, the double-layer interdigital capacitor C3, the double-layer interdigital capacitor C4, the double-layer interdigital capacitor C5, the double-layer interdigital capacitor C6, the double-layer interdigital capacitor C7, the double-layer interdigital capacitor C8, the double-layer interdigital capacitor C9, the double-layer interdigital capacitor C10, the double-layer interdigital capacitor C11, the double-layer interdigital capacitor C12, the double-layer interdigital capacitor C13, the double-layer interdigital capacitor C14, the double-layer interdigital capacitor C15 and the double-layer interdigital capacitor C16 have the same structure, and all include capacitor plate Plate1, capacitor plate Plate2, capacitor plate Plate3 and capacitor plate Plate4; The capacitor plate Plate1 and the capacitor plate Plate3 form an interdigital capacitor between the same layer; the capacitor plate Plate2 and the capacitor plate Plate4 form an interdigital capacitor between the same layer; The capacitor plate Plate1 is connected to the capacitor plate Plate4, and the capacitor plate Plate2 is connected to the capacitor plate Plate3; The thirteen TSV inductors include TSV inductor L1, TSV inductor L2, TSV inductor L3, TSV inductor L4, TSV inductor L5, TSV inductor L6, TSV inductor L7, TSV inductor L8, TSV inductor L9, TSV inductor L10, TSV inductor L11, TSV inductor L12 and TSV inductor L13; TSV inductor L1, TSV inductor L2, TSV inductor L3, TSV inductor L4, TSV inductor L5, TSV inductor L6, TSV inductor L7, TSV inductor L8, TSV inductor L9, TSV inductor L10, TSV inductor L11, TSV inductor L12 and TSV inductor L13 are all formed by spirally winding a plurality of TSVs, and the TSVs are connected end to end in sequence through RDL layers; The spiral winding direction of each TSV in the TSV inductor L1 is opposite to the spiral winding direction of each TSV in the TSV inductor L2; The starting end port1 of the TSV inductor L1 is connected to the capacitor plate plate2 of the double-layer interdigital capacitor C1; The end port2 of the TSV inductor L1 is connected to the end port2 of the TSV inductor L2 and the capacitor plate plate2 of the double-layer interdigital capacitor C2 respectively; The starting end port1 of the TSV inductor L2 is respectively connected to the capacitor plate plate4 of the double-layer interdigital capacitor C1, the capacitor plate plate2 of the double-layer interdigital capacitor C3, and the starting end port1 of the TSV inductor L3; The capacitor plate plate 4 of the double-layer interdigital capacitor C3 is connected to the capacitor plate plate 2 of the double-layer interdigital capacitor C5 and the capacitor plate plate 2 of the double-layer interdigital capacitor C4 respectively; The capacitor plate plate4 of the double-layer interdigital capacitor C4 is respectively connected to the end port2 of the TSV inductor L3, the starting end port1 of the TSV inductor L4, and the capacitor plate plate2 of the double-layer interdigital capacitor C6; The capacitor plate plate 4 of the double-layer interdigital capacitor C6 is connected to the capacitor plate plate 2 of the double-layer interdigital capacitor C7 and the capacitor plate plate 2 of the double-layer interdigital capacitor C8 respectively; The capacitor plate plate 4 of the double-layer interdigital capacitor C7 is connected to the end port 2 of the TSV inductor L4; The capacitor plate plate4 of the double-layer interdigital capacitor C5 is connected to the starting end port1 of the TSV inductor L5; The capacitor plate plate 4 of the double-layer interdigital capacitor C8 is connected to the end port 2 of the TSV inductor L6; The starting end port1 of the TSV inductor L8 is connected to the capacitor plate plate1 of the double-layer interdigital capacitor C9; the end port2 of the TSV inductor L8 is connected to the end port2 of the TSV inductor L9 and the capacitor plate plate1 of the double-layer interdigital capacitor C10 respectively; The starting end port1 of the TSV inductor L9 is respectively connected to the capacitor plate plate3 of the double-layer interdigital capacitor C9, the capacitor plate plate1 of the double-layer interdigital capacitor C11, and the starting end port1 of the TSV inductor L10; The capacitor plate plate 3 of the double-layer interdigital capacitor C11 is connected to the capacitor plate plate 1 of the capacitor plate C13 and the capacitor plate plate 1 of the double-layer interdigital capacitor C12 respectively; The capacitor plate plate3 of the double-layer interdigital capacitor C12 is connected to the end port2 of the TSV inductor L10, the starting end port1 of the TSV inductor L11, and the capacitor plate plate1 of the double-layer interdigital capacitor C14 respectively; The capacitor plate plate 3 of the double-layer interdigital capacitor C14 is connected to the capacitor plate plate 1 of the double-layer interdigital capacitor C15 and the capacitor plate plate 1 of the double-layer interdigital capacitor C16 respectively; The capacitor plate plate 3 of the double-layer interdigital capacitor C15 is connected to the end port 2 of the TSV inductor L11; The capacitor plate plate3 of the double-layer interdigital capacitor C13 is connected to the starting end port1 of the TSV inductor L12; The capacitor plate plate 3 of the double-layer interdigital capacitor C16 is connected to the end port 2 of the TSV inductor L13; The capacitor plate plate4 of the double-layer interdigital capacitor C2, the capacitor plate plate4 of the double-layer interdigital capacitor C10, the end port2 of the TSV inductor L5, the end port2 of the TSV inductor L12, the starting end port1 of the TSV inductor L6, and the starting end port1 of the TSV inductor L13 are all connected to the end port2 of the TSV inductor L7.

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