A storage renaming implementation method, processor and computer device

Abstract

The present invention discloses a method for implementing storage renaming, a processor and a computer device. The present invention includes: after instruction decoding and before register renaming: judging the instruction type of the instruction obtained by decoding and whether storage renaming is required; if storage renaming is required and the instruction type is a Store instruction, writing the source register number of the Store instruction into a value file; if storage renaming is required and the instruction type is a Load instruction, judging whether the Load instruction is dependent on the previous Store instruction by storage dependency prediction, and if there is a dependency on the previous Store instruction, performing value transfer between the Load instruction and the Store instruction on which it depends by register transfer. The present invention can reduce resource occupation caused by implementation, reduce execution power consumption, and further improve processor performance.

Description

Technical Field

[0001] The present invention relates to the field of processor architecture, and in particular to a method for implementing storage renaming, a processor and a computer device. Background Art

[0002] The storage problem has always been a problem that has plagued processor performance improvement. When storing data, the dependency between the load and store instructions needs to be determined by accessing the storage address. In other words, if the address of the store instruction overlaps with the address of the subsequent load instruction, the subsequent load instruction needs to obtain data from the data stored by the store instruction. This kind of data dependency requires waiting for both the store and load to be executed before the dependency can be determined by comparing the addresses.

[0003] The prior art (Tyson, GS, Austin, TM Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. International Journal of Parallel Programming 27, 357–380 (1999).) discloses a storage renaming technology, which predicts the data dependency between the Store instruction and the Load instruction and then transfers the data between the Store and Load instructions through a value file. That is, the data transfer between the Store instruction and the Load instruction is performed by renaming to the value file. When a Load instruction is predicted to be data-dependent with a Store instruction, the data can be directly obtained from the value file without waiting for the address to be calculated and then bypassing the data from the Store-related cache, or obtaining the data from the storage. This method can speed up the execution of instructions, thereby improving processor performance. However, the implementation method of the storage renaming technology has the following problems: (1) The data transfer between the Store and Load is performed through the value file, and each item in the value file is at least 64 bits, which occupies a large amount of storage resources. (2) After Store is executed, the corresponding data is written to the value file, and the delay of passing the value to Load is relatively large. (3) Store writes data to the value file, which consumes additional power. (4) Since register renaming is performed by prediction, the general implementation requires reading the predicted result in the register after the Load instruction is executed, comparing the results, and determining whether the prediction is correct. This comparison process requires additional pipeline support and register read port support. Summary of the invention

[0004] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a method for implementing storage renaming, a processor and a computer device are provided. The technical problem to be solved by the present invention is to implement storage renaming technology in an out-of-order microprocessor by borrowing the existing structure and pipeline in the processor, thereby reducing the resource occupation caused by the implementation, reducing the execution power consumption, and further improving the processor performance.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A method for implementing storage renaming includes the following steps after instruction decoding and before register renaming:

[0007] 1) Determine the instruction type of the instruction obtained by decoding and whether storage renaming is required;

[0008] 2) If storage renaming is required and the instruction type is a Store instruction, the source register number of the Store instruction is written to the value file; if storage renaming is required and the instruction type is a Load instruction, storage dependency prediction is used to determine whether the Load instruction has a dependency on previous Store instructions. If there is a dependency on previous Store instructions, the value transfer between the Load instruction and the Store instruction on which it depends is performed by register transfer.

[0009] Optionally, in step 2), transferring the value between the Load instruction and the Store instruction on which it depends by means of register transfer includes splitting the original Load instruction into Move instructions, wherein the Move instructions are used to complete the function of the original Load instruction writing the destination register, the source operand of the Move instruction is the source register of the Store instruction on which it depends, and the destination operand is the destination register of the original Load instruction; the Move instructions are used to implement the function of predicting the result of the original Load instruction, and the value transfer between the original Load instruction and the Store instruction on which it depends is completed by directly obtaining data from the source register of the dependent Store instruction and writing it into the result register of the original Load instruction, wherein the Move instructions utilize the existing Move instruction path of the microprocessor and complete the data transfer process by reading the register.

[0010] Optionally, when the value transfer between the Load instruction and the Store instruction on which it depends is performed by register transfer in step 2), the steps of verifying the result and correcting the execution status are also included.

[0011] Optionally, the step of performing result verification and correcting the execution status includes splitting the Load instruction into the following instructions: a Load0 instruction, used to complete the function of the original Load instruction and complete the verification of the storage dependency prediction, used to obtain data from the memory pointed to by the source register, and then put it into the temporary register temp; a Check instruction, used to compare the result of the storage dependency prediction with the result of the actual execution of the Load0 instruction. If the values ​​of the destination register of the original Load instruction and the temporary register temp are equal, it proves that the previous storage dependency prediction is correct. Otherwise, it is determined that the previous storage dependency prediction is wrong, and the specific Move instruction is executed incorrectly, and the status will be restored.

[0012] Optionally, the Load0 instruction is used to complete the test of the storage dependency prediction, and the execution path of the Load0 instruction is completely consistent with the original Load instruction execution path, and there is no need to modify the pipeline structure.

[0013] Optionally, the temporary register temp is a register used for data transfer inside the microarchitecture, which is invisible to the programmer, and the Load0 instruction writing to the temporary register temp will not destroy the state of the architecture.

[0014] Optionally, the Check instruction is a newly added instruction for checking the prediction result, and the data path of the Check instruction borrows the original path in the microprocessor.

[0015] Optionally, before the instruction decoding, the step of fetching instructions is also included; after the register renaming, the steps of instruction dispatching, instruction issuing, instruction executing and writing back results are also included.

[0016] In addition, the present invention also provides a microprocessor, including a value acquisition unit, a decoding unit, a register renaming unit, an instruction dispatching unit, an instruction issuing unit, an instruction execution unit and a write-back result unit, wherein a storage renaming unit is arranged between the decoding unit and the register renaming unit, and the storage renaming unit is programmed or configured to execute the steps of the aforementioned storage renaming implementation method.

[0017] In addition, the present invention also provides a computer device, including a microprocessor and a memory connected to each other, the microprocessor including a value acquisition unit, a decoding unit, a register renaming unit, an instruction dispatching unit, an instruction issuing unit, an instruction execution unit and a write-back result unit, a storage renaming unit is arranged between the decoding unit and the register renaming unit, and the storage renaming unit is programmed or configured to execute the steps of the aforementioned storage renaming implementation method.

[0018] Compared with the prior art, the present invention has the following advantages: the present invention includes the following steps: after instruction decoding and before register renaming: determining the instruction type of the instruction obtained by decoding and whether storage renaming is required; if storage renaming is required and the instruction type is a Store instruction, writing the source register number of the Store instruction into a value file; if storage renaming is required and the instruction type is a Load instruction, determining whether the Load instruction is dependent on previous Store instructions through storage dependency prediction, and if there is a dependency on previous Store instructions, transferring the value between the Load instruction and the Store instruction on which it depends through register transfer, which can speed up the execution of Load and reduce the extra power consumption overhead caused by Store writing value files, reduce resource occupation caused by implementation, reduce execution power consumption, and further improve processor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention. DETAILED DESCRIPTION

[0020] See also Figure 1 The implementation method of storage renaming in this embodiment includes the following steps after instruction decoding and before register renaming:

[0021] 1) Determine the instruction type of the instruction obtained by decoding and whether storage renaming is required;

[0022] 2) If storage renaming is required and the instruction type is a Store instruction, the source register number of the Store instruction is written to the value file; if storage renaming is required and the instruction type is a Load instruction, storage dependency prediction is used to determine whether the Load instruction has a dependency on previous Store instructions. If there is a dependency on previous Store instructions, the value transfer between the Load instruction and the Store instruction on which it depends is performed by register transfer.

[0023] The method of this embodiment realizes the optimization of the content stored in the value file. Originally, the value file stores the data value of the Store instruction. In this embodiment, the source register number of the data to be stored by the Store instruction is stored in the value file. Originally, each item in the value file needs to store the data of the Store instruction, so the storage space of each item is at least 64 bits. In this embodiment, it is changed to the source register number of the Store instruction. For a microprocessor with 32 architecture registers, only 5 bits are needed. It should be noted that this embodiment does not include improvements to the storage dependency prediction method. The storage dependency prediction still adopts the method recorded in the prior art (Tyson, GS, Austin, TMMemory Renaming: Fast, Early and Accurate Processing of Memory Communication. International Journal of Parallel Programming 27, 357–380 (1999).), that is, the index of the value file is marked for all the data stored in the Store. If a certain Load bypasses the data from the Store, the data source of the Load is marked as the corresponding value file index. In addition, other methods for implementing dependency judgment between Load instructions and Store instructions can also be adopted as needed.

[0024] Step 1) determining the instruction type of the decoded instruction to determine whether the instruction is a Load instruction or a Store instruction.

[0025] If storage renaming is required and the instruction type is a Store instruction, the storage dependency predictor needs to be accessed through the PC of the instruction to perform storage dependency prediction to determine whether it is a Store instruction that requires storage renaming. If the Store instruction is predicted to require storage renaming, then the Store instruction is allocated an item in the value file and the item is written as the register number where the Store is stored.

[0026] An example sequence of Store and Load instructions is:

[0027] Store r2,[r1]

[0028] Load r4,[r3]

[0029] For example, according to the above Store and Load instruction sequence example, the Store instruction writes the value of the r2 register to the memory address pointed to by the r1 register. If the Store instruction is predicted to perform a storage rename, that is, the Store instruction needs to pass data to other Load instructions, then an item needs to be allocated in the value file and the register number r2 stored by the Store instruction is written to the allocated value file.

[0030] If storage renaming is required and the instruction type is a Load instruction, the value file index of the Store instruction on which it depends will be obtained from the storage dependency predictor. Then the value file item of the source Store instruction is read to obtain the source register of the Store instruction. For example, according to the above Store and Load instruction sequence example, the Load instruction obtains data from the memory pointed to by the r3 register and writes it to r4. If the storage dependency predictor predicts that the Load instruction has data dependency with the previous Store instruction, the Load instruction will obtain the source data register to be stored by the Store instruction from the value file of the Store instruction, and obtain r2 here. In other words, the Store instruction stores the data in the r2 register into the memory pointed to by the r1 register. The Load instruction needs to retrieve the data in the memory pointed to by r3 and store it in the r4 register. The storage dependency predictor predicts that the address stored by the Store instruction is the same as the address obtained by the Load instruction, so the data in the destination register r4 to be written by the Load instruction is the data of r2 to be stored by the Store instruction. The r2 register is obtained from the value file of the Store instruction, which means that the data that the Load instruction needs to obtain from the memory can be obtained.

[0031] See also Figure 1In step 2) of this embodiment, the value transfer between the Load instruction and the Store instruction on which it depends by register transfer includes splitting the original Load instruction into Move instructions, wherein the Move instruction is used to complete the function of the original Load instruction writing the destination register, the source operand of the Move instruction is the source register of the Store instruction on which it depends, and the destination operand is the destination register of the original Load instruction; the Move instruction is used to realize the result prediction function of the original Load instruction, and the value transfer between the original Load instruction and the Store instruction on which it depends is completed by directly obtaining data from the source register of the Store instruction on which it depends and writing it into the result register of the original Load instruction. The Move instruction uses the existing Move instruction path of the microprocessor to complete the data transfer process by reading the register. For the Store and Load instruction sequence example shown above, if it is predicted that storage renaming can be performed between Store and Load, then the Move instruction is Mover4, r2. The instructions in the subsequent instructions that depend on the result r4 register of the Load instruction are now changed to depend on the Move instruction, and the entire process is not related to the execution of the Store instruction, which improves the instruction execution process.

[0032] The Load instruction can perform a storage renaming operation. Since the storage renaming process is performed speculatively, in addition to writing the destination register of the Load instruction, it is also necessary to verify the result and correct the execution status. In step 2) of this embodiment, when the value between the Load instruction and the Store instruction it depends on is transferred by register transfer, it also includes the steps of verifying the result and correcting the execution status.

[0033] In order to achieve result verification and execution status correction, this embodiment splits the Load that can execute storage renaming into multiple instructions that can be executed in the existing pipeline, thereby reusing the existing instruction path and avoiding excessive area and power consumption overhead caused by implementing storage renaming. Figure 1 , the step of performing result verification and execution status correction includes splitting the Load instruction into the following instructions:

[0034] The Load0 instruction is used to complete the function of the original Load instruction and complete the test of storage dependency prediction. It is used to obtain data from the memory pointed to by the source register and then put it into the temporary register temp;

[0035] The Check instruction is used to compare the result of the storage dependency prediction with the result of the actual execution of the Load0 instruction. If the value of the destination register of the original Load instruction is equal to the value of the temporary register temp, it proves that the previous storage dependency prediction is correct. Otherwise, it is determined that the previous storage dependency prediction is wrong and the specific Move instruction is executed incorrectly, and the state will be restored.

[0036] In this embodiment, the Load0 instruction is used to complete the verification of the storage dependency prediction. The execution of the Load0 instruction is completely consistent with the execution path of the original Load instruction, and there is no need to modify the pipeline structure. The Load0 instruction completes the function of the original Load, obtains data from the memory pointed to by the source register, and then puts it into the temporary register temp, which is named Load0 to distinguish it from the original Load instruction. The temporary register is a register used for data transfer inside the microarchitecture and is invisible to the programmer. The Load0 instruction writes to this register and does not destroy the state of the architecture. For the Store and Load instruction sequence example shown above, if it is predicted that storage renaming can be performed between Store and Load, then the Load0 instruction is Load0 temp, [r3]. Since the prediction of storage dependency is not always correct, the Load0 instruction mainly completes the verification of storage dependency prediction. The execution of this instruction is completely consistent with the execution path of the original Load instruction, and there is no need to modify the pipeline structure.

[0037] In this embodiment, the temporary register temp is a register used for data transfer inside the micro-architecture and is invisible to the programmer. The Load0 instruction writes to the temporary register temp without destroying the state of the architecture.

[0038] In this embodiment, the Check instruction is a newly added instruction for checking the prediction result, and the data path of the Check instruction borrows the original path in the microprocessor. The Check instruction mainly completes the comparison of the result of the storage dependency prediction and the result of the actual execution of the Load0 instruction. If the values ​​of the r4 and temp registers are equal, it proves that the previous storage dependency prediction is correct. Otherwise, a prediction error of storage renaming is detected, that is, an execution error of the Move instruction is detected, and the state will be restored. The Check instruction is a newly added instruction to check the prediction result. The data path can borrow the original path, but the function needs to be added. The traditional method is to add a special check logic in the Load pipeline to perform prediction verification and state rollback. Here it is divided into a check instruction, and the existing path is borrowed for modification, which can simplify the implementation process and reduce resource consumption. For the Store and Load instruction sequence example shown above, if it is predicted that storage renaming can be performed between Store and Load, then the Check instruction is Check r4, temp.

[0039] In summary, for the Store and Load instruction sequence examples shown above, all instructions split by the Load instruction are:

[0040] Move r4,r2

[0041] Load0 temp, [r3]

[0042] Check r4,temp

[0043] See also Figure 1 In this embodiment, before instruction decoding, the step of fetching instructions is also included; after register renaming, the steps of instruction dispatching, instruction issuing, instruction execution and result writing back are also included. The complete execution process of the instruction includes:

[0044] S1. Fetch instruction.

[0045] Get the corresponding instruction from the memory or instruction cache.

[0046] S2, instruction decoding.

[0047] The acquired instructions are decoded according to the instruction set encoding format corresponding to the microprocessor. The decoded information includes: instruction operation code, data source of instruction operation, instruction destination register, etc.

[0048] S3. The aforementioned method of this embodiment.

[0049] S4. Register renaming.

[0050] The instruction register is renamed according to the register renaming method in a common microprocessor.

[0051] S5. Instruction dispatching.

[0052] Instructions are dispatched to the corresponding execution units in sequence and are generally cached in the corresponding instruction queues.

[0053] S6. Command transmission.

[0054] Once the operands for the instruction are ready and the execution unit is idle, the instruction can be issued.

[0055] S7. Instruction execution.

[0056] The function of executing the instruction is performed according to the original execution path in the instruction. For the three instructions split out in step S3, the Move and Load instructions can be directly completed by borrowing the execution path of the original processor. For the Check instruction, the original execution path needs to be borrowed and the corresponding function needs to be added. The execution of the Check instruction first needs to read data from two registers. One of the two data is the result predicted after storage renaming, that is, the result of the Move instruction; the other is the result obtained by the actual execution of the Load instruction, that is, the temporary register written by the Load0 instruction. Since both data are written into the register of the microprocessor, the register reading path of the original execution component can be borrowed. Then, the Check instruction needs to check whether the two data are equal. If they are equal, it proves that the predicted result of the storage renaming is correct, and the entire instruction execution ends. If they are not equal, then the prediction of the storage renaming is wrong, and all subsequent executions using the predicted result are wrong. At this time, the state needs to be rolled back and the execution result of the Load instruction needs to be corrected. There are many ways to roll back the state. One feasible way is to clear the pipeline starting from the Load instruction that performs storage renaming and re-fetch the instruction for execution. The Check instruction can send an exception signal to the processor control center, and the processor starts the restart process of the instruction through the exception signal. In order to correct the execution result of the Load instruction, the Check instruction writes the data of the temporary register written by the Load instruction to the result register of the Move instruction, completing the function of the original Load instruction. In this way, the original Load instruction does not need to be re-executed.

[0057] S8. Write back the result.

[0058] The result of instruction execution is written back to the corresponding register through the data bus.

[0059] In summary, the implementation method of the aforementioned storage renaming in this embodiment provides an optimized storage renaming implementation process, which reduces implementation overhead and dynamic power consumption and improves performance by passing register numbers instead of actual data between Store and Load. Storage renaming is implemented by borrowing the existing microprocessor pipeline path through instruction splitting, further simplifying the implementation process.

[0060] In addition, this embodiment also provides a microprocessor, including a value acquisition unit, a decoding unit, a register renaming unit, an instruction dispatch unit, an instruction issuance unit, an instruction execution unit and a write-back result unit. A storage renaming unit is arranged between the aforementioned decoding unit and the register renaming unit. The aforementioned storage renaming unit is programmed or configured to execute the steps of the aforementioned storage renaming implementation method.

[0061] In addition, this embodiment also provides a computer device, including a microprocessor and a memory connected to each other, the aforementioned microprocessor includes a value acquisition unit, a decoding unit, a register renaming unit, an instruction dispatching unit, an instruction issuing unit, an instruction execution unit and a write-back result unit, and a storage renaming unit is arranged between the aforementioned decoding unit and the register renaming unit, and the aforementioned storage renaming unit is programmed or configured to execute the steps of the aforementioned storage renaming implementation method.

[0062] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0063] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for implementing storage renaming, characterized in that: It includes the following steps after instruction decoding and before register renaming: 1) Determine the instruction type of the decoded instruction and whether storage renaming is required; 2) If storage renaming is required and the instruction type is a Store instruction, the source register number of the Store instruction is written to the value file; if storage renaming is required and the instruction type is a Load instruction, storage dependency prediction is used to determine whether the Load instruction has a dependency on previous Store instructions. If there is a dependency on previous Store instructions, the value transfer between the Load instruction and the Store instruction on which it depends is performed by register transfer; In step 2), the value transfer between the Load instruction and the Store instruction on which it depends by register transfer includes splitting the original Load instruction into Move instructions, wherein the Move instruction is used to complete the function of the original Load instruction writing the destination register, the source operand of the Move instruction is the source register of the Store instruction on which it depends, and the destination operand is the destination register of the original Load instruction; the Move instruction is used to implement the result prediction function of the original Load instruction, and the value transfer between the original Load instruction and the Store instruction on which it depends is completed by directly obtaining data from the source register of the dependent Store instruction and writing it into the result register of the original Load instruction. The Move instruction uses the existing Move instruction path of the microprocessor to complete the data transfer process by reading the register.

2. The method for implementing storage renaming according to claim 1, characterized in that: When the value transfer between the Load instruction and the Store instruction on which it depends is performed by register transfer in step 2), the steps of verifying the result and correcting the execution status are also included.

3. The method for implementing storage renaming according to claim 2, characterized in that: The step of performing result verification and execution status correction includes splitting the Load instruction into the following instructions: a Load0 instruction, which is used to complete the function of the original Load instruction and complete the verification of the storage dependency prediction, and is used to obtain data from the memory pointed to by the source register and then put it into the temporary register temp; The Check instruction is used to compare the result of the storage dependency prediction with the result of the actual execution of the Load0 instruction. If the value of the destination register of the original Load instruction is equal to the value of the temporary register temp, it proves that the previous storage dependency prediction is correct. Otherwise, it is determined that the previous storage dependency prediction is wrong and the specific Move instruction is executed incorrectly, and the state will be restored.

4. The method for implementing storage renaming according to claim 3, characterized in that: The Load0 instruction is used to complete the test of the storage dependency prediction. The execution path of the Load0 instruction is completely consistent with the original Load instruction execution path, and there is no need to modify the pipeline structure.

5. The method for implementing storage renaming according to claim 4, characterized in that: The temporary register temp is a register used for data transfer inside the microarchitecture and is invisible to the programmer. The Load0 instruction writes to the temporary register temp without destroying the state of the architecture.

6. The method for implementing storage renaming according to claim 5, characterized in that: The Check instruction is a newly added instruction for checking the prediction result, and the data path of the Check instruction uses the original path in the microprocessor.

7. The method for implementing storage renaming according to claim 1, characterized in that: Before the instruction decoding is performed, the method further includes the step of fetching instructions; after the register renaming, the method further includes the steps of instruction dispatching, instruction issuing, instruction executing and writing back results.

8. A microprocessor comprising a value fetching unit, a decoding unit, a register renaming unit, an instruction dispatching unit, an instruction issuing unit, an instruction executing unit and a write-back result unit, characterized in that: A storage renaming unit is provided between the decoding unit and the register renaming unit, and the storage renaming unit is programmed or configured to execute the steps of the storage renaming implementation method described in any one of claims 1 to 7.

9. A computer device comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor includes a value acquisition unit, a decoding unit, a register renaming unit, an instruction dispatching unit, an instruction issuing unit, an instruction execution unit and a write-back result unit. A storage renaming unit is arranged between the decoding unit and the register renaming unit. The storage renaming unit is programmed or configured to execute the steps of the storage renaming implementation method described in any one of claims 1 to 7.

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