A method and device for repairing dual-crystal memory using single-crystal memory

Abstract

The present application provides a method and device for repairing a dual-crystal memory with a single-crystal memory, including dividing the bad IC into an address line group and a position line group according to the bad area of ​​the bad IC; selecting at least two bad ICs in any group within the address line group and selecting at least one bad IC in the address line group, and dividing the IC position area of ​​the address line position in the bad IC according to the grouping of the bad IC and a preset rule; adjusting the layout of the PCB board of the ×16IC dual-crystal package according to the IC position area and the type of the bad IC. By using the bad IC of the ×8 single-crystal package shipped from the factory to repair the bad IC of the ×16 dual-crystal package, the bad IC is reorganized into a qualified product, which efficiently utilizes the bad products, saves resources, and is also beneficial to environmental protection to a certain extent.

Description

Technical Field

[0001] The present application relates to the field of memory chips, and in particular to a method and device for repairing a dual-crystal memory with a single-crystal memory. Background Art

[0002] Memory, also known as random access memory (RAM), also known as main memory, is an internal memory that directly exchanges data with the CPU. It can be read and written at any time (except when refreshed) and is very fast. It is usually used as a temporary data storage medium for operating systems or other running programs. When RAM is working, information can be written (stored) or read (retrieved) from any specified address at any time. The biggest difference between it and ROM is the volatility of data, that is, once the power is off, the stored data will be lost. RAM is used in computers and digital systems to temporarily store programs, data, and intermediate results.

[0003] However, memory manufacturers cannot achieve 100% good quality products during wafer production and IC packaging processes.

[0004] At present, the defective products produced by memory manufacturers are around 10~15%, resulting in a large amount of resource waste. Since precious metals are used in the memory IC and packaging process, if the defective products are destroyed, it will also cause further resource waste. The current extraction of precious metals through chemical methods will cause environmental pollution to a certain extent. Summary of the invention

[0005] In view of the above problems, the present application is proposed to provide a method and device for repairing a dual-crystal memory with a single-crystal memory to overcome the above problems or at least partially solve the above problems, including:

[0006] A method for repairing a dual-crystal memory with a single-crystal memory is applied to the repackaging of a defective IC in a ×8 single-crystal package and a defective IC in a ×16 dual-crystal package, comprising:

[0007] Divide the bad IC into an address line group and an address line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in bad ICs with ×16 dual-die package only, and the address line group is a group of bad address lines in bad ICs with ×8 single-die package only; wherein the address line group includes an A group with bad areas of only 0-3 bits, a B group with bad areas of only 4-7 bits, a C group with bad areas of only 8-11 bits, a D group with bad areas of only 12-15 bits, and an E group with bad areas of only 8-15 bits; the address line group includes a group with bad address lines BA0, BG1, and BG0;

[0008] Select at least two bad ICs in any group within the address line group and select at least one bad IC in the address line group, and divide the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule;

[0009] According to the IC location area and the type of the defective IC, the layout of the PCB board of the ×16 IC dual die package is adjusted.

[0010] Optionally, the step of dividing the bad IC into address line groups and bit line groups according to the bad area of ​​the bad IC includes:

[0011] When the address line is defective, it is divided into an address line group;

[0012] When the address line is defective, it is divided into address line groups.

[0013] Optionally, when the address line is defective, the step of dividing it into address line groups further includes:

[0014] Determine a bad region of address lines within the bad IC;

[0015] The bad areas of the address line bits are divided into groups of address line groups; wherein the address line groups include group A with bad areas of only 0-3 bits, group B with bad areas of only 4-7 bits, group C with bad areas of only 8-11 bits, group D with bad areas of only 12-15 bits and group E with bad areas of only 8-15 bits.

[0016] Optionally, the step of dividing the IC bit area of ​​the address line bits in the bad IC according to the grouping of the bad IC and a preset rule comprises:

[0017] Determining available address line bits in the bad IC according to the grouping of the bad IC;

[0018] The available address line bits in the bad IC are combined into the IC bit area according to the preset rule.

[0019] Optionally, the step of combining available address line bits in the bad IC into the IC bit area according to the preset rule comprises:

[0020] When the MDQ digital sequence of the PCB board is 64 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 8, and the IC bit area includes 8 available address line bits.

[0021] Optionally, the step of combining available address line bits in the bad IC into the IC bit area according to the preset rule comprises:

[0022] When the MDQ digital sequence of the PCB board is 32 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 4, and the IC bit area includes 8 available address line bits.

[0023] Optionally, the step of adjusting the layout of the PCB board of the ×16 IC single crystal package according to the IC location area and the type of the defective IC includes:

[0024] Determining the arrangement order of the bad ICs according to the IC position area;

[0025] Adjusting the layout of the PCB board according to the type of the bad IC and the arrangement order of the bad IC;

[0026] Wherein, the layout adjustment of the PCB board includes:

[0027] Set the resistors R26, R29, R31, R34, R73, R76, R80 and R83 on the PCB board of the ×16 IC single crystal package to 0 ohms;

[0028] Set the T7 pin of the PCB board to be empty;

[0029] Short-circuiting the first pin and the second pin of each of the PCB boards Y1 to Y4;

[0030] Connecting the N9 pin of the PCB board to the VSS pin of the PCB board;

[0031] Connect the DGB1 pin of the PCB board to the VCC pin of the PCB board.

[0032] Optionally, after the step of adjusting the layout of the PCB board of the ×16 IC single crystal package according to the IC location area and the type of the defective IC, the method further comprises:

[0033] Determining the packaging position of the bad IC according to the IC location area, the type of the bad IC and the laid-out PCB board;

[0034] The defective IC is packaged on the laid-out PCB board according to the packaging position.

[0035] A device for repairing a dual-crystal memory with a single-crystal memory is used for repackaging defective ICs in ×8 single-crystal packages and defective ICs in ×16 dual-crystal packages, comprising:

[0036] A grouping module, used for dividing the bad IC into an address line group and an address line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in bad ICs of ×16 dual-crystal package only, and the address line group is a group of bad address lines in bad ICs of ×8 single-crystal package only; wherein the address line group includes an A group whose bad area is only 0-3 bits, a B group whose bad area is only 4-7 bits, a C group whose bad area is only 8-11 bits, a D group whose bad area is only 12-15 bits, and an E group whose bad area is only 8-15 bits; the address line group includes a group whose address lines BA0, BG1 and BG0 are bad;

[0037] A selection module, used for selecting at least two bad ICs in any group within the address line group and selecting at least one bad IC in the address line group, and dividing the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule;

[0038] An adjustment module is used to adjust the layout of the PCB board of the ×16IC dual-die package according to the IC location area and the type of the defective IC

[0039] An electronic device comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of the above method when executed by the processor.

[0040] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described above are implemented.

[0041] This application has the following advantages:

[0042] In an embodiment of the present application, the bad IC is divided into an address line group and a bit line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in a bad IC of only ×16 dual-crystal package, and the address line group is a group of bad address lines in a bad IC of only ×8 single-crystal package; wherein the address line group includes an A group with bad areas of only 0-3 bits, a B group with bad areas of only 4-7 bits, a C group with bad areas of only 8-11 bits, a D group with bad areas of only 12-15 bits, and a The good area is only the E group of 8-15 bits; the address line group includes the group of bad address lines BA0, BG1 and BG0; select at least two bad ICs in any group within the address line group and select at least one bad IC in the address line group; divide the IC bit area of ​​the address line position in the bad IC according to the grouping of the bad IC and the preset rules; determine the arrangement order of the bad IC according to the IC bit area; adjust the layout of the PCB board of the ×16IC dual crystal package according to the type and arrangement order of the bad IC. By using the bad IC of the ×8 single crystal package shipped from the factory to repair the bad IC of the ×16 dual crystal package, so as to reorganize it into a qualified product, the bad products are efficiently used, resources are saved, and it is also beneficial to environmental protection to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the description of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a flowchart of a method for repairing a dual-crystal memory with a single-crystal memory provided by an embodiment of the present application;

[0045] Figure 2 It is a structural block diagram of a device for repairing a dual-crystal memory using a single-crystal memory provided by an embodiment of the present application;

[0046] Figure 3 It is a schematic diagram of the layout of a PCB of a ×16IC dual die package provided in an embodiment of the present application;

[0047] Figure 4 It is a schematic diagram of the layout of a PCB of a ×8IC single crystal package provided in an embodiment of the present application;

[0048] Figure 5 It is a structural diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objects, features and advantages of the present application more obvious and understandable, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0050] It should be noted that in any embodiment of the present invention, the SDP package of the memory is a package containing a die (here refers to a memory particle, that is, a memory IC), that is, SDP (Signle-Die Package), and the capacity is still the capacity of a memory particle. DDP is a package containing two dies, that is, DDP (Dual-Die Package), and the capacity is the capacity of two memory particles; of course, the DDP packaging method can also be understood as connecting two memory particles in parallel to expand the bit width. For example, two ×8 memory particles are packaged in DDP, and then the whole can be regarded as a ×16 memory particle. IC chip (Integrated Circuit Chip) is an integrated circuit formed by a large number of microelectronic components (transistors) placed on a plastic substrate to make a chip; Package, that is, packaging (circuit integration term) is the process of assembling integrated circuits into chip final products. Simply put, it is to put the integrated circuit die (die) produced by the foundry on a substrate that plays a bearing role, lead out the pins, and then fix the package into a whole.

[0051] Reference Figure 1-Figure 4 , shows a method for single crystal memory to repair dual crystal memory provided by an embodiment of the present application; it is applied to the repackaging of defective ICs in ×8 single crystal package and defective ICs in ×16 single crystal package;

[0052] The method comprises:

[0053] S110, dividing the bad IC into an address line group and an address line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in bad ICs with ×16 dual-die package only, and the address line group is a group of bad address lines in bad ICs with ×8 single-die package only; wherein the address line group includes an A group with bad areas of only 0-3 bits, a B group with bad areas of only 4-7 bits, a C group with bad areas of only 8-11 bits, a D group with bad areas of only 12-15 bits, and an E group with bad areas of only 8-15 bits; the address line group includes a group with bad address lines BA0, BG1, and BG0;

[0054] S120, selecting at least two bad ICs in any group within the address line group and selecting at least one bad IC in the address line group, and dividing the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule;

[0055] S130 , adjusting the layout of the PCB board of the ×16 IC dual die package according to the IC location area and the type of the defective IC.

[0056] In an embodiment of the present application, the bad IC is divided into an address line group and a bit line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in a bad IC of only ×16 dual-crystal package, and the address line group is a group of bad address lines in a bad IC of only ×8 single-crystal package; wherein the address line group includes an A group with bad areas of only 0-3 bits, a B group with bad areas of only 4-7 bits, a C group with bad areas of only 8-11 bits, a D group with bad areas of only 12-15 bits, and a The good area is only the E group of 8-15 bits; the address line group includes the group of bad address lines BA0, BG1 and BG0; select at least two bad ICs in any group within the address line group and select at least one bad IC in the address line group; divide the IC bit area of ​​the address line position in the bad IC according to the grouping of the bad IC and the preset rules; determine the arrangement order of the bad IC according to the IC bit area; adjust the layout of the PCB board of the ×16IC dual crystal package according to the type and arrangement order of the bad IC. By using the bad IC of the ×8 single crystal package shipped from the factory to repair the bad IC of the ×16 dual crystal package, so as to reorganize it into a qualified product, the bad products are efficiently used, resources are saved, and it is also beneficial to environmental protection to a certain extent.

[0057] It should be noted that in the present application, ×8IC means an IC with a particle width of 8 bits, and ×16IC means an IC with a particle width of 16 bits.

[0058] Next, the method of repairing the dual-die memory with the single-die memory in this exemplary embodiment will be further described.

[0059] As described in step S110, the bad IC is divided into an address line group and a bit line group according to the bad area of ​​the bad IC; wherein the address line group is a grouping of bad address lines in a bad IC with only ×16 dual-crystal package, and the address line group is a grouping of bad address lines in a bad IC with only ×8 single-crystal package; wherein the address line group includes a group A whose bad area is only 0-3 bits, a group B whose bad area is only 4-7 bits, a group C whose bad area is only 8-11 bits, a group D whose bad area is only 12-15 bits, and a group E whose bad area is only 8-15 bits; the address line group includes a grouping of bad address lines BA0, BG1 and BG0.

[0060] In an embodiment of the present application, the specific process of "dividing the bad IC into address line groups and bit line groups according to the bad area of ​​the bad IC" in step S110 can be further explained in combination with the following description.

[0061] As described in the following steps, when the address line is defective, it is divided into an address line group;

[0062] As described in the following steps, when the address line is defective, it is divided into address line groups.

[0063] It should be noted that the address line group is a grouping of bad address lines in bad ICs with ×16 dual-die packages, and the address line group is a grouping of bad address lines in bad ICs with ×8 single-die packages.

[0064] As an example, based on the results of pre-detection of the address lines in the bad ICs, the bad ICs are divided into group A, group B, group C, group D and group E; specifically, the bad area of ​​group A is only bits 0-3, the bad area of ​​group B is only bits 4-7, the bad area of ​​group C is only bits 8-11, the bad area of ​​group D is only bits 12-15 and the bad area of ​​group E is only bits 8-15.

[0065] As an example, the address line group includes a group of bad address lines BA0, BG1 and BG0.

[0066] In the above embodiment, bad ICs are grouped, such as group A, group B, group C, group D and group E of the address line group and the address line group, so that an optimized grouping method can be obtained by combining and matching in different ways, thereby obtaining a group matching repair solution.

[0067] In one embodiment of the present invention, before the step of dividing the bad IC into address line groups and bit line groups according to the bad area of ​​the bad IC, the step includes:

[0068] According to the type of the bad IC, determine the address line position of the corresponding normal IC;

[0069] According to the address line position of the normal IC, the address line of the bad IC is detected to determine the address line position of the bad area of ​​the bad IC.

[0070] In the above embodiment, for example, the bad bits in the "address line" or "address line" in the test chip can be tested by simulating a test fixture for a "memory stick" application and general memory chip test software (such as memtest / RST / self-developed software) for segmentation and classification; the memory IC can be tested by simulating a memory model to obtain the bad area of ​​the address line in the bad IC. For example, if the bad area is located in the 0-3 bits of the address line, the bad IC is divided into group A. If the detected bad area is located in the 4-7 bits of the address line, the bad IC is divided into group B, and so on to group C and group D. If the detected bad area is located in the 8-11 bits and 12-15 bits of the address line, it is divided into group E. By dividing into different groups and making different combinations, the maximum reuse of the bad IC is achieved.

[0071] It should be noted that memory IC is a type of IC. Due to its high precision, some defective products will be produced during the production of the package, and the defective products cannot be used directly. According to the working principle of the CPU and memory, the data transmission between the CPU and the memory is multiple bits at a time (the specific number of bits is determined by the data bit width matching the CPU and the memory). In the current mainstream PC, it is generally 8 bits, that is, the 8-bit address lines of the memory IC need to receive data at the same time, otherwise the data transmission cannot be completed. Therefore, if there are bad address line bits in the memory IC, the entire memory will be unusable. Similarly, the defective products of the memory IC manufacturer are not directly used in memory production. Through this solution, the defective IC can be reused to reduce waste, while also reducing the defective rate in memory production, greatly reducing the high cost caused by defective products.

[0072] As described in step S120, at least two bad ICs in any group within the address line group and at least one bad IC in the address line group are selected, and the IC bit area of ​​the address line bit in the bad IC is divided according to the grouping of the bad ICs and preset rules.

[0073] It should be noted that the IC bit area is a set of 8 address line bits of the same type, such as 0-7 of the LDQS type or 8-15 of the UDQS type.

[0074] In an embodiment of the present application, the specific process of "dividing the IC bit area of ​​the address line bits in the bad IC according to the grouping of the bad IC and the preset rule" in step S120 can be further explained in combination with the following description.

[0075] It should be noted that the available address line bits in the bad IC are grouped into the IC bit area according to the preset rule.

[0076] As described in the following steps, determining available address line bits in the bad IC according to the grouping of the bad IC;

[0077] As described in the following steps, the available address line bits in the bad IC are grouped into the IC bit area according to the preset rule.

[0078] As an example, the IC bit area is determined based on the 64-bit MDQ digit order and the available address line bits and address line bit types in the bad IC; wherein the number of the IC bit areas is 8, and the IC bit area includes 8 available address line bits.

[0079] It should be noted that through the MDQ digital sequence, the defective ICs are grouped together to form a 64-bit memory stick, which is used in current mainstream computers.

[0080] In a specific implementation, 4 of the bad ICs are arbitrarily selected from the group determined in the address line group, and 2 of the bad ICs are arbitrarily selected from the address line group (for example, group F); according to the 64-bit MDQ digital sequence, the address line bits are grouped in groups of 8 bits each, and the address line bits of the bad area are masked to determine the arrangement order of the available address line bits in the bad IC; the high bit is the 8-bit UDQS address line, and the low bit is the 8-bit LDQS address line.

[0081] The following will take the C grouping + F grouping scheme as an example, but the present application is not limited to the grouping combination of the C grouping + F grouping scheme; as shown in the following table:

[0082]

[0083] As shown in the table above, 4 bad ICs in C groups and 2 bad ICs in F groups are selected for solution matching, that is, two bad ICs in C groups and one bad IC in F group are combined twice; the following is the specific content of combining the bad ICs in 2 C groups and 1 bad IC in F group:

[0084] Since the bad area of ​​group C is only 8-11 bits, that is, the available address line bits of its group C are 0-7 bits and 12-15 bits, the 12-15 bits of the two C groups are combined into one IC bit area according to the type of address line bits and the proximity principle, and the remaining available address line bits of the two C groups are respectively used as an IC bit area, so that the address line bits of the same type are grouped; at the same time, based on the 64-bit MDQ digital order, the available address line bits in the F group are filled to 32 bits.

[0085] It should be noted that since the defective ICs in the F group are defective ICs in ×8 single crystal packages, there is no distinction between the types of address lines, ie, LDQL and UDQS, and therefore there is no need to consider the type of address lines.

[0086] It should be noted that in the complete memory there are address lines and bit lines, and the basic grouping unit of the memory is the IC, and the address lines and bit lines of the memory are provided by the IC, wherein Figure 3 As shown, the address lines of the IC are DQS0-DQS7; the address lines are A0-An of the IC, wherein the number of address line bits of the memory IC (i.e., the size of n) determines the capacity of the memory IC, for example, when n=11, the memory IC capacity is 128Mbit (i.e., 16MB), when n=12, the memory IC capacity is 256Mbit (32MB), when n=13, the memory IC capacity is 512Mbit (64MB), when n=14, the memory IC capacity is 1024Mbit (128MB), when n=15, the memory IC capacity is 2048Mbit (256MB), when n=16, the memory IC capacity is 4096Mbit (512MB); wherein the address lines also include BA0, BA1, and BG0.

[0087] As an example, the IC bit area is determined based on the 32-bit MDQ digital order and the available address line bits and address line bit types in the bad IC; wherein the number of the IC bit areas is 4, and the IC bit area includes 8 available address line bits.

[0088] It should be noted that 32-bit memory with the same circuit mode is also the same and can also be used in product applications based on the main control IC of the "ARM" architecture and "DSP" architecture.

[0089] It should be noted that the patching process of 32-bit memory is basically the same as that of 64-bit memory, except that the number of IC bit areas of 32-bit memory is half of that of 64-bit memory, that is, 4 IC bit areas; the rest refers to the above-mentioned patching process of 64-bit memory.

[0090] In an embodiment of the present application, the arrangement order of the bad ICs is determined according to the IC location area.

[0091] In an embodiment of the present application, the specific process of the step of "determining the arrangement order of the bad ICs according to the IC location area" can be further explained in combination with the following description.

[0092] As described in the following steps, the arrangement order of the defective ICs is determined according to the arrangement order of the IC bit areas.

[0093] As described in step S130, the layout of the PCB board of the ×16 IC single crystal package is adjusted according to the IC location area and the type of the defective IC.

[0094] In an embodiment of the present application, the specific process of "adjusting the layout of the PCB board of the ×16 IC single crystal package according to the IC location area and the type of the defective IC" in step S130 can be further explained in combination with the following description.

[0095] As described in the following steps, determining the arrangement order of the bad ICs according to the IC position area;

[0096] As described in the following steps, adjusting the layout of the PCB board according to the type of the bad IC and the arrangement order of the bad IC;

[0097] Wherein, the layout adjustment of the PCB board includes:

[0098] Set the resistors R26, R29, R31, R34, R73, R76, R80 and R83 on the PCB board of the ×16IC dual-die package to 240 ohms;

[0099] Short-circuiting the second pin and the third pin of each of the PCB boards Y1 to Y4;

[0100] Connect the T7 pin and the VSS pin of the PCB board;

[0101] Connect the DBG1 pin of the PCB board to the MBG1 pin of the PCB board.

[0102] In an embodiment of the present application, the specific process after step S130 of "adjusting the layout of the PCB board of the ×16 IC single crystal package according to the IC location area and the type of the defective IC" can be further explained in combination with the following description.

[0103] As described in the following steps, the packaging position of the bad IC is determined according to the IC location area, the type of the bad IC and the laid out PCB board;

[0104] As described in the following steps, the defective IC is packaged on the laid-out PCB board according to the packaging position.

[0105] It should be noted that all the "function ball positions" of the ×16IC are connected in series with the "function ball positions" of the ×8IC and then connected to the module function PIN.

[0106] As an example, based on the set PCB board and the bad IC with matched address lines, the address bus, data bus and control bus of the bad IC and the PCB board are connected to perform memory repair. Specifically, the LDQS of the bad IC corresponds to the LDQS position of the PCB board to be repaired; the UDQS of the bad IC corresponds to the UDQS of the PCB board to be repaired.

[0107] It should be noted that the PCB board is set up according to the JEDEC (Solid State Technology Association is the standard organization of the microelectronics industry) specifications; the classification of bad bits in defective IC chips and the re-circuit design of PCBs all use the "JEDEC" specifications as the principle of application design to avoid related "compatibility" and electrical problems.

[0108] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0109] A device for repairing a dual-crystal memory with a single-crystal memory provided by an embodiment of the present application is shown; it is applied to the repackaging of defective ICs in ×8 single-crystal packages and defective ICs in ×16 dual-crystal packages;

[0110] Specifically include:

[0111] The grouping module 210 is used to divide the bad IC into an address line group and an address line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in bad ICs with ×16 dual-die package only, and the address line group is a group of bad address lines in bad ICs with ×8 single-die package only; wherein the address line group includes an A group with bad areas of only 0-3 bits, a B group with bad areas of only 4-7 bits, a C group with bad areas of only 8-11 bits, a D group with bad areas of only 12-15 bits, and an E group with bad areas of only 8-15 bits; the address line group includes a group with bad address lines BA0, BG1, and BG0;

[0112] A selection module 220, configured to select at least two bad ICs in any group within the address line group and select at least one bad IC in the address line group, and divide the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule;

[0113] The adjustment module 230 is used to adjust the layout of the PCB board of the ×16 IC dual die package according to the IC location area and the type of the defective IC.

[0114] Reference Figure 5 , showing a computer device of a method of single-crystal memory repairing dual-crystal memory of the present invention, which may specifically include the following:

[0115] The computer device 12 is in the form of a general-purpose computing device, and the components of the computer device 12 may include but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0116] The bus 18 represents one or more of several types of bus 18 structures, including a memory bus 18 or memory controller, a peripheral bus 18, an accelerated graphics port, a processor, or a local bus 18 using any of a variety of bus 18 architectures. These architectures include, by way of example, but are not limited to, an Industry Standard Architecture (ISA) bus 18, a Micro Channel Architecture (MAC) bus 18, an Enhanced ISA bus 18, an Audio Video Electronics Standards Association (VESA) local bus 18, and a Peripheral Component Interconnect (PCI) bus 18.

[0117] The computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0118] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"). Although Figure 5 Not shown, a disk drive for reading and writing to a removable non-volatile disk (such as a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM or other optical medium) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory may include at least one program product having a set (e.g., at least one) of program modules 42, which are configured to perform the functions of various embodiments of the present invention.

[0119] A program / utility 40 having a set (at least one) of program modules 42 may be stored in, for example, a memory, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules 42, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0120] The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboards, pointing devices, displays 24, cameras, etc.), one or more devices that enable an operator to interact with the computer device 12, and / or any device that enables the computer device 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may be performed via an input / output (I / O) interface 22. Furthermore, the computer device 12 may also communicate with one or more networks (e.g., local area networks (LANs)), wide area networks (WANs), and / or public networks (e.g., the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with the other modules of the computer device 12 via a bus 18. It should be understood that although Figure 5 Not shown, other hardware and / or software modules may be used in conjunction with the computer device 12, including but not limited to: microcode, device drivers, processing unit 16, external disk drive arrays, RAID systems, tape drives, and data backup storage systems 34, etc.

[0121] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the method of repairing a dual-die memory with a single-die memory provided in an embodiment of the present invention.

[0122] That is, when the processing unit 16 executes the above program, it is achieved that: the bad IC is divided into an address line group and an address line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in a bad IC of only ×16 dual-crystal package, and the address line group is a group of bad address lines in a bad IC of only ×8 single-crystal package; wherein the address line group includes an A group with bad areas of only 0-3 bits, a B group with bad areas of only 4-7 bits, a C group with bad areas of only 8-11 bits, and a The domain is only a D group of 12-15 bits and the bad area is only an E group of 8-15 bits; the address line group includes a group of bad address lines BA0, BG1 and BG0; select at least two bad ICs in any group within the address line group and select at least one bad IC in the address line group, and divide the IC bit area of ​​the address line bits in the bad IC according to the grouping of the bad IC and preset rules; adjust the layout of the PCB board of the ×16IC dual-crystal package according to the IC bit area and the type of the bad IC.

[0123] In an embodiment of the present invention, the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method of repairing a dual-crystal memory with a single-crystal memory provided in all embodiments of the present application is implemented:

[0124] That is, when the program is executed by the processor, it is implemented as follows: dividing the bad IC into an address line group and a position line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in a bad IC of only ×16 dual crystal package, and the address line group is a group of bad address lines in a bad IC of only ×8 single crystal package; wherein the address line group includes an A group whose bad area is only 0-3 bits, a B group whose bad area is only 4-7 bits, a C group whose bad area is only 8-11 bits, a D group whose bad area is only 12-15 bits, and an E group whose bad area is only 8-15 bits; the address line group includes a group whose address lines BA0, BG1 and BG0 are bad; selecting at least two bad ICs in any group within the address line group and selecting at least one bad IC in the address line group, and dividing the IC position area of ​​the address line position in the bad IC according to the grouping of the bad IC and the preset rules; adjusting the layout of the PCB board of the ×16 IC dual crystal package according to the IC position area and the type of the bad IC.

[0125] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPOM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, device or device.

[0126] Computer-readable signal media may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0127] The computer program code for performing the operation of the present invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the operator's computer, partially on the operator's computer, as a separate software package, partially on the operator's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the operator's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet). The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

[0128] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0129] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0130] The above is a detailed introduction to the method and device for repairing dual-crystal memory with a single-crystal memory provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for repairing a dual-crystal memory with a single-crystal memory, characterized in that: Applied to the repackaging of defective ICs in ×8 single die package and ×16 dual die package, including: Divide the bad IC into an address line group and an address line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in bad ICs with ×16 dual-die package only, and the address line group is a group of bad address lines in bad ICs with ×8 single-die package only; wherein the address line group includes an A group with bad areas of only 0-3 bits, a B group with bad areas of only 4-7 bits, a C group with bad areas of only 8-11 bits, a D group with bad areas of only 12-15 bits, and an E group with bad areas of only 8-15 bits; the address line group includes a group with bad address lines BA0, BG1, and BG0; Select at least two bad ICs in any group within the address line group and select at least one bad IC in the address line group, and divide the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule; According to the IC location area and the type of the defective IC, the layout of the PCB board of the ×16 IC dual die package is adjusted.

2. The method according to claim 1, characterized in that The step of dividing the bad IC into address line groups and bit line groups according to the bad area of ​​the bad IC includes: When the address line is defective, it is divided into an address line group; When the address line is defective, it is divided into address line groups.

3. The method according to claim 2, characterized in that The step of dividing the address line into address line groups when the address line is defective also includes: Determine a bad region of address lines in the bad IC; The bad areas of the address line bits are divided into groups of address line groups; wherein the address line groups include group A with bad areas of only 0-3 bits, group B with bad areas of only 4-7 bits, group C with bad areas of only 8-11 bits, group D with bad areas of only 12-15 bits and group E with bad areas of only 8-15 bits.

4. The method according to claim 1, characterized in that The step of dividing the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad IC and the preset rule comprises: Determining available address line bits in the bad IC according to the grouping of the bad IC; The available address line bits in the bad IC are combined into the IC bit area according to the preset rule.

5. The method according to claim 4, characterized in that The step of combining the available address line bits in the bad IC into the IC bit area according to the preset rule comprises: When the MDQ digital sequence of the PCB board is 64 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 8, and the IC bit area includes 8 available address line bits.

6. The method according to claim 4, characterized in that The step of combining the available address line bits in the bad IC into the IC bit area according to the preset rule comprises: When the MDQ digital sequence of the PCB board is 32 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 4, and the IC bit area includes 8 available address line bits.

7. The method according to claim 1, characterized in that After the step of adjusting the layout of the PCB board of the ×16 IC single crystal package according to the IC location area and the type of the defective IC, the method further comprises: Determining the packaging position of the bad IC according to the IC location area, the type of the bad IC and the laid-out PCB board; The defective IC is packaged on the laid-out PCB board according to the packaging position.

8. A device for repairing a dual-crystal memory with a single-crystal memory, characterized in that: Applied to the repackaging of defective ICs in ×8 single die package and ×16 dual die package, including: A grouping module, used for dividing the bad IC into an address line group and an address line group according to the bad area of ​​the bad IC; wherein the address line group is a group of bad address lines in bad ICs of ×16 dual-crystal package only, and the address line group is a group of bad address lines in bad ICs of ×8 single-crystal package only; wherein the address line group includes an A group whose bad area is only 0-3 bits, a B group whose bad area is only 4-7 bits, a C group whose bad area is only 8-11 bits, a D group whose bad area is only 12-15 bits, and an E group whose bad area is only 8-15 bits; the address line group includes a group whose address lines BA0, BG1 and BG0 are bad; A selection module, used for selecting at least two bad ICs in any group within the address line group and selecting at least one bad IC in the address line group, and dividing the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule; The adjustment module is used to adjust the layout of the PCB board of the ×16 IC dual-die package according to the IC location area and the type of the defective IC.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method according to any one of claims 1 to 7 when executed by the processor.

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