Semiconductor structure and method of forming the same, film deposition method
By forming an isolation layer with doped elements on the inner wall of the via in a semiconductor structure, the density is increased, which solves the problem of short lifespan of semiconductor structures, reduces manufacturing costs, and increases machine productivity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-11-24
- Publication Date
- 2026-06-09
AI Technical Summary
In existing technologies, semiconductor structures used to reduce loading effects have short lifespans, complex manufacturing processes, and high costs, leading to increased production costs for semiconductor devices and reduced machine capacity.
An isolation layer doped with elements is formed on the inner wall of the via in a semiconductor structure to increase the density of the isolation layer. The doping elements reduce the oxidation probability and improve the etching selectivity, thereby enhancing the durability of the isolation layer.
This extends the lifespan of semiconductor structures, reduces manufacturing costs, and increases machine productivity.
Smart Images
Figure CN114121608B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its formation method, and a film deposition method. Background Technology
[0002] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, limitations of existing development technologies, and limits of storage electron density. Against this backdrop, in order to solve the difficulties encountered by planar flash memory and to pursue lower production costs per unit of storage cell, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D NAND) flash memory and 3D NAND (3D NAND) flash memory.
[0003] Film deposition is a crucial step in the manufacturing of semiconductor devices such as 3D NAND flash memory. When depositing film on a batch of wafers in a furnace, to mitigate the impact of the loading effect on the quality of the deposited film, a semiconductor structure designed to reduce the loading effect is placed in addition to the wafers in the furnace. However, current semiconductor structures used to reduce the loading effect have short lifespans, and their manufacturing processes are complex and costly. This undoubtedly increases the film deposition cost of the wafers and reduces the throughput of semiconductor equipment.
[0004] Therefore, how to improve the lifespan of semiconductor structures and thus reduce the manufacturing cost of semiconductor devices is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This invention provides a semiconductor structure and its formation method, as well as a film deposition method, to solve the problem of short service life of semiconductor structures in the prior art, thereby reducing the manufacturing cost of semiconductor devices and increasing the production capacity of semiconductor equipment.
[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:
[0007] A substrate is formed, the substrate including a substrate, a dielectric layer on the substrate, and a first via in the dielectric layer;
[0008] An isolation layer comprising doped elements is formed on the inner wall of the first via, wherein the doped elements are used to increase the density of the isolation layer.
[0009] Optionally, the first through-hole is a channel hole; the specific steps for forming the substrate include:
[0010] Provide a substrate;
[0011] A dielectric layer is formed on the substrate, the dielectric layer comprising a sacrificial layer and an interlayer insulating layer stacked in a direction perpendicular to the substrate;
[0012] The channel hole is formed through the dielectric layer.
[0013] Optionally, the specific steps for forming an isolation layer including doped elements on the inner wall of the first via include:
[0014] A mixed gas comprising a reactive gas and a dopant source gas is transmitted into the first via, wherein the reactive gas is used to form the isolation layer and the dopant source gas is used to form the dopant element.
[0015] Optionally, the doped source gas accounts for 1% to 30% of the volume percentage in the mixed gas.
[0016] Optionally, the material of the isolation layer is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer.
[0017] Optionally, the material of the isolation layer is polycrystalline silicon, and the doping element is carbon.
[0018] Optionally, the isolation layer is a single-layer structure; or,
[0019] The isolation layer includes a plurality of sub-isolation layers stacked along the radial direction of the first via, and the doping element is capable of increasing the density of at least the outermost sub-isolation layer.
[0020] To address the above problems, the present invention also provides a semiconductor structure, comprising:
[0021] The substrate includes a substrate, a dielectric layer on the substrate, and a first via in the dielectric layer;
[0022] An isolation layer is provided, covering the inner wall of the first via, and the isolation layer includes a doping element, which is used to increase the density of the isolation layer.
[0023] Optionally, the dielectric layer includes a sacrificial layer and an interlayer insulating layer stacked in a direction perpendicular to the substrate;
[0024] The first through hole is a channel hole that penetrates the dielectric layer.
[0025] Optionally, the isolation layer is a single-layer structure; or,
[0026] The isolation layer includes a plurality of sub-isolation layers stacked along the radial direction of the first via, and the doping element is capable of increasing the density of at least the outermost sub-isolation layer.
[0027] Optionally, the material of the isolation layer is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer.
[0028] Optionally, the material of the isolation layer is polycrystalline silicon, and the doping element is carbon.
[0029] To address the above problems, the present invention also provides a film deposition method, comprising the following steps:
[0030] A semiconductor structure is formed, the semiconductor structure including a substrate, the substrate including a substrate, a dielectric layer on the substrate, and a first via in the dielectric layer, the inner wall of the first via being covered by an isolation layer, the isolation layer including a dopant element, the dopant element being used to increase the density of the isolation layer;
[0031] A batch of wafers to be processed and several semiconductor structures are placed in a reaction chamber, wherein the wafers to be processed include a second through-hole;
[0032] Simultaneously, the functional layer is formed on the inner wall of the second through hole and on the surface of the isolation layer;
[0033] The functional layer on the surface of the isolation layer is removed, exposing the semiconductor structure of the isolation layer for placement in the reaction chamber along with the next batch of wafers to be processed.
[0034] Optionally, the specific steps for removing the functional layer from the surface of the isolation layer include:
[0035] The functional layer is removed using a wet etching process.
[0036] Optionally, the functional layer can be a single-layer or multi-layer structure, and the doping element can further increase the etching selectivity ratio between the isolation layer and each layer in the functional layer.
[0037] Optionally, the material of the isolation layer is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer.
[0038] Optionally, the material of the isolation layer is polycrystalline silicon, and the doping element is carbon.
[0039] The semiconductor structure and its formation method and film deposition method provided by the present invention, by setting an isolation layer including doped elements, increase the density of the isolation layer by the doped elements, thereby reducing the probability of the isolation layer being oxidized by oxygen in the air, so as to reduce or even avoid damage to the isolation layer by subsequent processing, thereby improving the lifespan of the semiconductor structure that can be reused, reducing the manufacturing cost of semiconductor devices, and increasing the production capacity of semiconductor equipment. Attached Figure Description
[0040] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of the present invention;
[0041] Appendix Figure 2A-2B This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to a specific embodiment of the present invention;
[0042] Appendix Figure 3 This is a schematic diagram of the semiconductor structure in a specific embodiment of the present invention;
[0043] Appendix Figure 4 This is a flowchart of the film deposition method in a specific embodiment of the present invention;
[0044] Appendix Figures 5A-5E This is a cross-sectional schematic diagram of a specific embodiment of the present invention during the film deposition process;
[0045] Appendix Figure 6 This is a schematic diagram of the internal structure of the reaction chamber during the film deposition process;
[0046] Appendix Figures 7A-7B These are electron microscope images of the isolation layer before and after etching using existing technology;
[0047] Appendix Figure 8 This is a schematic diagram showing the relationship between different concentrations of doping elements and the grain size of the isolation layer in a specific embodiment of the present invention. Detailed Implementation
[0048] The specific embodiments of the semiconductor structure and its formation method and film deposition method provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0049] like Figure 6 This is a schematic diagram of the internal structure of the reaction chamber during the film deposition process. (Example:) Figure 6 To improve film deposition quality, in addition to placing a batch of product wafers 53 in the film deposition chamber 50, a semiconductor structure 52 for reducing loading effects is also placed. The semiconductor structure 52 has vias and an isolation layer covering the inner wall of the vias. The inner wall of the vias in the semiconductor structure 52 undergoes film deposition simultaneously with the product wafers 53. After the film deposition process is completed, the film layer formed on the inner wall of the vias is removed, thereby enabling the reuse of the semiconductor structure 52. The presence of the isolation layer prevents damage to the morphology of the vias or the semiconductor structure 52 when removing the film layer from the inner wall of the vias. The inventors of this invention have discovered that removing the film layer from the inner wall of the vias damages the isolation layer, thereby reducing the number of times the semiconductor structure 52 can be reused, i.e., reducing the lifespan of the semiconductor structure. Figures 7A-7BThese are electron microscope (EM) images of the isolation layer before and after etching using existing techniques. For example... Figure 7A and Figure 7B As shown, after the semiconductor structure 52 is reused several times, the etching process will damage the isolation layer and the via sidewalls of the semiconductor structure 52. However, the production of the semiconductor structure 52 also requires semiconductor equipment and the use of various semiconductor materials. The shortened lifespan of the semiconductor structure 52 will undoubtedly increase the production cost of semiconductor devices and reduce the wafer processing capacity of the semiconductor equipment.
[0050] To improve the lifespan of semiconductor structures and reduce the production cost of semiconductor devices, this specific embodiment provides a method for forming a semiconductor structure, with appended details. Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of the present invention. Figure 2A-2B This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to a specific embodiment of the present invention. For example... Figure 1 , Figures 2A-2B As shown, the method for forming the semiconductor structure includes the following steps:
[0051] Step S11, forming a substrate, the substrate including a substrate 20, a dielectric layer 21 located on the substrate 20, and a first via 22 located in the dielectric layer 21, such as Figure 2A As shown.
[0052] Optionally, the first through-hole 22 is a channel hole; the specific steps for forming the substrate include:
[0053] Provide a substrate 20;
[0054] A dielectric layer 21 is formed on the substrate 20, the dielectric layer 21 including a sacrificial layer and an interlayer insulating layer stacked in a direction perpendicular to the substrate 20;
[0055] The channel hole is formed through the dielectric layer 21.
[0056] Specifically, the substrate 20 can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc. In this specific embodiment, the substrate 20 is preferably a Si substrate, used to support the device structure thereon. The dielectric layer 21 includes the sacrificial layer and the interlayer insulating layer alternately stacked along a direction perpendicular to the top surface of the substrate 20 (i.e., the direction from the substrate 20 to the dielectric layer 21). The first via is a channel hole penetrating the dielectric layer 21 along a direction perpendicular to the top surface of the substrate 20. The material of the sacrificial layer can be, but is not limited to, a nitride material (e.g., silicon nitride), and the material of the interlayer insulating layer can be, but is not limited to, an oxide material (e.g., silicon dioxide).
[0057] This specific embodiment is illustrated using the example of a multi-layered dielectric layer 21 and the first through-hole 22 penetrating through the dielectric layer 21. In other embodiments, the dielectric layer 21 may also be a single-layered structure, and the first through-hole 22 may not penetrate the dielectric layer 21.
[0058] Step S12: An isolation layer 23 comprising doped elements is formed on the inner wall of the first via 22. The doped elements are used to increase the density of the isolation layer 23, such as... Figure 2B As shown.
[0059] The density refers to the percentage of volume occupied by atoms within a unit cell, that is, the ratio of the volume of atoms contained in the unit cell to the volume of the unit cell. In this specific embodiment, by increasing the density of the isolation layer 23, on the one hand, the probability of the isolation layer 23 being oxidized by oxygen in the air can be reduced, thereby ensuring the performance and structural stability of the semiconductor structure; on the other hand, the high density of the isolation layer 23 can effectively prevent etching reagents used in subsequent processes (e.g., the etchant used to remove the functional layer on the surface of the isolation layer 23) from damaging the patterned structure in the semiconductor structure (e.g., the first via 22 in the semiconductor structure), which is equivalent to increasing the etching selectivity between the isolation layer 23 and the functional layer subsequently formed on the surface of the isolation layer 23. Both of these effects can improve the lifespan of the semiconductor structure, thereby reducing the manufacturing cost of semiconductor devices and increasing the wafer throughput of semiconductor processing equipment.
[0060] The isolation layer 23 can be deposited using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Optionally, the specific steps for forming the isolation layer 23, which includes doped elements, on the inner wall of the first through-hole 22 include:
[0061] A mixed gas comprising a reactive gas and a dopant source gas is transmitted into the first via 22, wherein the reactive gas is used to form the isolation layer 23 and the dopant source gas is used to form the dopant element.
[0062] For example, when forming the isolation layer 23 using a chemical vapor deposition process, the reactive gas and the dopant source gas can be simultaneously transported into the first via 22. The reactive gas undergoes a chemical reaction to generate the isolation layer 23, which covers the inner wall of the first via 22 and the top surface of the dielectric layer 21 (i.e., the surface of the dielectric layer 21 facing away from the substrate 20). Simultaneously, the dopant source gas, through plasma treatment, generates a dopant element that is then incorporated into the isolation layer 23, forming the isolation layer 23 with the dopant element. Those skilled in the art can select the specific type of dopant element according to actual needs, such as based on the material of the isolation layer 23. This specific embodiment does not impose specific limitations on this, as long as it increases the density of the isolation layer 23.
[0063] The proportion of the dopant source gas in the mixed gas should not be too high. This is because the first via 22 in the semiconductor structure has a high aspect ratio, and an excessively high proportion of the dopant source gas will affect the adhesion of the isolation layer 23 to the inner wall of the first via 22 (especially the bottom of the first via 22), thus causing the isolation layer 23 to not fully cover the inner wall of the first via 22. Optionally, the volume percentage of the dopant source gas in the mixed gas is 1% to 30%.
[0064] Optionally, the material of the isolation layer 23 is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer 23.
[0065] Optionally, the material of the isolation layer 23 is polycrystalline silicon, and the doping element is carbon.
[0066] The following description uses polycrystalline silicon as the material of the isolation layer 23, carbon as the dopant element, and C2H4 as the dopant source gas as an example. After the reactant gas is transported into the first through-hole 22, amorphous silicon is generated, and the dopant element generated by the dopant source gas is incorporated into the amorphous silicon. Subsequently, the amorphous silicon is crystallized to form the isolation layer 23, which contains the dopant element and is made of polycrystalline silicon. During the formation of the isolation layer 23, the grain size of the final polycrystalline silicon can be adjusted by changing the proportion of the dopant source gas in the mixed gas. (Appendix) Figure 8 This is a schematic diagram illustrating the relationship between different concentrations of doping elements and the grain size of the isolation layer in a specific embodiment of the present invention. For example, as... Figure 8As shown, when the volume percentage of the dopant source gas in the mixed gas is 0 (i.e., when the dopant source gas is not present), the resulting polycrystalline silicon grain size is 314 nm; when the volume percentage of the dopant source gas in the mixed gas is 2%, the resulting polycrystalline silicon grain size is 278 nm; when the volume percentage of the dopant source gas in the mixed gas is 10%, the resulting polycrystalline silicon grain size is 67 nm; and when the volume percentage of the dopant source gas in the mixed gas is 20%, the resulting polycrystalline silicon grain size is 19 nm. This is because the dopant element (e.g., carbon) can slow down the deposition rate of the isolation layer 23 (e.g., silicon film), thereby reducing the size of the grains (e.g., polycrystalline silicon grains) in the isolation layer 23 and increasing the density of the isolation layer (e.g., polycrystalline silicon film).
[0067] This specific embodiment uses carbon as the dopant element as an example for illustration. Because carbon has weak diffusion properties, it can prevent carbon from diffusing into the dielectric layer 21. In other specific embodiments, those skilled in the art can also select other elements as the dopant element according to actual needs.
[0068] Optionally, the isolation layer 23 is a single-layer structure; or,
[0069] The isolation layer 23 includes a plurality of sub-isolation layers stacked along the radial direction of the first through-hole 33, and the doping element can at least increase the density of the outermost sub-isolation layer.
[0070] Specifically, the isolation layer 23 can be a single-layer structure, thereby simplifying the manufacturing process of the isolation layer. The doping element is used to increase the density of the single-layer isolation layer 23. Alternatively, the isolation layer 23 can be a multi-layer structure, that is, the isolation layer 23 includes a plurality of sub-isolation layers stacked sequentially along the inner wall of the first through hole 22 towards the center of the first through hole 22 (i.e., the radial direction). The doping element can be doped into one or more of the sub-isolation layers, thereby at least increasing the density of the outermost sub-isolation layer (i.e., the sub-isolation layer furthest from the inner wall of the first through hole 22 in the radial direction). When the isolation layer 23 includes multiple sub-isolation layers, the materials of the multiple sub-isolation layers can be different, and the protection of the sidewall of the first through hole 22 is enhanced by the multiple sub-isolation layers. In this specific embodiment, "multiple" refers to two or more.
[0071] Furthermore, this specific embodiment also provides a semiconductor structure. (See attached document) Figure 3This is a schematic diagram of a semiconductor structure according to a specific embodiment of the present invention. The semiconductor structure provided in this specific embodiment can be adopted as follows: Figure 1 , Figures 2A-2B The semiconductor structure shown is formed using the method described. Figure 3 As shown, the semiconductor structure includes:
[0072] The substrate includes a substrate 20, a dielectric layer 21 located on the substrate 20, and a first via 22 located in the dielectric layer 21;
[0073] An isolation layer 23 covers the inner wall of the first through-hole 22. The isolation layer 23 includes doping elements, which are used to increase the density of the isolation layer 23.
[0074] Optionally, the dielectric layer 21 includes a sacrificial layer and an interlayer insulating layer stacked alternately in a direction perpendicular to the substrate 20 (the alternately stacked sacrificial layer and interlayer insulating layer are not shown in the figure);
[0075] The first through hole 22 is a channel hole, and the channel hole penetrates the dielectric layer 21.
[0076] Optionally, the isolation layer 23 is a single-layer structure; or,
[0077] The isolation layer 23 includes a plurality of sub-isolation layers stacked along the radial direction of the first through-hole 22, and the doping element can at least increase the density of the outermost sub-isolation layer.
[0078] Optionally, the material of the isolation layer 23 is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer 23.
[0079] Optionally, the material of the isolation layer 23 is polycrystalline silicon, and the doping element is carbon.
[0080] Furthermore, this invention also provides a method for film deposition. (See attached document.) Figure 4 This is a flowchart of the film deposition method in a specific embodiment of the present invention, attached. Figures 5A-5E This is a cross-sectional schematic diagram of a specific embodiment of the present invention during the film deposition process, attached. Figure 6 This is a schematic diagram of the internal structure of the reaction chamber during the film deposition process in a specific embodiment of the present invention. The semiconductor structure in this specific embodiment can adopt, for example... Figure 1 , Figures 2A-2B The semiconductor structure shown is formed by the method described in this specific embodiment. A schematic diagram of the semiconductor structure described in this embodiment can be found in [reference needed]. Figure 3 .like Figure 1 , Figures 2A-2B , Figure 3 , Figures 5A-5E as well as Figure 6 As shown, the film deposition method includes the following steps:
[0081] Step S41: Forming a semiconductor structure 52, the semiconductor structure 52 including a substrate, the substrate including a substrate 20, a dielectric layer 21 located on the substrate 20, and a first via 22 located in the dielectric layer 21, the inner wall of the first via 22 being covered by an isolation layer 23, such as... Figure 5A As shown, the isolation layer 23 includes doping elements, which are used to increase the density of the isolation layer 23;
[0082] Step S42: Place a batch of wafers 53 to be processed and several semiconductor structures 52 in the reaction chamber 50, wherein the wafers 53 to be processed include a second through-hole;
[0083] Step S43, simultaneously forming the functional layer 60 on the inner wall of the second through hole and the surface of the isolation layer 23, such as... Figure 5B As shown;
[0084] Step S44, remove the functional layer 60 from the surface of the isolation layer 23, such as Figure 5C As shown, the semiconductor structure exposing the isolation layer 23 is used to be placed in the reaction chamber 50 together with the next batch of wafers to be processed.
[0085] Specifically, the reaction chamber 50 can be a furnace tube chamber. The reaction chamber 50 has at least two support pillars 51, each with a wafer slot for accommodating a wafer. To reduce the impact of loading effects on the film deposition process of the wafer 53 to be processed, the wafer 53 to be processed is placed in the middle of the reaction chamber 50, and the semiconductor structure 52 is placed at the bottom and top of the reaction chamber (i.e., the semiconductor structure 52 is placed at opposite ends of a batch of wafers 53 to be processed), as shown in Figure 5.
[0086] After the film deposition process in the reaction chamber 50 is completed, the wafer 53 to be processed enters the next processing flow. The functional layer 60 generated in the semiconductor structure 52 is removed, exposing the isolation layer 23 on the inner wall of the first via 22. This allows the semiconductor structure 52 to enter the reaction chamber 50 with the next batch of wafers to be processed during the next film deposition process, thereby reducing the loading effect in the film deposition process of the next batch of wafers to be processed, i.e., cyclical processing. Figures 5A-5C The steps. After performing multiple times, as... Figures 5A-5C After the cyclic steps, the thickness of the isolation layer 23 may become thinner or the structure of the isolation layer 23 may be damaged. In this case, the isolation layer 23 can be removed by an etching process, such as... Figure 5DAs shown. Then, the isolation layer 23 is formed again on the inner wall of the first through-hole 22 of the semiconductor structure 52, as shown. Figure 5E As shown, to perform again as Figures 5A-5C The cyclical steps.
[0087] This specific embodiment increases the density of the isolation layer 23, which on the one hand reduces the probability of the isolation layer 23 being oxidized by oxygen in the air, thereby ensuring the performance and structural stability of the semiconductor structure; on the other hand, it effectively prevents the etchant used to remove the functional layer 60 from damaging the inner wall of the first via 22. Furthermore, the doping element also improves the etch selectivity between the isolation layer 23 and the functional layer 60, reducing the probability of the isolation layer 23 being removed by the etchant used to etch the functional layer 60. These three aspects all contribute to improving the lifespan of the semiconductor structure, thereby reducing the manufacturing cost of semiconductor devices and increasing the wafer throughput of semiconductor processing equipment.
[0088] Optionally, the specific steps for removing the functional layer 60 from the surface of the isolation layer 23 include:
[0089] The functional layer 60 is removed using a wet etching process.
[0090] In other specific embodiments, those skilled in the art may also select dry etching process or other processes to remove the functional layer 60 according to actual needs.
[0091] Optionally, the functional layer 60 may be a single-layer or multi-layer structure, and the doping element may further increase the etching selectivity ratio between the isolation layer 23 and each layer of the functional layer 60.
[0092] Optionally, the material of the isolation layer 23 is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer 23.
[0093] Optionally, the material of the isolation layer 23 is polycrystalline silicon, and the doping element is carbon.
[0094] For example, the first via 22 can be a channel via, and the functional layer 60 includes at least an electron blocking layer (material can be an oxide material, such as silicon dioxide) covering the surface of the isolation layer 23, an electron trapping layer (material can be a nitride material, such as silicon nitride) covering the surface of the electron blocking layer, and a tunneling layer (material can be an oxide material, such as silicon dioxide) covering the surface of the electron trapping layer, that is, the functional layer 60 forms an ONO structure. Doping with carbon (i.e., the dopant element) can improve the etching selectivity between the polysilicon layer (i.e., the isolation layer 23) and the ONO structure, and increase the density of the polysilicon layer, thereby reducing the probability of damage to the polysilicon layer during etching of the ONO structure. Furthermore, carbon doping can reduce the deposition rate of polysilicon, increase the density of polysilicon, and reduce the probability of polysilicon being oxidized by oxygen in the air.
[0095] This specific implementation method is illustrated using the functional layer 60 as an ONO structure as an example.
[0096] The semiconductor structure and its formation method, as well as the film deposition method provided in this specific embodiment, by incorporating an isolation layer including doped elements, increases the density of the isolation layer. This reduces the probability of the isolation layer being oxidized by oxygen in the air and also increases the etching selectivity between the isolation layer and the functional layer subsequently formed on the surface of the isolation layer. Consequently, damage to the isolation layer can be reduced or even avoided during the removal of the functional layer. Both of these aspects contribute to improving the reusability of the semiconductor structure, reducing the manufacturing cost of semiconductor devices, and increasing the throughput of semiconductor equipment.
[0097] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for forming a semiconductor structure, the semiconductor structure being placed simultaneously in a reaction chamber with a batch of wafers to be processed, the wafers to be processed including a second through-hole; characterized in that, The method for forming the semiconductor structure includes the following steps: A substrate is formed, the substrate including a substrate, a dielectric layer located on the substrate, and a first via penetrating the dielectric layer; An isolation layer comprising doped elements is formed on the inner wall of the first via and on the surface of the dielectric layer opposite to the substrate. The isolation layer directly covers the surface of the dielectric layer exposed in the first via. The doped elements are used to increase the density of the isolation layer. The material of the isolation layer includes polycrystalline silicon, and the doped elements include carbon. Simultaneously, a functional layer is formed on the inner wall of the second through hole and on the surface of the isolation layer; Remove the functional layer from the surface of the isolation layer to expose the isolation layer.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first through-hole is a channel hole; the specific steps for forming the substrate include: Provide a substrate; A dielectric layer is formed on the substrate, the dielectric layer comprising sacrificial layers and interlayer insulating layers alternately stacked in a direction perpendicular to the substrate; The channel hole is formed through the dielectric layer.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming an isolation layer including doped elements on the inner wall of the first via include: A mixed gas comprising a reactive gas and a dopant source gas is transmitted into the first via, wherein the reactive gas is used to form the isolation layer and the dopant source gas is used to form the dopant element.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, The dopant source gas accounts for 1% to 30% of the volume percentage in the mixed gas.
5. The method for forming a semiconductor structure according to claim 1, characterized in that, The isolation layer is made of a crystalline material, and the doping elements are used to reduce the grain size of the isolation layer.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The isolation layer is a single-layer structure; or... The isolation layer includes a plurality of sub-isolation layers stacked along the radial direction of the first via, and the doping element is capable of increasing the density of at least the outermost sub-isolation layer.
7. A semiconductor structure for simultaneous placement in a reaction chamber with a batch of wafers to be processed, the wafers to be processed including a second through-hole; characterized in that, The semiconductor structure includes: The substrate includes a substrate, a dielectric layer on the substrate, and a first via through the dielectric layer; An isolation layer covers the inner wall of the first via and the surface of the dielectric layer facing away from the substrate. The isolation layer directly covers the surface of the dielectric layer exposed in the first via. The isolation layer includes doping elements to increase the density of the isolation layer. The material of the isolation layer includes polycrystalline silicon, and the doping elements include carbon. A functional layer is formed simultaneously on the surface of the isolation layer and the inner wall of the second via. After the film deposition process is completed, the functional layer on the surface of the isolation layer is removed, exposing the isolation layer.
8. The semiconductor structure according to claim 7, characterized in that, The dielectric layer includes sacrificial layers and interlayer insulating layers that are alternately stacked in a direction perpendicular to the substrate; The first through hole is a channel hole, which penetrates the dielectric layer.
9. The semiconductor structure according to claim 7, characterized in that, The isolation layer is a single-layer structure; or... The isolation layer includes a plurality of sub-isolation layers stacked along the radial direction of the first via, and the doping element is capable of increasing the density of at least the outermost sub-isolation layer.
10. The semiconductor structure according to claim 7, characterized in that, The isolation layer is made of a crystalline material, and the doping elements are used to reduce the grain size of the isolation layer.
11. A film deposition method, characterized in that, Includes the following steps: A semiconductor structure is formed, the semiconductor structure including a substrate, the substrate including a base, a dielectric layer on the substrate, and a first via in the dielectric layer, the inner wall of the first via and the surface of the dielectric layer facing away from the substrate being covered by an isolation layer, the isolation layer directly covering the surface of the dielectric layer exposed in the first via, the isolation layer including a dopant element, the dopant element being used to increase the density of the isolation layer, the material of the isolation layer including polycrystalline silicon, and the dopant element including carbon. A batch of wafers to be processed and several semiconductor structures are placed in a reaction chamber, wherein the wafers to be processed include a second through-hole; Simultaneously, a functional layer is formed on the inner wall of the second through hole and on the surface of the isolation layer; The functional layer on the surface of the isolation layer is removed, exposing the semiconductor structure of the isolation layer for placement in the reaction chamber along with the next batch of wafers to be processed.
12. The film deposition method according to claim 11, characterized in that, The specific steps for removing the functional layer from the surface of the isolation layer include: The functional layer is removed using a wet etching process.
13. The film deposition method according to claim 11, characterized in that, The functional layer can be a single-layer or multi-layer structure, and the doping element can also increase the etching selectivity ratio of the isolation layer to each layer in the functional layer.
14. The film deposition method according to claim 11, characterized in that, The isolation layer is made of a crystalline material, and the doping elements are used to reduce the grain size of the isolation layer.