Methods for adjusting NWE

Abstract

The present invention discloses a method for adjusting NWE, which is characterized by comprising the following steps: using a general process to complete the wafer pre-process steps until SiGe hard mask deposition; adjusting the T2G parameter by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe groove etching; and / or adjusting the RCD parameter by adjusting the vertical etching time of the SiGe groove; etching to form the final SiGe groove, and finally forming SiGe through SiGe epitaxial growth; and using a general process to complete the post-process steps. The present invention adjusts the T2G parameter by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe groove etching, and / or adjusts the RCD parameter by adjusting the vertical etching time of the SiGe groove, thereby changing the Through AA Width Effect Trend of PMOS, and then adjusting the LDD Implantation Dose to match the device speed with the PCM Target. Compared with the method of publishing AA mask and changing AA CD commonly used in the industry, the present invention is equally effective, has lower cost, has a certain adjustable range, and can be used for KWL Matching of PMOS.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for adjusting NWE. Background Art

[0002] In the prior art, the matching of NWE (Narrow Width Effect) is achieved by adjusting the critical dimension AA CD of the active area under different active area widths AAWidth.

[0003] The prior art technical solution of adjusting the width of the active area has the following disadvantages:

[0004] 1. The solution to adjust the active area width requires re-issuing the active area mask, and at 28nm and more advanced technology nodes, the mask cost at the Immersion lithography level is also quite high.

[0005] 2. Adjustment of the active area width: The active area width is artificially grouped and assigned different compensation values. The adjustment is relatively inflexible and is not conducive to improving production efficiency. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] The technical problem to be solved by the present invention is to provide a method for adjusting NWE under the premise of increasing the cost of the mask.

[0008] In order to solve the above technical problems, the method for adjusting NWE provided by the present invention comprises the following steps:

[0009] S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition;

[0010] S2, adjust the T2G parameter by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe trench etching. T2G (Tip to Gate) is the lateral distance between the tip of SiGeΣshape and the gate channel.

[0011] and / or, by adjusting the vertical etching time of the SiGe trench, adjusting the RCD parameter, RCD (Recess Depth) being the overall depth of the SiGe trench;

[0012] S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth;

[0013] S4, complete the subsequent process steps using a general process.

[0014] Optionally, the method for adjusting NWE is further improved, further comprising:

[0015] S5, verify the NWE adjustment result through electrical parameter test.

[0016] Optionally, the method for adjusting NWE is further improved, in step S2, the speed difference between the small width active area device and the large width active area device is enlarged by reducing the T2G parameter;

[0017] The speed difference between devices with small active area width and devices with large active area width is reduced by increasing the external T2G parameter.

[0018] Optionally, the method of adjusting NWE is further improved by:

[0019] In step S2, the speed difference between the small width active area device and the large width active area device is enlarged by increasing the RCD parameter;

[0020] The speed difference between the device with small active area width and the device with large active area width is reduced by reducing the RCD parameter.

[0021] Optionally, the method for adjusting NWE is further improved, and the preceding process steps in step S1 include wafer active area patterning, High-k dielectric deposition, gate patterning, first sidewall patterning, and LDD ion implantation.

[0022] Optionally, the method for adjusting NWE is further improved, and the subsequent process steps in step S6 include a second sidewall spacer, source and drain implantation, a contact hole process, and a metal interconnection process.

[0023] In step S3, the final SiGe trench is formed by TMAH wet etching.

[0024] Optionally, the method for adjusting NWE is further improved so that it can be used for NWE adjustment of 32nm, 28nm, 22nm, 20nm and less than 16nm processes.

[0025] Optionally, the method for adjusting NWE is further improved so that it can be used for high-k dielectric gate, Poly SiON or embedded SiGe structure.

[0026] In the semiconductor device manufacturing process, taking the 28HK project as an example, the actual PMOS NWE trend is quite different from the Ref.Fab, especially the Large AA Width PMOS device is too fast, resulting in high leakage and serious yield failure. The existing technology re-publishes the active area mask and adjusts the active area width artificially to group them and assign different compensation values, which results in high production costs and is not conducive to improving production efficiency.

[0027] The present invention adjusts the T2G parameters by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe groove etching, and / or adjusts the RCD parameters by adjusting the vertical etching time of SiGe groove, thereby changing the Through AA Width Effect Trend of PMOS, and then adjusting the LDD Implantation Dose to match the device speed with the PCM Target. The present invention is as effective as the method of publishing AA mask and changing AA CD commonly used in the industry, and has lower cost and a certain adjustable range, and can be used for KWL Matching of PMOS. It has been verified that the technical solution of the present invention has achieved PMOS NWE matching Ref.Fab, and the device matching degree at each level of AA Width is higher than 95%. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0029] Figure 1 This is a schematic diagram of the process of the present invention Figure 1 .

[0030] Figure 2 This is a schematic diagram of the process of the present invention Figure 2 .

[0031] Figure 3 This is a schematic diagram of the process of the present invention Figure 3 .

[0032] Figure 4 This is a schematic diagram of SiGe critical dimensions. DETAILED DESCRIPTION

[0033] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. The difference is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all figures, the same reference numerals always represent the same element. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.

[0034] First embodiment;

[0035] like Figure 1 As shown, the present invention provides a method for adjusting NWE, comprising the following steps:

[0036] S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition;

[0037] S2.1, adjusting the T2G parameters by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe trench etching;

[0038] S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth;

[0039] S4, complete the subsequent process steps using a general process.

[0040] Second embodiment;

[0041] The present invention provides a method for adjusting NWE, comprising the following steps:

[0042] S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition;

[0043] S2.1, adjusting the T2G parameters by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe trench etching;

[0044] S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth;

[0045] S4, completing the subsequent process steps using a general process;

[0046] S5, verify the NWE adjustment result through electrical parameter test.

[0047] Third embodiment;

[0048] like Figure 2 As shown, the present invention provides a method for adjusting NWE, comprising the following steps:

[0049] S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition;

[0050] S2.2, by adjusting the vertical etching time of the SiGe trench, the RCD parameter is adjusted; more specifically, the SiGe trench is usually divided into two steps of vertical etching, and the first step of vertical etching is used to determine the vertical distance SMD (Sigma Depeth) of the tip of SiGe from the trench. The present invention adjusts the RCD parameter by adjusting the second step of vertical etching time;

[0051] S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth;

[0052] S4, complete the subsequent process steps using a general process.

[0053] Fourth embodiment;

[0054] The present invention provides a method for adjusting NWE, comprising the following steps:

[0055] S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition;

[0056] S2.2, adjusting the RCD parameters by adjusting the vertical etching time of the SiGe trench;

[0057] S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth;

[0058] S4, completing the subsequent process steps using a general process;

[0059] S5, verify the NWE adjustment result through electrical parameter test.

[0060] Fifth embodiment;

[0061] like Figure 3As shown, the present invention provides a method for adjusting NWE, comprising the following steps:

[0062] S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition;

[0063] S2.3, adjusting the T2G parameters by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe trench etching;

[0064] And, by adjusting the vertical etching time of the SiGe trench, the RCD parameters are adjusted;

[0065] S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth;

[0066] S4, complete the subsequent process steps using a general process.

[0067] Sixth embodiment;

[0068] The present invention provides a method for adjusting NWE, comprising the following steps:

[0069] S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition;

[0070] S2.3, adjusting the T2G parameters by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe trench etching;

[0071] And, by adjusting the vertical etching time of the SiGe trench, the RCD parameters are adjusted;

[0072] S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth;

[0073] S4, completing the subsequent process steps using a general process;

[0074] S5, verify the NWE adjustment result through electrical parameter test.

[0075] In addition, it should be understood that, although the terms "first", "second", etc. may be used herein to describe different elements, parameters, components, regions, layers and / or parts, these elements, parameters, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or part from another element, parameter, component, region, layer or part. Therefore, without departing from the teachings of exemplary embodiments of the present invention, the first element, parameter, component, region, layer or part discussed below may also be referred to as the second element, parameter, component, region, layer or part.

[0076] Seventh embodiment;

[0077] The present invention provides a method for adjusting NWE, comprising the following steps:

[0078] S1, using common processes to complete wafer active area patterning, High-k dielectric deposition, gate patterning, first sidewall patterning and LDD ion implantation until SiGe hard mask deposition;

[0079] S2.3, adjusting the T2G parameters by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe trench etching;

[0080] And, by adjusting the vertical etching time of the SiGe trench, the RCD parameters are adjusted;

[0081] S3, TMAH wet etching to form the final SiGe trench, and SiGe is finally formed through SiGe epitaxial growth;

[0082] S4, forming the second sidewall spacer, source and drain implantation, contact hole process and metal interconnection process and other subsequent process steps by common process;

[0083] S5, verify the NWE adjustment result through electrical parameter test;

[0084] Among them, the speed difference between the small width active area device and the large width active area device is enlarged by reducing the T2G parameter;

[0085] The speed difference between devices with small active area width and devices with large active area width is reduced by increasing the T2G parameter.

[0086] By increasing the RCD parameter, the speed difference between the small width active area device and the large width active area device is enlarged;

[0087] The speed difference between the device with small active area width and the device with large active area width is reduced by reducing the RCD parameter.

[0088] Optionally, the method for adjusting NWE described in any one of the first to sixth embodiments can be used for NWE adjustment of 32nm, 28nm, 22nm, 20nm and less than 16nm processes.

[0089] Optionally, the method for adjusting NWE described in any one of the first to sixth embodiments can be used for high-k dielectric gate, Poly SiON or embedded SiGe structure.

[0090] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0091] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for adjusting NWE, characterized in that: The following steps are involved: S1, using a common process to complete the wafer pre-process steps until SiGe hard mask deposition; S2, adjust the T2G parameter by adjusting the trimming time of SiGe hard mask etching or the lateral etching time of SiGe trench etching, where T2G is the lateral distance between the SiGe tip and the gate channel; and / or, adjusting the RCD parameter by adjusting the vertical etching time of the SiGe trench, where RCD is the overall depth of the SiGe trench; By reducing the T2G parameter, the speed difference between the small width active area device and the large width active area device is enlarged; By increasing the T2G parameter, the speed difference between devices with small active area width and devices with large active area width can be reduced; By increasing the RCD parameter, the speed difference between the small width active area device and the large width active area device is enlarged; By reducing the RCD parameter, the speed difference between the small width active area device and the large width active area device is reduced; S3, etching to form the final SiGe trench, and finally forming SiGe through SiGe epitaxial growth; S4, complete the subsequent process steps using a general process.

2. The method for adjusting NWE according to claim 1, characterized in that: Also includes: S5, verify the NWE adjustment result through electrical parameter test.

3. The method for adjusting NWE according to claim 1, characterized in that: The preceding process steps in step S1 include wafer active area patterning, High-k dielectric deposition, gate patterning, first sidewall patterning and LDD ion implantation.

4. The method for adjusting NWE according to claim 1, characterized in that: The subsequent process steps in step S6 include a second sidewall spacer, source and drain implantation, a contact hole process and a metal interconnection process.

5. The method for adjusting NWE according to claim 1, characterized in that: In step S3, a final SiGe trench is formed by TMAH wet etching.

6. The method for adjusting NWE according to any one of claims 1 to 5, characterized in that: It can be used for NWE adjustment of 32nm, 28nm, 22nm, 20nm and less than 16nm processes.

7. The method for adjusting NWE according to any one of claims 1 to 5, characterized in that: It can be used for high-k dielectric gate, Poly SiON or embedded SiGe structures.

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