A package structure of a full silicon carbide double-sided heat dissipation module and a packaging method thereof

Abstract

The application belongs to the technical field of packaging integration of power semiconductor modules, and discloses a packaging structure and a packaging method of a large-power all-silicon carbide module. The packaging structure comprises a bottom layer direct copper clad ceramic (DBC) substrate, a silicon carbide power chip (MOSFET) attached to the bottom layer DBC substrate, a driving resistor, a gasket, a top layer DBC substrate and a connection terminal. The main power input terminal of the packaging structure adopts double-end outgoing lines, and the power lead has a structure in which the current flow directions are opposite. The mutual inductance is used to offset part of the parasitic inductance on the power loop, and the parasitic inductance of the parallel chip commutation loop is more balanced. The upper and lower surfaces can be assembled with radiators, two parallel heat dissipation paths are provided for the power chip, and the chip thermal resistance is reduced. The driving circuit adopts a Kelvin structure, the influence of the common source inductance on the driving signal is reduced, and the stability of the driving signal is enhanced. The packaging method provides a reliable processing method for the packaging structure, so that the packaging structure can be realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of packaging integration of power semiconductor modules, and more particularly to a packaging structure of a full silicon carbide double-sided heat dissipation module and a packaging method thereof. BACKGROUND

[0002] The rapid iterative development of power electronic systems has higher requirements for the performance of power electronic devices, and the performance of traditional Si devices has basically reached its physical limit, so it is urgent to develop new semiconductor material devices as substitutes. In order to further improve the switching characteristics and conduction characteristics, wide bandgap semiconductors (WBG) gradually come into people's field of vision. Under the same conditions, wide bandgap semiconductor material devices have higher breakdown voltage, higher conduction current, higher working temperature, higher switching speed and lower switching loss than traditional Si devices.

[0003] However, the inductance value of each pin of the existing silicon carbide discrete device (TO247 package) is about 4nH, and the inductance value of the commutation loop inside the commercial high-power silicon carbide module is generally above 15nH. The larger parasitic inductance makes the switching device bear a larger voltage overshoot during the switching process, and is accompanied by voltage oscillation during the transient process. In addition, the existing single silicon carbide chip has limited current-carrying capacity, so in high-power applications, multiple chips are usually connected in parallel to expand the current. However, the parasitic inductance values of the drive circuits of each parallel chip are different, which will cause uneven current distribution and dynamic imbalance during the turn-on / off process. With the increase of the loop inductance value, the influence is more serious, which greatly limits the application of silicon carbide devices / modules in high-frequency applications.

[0004] In addition, thermal performance is an important indicator for evaluating the reliability of a module. With the development of power electronic systems, the power level handled by power electronic modules is constantly rising, which in turn brings a large amount of loss. For traditional wire bonding modules, due to the fact that only single-sided cooling can be achieved, the heat dissipation power is insufficient, so it is difficult to meet the requirements of high-power applications. SUMMARY

[0005] In view of the defects of the related art, the purpose of the present application is to provide a new double-sided heat dissipation packaging structure with low parasitic inductance, low thermal resistance and relatively balanced parasitic parameters of each parallel power device, and a packaging method thereof, aiming to solve the problems of large parasitic inductance in the existing silicon carbide power package, uneven dynamic caused by unbalanced parasitic parameters between parallel power devices, and poor heat dissipation capacity of traditional modules.

[0006] To achieve the above-mentioned purpose, one aspect of the present application provides a full silicon carbide double-sided heat dissipation packaging structure, comprising a bottom DBC substrate, a silicon carbide power chip, a driving resistor, a gasket, a top DBC substrate, a first heat sink and a second heat sink.

[0007] The silicon carbide power chip and the driving resistor are directly attached to the bottom DBC substrate, and the pad is directly welded to the top DBC substrate;

[0008] The silicon carbide power chip, the driving resistor and the pad are located between the top DBC substrate and the bottom DBC substrate;

[0009] The first heat sink and the second heat sink are respectively arranged on the outer side of the top DBC substrate and the bottom DBC substrate.

[0010] Further, the packaging structure further comprises:

[0011] The connection terminal comprises a main power input terminal, a main power output AC terminal and a driving circuit terminal.

[0012] Further, the main power input terminal comprises two groups of power outlet terminals, and the two groups of power outlet terminals are symmetrically arranged about the silicon carbide power chip.

[0013] Further, the two groups of power outlet terminals symmetrically arranged about the silicon carbide power chip comprise:

[0014] When the silicon carbide power chip is a plurality of chips in parallel, the main power input terminal comprises a first power outlet terminal and a second power outlet terminal; wherein the sum of the distances from the first power outlet terminal to each chip is equal to the sum of the distances from the second power outlet terminal to each chip.

[0015] Further, the silicon carbide power chip comprises two groups of silicon carbide MOSFET chips to form a half-bridge circuit, and each group of silicon carbide MOSFET chips is connected in parallel to form an upper bridge arm and a lower bridge arm of the half-bridge circuit, respectively;

[0016] The driving resistor comprises an upper bridge arm driving resistor and a lower bridge arm driving resistor;

[0017] The driving circuit terminal comprises an upper bridge arm source driving terminal, a lower bridge arm source driving terminal, an upper bridge arm gate driving terminal and a lower bridge arm gate driving terminal;

[0018] The source of the silicon carbide MOSFET chip of the upper bridge arm is led out to the corresponding copper block of the bottom DBC through the upper bridge arm source bonding wire, and is connected with the upper bridge arm source driving terminal; the gate of the silicon carbide MOSFET chip of the upper bridge arm is connected to the corresponding copper block of the bottom DBC through the upper bridge arm gate bonding wire, and is connected with the upper bridge arm driving resistor;

[0019] The source of the silicon carbide MOSFET chip of the lower bridge arm is led out to the corresponding copper block of the underlying DBC through a lower bridge arm source bonding wire and connected with the lower bridge arm source driving terminal; the gate of the silicon carbide MOSFET chip of the lower bridge arm is connected to the corresponding copper block of the underlying DBC through a lower bridge arm gate bonding wire and connected with the lower bridge arm driving resistor.

[0020] Further, the top layer DBC substrate and the bottom layer DBC substrate are both divided into a three-layer structure, and the upper and lower layers are both metal copper, and the middle layer is aluminum nitride ceramic.

[0021] Further, the top layer DBC substrate and the bottom layer DBC substrate both adopt oxygen-free copper material, and the surface is subjected to nickel plating treatment.

[0022] Another aspect of the present application also provides a packaging method of the packaging structure as described above, comprising the following steps:

[0023] The top layer DBC substrate and the bottom layer DBC substrate are prepared according to the packaging structure, and the corresponding connecting surface structure is etched;

[0024] The solder one is uniformly coated on the corresponding soldering position of the bottom layer DBC substrate, the silicon carbide power chip is placed on the solder one, fixed by using a clamp and heated and sintered by using a vacuum reflow soldering method; then the electrode of the silicon carbide power chip is electrically connected with the corresponding copper block of the bottom layer DBC substrate by using a wire bonding process;

[0025] The solder two is uniformly coated on the corresponding soldering position of the top layer DBC substrate, the gasket is placed on the solder two, fixed by using a clamp and heated and sintered by using a vacuum reflow soldering method;

[0026] The solder three is uniformly coated on the upper surface of the silicon carbide power chip, the top layer DBC substrate is placed on the solder three, the gasket is aligned with the surface of the silicon carbide power chip, fixed by using a clamp and heated and sintered by using a vacuum reflow soldering method;

[0027] The solder four is used to weld the first heat sink and the second heat sink to the outer side of the top layer DBC substrate and the bottom layer DBC substrate respectively, then the insulating gel is injected into the shell and condensed until the insulating gel is solidified.

[0028] Further, the solder one, the solder two and the solder three are nano-silver materials.

[0029] Further, the solder four adopts Sn63Pb37 material.

[0030] Through the above technical scheme conceived by the present application, compared with the prior art, the following beneficial effects can be achieved:

[0031] (1) The full silicon carbide double-sided heat dissipation packaging structure provided by the application integrates two layers of DBC, the inner side metal of the DBC is used to realize the connection of the power loop and the driving loop, and the outer side metal is used to connect the heat sink. The double-sided heat dissipation realizes great improvement in thermal performance compared with the current single-sided heat dissipation module.

[0032] (2) In the full silicon carbide double-sided heat dissipation packaging structure provided by the application, the power terminals DC+ and DC- adopt a double-end outgoing line mode, which greatly reduces the dynamic uneven influence caused by the unbalanced parasitic parameters of each switch tube power loop when multiple chips are connected in parallel.

[0033] (3) In the full silicon carbide double-sided heat dissipation packaging structure provided by the application, the driving loop of each silicon carbide MOSFET chip adopts Kelvin connection, which reduces the common source inductance and further reduces the influence of the power loop on the driving loop, and improves the stability of the driving signal. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is the external structure diagram of the packaging structure of the full silicon carbide double-sided heat dissipation module provided by the embodiment of the application;

[0035] Figure 2 is the internal structure diagram of the packaging structure provided by the embodiment of the application;

[0036] Figure 3 is the internal plane diagram of the packaging structure provided by the embodiment of the application;

[0037] Figure 4 is the bottom DBC substrate diagram of the packaging structure provided by the embodiment of the application;

[0038] Figure 5 is the top DBC substrate diagram of the packaging structure provided by the embodiment of the application;

[0039] Figure 6 is the half-bridge circuit diagram corresponding to the packaging structure provided by the embodiment of the application;

[0040] Figure 7 is the flowchart of the packaging method provided by the embodiment of the application.

[0041] Mark No. : 1 - upper bridge arm source drive terminal, 2 - upper bridge arm gate drive terminal, 3 - first DC bus voltage detection terminal, 4 - main power DC+ terminal, 5 - main power DC- terminal, 6 - second DC bus voltage detection terminal, 7 - lower bridge arm gate drive terminal, 8 - lower bridge arm source drive terminal, 9 - bottom layer DBC, 10 - main power output AC terminal, 11 - top layer DBC, 12 - AC gasket, 13 - lower bridge arm switch tube, 14 - lower bridge arm gasket, 15 - upper bridge arm gasket, 16 - upper bridge arm switch tube, 17 - upper bridge arm gate bonding wire, 18 - lower bridge arm gate bonding wire, 19 - lower bridge arm drive resistance, 20 - lower bridge arm source bonding wire, 21 - upper bridge arm drive resistance, 22 - upper bridge arm source bonding wire, 23 - first copper block, 24 - second copper block, 25 - DC+ copper block, 26 - AC2 copper block, 27 - fifth copper block, 28 - sixth copper block, 29 - fourth copper block, 30 - third copper block, 31 - DC- copper block, 32 - AC1 copper block. DETAILED DESCRIPTION

[0042] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0043] To achieve the above object, the embodiment of the present application provides a full silicon carbide double-sided heat dissipation packaging structure, comprising a bottom layer DBC substrate, a silicon carbide power chip, a drive resistance, a gasket, a top layer DBC substrate, a first heat sink and a second heat sink;

[0044] The silicon carbide power chip and the drive resistance are directly attached to the bottom layer DBC substrate, and the gasket is directly welded to the top layer DBC substrate.

[0045] The silicon carbide power chip, the drive resistance and the gasket are all located between the top layer DBC substrate and the bottom layer DBC substrate.

[0046] The first heat sink and the second heat sink are respectively assembled on the outer side of the top layer DBC substrate and the bottom layer DBC substrate.

[0047] Further, the packaging structure further comprises:

[0048] A connection terminal; the connection terminal comprises a main power input terminal, a main power output AC terminal and a drive circuit terminal.

[0049] Further, the main power input terminal comprises two groups of power output terminals, and the two groups of power output terminals are symmetrically arranged with respect to the silicon carbide power chip.

[0050] Further, the two groups of power output terminals are symmetrically arranged with respect to the silicon carbide power chip, comprising:

[0051] When the silicon carbide power chip is a plurality of chips in parallel, the main power input terminal comprises a first power output terminal and a second power output terminal; wherein the sum of the distances from the first power output terminal to each chip is equal to the sum of the distances from the second power output terminal to each chip.

[0052] Further, the silicon carbide power chip comprises two groups of silicon carbide MOSFET chips to form a half-bridge circuit, and each group of silicon carbide MOSFET chips is connected in parallel to form an upper bridge arm and a lower bridge arm of the half-bridge circuit, respectively.

[0053] The driving resistor comprises an upper bridge arm driving resistor and a lower bridge arm driving resistor.

[0054] The driving circuit terminal comprises an upper bridge arm source driving terminal, a lower bridge arm source driving terminal, an upper bridge arm gate driving terminal and a lower bridge arm gate driving terminal.

[0055] The source of the silicon carbide MOSFET chip of the upper bridge arm is led out to the corresponding copper block of the underlying DBC through the upper bridge arm source bonding wire, and is connected to the upper bridge arm source driving terminal; the gate of the silicon carbide MOSFET chip of the upper bridge arm is connected to the corresponding copper block of the underlying DBC through the upper bridge arm gate bonding wire, and is connected to the upper bridge arm driving resistor.

[0056] The source of the silicon carbide MOSFET chip of the lower bridge arm is led out to the corresponding copper block of the underlying DBC through the lower bridge arm source bonding wire, and is connected to the lower bridge arm source driving terminal; the gate of the silicon carbide MOSFET chip of the lower bridge arm is connected to the corresponding copper block of the underlying DBC through the lower bridge arm gate bonding wire, and is connected to the lower bridge arm driving resistor.

[0057] Further, the top layer DBC substrate and the bottom layer DBC substrate are both divided into a three-layer structure, and the upper and lower layers are both metal copper, and the middle layer is aluminum nitride ceramic.

[0058] Further, the top layer DBC substrate and the bottom layer DBC substrate both adopt oxygen-free copper material, and the surface is subjected to nickel plating treatment.

[0059] The embodiment of the application also provides a packaging method of the packaging structure as described above, comprising the following steps:

[0060] The top layer DBC substrate and the bottom layer DBC substrate are prepared according to the packaging structure, and a corresponding connecting surface structure is etched;

[0061] The solder I is uniformly coated on the corresponding soldering positions of the bottom layer DBC substrate, the silicon carbide power chip is placed on the solder I, fixed by using a clamp and heated and sintered by using a vacuum reflow soldering method, and then the electrode of the silicon carbide power chip is electrically connected to the corresponding copper block of the bottom layer DBC substrate by using a wire bonding process.

[0062] The solder II is uniformly coated on the corresponding soldering positions of the top layer DBC substrate, the spacer is placed on the solder II, fixed by using a clamp and heated and sintered by using a vacuum reflow soldering method.

[0063] The solder III is uniformly coated on the upper surface of the silicon carbide power chip, the top layer DBC substrate is placed on the solder III, the spacer is aligned with the surface of the silicon carbide power chip, fixed by using a clamp and heated and sintered by using a vacuum reflow soldering method.

[0064] The solder IV is used to weld the first heat sink and the second heat sink to the outer side of the top layer DBC substrate and the bottom layer DBC substrate respectively, then the insulating gel is injected into the shell and condensed until the insulating gel is solidified.

[0065] Further, the solder I, the solder II and the solder III are nano-silver materials.

[0066] Further, the solder IV is Sn63Pb37 material.

[0067] The above-mentioned contents involved in the embodiment will be described in combination with a preferred embodiment.

[0068] The packaging structure of the high-power full-silicon carbide power module provided by the embodiment of the application includes a bottom layer direct copper clad ceramic (DBC) substrate, a silicon carbide power chip attached to the bottom layer DBC substrate, a driving resistor, a spacer, a top layer DBC substrate and a connecting terminal. In the following embodiment, the silicon carbide power chip is specifically a silicon carbide MOSFET chip.

[0069] The silicon carbide MOSFET chip and the driving resistor are both attached to the bottom layer DBC substrate. Six silicon carbide MOSFET chips are connected in parallel in three to form a half-bridge circuit structure. The connecting terminal includes a main power input terminal (DC+ terminal and DC- terminal), a main power output AC terminal and a driving circuit terminal.

[0070] The drain of the three silicon carbide MOSFET chips of the upper bridge arm is connected to the DC+ copper block of the bottom layer DBC through nano-silver sintering; the drain of the three silicon carbide MOSFET chips of the lower bridge arm is connected to the AC2 copper block of the bottom layer DBC through nano-silver sintering.

[0071] The source of the three silicon carbide MOSFET chips of the upper bridge arm is connected to the respective gasket (i.e. the upper bridge arm gasket) through nano-silver sintering, and the three gaskets are connected to the AC1 copper block of the top layer DBC through nano-silver sintering; the source of the three silicon carbide MOSFET chips of the lower bridge arm is connected to the respective gasket (i.e. the lower bridge arm gasket) through nano-silver sintering, and the three gaskets are connected to the DC- copper block of the top layer DBC through nano-silver sintering. The AC1 copper block of the top layer DBC and the AC2 copper block of the bottom layer DBC are also connected to the AC gasket through silver sintering.

[0072] The gate of the three silicon carbide MOSFET chips of the upper bridge arm is connected to the third copper block of the bottom layer DBC through a bonding wire and connected to the second copper block through the upper bridge arm driving resistor, and finally connected to the upper bridge arm gate driving end; the gate of the three silicon carbide MOSFET chips of the lower bridge arm is connected to the fourth copper block of the bottom layer DBC through a bonding wire and connected to the fifth copper block through the lower bridge arm driving resistor, and finally connected to the lower bridge arm gate driving end.

[0073] In addition, the source of the three silicon carbide MOSFET chips of the upper bridge arm is also connected to the first copper block of the bottom layer DBC through a bonding wire and connected to the upper bridge arm source driving end, forming a Kelvin connection of the three silicon carbide MOSFET chips driving of the upper bridge arm; the source of the three silicon carbide MOSFET chips of the lower bridge arm is also connected to the sixth copper block of the bottom layer DBC through a bonding wire and connected to the lower bridge arm source driving end, forming a Kelvin connection of the three silicon carbide MOSFET chips driving of the lower bridge arm.

[0074] The DC+ copper block is connected to three DC+ terminals, two of which constitute a double-ended power output line, and one (i.e. a first DC bus voltage detection terminal) and a corresponding DC- terminal (i.e. a second DC bus voltage detection terminal) form a detection circuit; the DC- copper block is connected to three DC- terminals, two of which constitute a double-ended power output line, and one (i.e. a second DC bus voltage detection terminal) and a corresponding DC+ terminal (i.e. a first DC bus voltage detection terminal) form a detection circuit; the AC2 copper block is connected to the AC terminal.

[0075] As can be understood by those skilled in the art, the above-mentioned double-ended output line refers to the main power input terminal comprising two groups of power output terminals, and the two groups of power output terminals are symmetrically arranged with respect to the silicon carbide power chip.

[0076] For example, when the silicon carbide power chips are in parallel, the main power input terminal includes a first power outlet terminal and a second power outlet terminal; wherein the sum of the distances from the first power outlet terminal to each chip is equal to the sum of the distances from the second power outlet terminal to each chip.

[0077] For occasions with higher power requirements, the two terminals constituting the double-ended power outlet can also be four, six or even more even-numbered terminals, and the specific number of terminals is determined according to the specific power requirement. As long as the number of power outlet terminals is even and symmetrically arranged with respect to the silicon carbide power chip, the power lead has a structure in which the current flows in opposite directions, which can use mutual inductance to offset a part of the parasitic inductance on the power loop, making the parasitic inductance of the parallel chip commutation loop more balanced.

[0078] Preferably, the packaging structure of the silicon carbide power device comprises a two-layer DBC structure, and the silicon carbide power devices of the upper and lower bridge arms of the half-bridge structure are connected to the bottom layer DBC copper block.

[0079] Preferably, the packaging structure of the silicon carbide power device directly welds a heat sink on the upper and lower surfaces, which saves the bottom plate and realizes double-sided heat dissipation to reduce thermal resistance.

[0080] Preferably, the packaging structure of the silicon carbide power device adopts a double-ended outlet for the power lead, which reduces the dynamic imbalance caused by the imbalance of parasitic parameters caused by the parallel connection of multiple power chips.

[0081] Preferably, the packaging structure of the silicon carbide power device adopts Kelvin connection for the control lead, which reduces the coupling between the drive loop and the power loop and reduces the interference of the power loop on the drive loop.

[0082] Preferably, the DC+ and DC- are provided with signal outlets for detecting the bus voltage to play a protective role.

[0083] Preferably, the DBC substrate is divided into a three-layer structure, the upper and lower layers are both metal copper, and the middle layer is aluminum nitride ceramic.

[0084] The non-inverted structure (the silicon carbide power devices of the upper and lower bridge arms are on the same layer) is connected to form a half-bridge structure by AC spacers, and the upper and lower bridge arms are each composed of three silicon carbide MOSFET chips.

[0085] The copper layer of the bottom layer DBC has eight copper blocks (connection surfaces), which are: first copper block, second copper block, third copper block, DC+ copper block, AC2 copper block, fourth copper block, fifth copper block, and sixth copper block.

[0086] The copper layer of the top layer DBC has two connection surfaces: AC1 copper block and DC- copper block.

[0087] Preferably, the distance between the copper blocks should be no less than 1mm to ensure insulation.

[0088] The embodiment of the present application also provides a packaging method of the full silicon carbide double-sided heat dissipation module, comprising the following steps:

[0089] (1) According to the structure of the full silicon carbide double-sided heat dissipation module to be packaged, the top layer and the bottom layer DBC substrates are prepared, and the connecting surface structure of the DBC substrate is etched;

[0090] (2) The silicon carbide MOSFET chip is welded to the corresponding position of the bottom layer DBC substrate by using the solder 1 and using the jig alignment;

[0091] (3) The gate and the source of the silicon carbide MOSFET chip are electrically connected to the corresponding copper blocks of the bottom layer DBC substrate by using the wire bonding process;

[0092] (4) The gasket is connected to the top layer DBC substrate by using the solder 2;

[0093] (5) The gasket is connected to the chip by using the solder 3 and using the jig alignment;

[0094] (6) The heat sink is welded to the top / bottom layer DBC by using the solder 4; the insulating gel is injected into the shell; and the insulating gel is solidified by condensation.

[0095] Preferably, the solder 1, the solder 2 and the solder 3 use the nano-silver material to realize the connection by sintering.

[0096] Preferably, the solder 4 uses the Sn63Pb37 material, and the melting point thereof is 183℃.

[0097] Preferably, the silicon carbide MOSFET chip is welded to the bottom layer DBC substrate, and the gasket is welded to the top layer DBC substrate, both of which are placed with the solder at the corresponding position first, the chip is placed by using the jig to fix and align, and finally the vacuum reflow soldering method is used for welding.

[0098] The embodiment of the present application will be further explained below with reference to the accompanying drawings. Figure 1 It is shown that the external structure of the packaging structure of the full silicon carbide double-sided heat dissipation module provided by the embodiment of the present application. The main power DC+ terminal 4, the main power DC- terminal 5, the main power output AC terminal 10, the upper bridge arm source electrode driving terminal 1, the upper bridge arm gate electrode driving terminal 2, the first direct current bus voltage detection terminal 3, the second direct current bus voltage detection terminal 6, the lower bridge arm gate electrode driving terminal 7 and the lower bridge arm source electrode driving terminal 8 are all connected to the corresponding copper blocks inside the top layer DBC 11 and the bottom layer DBC 9.

[0099] Figure 2 It is shown that the internal structure of the packaging structure provided by the embodiment of the present application,Figure 3 Fig. 2 is a schematic diagram of the internal plane of the packaging structure provided by the embodiment of the present application. The upper bridge arm gasket 15, the lower bridge arm gasket 14, the upper and lower surfaces of the AC gasket 12 and the copper layer of the top / bottom layer DBC are connected by silver sintering. The upper bridge arm switch tube 16 and the lower bridge arm switch tube 13 are respectively composed of three silicon carbide MOSFETs in parallel, the source thereof is connected to the corresponding gasket by solder, and is respectively led out to the corresponding copper block by the upper bridge arm source bonding wire 22 and the lower bridge arm source bonding wire 20 for constituting Kelvin connection, the gate thereof is connected to the corresponding copper block by the upper bridge arm gate bonding wire 17 and the lower bridge arm gate bonding wire 18 and is connected with the respective driving resistors 21, 19; the drain of the upper bridge arm switch tube 16 is connected with the DC+ copper block 25 by silver sintering, and the drain of the lower bridge arm switch tube 13 is connected with the AC2 copper block 26 by silver sintering.

[0100] Figure 4 Fig. 3 is a schematic diagram of the bottom layer DBC substrate of the packaging structure provided by the embodiment of the present application, the upper surface copper layer of which is divided into eight parts: the first copper block, the second copper block, the third copper block, the DC+ copper block, the AC2 copper block, the fourth copper block, the fifth copper block, and the sixth copper block.

[0101] The first copper block 23 is connected with the source of the upper bridge arm switch tube 16 by the upper bridge arm source bonding wire 22; the second copper block 24 is connected with one end of the upper bridge arm driving resistor 21, the third copper block 30 is connected with the other end of the upper bridge arm driving resistor 21, and is connected with the gate of the upper bridge arm switch tube 16 by the upper bridge arm gate bonding wire 17; the DC+ copper block 25 is connected with the drain of the upper bridge arm switch tube 16, and is connected with the DC+ terminal 4, and is also connected with the first DC bus voltage detection terminal 3. The AC2 copper block 26 is connected with the drain of the lower bridge arm switch tube 13, and is connected with the lower surface of the AC gasket 12, and is also connected with the main power output AC terminal 10; the sixth copper block 28 is connected with the source of the lower bridge arm switch tube 13 by the lower bridge arm source bonding wire 20; the fifth copper block 27 is connected with one end of the lower bridge arm driving resistor 19, and the fourth copper block 29 is connected with the other end of the lower bridge arm driving resistor 19, and is connected with the gate of the lower bridge arm switch tube 13 by the lower bridge arm gate bonding wire 18.

[0102] Figure 5 Fig. 4 is a schematic diagram of the top layer DBC substrate of the packaging structure provided by the embodiment of the present application, the lower surface copper layer of which is divided into two parts: the DC- copper block 31 and the AC1 copper block 32.

[0103] The DC- copper block 31 is connected with the upper surface of the lower bridge arm gasket 14, and is also connected with the DC- terminal 5, and is connected with the second DC bus voltage detection terminal 6; the AC1 copper block 32 is connected with the upper surface of the AC gasket 12.

[0104] The top / bottom layer DBC substrate adopts oxygen-free copper material, and the surface is plated with nickel to enhance the surface oxidation resistance and facilitate wire bonding.

[0105] By Figure 1 、 Figure 2 With Figure 3 It can be seen that, since the main power DC+ terminal 4 and the main power DC- terminal 5 both adopt double-end wiring, the power lead has a structure in which the current flows in opposite directions, and the mutual inductance cancels out part of the parasitic inductance on the power loop, and the parasitic inductance of the parallel chip commutation loop is more balanced. On the other hand, it can be seen that the upper bridge arm drive loop terminals (the upper bridge arm gate drive terminal 2 and the upper bridge arm source drive terminal 1) and the lower bridge arm drive loop terminals (the lower bridge arm gate drive terminal 7 and the lower bridge arm source drive terminal 8) both adopt a Kelvin connection mode, which greatly reduces the parasitic inductance of the drive loop, and avoids the interference of the common-source inductance in the traditional connection mode (for example, the upper bridge arm source drive terminal is directly connected to the main power output AC terminal 10, and the lower bridge arm source drive terminal is directly connected to the main power DC- terminal 5) on the drive loop.

[0106] Figure 6 The figure shows a half-bridge circuit schematic diagram corresponding to the packaging structure provided by the embodiment of the application; the half-bridge circuit structure is formed by the main power DC+ terminal 4, the main power DC- terminal 5, the main power output AC terminal 10, the upper bridge arm gate drive terminal 2, the upper bridge arm source drive terminal 3, the lower bridge arm gate drive terminal 6, the lower bridge arm source drive terminal 7, the upper bridge arm switch tube 16, the upper bridge arm drive resistor 21, the lower bridge arm switch tube 13, the lower bridge arm drive resistor 19, and the electrical connection therebetween.

[0107] Figure 7 The figure is a flowchart of the full silicon carbide double-sided heat dissipation module packaging method provided by the embodiment of the application, which specifically includes the following steps:

[0108] Step S101, selecting a DBC substrate, wherein the insulating layer material of the DBC substrate is selected to be aluminum nitride (AlN) material with high thermal conductivity, and the top layer DBC and the bottom layer DBC are both etched according to the corresponding patterns shown in Figure 4 、 Figure 5 ;

[0109] Step S102, uniformly applying nano-silver material on the corresponding soldering position of the bottom layer DBC, placing the silicon carbide MOSFET chip or terminal to be soldered on the top, fixing it using a clamp, and finally heating and sintering by vacuum reflow soldering;

[0110] Step S103, connecting the gate and source of the silicon carbide MOSFET chip to the corresponding copper blocks of the bottom layer DBC substrate by wire bonding;

[0111] Step S104, first, evenly coat the nano-silver material on the top layer DBC corresponding welding position, put the gasket and DC-terminal, use the fixture to fix, finally, use the vacuum reflow soldering method to heat sintering;

[0112] Step S105, first, evenly coat the nano-silver material on the chip upper surface, put the top layer DBC on it, wherein the gasket is aligned with the chip surface, use the fixture to fix, finally, use the vacuum reflow soldering method to heat sintering;

[0113] Step S106, weld the heat sink on the top layer and bottom layer DBC outer side, fill the silicon gel into it, after the filling, stand for 24 hours until the silicon gel solidifies.

[0114] Those skilled in the art will easily understand that the above description is only the preferred embodiment of the present application, and is not intended to limit the present application, any modification, equivalent replacement and improvement within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A fully silicon carbide double-sided heat dissipation packaging structure, characterized in that, It includes a bottom DBC substrate, a silicon carbide power chip, a drive resistor, a pad, a top DBC substrate, a first heat sink, a second heat sink, and connection terminals; The silicon carbide power chip and the driving resistor are directly mounted on the bottom DBC substrate, and the pad is directly soldered to the top DBC substrate. The silicon carbide power chip, drive resistor, and pad are all located between the top DBC substrate and the bottom DBC substrate. The first heat sink and the second heat sink are respectively mounted on the outside of the top DBC substrate and the bottom DBC substrate; The connection terminals include a main power input terminal, a main power output AC terminal (10), and a drive circuit terminal; the main power input terminal includes a main power DC+ terminal (4) and a main power DC- terminal (5). Each main power input terminal adopts a double-ended output structure so that the power leads have current flows in opposite directions. The double-ended output includes two sets of power output terminals, namely a first power output terminal and a second power output terminal. The two sets of power output terminals are symmetrically arranged about the silicon carbide power chip. The silicon carbide power chip is a plurality of chips connected in parallel. The sum of the distances from the first power output terminal to each chip is equal to the sum of the distances from the second power output terminal to each chip. The silicon carbide power chip includes two sets of silicon carbide MOSFET chips forming a half-bridge circuit. The silicon carbide MOSFET chips are connected in parallel to each other to form the upper and lower arms of the half-bridge circuit, respectively. The driving resistors include the upper bridge arm driving resistor (21) and the lower bridge arm driving resistor (19); The drive circuit terminals include an upper bridge arm source drive terminal (1), a lower bridge arm source drive terminal (8), an upper bridge arm gate drive terminal (2), and a lower bridge arm gate drive terminal (7); The drain of the silicon carbide MOSFET chip in the upper bridge arm is electrically connected to the main power DC+ terminal (4). The source of the silicon carbide MOSFET chip in the upper bridge arm is led out to the corresponding copper block of the bottom DBC through the upper bridge arm source bonding line (22) and connected to the upper bridge arm source drive terminal (1). The gate of the silicon carbide MOSFET chip in the upper bridge arm is connected to the corresponding copper block of the bottom DBC through the upper bridge arm gate bonding line (17) and connected to the upper bridge arm drive resistor (21). The three silicon carbide MOSFET chips in the upper bridge arm form a Kelvin connection. The drain of the silicon carbide MOSFET chip in the lower bridge arm is electrically connected to the main power output AC terminal (10). The source of the silicon carbide MOSFET chip in the lower bridge arm is led out to the corresponding copper block of the bottom layer DBC through the lower bridge arm source bonding line (20) and connected to the lower bridge arm source drive terminal (8). The lower bridge arm source drive terminal (8) is electrically connected to the main power DC terminal (5). The gate of the silicon carbide MOSFET chip in the lower bridge arm is connected to the corresponding copper block of the bottom layer DBC through the lower bridge arm gate bonding line (18) and connected to the lower bridge arm drive resistor (19). The three silicon carbide MOSFET chips in the lower bridge arm form a Kelvin connection.

2. The packaging structure as described in claim 1, characterized in that, Both the top and bottom DBC substrates are composed of three layers: the top and bottom layers are made of copper, and the middle layer is made of aluminum nitride ceramic.

3. The packaging structure as described in claim 2, characterized in that, Both the top-layer DBC substrate and the bottom-layer DBC substrate are made of oxygen-free copper and are nickel-plated on the surface.

4. A packaging method for the packaging structure as described in claim 1, characterized in that, Includes the following steps: The top DBC substrate and the bottom DBC substrate are prepared according to the packaging structure, and the corresponding connection surface structure is etched out. Solder 1 is uniformly applied to the welding position corresponding to the bottom DBC substrate. The silicon carbide power chip is placed on the solder 1, fixed with a fixture, and heated and sintered by vacuum reflow soldering. Then, the electrodes of the silicon carbide power chip are electrically connected to the corresponding copper blocks of the bottom DBC substrate by wire bonding process. Solder II is uniformly applied to the welding position corresponding to the top DBC substrate, the gasket is placed on the solder II, and the fixture is used to fix it and heat and sinter it by vacuum reflow soldering. Solder 3 is uniformly coated on the upper surface of the silicon carbide power chip, the top layer DBC substrate is placed on the solder 3, the pad is aligned with the surface of the silicon carbide power chip, and the chip is fixed with a fixture and heated and sintered by vacuum reflow soldering. Using solder four, the first heat sink and the second heat sink are respectively soldered to the outer side of the top DBC substrate and the bottom DBC substrate. Then, the insulating gel is injected into the shell and condensed until the insulating gel is cured.

5. The packaging method as described in claim 4, characterized in that, Solder 1, Solder 2, and Solder 3 are nano-silver materials.

6. The packaging method as described in claim 4 or 5, characterized in that, The solder four uses Sn63Pb37 material.

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