Mirrored SONOS flash memory cell and method for manufacturing the same

Abstract

The present invention discloses a mirror-position SONOS flash memory unit, comprising an enhanced selection tube and a depletion storage tube, wherein the selection tube and the storage tube share a source region and a drain region heavily doped with a first conductive type, and a buried channel layer lightly doped with a first conductive type is formed between the source and drain regions. The channel region is formed by a combination of a well region and a buried channel layer between the source region and the drain region; a first gate structure of the selection tube and a second gate structure of the storage tube are arranged on the channel region. A first groove that cuts off the buried channel layer is formed in the formation region of the first gate structure, so that the bottom surface of the first gate dielectric layer directly contacts the well region, and the bottom surface of the second gate storage dielectric layer directly contacts the buried channel layer, thereby realizing separate adjustment of the threshold voltage of the selection tube and the storage tube. The present invention also discloses a method for manufacturing a mirror-position SONOS flash memory unit. The present invention can simplify the formation process of the channel region of the selection tube and the storage tube, which is conducive to reducing the channel length of the entire selection tube, the storage tube and the entire unit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a mirror-bit SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory unit. The present invention also relates to a manufacturing method of the mirror-bit SONOS flash memory unit. Background Art

[0002] Mirror-Bit SONOS Flash is usually composed of an enhancement mode NMOS selection tube and two symmetrical depletion mode N-type SONOS memory devices, namely depletion mode memories.

[0003] In order to obtain a depletion-type memory, it is necessary to ion-implant N-type impurities into the P-well (Pwell) to adjust the initial threshold voltage of the memory to a negative value.

[0004] The 1.5T Mirror-Bit SONOS Flash cell uses a structure where the memory channel and the selector channel are closely connected, and the selector does not have a separate source and drain region. The channel of the entire memory cell is very short, and it becomes very difficult to perform ion implantation to adjust the threshold voltage of the memory channel alone. This further limits the size reduction of the SONOS Flash cell. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a mirrored SONOS flash memory unit, which can simplify the formation process of the channel region of the selection tube and the storage tube, and is conducive to reducing the channel length of the entire selection tube, the storage tube and the entire unit. To this end, the present invention also provides a manufacturing method of the mirrored SONOS flash memory unit.

[0006] To solve the above technical problems, the mirror bit SONOS flash memory unit provided by the present invention includes: a selection tube and a storage tube, the selection tube is an enhancement MOS transistor and has a first threshold voltage, and the storage tube is a depletion SONOS storage transistor and has a second threshold voltage in a state where no charge is stored.

[0007] The selection tube and the storage tube share a source region and a drain region heavily doped with a first conductivity type formed on a well region doped with a second conductivity type; the well region is formed on a semiconductor substrate.

[0008] A buried channel layer lightly doped with a first conductivity type is formed on the surface of the well region between the source region and the drain region.

[0009] The channel region is formed by combining the well region between the source region and the drain region and the buried channel layer.

[0010] A first gate structure of a selection tube and a second gate structure of a storage tube are arranged on the channel region. The first gate structure and the second gate structure perform segmented control on the channel region. The channel region in the area covered by the first gate structure is a first segment channel region, and the channel region in the area covered by the second gate structure is a second segment channel region.

[0011] The first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer.

[0012] The second gate structure is formed by stacking a second gate storage dielectric layer and a second gate conductive material layer; the second gate storage dielectric layer is an ONO layer.

[0013] The bottom surface of the second gate storage dielectric layer directly contacts the buried channel layer, the second channel region is composed of the buried channel layer, and the first conductivity type lightly doped structure of the buried channel layer enables the storage tube to have a second threshold voltage when no charge is stored.

[0014] A first groove is formed in the formation area of ​​the first gate structure, the first groove passes through the buried channel layer and exposes the surface of the well region at the bottom of the buried channel layer, and the first groove cuts off the buried channel layer; the first gate dielectric layer is formed in the first groove, the bottom surface of the first gate dielectric layer directly contacts the well region, the first section of the channel region is composed of the well region, and the second conductive type doping structure of the well region enables the selection transistor to have the first threshold voltage. The first groove makes the first section of the channel region and the second section of the channel region staggered longitudinally, so that the buried channel layer is a full injection layer between the source region and the drain region, so as to reduce the channel length.

[0015] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0016] A further improvement is that a first inner sidewall is provided between the first gate structure and the second gate structure.

[0017] The first groove is formed by etching the semiconductor material of the semiconductor substrate with the first inner sidewall as a self-alignment condition.

[0018] A further improvement is that the mirrored SONOS flash memory cell has a 1.5T structure.

[0019] A further improvement is that two second gate structures are arranged on the channel region, and the two second gate structures are symmetrically arranged on both sides of the first gate structure.

[0020] The first inner sidewall forms an inner side surface corresponding to the second gate structure.

[0021] The two first inner sidewalls are self-aligned to define the first groove and a formation area of ​​the entire first gate structure.

[0022] A further improvement is that outer sidewalls are formed on the outer side surfaces of the two second gate structures in a self-aligned manner.

[0023] The source region and the drain region are self-aligned with the corresponding outer sidewalls.

[0024] A further improvement is that two lightly doped drain regions of the first conductivity type are self-alignedly formed in the well regions on the outer sides of the two second gate structures.

[0025] A further improvement is that the storage tube and the selection tube are both N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type; the first gate conductive material layer uses an N-type heavily doped first polysilicon gate, and the second gate conductive material layer uses an N-type heavily doped second polysilicon gate.

[0026] A further improvement is that both the storage tube and the selection tube are P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type; the first gate conductive material layer uses a P-type heavily doped first polysilicon gate, and the second gate conductive material layer uses a P-type heavily doped second polysilicon gate.

[0027] In order to solve the above technical problems, the present invention provides a method for manufacturing a mirrored SONOS flash memory cell, wherein the mirrored SONOS flash memory cell includes a selection tube and a storage tube, wherein the selection tube is an enhancement MOS transistor and has a first threshold voltage, and the storage tube is a depletion SONOS storage transistor and has a second threshold voltage in a state where no charge is stored, and the formation steps include:

[0028] Step 1: forming a well region doped with a second conductivity type on a semiconductor substrate.

[0029] Step 2: Performing buried channel ion implantation with light doping of the first conductivity type to form a buried channel layer on the surface of the well region. In the formation area of ​​the mirror position SONOS flash memory cell, the buried channel ion implantation is a full implantation to help reduce the channel length.

[0030] Step three: forming a first gate structure of the selection tube and a second gate structure of the storage tube on the formation area of ​​the channel region.

[0031] The first gate structure and the second gate structure perform segmented control on the channel region. The channel region in the area covered by the first gate structure is a first segment of the channel region, and the channel region in the area covered by the second gate structure is a second segment of the channel region.

[0032] The first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer.

[0033] The second gate structure is formed by stacking a second gate storage dielectric layer and a second gate conductive material layer; the second gate storage dielectric layer is an ONO layer.

[0034] The bottom surface of the second gate storage dielectric layer directly contacts the buried channel layer, the second channel region is composed of the buried channel layer, and the first conductivity type lightly doped structure of the buried channel layer enables the storage tube to have a second threshold voltage when no charge is stored.

[0035] A first groove is formed in the formation area of ​​the first gate structure, the first groove passes through the buried channel layer and exposes the surface of the well region at the bottom of the buried channel layer, and the first groove cuts off the buried channel layer; the first gate dielectric layer is formed in the first groove, the bottom surface of the first gate dielectric layer directly contacts the well region, the first section of the channel region is composed of the well region, and the second conductive type doping structure of the well region enables the selection tube to have the first threshold voltage.

[0036] Step 4: Perform source and drain implantation to self-align on the well regions on both sides of the channel region to form heavily doped source and drain regions of the first conductivity type, wherein the source and drain regions are shared by the selection tube and the storage tube.

[0037] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0038] A further improvement is that in step three, a first inner sidewall is provided between the first gate structure and the second gate structure.

[0039] The first groove is formed by etching the semiconductor material of the semiconductor substrate with the first inner sidewall as a self-alignment condition.

[0040] A further improvement is that the mirrored SONOS flash memory cell has a 1.5T structure.

[0041] A further improvement is that two second gate structures are arranged on the channel region, and the two second gate structures are symmetrically arranged on both sides of the first gate structure.

[0042] The first inner sidewall forms an inner side surface corresponding to the second gate structure.

[0043] The two first inner sidewalls are self-aligned to define the first groove and a formation area of ​​the entire first gate structure.

[0044] A further improvement is that step three includes the following sub-steps:

[0045] Step 31 : sequentially forming the second gate storage dielectric layer and the second gate conductive material layer.

[0046] Step 32: forming a hard mask layer on the surface of the second gate conductive material layer.

[0047] Step 33: pattern-etching the hard mask layer to form a first opening surrounded by the hard mask layer.

[0048] Step 34: forming a second inner side wall on the inner side surface of the first opening, and forming a second opening in the first opening surrounded by the inner side surface of the second inner side wall.

[0049] Step 35 , performing self-aligned etching on the second gate conductive material layer at the bottom of the second opening to form two inner side surfaces of the second gate structure.

[0050] Step 36: Form the first inner sidewall on the inner side surface of the second gate structure and the inner side surface of the second inner sidewall, wherein the inner side surface of the first inner sidewall encloses a third opening.

[0051] Step 37 , performing self-aligned etching on the second gate conductive material layer at the bottom of the third opening, and then performing self-aligned etching on the semiconductor material of the semiconductor substrate at the bottom to form the first groove.

[0052] Step 38: forming the first gate dielectric layer on the surface of the well region exposed by the first groove.

[0053] Step 39: Fill the first gate conductive material layer in the third opening and in a bottom region of the third opening located above the surface of the first gate dielectric layer.

[0054] Step 310: remove the hard mask layer to expose the outer side surface of the second inner sidewall.

[0055] Step 311 , performing self-aligned etching on the second gate conductive material layer and the second gate conductive material layer with the outer side surface of the second inner sidewall as a self-aligned condition to form two outer side surfaces of the second gate structure.

[0056] A further improvement is that after step 311 is completed, a step of self-aligning and forming outer sidewalls on the outer side surfaces of the two second gate structures is also included.

[0057] In step 4, the source and drain implantation is performed using the outer side surface of the outer wall as a self-alignment condition.

[0058] A further improvement is that after step 311 is completed and before the outer side wall is formed, the following steps are further included:

[0059] Lightly doped drain implantation is performed to form lightly doped drain regions in a self-aligned manner in the well regions on the outer sides of the two second gate structures.

[0060] A further improvement is that the storage tube and the selection tube are both N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type; the first gate conductive material layer uses an N-type heavily doped first polysilicon gate, and the second gate conductive material layer uses an N-type heavily doped second polysilicon gate;

[0061] A further improvement is that both the storage tube and the selection tube are P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type; the first gate conductive material layer uses a P-type heavily doped first polysilicon gate, and the second gate conductive material layer uses a P-type heavily doped second polysilicon gate.

[0062] In the prior art, in order to set the selection tube and the storage tube in the mirror position SONOS flash memory unit to the enhancement type and the depletion type structure respectively, it is necessary to use the method of photolithography definition plus ion implantation to realize different doping in the regional segments of the channel region controlled by the selection tube and the storage tube respectively; unlike the prior art, the ion implantation process structure in different regional segments of the channel region of the present invention is the same, and is realized by using the well region and the buried channel layer formed on the well region, and at the same time, the first groove passing through the buried channel layer is combined to make the first channel region and the second channel region corresponding to the selection tube and the storage tube mutually vertically connected. The first channel region and the second channel region are staggered, thereby realizing the doping difference between the first channel region and the second channel region and realizing the adjustment of the threshold voltage of the selection tube and the storage tube. Therefore, the present invention does not need to perform photolithography definition on the ion implantation area in the channel region, and can realize full implantation to form a buried channel layer in the flash memory unit region. Finally, the limitation on size reduction caused by the photolithography process between the ion implantation areas in different regional segments of the channel region can be eliminated, and the formation process of the channel region of the selection tube and the storage tube can be simplified, which is beneficial to the reduction of the channel length of the entire selection tube, the storage tube and the entire unit, thereby improving the chip integration.

[0063] The first groove of the present invention can be realized by using a self-alignment process. Compared with the prior art which needs to use a photolithography process to define different doping regions of the channel region, the present invention can save the number of photolithography processes and reduce process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0065] Figure 1 1 is a schematic diagram of the structure of a mirrored SONOS flash memory unit according to an embodiment of the present invention;

[0066] Figure 2A-2MIt is a schematic diagram of the structures in each step of the method for manufacturing a mirrored SONOS flash memory unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0067] like Figure 1 , which is a schematic diagram of the structure of a mirror-bit SONOS flash memory unit according to an embodiment of the present invention; the mirror-bit SONOS flash memory unit according to the embodiment of the present invention comprises: a selection tube and a storage tube, wherein the selection tube is an enhancement-type MOS transistor and has a first threshold voltage, and the storage tube is a depletion-type SONOS storage transistor and has a second threshold voltage in a state where no charge is stored.

[0068] The selection tube and the storage tube share a source region and a drain region heavily doped with the first conductivity type formed on a well region 102 doped with the second conductivity type; the well region 102 is formed on a semiconductor substrate 101 . Figure 1 In the embodiment, the source region and the drain region are symmetrically structured and are both composed of the heavily doped region 113 of the first conductivity type.

[0069] In the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

[0070] A buried channel layer 103 lightly doped with a first conductivity type is formed on the surface of the well region 102 between the source region and the drain region.

[0071] The channel region is formed by combining the well region 102 and the buried channel layer 103 between the source region and the drain region.

[0072] A first gate structure of a selection tube and a second gate structure of a storage tube are arranged on the channel region. The first gate structure and the second gate structure perform segmented control on the channel region. The channel region in the area covered by the first gate structure is a first segment channel region, and the channel region in the area covered by the second gate structure is a second segment channel region.

[0073] The first gate structure is formed by stacking a first gate dielectric layer 109 and a first gate conductive material layer 110 .

[0074] The second gate structure is formed by stacking a second gate storage dielectric layer 104 and a second gate conductive material layer 105; the second gate storage dielectric layer 104 is an ONO layer, and the ONO layer includes a bottom oxide layer 104a, an intermediate nitride layer 104b and a top oxide layer 104c. The bottom oxide layer 104a is used as a tunneling layer, the intermediate nitride layer 104b is used as a storage layer, and the top oxide layer 104c is used as a control oxide layer.

[0075] The bottom surface of the second gate storage dielectric layer 104 directly contacts the buried channel layer 103, the second channel region is composed of the buried channel layer 103, and the first conductivity type lightly doped structure of the buried channel layer 103 enables the storage tube to have a second threshold voltage when no charge is stored, and the second threshold voltage makes the storage tube a depletion-type SONOS storage transistor.

[0076] A first groove 108 is formed in the formation area of ​​the first gate structure. The first groove 108 passes through the buried channel layer 103 and exposes the surface of the well region 102 at the bottom of the buried channel layer 103. The first groove 108 cuts off the buried channel layer 103. The first gate dielectric layer 109 is formed in the first groove 108. The bottom surface of the first gate dielectric layer 109 directly contacts the well region 102. The first section of the channel region is composed of the well region 102. The second conductive type doping structure of the well region 102 enables the selection transistor to have the first threshold voltage. The first threshold voltage enables the selection transistor to be an enhancement MOS transistor. The first groove 108 causes the first section of the channel region and the second section of the channel region to be longitudinally staggered, so that the buried channel layer 103 is a full injection layer between the source region and the drain region, so as to reduce the channel length.

[0077] In the embodiment of the present invention, a first inner sidewall 107 is provided between the first gate structure and the second gate structure.

[0078] The first groove 108 is formed by etching the semiconductor material of the semiconductor substrate 101 under the self-alignment condition of the first inner sidewall 107 .

[0079] The mirrored SONOS flash memory cell has a 1.5T structure.

[0080] Two second gate structures are disposed on the channel region, and the two second gate structures are symmetrically arranged on both sides of the first gate structure.

[0081] The first inner sidewall 107 forms an inner side surface corresponding to the second gate structure.

[0082] The two first inner sidewalls 107 are self-aligned to define the first groove 108 and the formation area of ​​the entire first gate structure.

[0083] External sidewalls 112 are formed on the outer sides of the two second gate structures in a self-aligned manner. Figure 1 In the embodiment, the outer sidewall 112 is formed by stacking a silicon oxide sidewall 112a and a silicon nitride sidewall 112b.

[0084] The source region and the drain region are self-aligned with the corresponding outer sidewalls 112 .

[0085] Two lightly doped drain regions 111 of the first conductivity type are formed in the well region 102 on the outer side surfaces of the two second gate structures in a self-aligned manner.

[0086] Figure 1 In the embodiment, a second inner sidewall 106 is further formed on the top of the second gate structure. In the embodiment of the present invention, the inner and outer side surfaces of the second gate structure are respectively defined by the inner and outer side surfaces of the second inner sidewall 106 being self-aligned.

[0087] In the embodiment of the present invention, the storage tube and the selection tube are both N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type; the first gate conductive material layer 110 uses a first polysilicon gate heavily doped with N-type, and the second gate conductive material layer 105 uses a second polysilicon gate heavily doped with N-type. In other embodiments, it can also be: the storage tube and the selection tube are both P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type; the first gate conductive material layer 110 uses a first polysilicon gate heavily doped with P-type, and the second gate conductive material layer 105 uses a second polysilicon gate heavily doped with P-type.

[0088] In the field of semiconductor technology, the threshold voltage of MOS transistors corresponds to the type of device, i.e., depletion type and enhancement type. For N-type devices, the threshold voltage of depletion type MOS transistors will be less than 0V, so that they will be turned on when the gate-source voltage of the device is 0V. When the device needs to be turned off, a negative voltage needs to be added to the gate, so that the gate-source voltage is negative and the absolute value is greater than the threshold voltage, so that the carriers, i.e., electrons, in the channel region can be depleted and the device can be cut off. Conversely, the threshold voltage of enhancement type MOS transistors will be greater than 0V, and the device will be cut off when the gate-source voltage is 0V; if the device is to be turned on, a positive voltage needs to be added to the gate, so that the gate-source voltage is greater than the threshold voltage, so that the carriers will be attracted to the channel, thereby turning on the device.

[0089] According to the working principle, when both the selection tube and the storage tube are N-type devices, the first threshold voltage will be positive, so that the selection tube is an enhancement MOS transistor, so the first threshold voltage is positive and the selection tube is an enhancement MOS transistor. There is a one-to-one correspondence; and the second threshold voltage is negative, so that the storage tube is a depletion SONOS storage transistor, so the second threshold voltage is negative and the storage tube is a depletion SONOS storage transistor. There is also a one-to-one correspondence. Under the condition that the selection tube is depletion type, the specific size of the first threshold voltage can be set according to actual needs, and under the condition that the storage tube is a depletion SONOS storage transistor, the specific size of the second threshold voltage can be set according to actual needs.

[0090] In the prior art, in order to set the selection tube and the storage tube in the mirrored SONOS flash memory cell to the enhancement type and the depletion type structure respectively, it is necessary to use a method of photolithography definition plus ion implantation to realize different doping in the regional segments of the channel region controlled by the selection tube and the storage tube respectively; unlike the prior art, the ion implantation process structure in different regional segments of the channel region in the embodiment of the present invention is the same, and is realized by using the well region 102 and the buried channel layer 103 formed on the well region 102, and at the same time, the first groove 108 passing through the buried channel layer 103 is combined to make the first channel region and the second channel region corresponding to the selection tube and the storage tube They are staggered in the vertical direction, so as to achieve the doping difference between the first channel region and the second channel region and realize the adjustment of the threshold voltage of the selection tube and the storage tube. Therefore, the embodiment of the present invention does not need to perform photolithography definition on the ion implantation area in the channel region, and can achieve full implantation to form the buried channel layer 103 in the flash memory unit area. Finally, the limitation on size reduction caused by the photolithography process between the ion implantation areas in different regional segments of the channel region can be eliminated, and the formation process of the channel region of the selection tube and the storage tube can be simplified, which is beneficial to the reduction of the channel length of the entire selection tube, the storage tube and the entire unit, thereby improving the chip integration.

[0091] The first groove 108 of the embodiment of the present invention can be implemented by a self-alignment process. Compared with the prior art which requires a photolithography process to define different doping regions of the channel region, the embodiment of the present invention can save the number of photolithography processes and reduce process costs.

[0092] like Figures 2A to 2M , which is a schematic diagram of the structure of each step of the manufacturing method of the mirror position SONOS flash memory cell according to the embodiment of the present invention; in the manufacturing method of the mirror position SONOS flash memory cell according to the embodiment of the present invention, the mirror position SONOS flash memory cell includes a selection tube and a storage tube, the selection tube is an enhancement MOS transistor and has a first threshold voltage, the storage tube is a depletion SONOS storage transistor and has a second threshold voltage in a state where no charge is stored, and the formation steps include:

[0093] Step 1: Figure 2A As shown, a well region 102 doped with a second conductivity type is formed on a semiconductor substrate 101 .

[0094] In the method of the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

[0095] Step 2: Figure 2A As shown, buried channel ion implantation with light doping of the first conductivity type is performed to form a buried channel layer 103 on the surface of the well region 102. In the formation area of ​​the mirror position SONOS flash memory cell, the buried channel ion implantation is a full implantation to help reduce the channel length.

[0096] Step three: forming a first gate structure of the selection tube and a second gate structure of the storage tube on the formation area of ​​the channel region.

[0097] The first gate structure and the second gate structure perform segmented control on the channel region. The channel region in the area covered by the first gate structure is a first segment of the channel region, and the channel region in the area covered by the second gate structure is a second segment of the channel region.

[0098] The first gate structure is formed by stacking a first gate dielectric layer 109 and a first gate conductive material layer 110 .

[0099] The second gate structure is formed by stacking a second gate storage dielectric layer 104 and a second gate conductive material layer 105 ; the second gate storage dielectric layer 104 is an ONO layer.

[0100] The bottom surface of the second gate storage dielectric layer 104 directly contacts the buried channel layer 103. The second channel region is composed of the buried channel layer 103. The first conductivity type lightly doped structure of the buried channel layer 103 enables the storage tube to have a second threshold voltage when no charge is stored.

[0101] A first groove 108 is formed in the formation area of ​​the first gate structure, the first groove 108 passes through the buried channel layer 103 and exposes the surface of the well region 102 at the bottom of the buried channel layer 103, and the first groove 108 cuts off the buried channel layer 103; the first gate dielectric layer 109 is formed in the first groove 108, the bottom surface of the first gate dielectric layer 109 directly contacts the well region 102, the first section of the channel region is composed of the well region 102, and the second conductive type doping structure of the well region 102 enables the selection tube to have the first threshold voltage.

[0102] In the method of the embodiment of the present invention, the first gate structure and the second gate structure are separated by a first inner sidewall 107 .

[0103] The first groove 108 is formed by etching the semiconductor material of the semiconductor substrate 101 under the self-alignment condition of the first inner sidewall 107 .

[0104] The mirrored SONOS flash memory cell has a 1.5T structure.

[0105] Two second gate structures are disposed on the channel region, and the two second gate structures are symmetrically arranged on both sides of the first gate structure.

[0106] The first inner sidewall 107 forms an inner side surface corresponding to the second gate structure.

[0107] The two first inner sidewalls 107 are self-aligned to define the first groove 108 and the formation area of ​​the entire first gate structure.

[0108] Preferably, step three includes the following sub-steps:

[0109] Step 31: Figure 2B As shown, the second gate storage dielectric layer 104 is formed. The ONO layer of the second gate storage dielectric layer 104 includes a bottom oxide layer 104a, a middle nitride layer 104b and a top oxide layer 104c.

[0110] like Figure 2C As shown, the second gate conductive material layer 105 is formed.

[0111] Step 32: Figure 2C As shown, a hard mask layer 201 is formed on the surface of the second gate conductive material layer 105 .

[0112] Step 33: Figure 2D As shown, the hard mask layer 201 is patterned and etched to form a first opening 202 surrounded by the hard mask layer 201 .

[0113] Step 34: Figure 2E As shown, a second inner side wall 106 is formed on the inner side surface of the first opening 202 , and a second opening 203 surrounded by the inner side surface of the second inner side wall 106 is formed in the first opening 202 .

[0114] Step 35: Figure 2F As shown, the second gate conductive material layer 105 at the bottom of the second opening 203 is self-aligned and etched to form two inner side surfaces of the second gate structure.

[0115] Step 36: Figure 2G As shown, the first inner sidewall 107 is formed on the inner side surface of the second gate structure and the inner side surface of the second inner sidewall 106 , and the inner side surface of the first inner sidewall 107 encloses a third opening 204 .

[0116] Step 37: Figure 2H As shown, the second gate conductive material layer 105 at the bottom of the third opening 204 is self-aligned and etched.

[0117] like Fig.2I As shown, the semiconductor material of the semiconductor substrate 101 at the bottom is then self-aligned and etched to form the first groove 108 .

[0118] Step 38: Figure 2JAs shown, the first gate dielectric layer 109 is formed on the surface of the well region 102 exposed by the first groove 108 .

[0119] Step 39: Figure 2K As shown, the first gate conductive material layer 110 is filled in the third opening 204 and in the bottom region of the third opening 204 located above the surface of the first gate dielectric layer 109 .

[0120] Step 310: Figure 2L As shown, the hard mask layer 201 is removed to expose the outer side surface of the second inner sidewall 106 .

[0121] Step 311: Figure 2L As shown, the second gate conductive material layer 105 and the second gate conductive material layer 105 are self-aligned and etched with the outer side surface of the second inner spacer 106 as a self-alignment condition to form the outer side surfaces of two second gate structures.

[0122] Afterwards, if Figure 2M As shown, a lightly doped drain implantation is performed to form a lightly doped drain region 111 in a self-aligned manner in the well region 102 on the outer sides of the two second gate structures.

[0123] Afterwards, if Figure 1 As shown, outer sidewalls 112 are formed on the outer side surfaces of the two second gate structures in a self-aligned manner.

[0124] Step 4: Figure 1 As shown, the outer side surface of the outer wall 112 is used as a self-alignment condition to perform source and drain implantation to self-align on the well region 102 on both sides of the channel region to form a first conductive type heavily doped source region and drain region, and the source region and the drain region are shared by the selection tube and the storage tube.

[0125] In the method of the embodiment of the present invention, the storage tube and the selection tube are both N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type; the first gate conductive material layer 110 uses a first polysilicon gate heavily doped with N-type, and the second gate conductive material layer 105 uses a second polysilicon gate heavily doped with N-type. In other embodiments, the storage tube and the selection tube are both P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type; the first gate conductive material layer 110 uses a first polysilicon gate heavily doped with P-type, and the second gate conductive material layer 105 uses a second polysilicon gate heavily doped with P-type.

[0126] As can be seen from the above description, in the method of the embodiment of the present invention, the inner side surface of the second gate structure of the storage tube is first formed, and then the first groove 108 is formed by self-alignment. The buried channel layer 103 does not need to be defined by photolithography within the formation area of ​​the entire flash memory unit, that is, there is no need to perform separate photolithography definition on the buried channel layer 103 in the control area of ​​the storage tube and the selection tube, which is conducive to reducing the size of the entire channel area. In the method of the embodiment of the present invention, the inner side surface and the outer side surface of the second gate structure are both defined by self-alignment of the inner and outer side surfaces of the second side wall 106, and the outer side surface of the second side wall 106 is actually Figure 2D The inner side of the first opening 202 in the embodiment of the present invention only needs to be used. Figure 2D The corresponding one-time photolithography process can be formed, and the widths of the first gate structure and the second gate structure are formed by a self-alignment process, which can not only greatly reduce the process cost, but also minimize the size of the channel region.

[0127] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A mirrored SONOS flash memory cell, characterized in that: include: A selection tube and a storage tube, wherein the selection tube is an enhancement MOS transistor and has a first threshold voltage, and the storage tube is a depletion SONOS storage transistor and has a second threshold voltage in a state where no charge is stored; The selection tube and the storage tube share a source region and a drain region heavily doped with a first conductivity type formed on a well region doped with a second conductivity type; the well region is formed on a semiconductor substrate; A buried channel layer lightly doped with a first conductivity type is formed on the surface of the well region between the source region and the drain region; The channel region is formed by combining the well region and the buried channel layer between the source region and the drain region; A first gate structure of a selection tube and a second gate structure of a storage tube are arranged on the channel region, the first gate structure and the second gate structure perform segmented control on the channel region, the channel region in the area covered by the first gate structure is a first segment channel region, and the channel region in the area covered by the second gate structure is a second segment channel region; The first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer; The second gate structure is formed by stacking a second gate storage dielectric layer and a second gate conductive material layer; the second gate storage dielectric layer is an ONO layer; The bottom surface of the second gate storage dielectric layer directly contacts the buried channel layer, the second channel region is composed of the buried channel layer, and the first conductivity type lightly doped structure of the buried channel layer enables the storage tube to have a second threshold voltage in a state where no charge is stored; A first groove is formed in the formation area of ​​the first gate structure, the first groove passes through the buried channel layer and exposes the surface of the well region at the bottom of the buried channel layer, and the first groove cuts off the buried channel layer; the first gate dielectric layer is formed in the first groove, the bottom surface of the first gate dielectric layer directly contacts the well region, the first section of the channel region is composed of the well region, and the second conductive type doping structure of the well region enables the selection transistor to have the first threshold voltage; The first groove causes the first section of the channel region and the second section of the channel region to be longitudinally offset, so that the buried channel layer is a full-scale injection layer between the source region and the drain region, which is beneficial to shortening the channel length.

2. The mirrored SONOS flash memory cell according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.

3. The mirrored SONOS flash memory cell according to claim 1, wherein: A first inner sidewall is separated between the first gate structure and the second gate structure; The first groove is formed by etching the semiconductor material of the semiconductor substrate with the first inner sidewall as a self-alignment condition.

4. The mirrored SONOS flash memory cell according to claim 3, wherein: The mirrored SONOS flash memory cell has a 1.5T structure.

5. The mirrored SONOS flash memory cell according to claim 4, wherein: Two second gate structures are arranged on the channel region, and the two second gate structures are symmetrically arranged on both sides of the first gate structure; The first inner sidewall forms a corresponding inner side surface of the second gate structure; The two first inner sidewalls are self-aligned to define the first groove and a formation area of ​​the entire first gate structure.

6. The mirrored SONOS flash memory cell according to claim 5, wherein: External sidewalls are formed on the outer side surfaces of the two second gate structures in a self-aligned manner; The source region and the drain region are self-aligned with the corresponding outer sidewalls.

7. The mirrored SONOS flash memory cell according to claim 6, wherein: Two lightly doped drain regions of the first conductivity type are self-alignedly formed in the well regions on the outer sides of the two second gate structures.

8. The mirrored SONOS flash memory cell according to claim 1, wherein: The storage tube and the selection tube are both N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type; the first gate conductive material layer uses an N-type heavily doped first polysilicon gate, and the second gate conductive material layer uses an N-type heavily doped second polysilicon gate.

9. The mirrored SONOS flash memory cell according to claim 1, wherein: The storage tube and the selection tube are both P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type; the first gate conductive material layer uses a P-type heavily doped first polysilicon gate, and the second gate conductive material layer uses a P-type heavily doped second polysilicon gate.

10. A method for manufacturing a mirrored SONOS flash memory cell, characterized in that: The mirror bit SONOS flash memory cell includes a selection tube and a storage tube, wherein the selection tube is an enhancement MOS transistor and has a first threshold voltage, and the storage tube is a depletion SONOS storage transistor and has a second threshold voltage in a state where no charge is stored. The formation steps include: Step 1: forming a well region doped with a second conductivity type on a semiconductor substrate; Step 2: Performing buried channel ion implantation of lightly doped first conductivity type to form a buried channel layer on the surface of the well region. In the formation area of ​​the mirror position SONOS flash memory cell, the buried channel ion implantation is a full implantation to help reduce the channel length. Step 3: forming a first gate structure of the selection tube and a second gate structure of the storage tube on the formation area of ​​the channel region; The first gate structure and the second gate structure perform segmented control on the channel region, the channel region in the area covered by the first gate structure is a first segment of the channel region, and the channel region in the area covered by the second gate structure is a second segment of the channel region; The first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer; The second gate structure is formed by stacking a second gate storage dielectric layer and a second gate conductive material layer; the second gate storage dielectric layer is an ONO layer; The bottom surface of the second gate storage dielectric layer directly contacts the buried channel layer, the second channel region is composed of the buried channel layer, and the first conductivity type lightly doped structure of the buried channel layer enables the storage tube to have a second threshold voltage in a state where no charge is stored; A first groove is formed in the formation area of ​​the first gate structure, the first groove passes through the buried channel layer and exposes the surface of the well region at the bottom of the buried channel layer, and the first groove cuts off the buried channel layer; the first gate dielectric layer is formed in the first groove, the bottom surface of the first gate dielectric layer directly contacts the well region, the first section of the channel region is composed of the well region, and the second conductive type doping structure of the well region enables the selection transistor to have the first threshold voltage; Step 4: Perform source and drain implantation to self-align on the well regions on both sides of the channel region to form a heavily doped source region and drain region of the first conductivity type, wherein the source region and the drain region are shared by the selection tube and the storage tube.

11. The method for manufacturing a mirrored SONOS flash memory cell according to claim 10, wherein: The semiconductor substrate includes a silicon substrate.

12. The method for manufacturing a mirrored SONOS flash memory cell according to claim 10, wherein: In step three, a first inner sidewall is provided between the first gate structure and the second gate structure; The first groove is formed by etching the semiconductor material of the semiconductor substrate with the first inner sidewall as a self-alignment condition.

13. The method for manufacturing a mirrored SONOS flash memory cell according to claim 12, wherein: The mirrored SONOS flash memory cell has a 1.5T structure.

14. The method for manufacturing a mirrored SONOS flash memory cell according to claim 13, wherein: Two second gate structures are arranged on the channel region, and the two second gate structures are symmetrically arranged on both sides of the first gate structure; The first inner sidewall forms a corresponding inner side surface of the second gate structure; The two first inner sidewalls are self-aligned to define the first groove and a formation area of ​​the entire first gate structure.

15. The method for manufacturing a mirrored SONOS flash memory cell according to claim 14, wherein: Step 3 includes the following sub-steps: Step 31, sequentially forming the second gate storage dielectric layer and the second gate conductive material layer; Step 32, forming a hard mask layer on the surface of the second gate conductive material layer; Step 33, patterning and etching the hard mask layer to form a first opening surrounded by the hard mask layer; Step 34, forming a second inner side wall on the inner side surface of the first opening, and forming a second opening surrounded by the inner side surface of the second inner side wall in the first opening; Step 35, performing self-aligned etching on the second gate conductive material layer at the bottom of the second opening to form two inner side surfaces of the second gate structure; Step 36, forming the first inner sidewall on the inner side surface of the second gate structure and the inner side surface of the second inner sidewall, wherein the inner side surface of the first inner sidewall encloses a third opening; Step 37, performing self-aligned etching on the second gate conductive material layer at the bottom of the third opening, and then performing self-aligned etching on the semiconductor material of the semiconductor substrate at the bottom to form the first groove; Step 38, forming the first gate dielectric layer on the surface of the well region exposed by the first groove; Step 39, filling the first gate conductive material layer in the third opening and in the bottom region of the third opening located above the surface of the first gate dielectric layer; Step 310, removing the hard mask layer to expose the outer side surface of the second inner sidewall; Step 311 , performing self-aligned etching on the second gate conductive material layer and the second gate conductive material layer with the outer side surface of the second inner sidewall as a self-aligned condition to form two outer side surfaces of the second gate structure.

16. The method for manufacturing a mirrored SONOS flash memory cell according to claim 15, wherein: After step 311 is completed, the step of self-aligning and forming outer sidewalls on the outer side surfaces of the two second gate structures is also included; In step 4, the source and drain implantation is performed using the outer side surface of the outer wall as a self-alignment condition.

17. The method for manufacturing a mirrored SONOS flash memory cell according to claim 16, wherein: After step 311 is completed and before the outer wall is formed, the following steps are also included: Lightly doped drain implantation is performed to form lightly doped drain regions in a self-aligned manner in the well regions on the outer sides of the two second gate structures.

18. The method for manufacturing a mirrored SONOS flash memory cell according to claim 10 or 15, characterized in that: The storage tube and the selection tube are both N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type; the first gate conductive material layer uses an N-type heavily doped first polysilicon gate, and the second gate conductive material layer uses an N-type heavily doped second polysilicon gate.

19. The method for manufacturing a mirrored SONOS flash memory cell according to claim 10 or 15, characterized in that: The storage tube and the selection tube are both P-type devices, the first conductivity type is P-type, and the second conductivity type is N-type; the first gate conductive material layer uses a P-type heavily doped first polysilicon gate, and the second gate conductive material layer uses a P-type heavily doped second polysilicon gate.

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