Pulse width modulation generated by a Σ-Δ loop

Abstract

Embodiments of the present disclosure relate to pulse width modulation generated by a Σ-Δ loop. A Σ-Δ (SD) pulse width modulation (PWM) loop includes a loop filter that implements a linear transfer function to generate a loop filter signal, where the loop filter is configured to receive an input signal and a first feedback signal, and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator being configured to receive the loop filter signal and generate a Σ-Δ PWM signal based on the loop filter signal, where the first feedback signal is derived from the Σ-Δ PWM signal.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to pulse width modulation generated by a Σ-Δ loop. Background Art

[0002] Many applications for pulse width modulation (PWM) include voltage regulation, power level control, and motor control, to name just a few. Each PWM cycle (i.e., transmission cycle) includes a high time for the first part of the PWM cycle, followed by a low time for the second part of the PWM cycle, and vice versa. The durations of the first and second parts are regulated by a pulse width modulator, which is typically a PWM circuit or a processor. In both states, the power consumption is low because in one state, there is no current through the driver, and in the other state, there is a low switching resistance at the driver.

[0003] PWM is widely used for transmitting sensor data due to its simplicity. However, it has a serious drawback, which is the long time required to transmit a single value. This latency problem increases exponentially with the resolution of the required data transmission. The reception of data is significantly delayed relative to the sampling time. This delay will limit the achievable speed of the control loop that utilizes the sensor data.

[0004] The PWM signal approximates a continuous analog signal by a fast sequence of rectangular signals. Adequate oversampling rate is required for proper approximation of the signal. The spectrum of the resulting approximated signal contains: (1) the carrier frequency and its harmonics, and (2) quantization noise due to the finite number of clocks belonging to the PWM cycle. Of course, it also includes the spectrum of the band-limited approximated signal. There should be sufficient gap between the PWM carrier and the end of the signal band to allow reconstruction of the signal with a low-pass filter.

[0005] For example, Figure 1A includes an input signal (top) and a digital PWM output signal (bottom). The duty cycle of the digital PWM output signal changes based on the value of the input signal with a constant switching frequency. In particular, the duty cycle is highest at the zero-crossing points of the sinusoidal input signal and lowest at the two extreme values of the sinusoidal input signal.

[0006] Figure 1B shows Figure 1A the signal spectrum of the digital PWM output signal shown in. As can be seen from the signal spectrum, PWM causes a relatively high level of harmonics of the carrier frequency of the PWM signal, where the first harmonic is substantially equal to or greater than the peak of the carrier frequency. The harmonics of the switching frequency repeat with a decreasing spectral density. These harmonics can be referred to as distortion harmonics. It is desirable to reduce the spectral density of the distortion harmonics.

[0007] A known alternative to PWM is a Σ-Δ modulated signal that uses a loop filter to distribute quantization noise over the entire spectrum according to a noise transfer function that is designed to shift the quantization noise to high frequencies where it can be easily attenuated by the filter. Compared to one in PWM, its spectrum is significantly improved with respect to the noise spectral density in the frequency range around the PWM switching frequency and the maximum value of the higher frequency spectral components related to electromagnetic emissions. Unfortunately, it comes at the cost of a far higher number of transitions, where the transitions in the output stage result in a significant increase in power consumption. In addition, the rising and falling edges can have different steepness because they are generated by pull-up or pull-down devices that do not match very accurately. This results in an increase in the inaccuracy of the approximate signal, which gets worse as the number of edges increases.

[0008] Accordingly, embodiments provided herein provide a pulse width modulator and a PWM method having a reduced spectral density of distortion harmonics. SUMMARY OF THE INVENTION

[0009] An embodiment provides a Σ-Δ (SD) pulse width modulation (PWM) loop that includes a loop filter that implements a linear transfer function to generate a loop filter signal, where the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator being configured to receive the loop filter signal and generate a Σ-Δ PWM signal based on the loop filter signal, where the first feedback signal is derived from the Σ-Δ PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments are described herein with reference to the drawings.

[0011] Figure 1A An analog input signal (top) and a digital PWM output signal (bottom) including a conventional pulse width modulator (PWM);

[0012] Figure 1B shows Figure 1A the signal spectrum of the digital PWM output signal shown in;

[0013] Figure 2A is a schematic block diagram of a system using a pulse width modulator according to one or more embodiments;

[0014] Figure 2B is a schematic block diagram of another system using a pulse width modulator according to one or more embodiments;

[0015] Figure 3Schematic diagram of Σ-Δ PWM according to one or more embodiments;

[0016] Figure 4A including the input signal Sin (top) of the Σ-Δ PWM corresponding to Figure 3 and the Σ-Δ PWM output signal Sout (bottom);

[0017] Figure 4B showing Figure 4A the signal spectrum of the output signal Sout shown in

[0018] Figure 5 Schematic diagram of Σ-Δ PWM according to one or more embodiments;

[0019] Figure 6A including the input signal Sin (top) of the Σ-Δ PWM corresponding to Figure 5 and the Σ-Δ PWM output signal Sout (bottom);

[0020] Figure 6B showing Figure 6A the signal spectrum of the output signal Sout shown in

[0021] Figure 7 Generalized schematic block diagram of a Σ-Δ PWM modulator with a loop filter according to one or more embodiments;

[0022] Figure 8 Schematic diagram of Σ-Δ PWM according to one or more embodiments;

[0023] Figure 9A including the input signal Sin (top) of the Σ-Δ PWM corresponding to Figure 8 and the Σ-Δ PWM output signal Sout (bottom); and

[0024] Figure 9B showing Figure 9A the signal spectrum of the output signal Sout shown in Detailed implementation

[0025] Details are set forth below to provide a more thorough explanation of the exemplary embodiments. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form or in schematic views rather than in detail to avoid obscuring the embodiments. Additionally, the features of the different embodiments described below may be combined with each other unless otherwise specifically noted.

[0026] In addition, in the following description, like or similar reference numerals are used to denote like or similar elements or elements having like or similar functions. Since like or functionally equivalent elements are given the same reference numerals in the drawings, the repeated description of elements provided with the same reference numerals may be omitted. Thus, the descriptions provided for elements with the same or similar reference numerals are mutually interchangeable.

[0027] In this regard, directional terms such as "top", "bottom", "below", "above", "forward", "backward", "rear", "front", "rear", etc. may be used with reference to the orientation of the described drawings. Since parts of the embodiments may be positioned in many different orientations, the directional terms are for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Thus, the following detailed description should not be taken in a limiting sense.

[0028] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.).

[0029] In the embodiments described herein or shown in the drawings, any direct electrical connection or coupling (i.e., any connection or coupling without additional intervening elements) can also be achieved by an indirect connection or coupling (i.e., a connection or coupling having one or more additional intervening elements, or vice versa), as long as the general purpose of the connection or coupling (e.g., transmitting a particular type of signal or transmitting a particular type of information) is substantially maintained. Features from different embodiments can be combined to form additional embodiments. For example, changes or modifications described with respect to one of the embodiments may also apply to other embodiments, unless stated to the contrary.

[0030] The term "substantially" may be used herein to explain small manufacturing tolerances (e.g., within 5%) that are considered acceptable in the industry without departing from the aspects of the embodiments described herein.

[0031] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. may modify various elements. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only for the purpose of distinguishing elements from other elements. For example, the first box and the second box indicate different boxes, but both are boxes. Also, for example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0032] One or more aspects of the present disclosure may be implemented as a non-transitory computer-readable recording medium having recorded thereon a program of a method / algorithm for instructing a processor to execute the method / algorithm. Thus, the non-transitory computer-readable recording medium may have an electronically readable control signal stored thereon that cooperates (or is capable of cooperating) with a programmable computer system such that the corresponding method / algorithm is executed. The non-transitory computer-readable recording medium may be, for example, a CD-ROM, DVD, Blu-ray disc, RAM, ROM, PROM, EPROM, EEPROM, flash memory, or an electronic memory device.

[0033] Each element in the elements of the present disclosure may be configured by implementing dedicated hardware or a software program on a memory that controls a processor to execute the functions of any component or a combination thereof. Any one of the components may be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a recording medium such as a hard disk or a semiconductor memory device. For example, the instructions may be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuitry.

[0034] Accordingly, as used herein, the term "processor" refers to any one of the foregoing structures or any other structure suitable for implementing the techniques described herein. A controller including hardware may also execute one or more of the techniques of the present invention. A controller including one or more processors may use electrical signals and digital algorithms to perform its receiving, analyzing, and controlling functions, which may further include correction functions. Such hardware, software, and firmware may be implemented within the same device or within separate devices to support the various techniques described in the present invention.

[0035] A signal processing circuit and / or a signal conditioning circuit can receive one or more signals from one or more components and perform signal conditioning or processing thereon. As used herein, signal conditioning refers to manipulating a signal in a manner such that the signal meets the requirements of the next stage for further processing. Signal conditioning can include converting from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, bypassing, range matching, isolation, and any other processes required to make the signal suitable for processing after conditioning.

[0036] Accordingly, the signal processing circuit can include an analog-to-digital converter (ADC) that converts an analog signal from one or more sensor elements into a digital signal. The signal processing circuit can also include a digital signal processor (DSP) that performs some processing on the digital signal.

[0037] Figure 2A FIG. 7 is a schematic block diagram of a system 100 in accordance with one or more embodiments that uses a pulse-width modulator. The system includes a data source 10, a Σ-Δ pulse-width modulator (SDPWM) 12, an RC circuit 14, and an analog output Aout. The data source 10 can be a sensor configured to generate a sensor signal (i.e., a data signal) in response to measuring a physical quantity such as temperature, pressure, magnetic field, voltage, current, etc. The SDPWM 12 includes an input Din that receives the sensor signal. The SD PWM 12 samples the sensor signal received at the input Din at a predetermined time interval and generates a PWM signal based on the received data.

[0038] The RC circuit 14 is a low-pass filter (LPF) that converts the PWM signal into an analog signal. Thus, the analog signal is output from the RC circuit 14 via the analog output Aout. The analog signal is an average signal that represents the average value of a plurality of PWM periods or cycles.

[0039] The SD PWM 12 can be used to transfer data from the sensor to a microcontroller (not shown) of an electronic control unit (ECU). In this case, it is also used to replace an analog signal that is very sensitive to electromagnetic interference (EMI) and thus requires a large and expensive linear output driver. The SD PWM 12 transmits the PWM signal in binary encoding, and the RC circuit 14 on the receiving side can be used to convert the PWM signal into an analog signal. The pulse-width modulator 12 drives the switching of the PWM signal to a voltage source or ground, and thus requires only a minimum chip area compared to the linear output stage of an analog signal. Accordingly, the system 100 can be an output stage of a communication interface.

[0040] Figure 2BSchematic block diagram of a system 200 using SDPWM according to one or more embodiments. The system 200 may include an inverter control unit 20, a power inverter 21, and an electric motor 22. The inverter control unit 20 acts as a motor control unit for controlling the electric motor 22. The power inverter 21 may include a transistor bridge configured to provide three-phase power, for example, by providing three-phase voltages to drive the electric motor 22. The inverter control unit 20 includes a motor control circuit 24, such as a microcontroller implementing a motor control algorithm, and an SDPWM 26 that transmits a PWM control signal to the gates of a switch array that controls the transistor bridge.

[0041] In this case, the motor control circuit 24 is a data source that generates a data signal according to a motor control algorithm and receives the data signal at the input Din of the SD PWM 26. The SD PWM 26 samples the data signal received at the input Din at a predetermined interval and generates a PWM control signal based on the received data. Thus, the system 200 may be an output stage used in a power application.

[0042] Note that a low-pass filter for smoothing the switching current signal is not required because the smoothing is achieved by the mechanical inertia of the electric motor 22.

[0043] Figure 3 Schematic diagram of a Σ-Δ PWM 300 according to one or more embodiments. The Σ-Δ PWM 300 includes a digital Σ-Δ loop (e.g., a first-order Σ-Δ loop), which includes a loop filter 30, a digital hysteresis comparator 35, and a feedback path 36. The loop filter 30 receives an input signal Sin and a feedback signal FB (e.g., FB1) from the output of the hysteresis comparator and implements a linear transfer function. The hysteresis comparator 35 generates a Σ-Δ (SD) PWM signal as an output signal, and the feedback signal FB is derived therefrom.

[0044] The loop filter 30 includes a digital summer 31, a digital integrator 32, and a digital inverter 37. In particular, the Σ-Δ PWM 300 includes a digital summer 31, a digital integrator 32, a digital hysteresis comparator 35, and a feedback path 36 including a digital inverter 37. The inverter 37 multiplies the output Sout of the Σ-Δ PWM 300 by a first feedback coefficient having a value of -1. Other types of inverters that invert the output signal Sout may also be used. It should also be understood that a digital subtractor may be used instead of the digital summer 31 to subtract the output signal Sout from the input signal Sin to generate a subtracted signal. In this case, the output signal Sout will be the feedback signal, and the inverter 37 will not be required.

[0045] The hysteresis comparator 35 generates a digital output signal Sout (i.e., the Σ-Δ PWM signal) that switches between a high value or a low value, where high represents a + 1 and low represents a - 1. Thus, the output of the inverter 37 (feedback signal FB1) also switches between a low value or a high value (i.e., - 1 or 1), being the inversion of the digital output signal Sout. Similarly, the input signal Sin is a digital signal with a normalized amplitude that has discrete values limited within the range of + / - 1. It should be understood that the input signal is shown as being normalized merely for ease of understanding and is not limited thereto.

[0046] The input signal Sin and the feedback signal FB1 are added by the summer 31. The feedback signal FB1 is the inversion of the output signal Sout generated by the hysteresis comparator 35. The integrator 32 receives the sum signal S1sum, which is the sum of the input signal Sin and the feedback signal FB1 generated by the summer 31, and generates an integration signal S1int (i.e., the loop filter signal) based thereon. The hysteresis comparator 35 receives the integration signal S1int and generates the output signal Sout based on the comparison of S1int with its two hysteresis thresholds THup and THlow.

[0047] A value of - 1 at the input signal Sin results in a permanent low (i.e., - 1) at the output signal Sout for the Σ-Δ PWM period. Conversely, a value of + 1 at the input signal Sin results in a permanent high (i.e., + 1) at the output signal Sout for the Σ-Δ PWM period. A value of the input signal Sin between - 1 and + 1 is represented by the duty cycle of the output signal Sout, specifically the high time / (high time + low time) represented by the variation of the Σ-Δ PWM period. This means that even for a constant input value, depending on the history of the state of the integrator in the loop, the high time and the adjacent low time of adjacent Σ-Δ PWM periods will vary according to some clock cycles. This allows the implementation of the desired noise shaping characteristics. It is a hybrid of a standard PWM without any noise shaping and a standard Σ-Δ architecture without noise shaping, which has the highest relative difference with respect to the average length of the high state and the low state, which is much shorter than one of the Σ-Δ PWMs.

[0048] The absolute value of the feedback signal FB1 is always equal to or greater than the absolute value of the signal amplitude of the input signal Sin. In particular, in Figure 3 the case of the shown first-order Σ-Δ modulator, the absolute value of the input signal Sin can be less than or equal to the absolute value of the feedback signal FB1. In the case where the input signal Sin is equal to the output signal Sout, the sum signal S1sum generated by the summer 31 will be 0, and the integration signal S1int of the integrator 32 will not change until the absolute value of the input signal Sin becomes less than the absolute value of the feedback signal FB1 (for a normalized digital signal, Sin < 1).

[0049] However, for higher-order loops, the absolute value of the feedback signal FB1 should always be greater than the absolute value of the input signal Sin. The higher the order of the loop, the higher the margin required. Typical values for second- and third-order loops are 0.9 and 0.7 of the maximum (normalized) input amplitude, respectively. Thus, since the output value of the output signal is +1 or -1, its absolute value will always be greater than the input amplitude of the input signal Sin for second-order or higher-order loops.

[0050] When the sign of the feedback signal FB1 is the same as the sign of the input signal Sin, the integrated signal S1int is greater than the case where the signs of the input signal Sin and the feedback signal FB1 are opposite.

[0051] Since the absolute value feedback signal FB1 is always equal to or greater than the absolute value of the input signal Sin, both cases (Case 1 and Case 2 below) have opposite signs. Case 1: Sign(sin)=sign(FB1) results in a large integration step in the first direction depending on the signs of the two signals. Case 2: Sign(sin)=-Sign(FB1) results in a smaller integration step with the opposite sign compared to the first case, assuming the sign of the input signal Sin is the same in both cases.

[0052] Therefore, the integrator 32 will integrate the summing signal S1sum up or down to equal the increment / decrement of the sum or difference of the input signal Sin and the feedback signal FB1 according to the hysteresis comparator output. Additionally, depending on the signs of the input signal Sin and the feedback signal FB1, the integrator 32 will integrate at different speeds. When the input signal Sin and the feedback signal FB1 have the same sign, the integration speed is faster, and when the signals have opposite signs, the integration speed is slower. Thus, depending on the value of the input signal Sin, the periods of integration up and down between the two thresholds THup and THlow of the hysteresis comparator 35 will be different.

[0053] The hysteresis comparator 35 operates by checking its input (i.e., the integrated signal S1int) against an upper threshold THup and a lower threshold THlow. The upper threshold THup can be a positive value (greater than 1), and the lower threshold THlow can be a negative value (less than -1). The hysteresis of the comparator 35 is exactly the difference between the positive and negative thresholds THup and THlow. The hysteresis comparator 35 has a large hysteresis, for example, at least greater than the maximum amplitude of the input signal Sin. For example, for motor control, the hysteresis value can be at least 50 times the maximum amplitude of the input signal Sin, but the hysteresis value can vary according to the clock of the integrator 32. The faster the integrator, the higher the hysteresis for the same pseudo-PWM frequency. Thus, if the maximum amplitude of the input signal Sin is 1, a hysteresis level 50 times higher will provide an upper threshold THup of 50 and a lower threshold THlow of -50. Depending on the application, higher hysteresis levels greater than 100 times are possible, but as the switching frequency decreases as the hysteresis level increases, it will affect the switching frequency of the output signal Sout.

[0054] The hysteresis comparator 35 checks the two thresholds separately, and if the integrated signal S1int exceeds the positive threshold THup, the hysteresis comparator 35 uses logic to switch the sign of its output from positive (+) to negative (-) (e.g., from +1 to -1), and if the integrated signal S1int drops below the negative threshold THlow, the hysteresis comparator 35 uses logic to switch the sign of its output from negative (-) to positive (+) (e.g., from -1 to +1). Thus, the hysteresis comparator 35 can include two comparators that perform two threshold comparisons.

[0055] Returning to the operation of the digital Σ-Δ modulator, if the input signal Sin gets closer and closer to the feedback limit [-1,1] of the feedback signal FB1, the difference between the input signal Sin and the feedback signal FB1 becomes smaller, and the time required to integrate upward to the threshold THup or integrate in the opposite direction of the sign of the input signal Sin to THlow becomes quite long. Thus, in these cases, the PWM period (i.e., the switching frequency of the PWM signal Sout) increases. As the difference between the input signal Sin and the feedback signal FB1 increases, the PWM period (i.e., the switching frequency of the PWM signal Sout) decreases. Thus, the PWM period of the output signal Sout varies based on the difference between the input signal Sin and the feedback signal FB1.

[0056] If the input signal Sin will reach the feedback value of the feedback signal FB1, the integrator state will no longer change, and thus the feedback will remain constant until the input signal Sin becomes smaller than the feedback signal FB1. Therefore, the input signal Sin must necessarily be limited to values within the feedback range of the feedback signal FB1. In other words, the absolute value of the feedback signal FB1 is always equal to or greater than the absolute value of the input signal Sin, which can depend on the order of the Σ-Δ modulator as described above. The feedback limits [-1, 1] of the feedback signal FB1 represent the maximum and minimum values of the feedback signal FB1. Since the output value Sout of the hysteresis comparator 35 switches between +1 and -1, the feedback signal FB1 is also either -1 or +1. Naturally, any set of digital values can be used. For example, asymmetric values (e.g., 0 and 2) can also be used.

[0057] Although the Σ-Δ PWM 300 is described as a digital circuit, it can alternatively be composed of analog components. However, whether the Σ-Δ modulator is digital or analog depends on the application. Generally, if the input signal Sin is digital, the Σ-Δ modulator will be digital.

[0058] Figure 4A Includes the input signal Sin (top) corresponding to the Σ-Δ PWM 00 and the Σ-Δ PWM output signal Sout (bottom). The PWM period and switching frequency of the output signal Sout change based on the value of the input signal Sin. When the input signal Sin is zero, the switching frequency is the highest (and the PWM period is the lowest), and when the input signal Sin is at its maximum or minimum amplitude, the switching frequency is the lowest (and the PWM period is the highest). This change in the PWM period is non-linear when the input signal increases or decreases.

[0059] Figure 4B Shows Figure 4A The signal spectrum of the output signal Sout shown in. It can be seen from the signal spectrum that a continuous decreasing high-frequency spectrum with the maximum (peak) amplitude below the Σ-Δ PWM harmonics (i.e., harmonics below the carrier frequency of the Σ-Δ PWM 100) is generated. Therefore, the distortion spectrum is improved compared to the PWM spectrum.

[0060] Higher-order Σ-Δ loops can be used to obtain a steeper noise shaping transfer function. Figure 5Schematic diagram of a Σ-Δ PWM 400 according to one or more embodiments. The Σ-Δ PWM 400 includes a second-order digital Σ-Δ loop, which includes a loop filter 30, a digital hysteresis comparator 35, and a feedback path 36 that branches into two. Generally, compared with a first-order loop, a second-order loop has steeper noise shaping. The loop filter 30 receives both the input signal Sin and two feedback signals FB1 and FB2 from the output of the hysteresis comparator, and implements a linear transfer function. The hysteresis comparator 35 generates an SD PWM signal as the output signal, and the feedback signals FB1 and FB2 are derived therefrom.

[0061] The loop filter 30 includes a digital summer 31, a digital integrator 32 (i.e., the first digital integrator), a digital summer 33, a second digital integrator 34, a first digital coefficient multiplier 38, and a second digital coefficient multiplier 39.

[0062] The first digital coefficient multiplier 38 applies a first negative feedback coefficient N to the output signal Sout to generate a first feedback signal FB1. In the case where N is equal to -1, the first digital coefficient multiplier 38 can be an inverter. Alternatively, in the case where N is equal to +1, a digital subtractor can be used instead of the digital summer 31 to subtract the output signal Sout from the input signal Sin to generate a subtracted signal. In this case, the output signal Sout will be the feedback signal, and the first digital coefficient multiplier 38 or the inverter is not required.

[0063] More specifically, the Σ-Δ PWM 400 includes a digital summer 31, a digital integrator 32, a digital hysteresis comparator 35, and a feedback path 36. The feedback path 36 splits into two feedback paths or loops 36a and 36b, both of which are coupled to the output of the hysteresis comparator 35 and both receive the output signal Sout. The first feedback path 36a is similar to the feedback path described in Figure 3 It includes a first digital coefficient multiplier 38 that applies a negative feedback coefficient having a value N (e.g., -1). The second feedback path 36b is responsible for the stability of the Σ-Δ modulator and includes a second digital coefficient multiplier 39 that applies a second negative feedback coefficient M to the output signal Sout. The second negative feedback coefficient M is a negative value, which can be set, for example, to a value that is -2 to -0.25 times the hysteresis level. This will generally result in a value from -1 to -10, and more specifically, a value between -2 and -4. The second digital multiplier 39 receives the output signal Sout and multiplies it by its negative feedback coefficient M to generate a second feedback signal FB2.

[0064] The Σ-Δ PWM 400 further includes a second digital summer 33 and a second digital integrator 34 that are serially coupled between the first digital integrator 32 and the hysteresis comparator 35. If M is set to +1, the second summer 33 can be replaced by a subtractor, and the second digital multiplier 39 can be removed.

[0065] The second summer 33 receives the first integration signal S1int and the second feedback signal FB2, and sums them together to produce a second sum signal S2sum. The second sum signal S2sum is input to the second integrator 34, and the second integrator 34 generates a second integration signal S2int (i.e., the loop filter signal) based on this. The hysteresis comparator 35 receives the second integration signal S2int, and uses two separate comparisons in the above manner to generate an output signal Sout based on the comparison of S2int with its two hysteresis thresholds THup and THlow. Depending on whether the second integration signal S2int exceeds the upper threshold THup or the second integration signal S2int is less than the lower threshold THlow, the output signal Sout is again a value of +1 or -1.

[0066] The second negative feedback coefficient M is set to a negative value, which prevents the second integrator 34 from integrating upward or downward too fast, which may cause instability in the Σ-Δ loop. As described above, values in the range of 2*hysteresis to -0.25*hysteresis for M will generally be sufficient to meet this criterion. However, it is conceivable that depending on the application, values outside this range can be used.

[0067] The first integrator 32 and the second integrator 34 perform two integrations in series together. The output of the first integrator 32 is larger, and the feedback coefficient M of the input of the second integrator 34 can be increased according to the selected hysteresis of the comparator 35.

[0068] At least one additional control signal CTRL can be provided as an input to the loop filter 30 to modify the state and / or transfer function of the loop filter. The modification of the state can be at least one of the following: keeping the value constant, setting the value to the initial state, or overwriting the value with a new value. The modification of the transfer function H can include at least one of the following: changing the filter coefficients, disabling one or more elements of the loop filter, or bypassing one or more elements of the loop filter.

[0069] Four control signals CTRL1, CTRL2, CTRL3, and CTRL4 are provided in this example. The control signals are generated by a controller configured to modify the state and / or transfer function of the loop filter. For example, the control signal CTRL1 can be provided to the first coefficient multiplier 38 to change the negative feedback coefficient N to adjust the conversion gain of the SDPWM loop, the control signal CTRL2 can be provided to the reset integrator 32, the control signal CTRL3 can be provided to the integrator 34 to keep its value constant, and the control signal CTRL4 can be provided to the second coefficient multiplier 39 to change its negative feedback coefficient M to modify the noise shaping behavior of the SD PWM loop. One or more different types of control signals can be provided to each element of the loop filter 30 based on desired settings.

[0070] Figure 6A Including the input signal Sin (top) corresponding to the Σ-Δ PWM 400 and the Σ-Δ PWM output signal Sout (bottom). The PWM period and switching frequency of the output signal Sout change based on the value of the input signal Sin. When the input signal Sin is zero, the switching frequency is the highest (and the PWM period is the lowest), and when the input signal Sin is at its maximum or minimum amplitude, the switching frequency is the lowest (and the PWM period is the highest). This change in the PWM period is non-linear as the input signal increases or decreases.

[0071] Figure 6B Show Figure 6A The signal spectrum of the output signal Sout shown in. It can be seen from the signal spectrum that a high-frequency spectrum with a continuously decreasing maximum (peak) amplitude below the Σ-Δ PWM harmonics (i.e., harmonics below the carrier frequency of the Σ-Δ PWM 400) is generated. Additionally, the distortion spectrum is improved compared to the PWM spectrum and the first-order Σ-Δ modulator 300. For example, the spectrum clearly visualizes that the maximum value of the higher-frequency spectral density is limited to approximately 1 / 10 of the conventional PWM spectrum (i.e., the carrier frequency). Secondly, according to the noise transfer function, the noise spectral density in the lower-frequency range around the Σ-Δ PWM output signal Sout (i.e., around the carrier frequency) is also significantly reduced.

[0072] It should be understood that the transfer function (H) of the loop filter can be used to implement and describe loops of different orders and architectures in their general form, depending on its two inputs and the frequency variable of the spectral transformation (s for the Laplace transform in the case of a continuous-time loop filter, or z for the z-transform transfer function in the case of a discrete-time loop filter). Thus, Figure 7is a generalized schematic block diagram of a Σ-Δ PWM modulator 500, where block 30 represents the transfer function H of a loop filter that receives two inputs, namely an input signal Sin and a feedback signal FB. The transfer function H represents a loop filter of any order fed into a hysteresis comparator 35. The transfer function H may include at least one of the following: at least one integrator, at least one register (i.e., a signal delay unit), at least one coefficient multiplier, at least one inverter, at least one adder, or at least one subtractor. Signals inside the loop filter may be clamped (saturated) to values defined for a maximum state and a minimum state to avoid overflow.

[0073] The previously explained effect of increasing the time (PWM period) between different output states can be compensated by a forward control of the hysteresis level of the hysteresis comparator 35. That is, by using forward control, when the input signal Sin approaches or is at the zero crossing, the upper hysteresis threshold THup and the lower hysteresis threshold THlow can be adjusted so as to reduce the high switching frequency (i.e., low PWM period). According to the following embodiments, the forward control uses the input signal Sin to adjust the upper hysteresis threshold THup and the lower hysteresis threshold THlow.

[0074] Figure 8 is a schematic diagram of a Σ-Δ PWM 600 according to one or more embodiments. The Σ-Δ PWM 600 includes a loop filter block 30 that represents the transfer function H of a loop filter that receives two inputs, namely an input signal Sin and a feedback signal FB. The Σ-Δ PWM 600 also includes a hysteresis comparator 35 whose hysteresis thresholds THup and THlow are adjustable based on a control signal. The Σ-Δ PWM 600 also includes a threshold controller 40 that receives the input signal Sin and adjusts the hysteresis level of the hysteresis comparator 35 via a control signal based on the input signal Sin. When the hysteresis level increases, the magnitudes of the hysteresis thresholds THup and THlow increase equally but in opposite directions. Conversely, when the hysteresis level decreases, the magnitudes of the hysteresis thresholds Thup and Thlow decrease.

[0075] In this case, when the input signal Sin approaches or is zero, the hysteresis level can be set higher to reduce the number of transition edges of the output signal Sout. Conversely, for a higher input signal Sin, the hysteresis level can be proportionally decreased to avoid an overly long duration between edges. A scale factor or scaling factor of the hysteresis level can be used to adjust the ratio between the shortest and the longest times between edges. This scale factor can be adjustable and programmable at the threshold controller 40.

[0076] Specifically, when the input signal is close to or at zero, the hysteresis level can increase proportionally to the absolute value of the input signal Sin. Thus, the hysteresis level decreases as the amplitude of the input signal Sin increases, where the hysteresis level is minimum when the input signal Sin is at its maximum or minimum value, and the hysteresis level increases as the amplitude of the input signal Sin decreases, where the hysteresis level is at its maximum when the input signal Sin is at the zero crossing. As the hysteresis of the comparator 35 increases, the PWM period of the output signal Sout automatically increases (i.e., the switching frequency automatically decreases). Thus, the faster switching that occurs at or around zero can be reduced, and the difference between the minimum and maximum values of the PWM period can be controlled by a scaling factor implemented by the threshold controller 40. The forward control implemented by the threshold controller 40 also improves the spectrum of the Σ-Δ PWM output signal Sout.

[0077] At least one additional control signal CTRL can be provided as an input to the loop filter block 30 to modify the state and / or transfer function of the loop filter. The modification of the state can be at least one of the following: keeping the value constant, setting the value to the initial state, or overwriting the value with a new value. The modification of the transfer function H can include at least one of the following: changing the filter coefficients, disabling one or more elements of the loop filter, or bypassing one or more elements of the loop filter.

[0078] The control function of modifying the state of the loop filter via one or more control signals CTRL is signaled by a controller 50, which can be an external control loop and is intended to change the behavior of the SD PWM signal Sout to allow a specific function. For example, an interference-free window is used for external measurements, where the transients of the SD PWM will be suppressed. This will be achieved by the hold function as described above. In another example, a soft reset can be sent, which will reset all integrators in order to start over again as an exception handling function of the external control loop, or as a safety function that can be initiated after a soft error is detected by the safety monitor of the external control loop. In another example, the value of the last integrator (e.g., integrator 34) is overwritten with a value from the external controller 50 in order to force the SD PWM into a specific state (e.g., an immediately forced high output, or a low output under the SD PWM signal).

[0079] Additionally or alternatively, the control function for modifying the transfer function of the loop filter 30 via one or more control signals CTRL is signaled by the controller 50. Examples of the control function for modifying the transfer function of the loop filter include, but are not limited to: bypassing the second integrator 34 so as to change from a second-order SD PWM loop to a first-order SD PWM loop; changing the coefficient M of the coefficient multiplier 38 to modify the noise shaping behavior of the SD PWM loop; and / or changing the coefficient N of the coefficient multiplier 37 to modify the conversion gain of the SD PWM loop.

[0080] Figure 9A Including an input signal Sin (top) corresponding to the Σ-Δ PWM 600 and a Σ-Δ PWM output signal Sout (bottom). The PWM period and switching frequency of the output signal Sout change based on the value of the input signal Sin. The difference in the PWM period and switching frequency of the output signal Sout can be reduced or eliminated by the threshold controller 40.

[0081] In the case where the difference is reduced but not eliminated, the switching frequency is controlled or limited by the threshold controller 40, being highest (and the PWM period is lowest) when the input signal Sin is at zero, and lowest (and the PWM period is highest) when the input signal Sin is at its maximum or minimum amplitude. This variation in the PWM period is proportional to the input signal. However, here, the difference between the highest and lowest switching frequencies in the output signal Sout has been reduced by the dynamic adjustment made by the threshold controller 40.

[0082] In the case where the difference is eliminated, due to the dynamic adjustment by the threshold controller 40, the PWM period and switching frequency of the output signal Sout remain constant.

[0083] Figure 9B Shows Figure 9A The signal spectrum of the output signal Sout shown in. As can be seen from the signal spectrum, a continuous decreasing high-frequency spectrum with the maximum (peak) amplitude lower than the Σ-Δ PWM harmonics (i.e., harmonics below the carrier frequency of the Σ-Δ PWM 600) is generated. Additionally, due to the feedforward control, the distortion spectrum is improved compared to the PWM spectrum and the first-order Σ-Δ modulator 300 and second-order Σ-Δ modulator 400. For example, the spectrum clearly visualizes that the maximum value of the higher-frequency spectral density is less than Figure 4B And 6B The spectral density shown in.

[0084] Additional embodiments are provided below.

[0085] 1. A pulse width modulation (PWM) output stage, comprising:

[0086] A Σ-Δ loop, comprising:

[0087] A first summer, arranged at an input of a Σ-Δ loop, wherein the first summer is configured to receive an input signal and a first feedback signal, and to generate a first summing signal based on a sum of the input signal and the first feedback signal;

[0088] At least one integrator, configured to generate an integrated signal based on the first summing signal;

[0089] A hysteresis comparator, arranged at an output of the Σ-Δ loop, wherein the hysteresis comparator is configured to receive the integrated signal and to generate a Σ-Δ PWM signal based on comparing the integrated signal with a first hysteresis threshold and a second hysteresis threshold; and

[0090] An inverter, arranged on a first feedback path, the first feedback path being coupled between an output of the hysteresis comparator and the first summer, wherein the inverter is configured to receive the Σ-Δ PWM signal, and to generate the first feedback signal by inverting the Σ-Δ PWM signal.

[0091] 2. The PWM output stage of embodiment 1, wherein the Σ-Δ loop is digital such that the first summer, the at least one integrator, the hysteresis comparator, and the inverter are digital.

[0092] 3. The PWM output stage of embodiment 1, wherein the hysteresis comparator has a hysteresis level greater than a maximum amplitude of the input signal.

[0093] 5. The PWM output stage of embodiment 1, wherein the Σ-Δ PWM signal is a digital signal that switches between values of +1 and -1, and wherein a duty cycle of the Σ-Δ PWM signal depends on a value of the input signal.

[0094] 6. The PWM output stage of embodiment 1, wherein the Σ-Δ PWM signal has a variable PWM period, the variable PWM period having a minimum duration when the input signal is at zero and a maximum duration when the input signal is at a maximum amplitude or a minimum amplitude of the input signal.

[0095] 7. The PWM output stage of embodiment 1, wherein the Σ-Δ PWM signal has a variable switching frequency, the variable switching frequency having a maximum frequency when the input signal is at zero and a minimum frequency when the input signal is at a maximum amplitude or a minimum amplitude of the input signal.

[0096] 8. The PWM output stage of claim 1, wherein an absolute value of the first feedback signal is always equal to or greater than an absolute value of the input signal.

[0097] 9. The PWM output stage of claim 1, wherein at least one integrator integrates faster under a first condition where the input signal and the first feedback signal have the same sign, and integrates slower under a second condition where the input signal and the first feedback signal have opposite signs.

[0098] 10. The PWM output stage of embodiment 1, wherein:

[0099] The hysteresis comparator has a hysteresis level greater than the maximum amplitude of the input signal, and

[0100] The absolute value of the first feedback signal is always equal to or greater than the absolute value of the input signal.

[0101] 11. The PWM output stage of embodiment 1, wherein:

[0102] At least one integrator includes a first integrator and a second integrator serially coupled between a first summing element and the hysteresis comparator.

[0103] 12. The PWM output stage of embodiment 11, wherein the absolute value of the first feedback signal is always greater than the absolute value of the input signal.

[0104] 13. The PWM output stage of embodiment 11, wherein:

[0105] The Σ-Δ loop includes a second summing element serially arranged between the first integrator and the second integrator, and a multiplier arranged on a second feedback path, between the output of the hysteresis comparator and the second summing element,

[0106] The multiplier is configured to generate the second feedback signal by applying a negative coefficient to the Σ-Δ PWM signal.

[0107] 14. The PWM output stage of embodiment 13, wherein the negative coefficient has a value in the range of -1 to -10.

[0108] 15. The PWM output stage of embodiment 13, wherein:

[0109] The first integrator is configured to generate a first integral signal based on the first summing signal,

[0110] The second summing element is configured to receive the first integral signal and the second feedback signal, and generate a second summing signal based on the sum of the first integral signal and the second feedback signal,

[0111] The second integrator is configured to generate a second integral signal based on the second summing signal, and

[0112] The hysteresis comparator is configured to receive the second integral signal as the integral signal, and generate the Σ-Δ PWM signal based on comparing the second integral signal with a first hysteresis threshold and a second hysteresis threshold.

[0113] The PWM output stage of Example 1 further includes:

[0114] A controller, arranged on a forward control path coupled to the input of the Σ-Δ loop, wherein the controller is configured to receive an input signal and adjust a first hysteresis threshold and a second hysteresis threshold based on the value of the input signal.

[0115] 17. The PWM output stage of Example 16, wherein:

[0116] The controller is configured to set the absolute values of the first hysteresis threshold and the second hysteresis threshold to a maximum value in response to the value of the input signal being zero, and

[0117] The controller is configured to set the absolute values of the first hysteresis threshold and the second hysteresis threshold to a minimum value in response to the value of the input signal having a maximum amplitude or a minimum amplitude.

[0118] 18. The PWM output stage of Example 16, wherein the Σ-Δ PWM signal has a variable PWM period, the variable PWM period having a minimum duration when the input signal is at zero, and having a maximum duration when the input signal is at the maximum amplitude or the minimum amplitude of the input signal.

[0119] 19. The PWM output stage of Example 17, wherein the controller is configured to dynamically set the absolute values of the first hysteresis threshold and the second hysteresis threshold such that the Σ-Δ PWM signal has a constant PWM period.

[0120] 20. A pulse width modulation (PWM) output stage, comprising:

[0121] A Σ-Δ loop, comprising:

[0122] A subtractor, arranged at the input of the Σ-Δ loop, wherein the subtractor is configured to receive an input signal and a first feedback signal, and subtract the first feedback signal from the input signal to generate a subtracted signal based on the difference between the input signal and the feedback signal;

[0123] At least one integrator, configured to generate an integration signal based on the first subtracted signal;

[0124] A hysteresis comparator, arranged at the output of the Σ-Δ loop, wherein the hysteresis comparator is configured to receive the integration signal and generate a Σ-Δ PWM signal based on comparing the integration signal with a first hysteresis threshold and a second hysteresis threshold; and

[0125] A first feedback path, coupled between the output of the hysteresis comparator and the subtractor, wherein the subtractor is configured to receive the Σ-Δ PWM signal as the first feedback signal via the first feedback path.

[0126] 21. The PWM output stage of embodiment 20, wherein:

[0127] The hysteresis comparator has a hysteresis level greater than the maximum amplitude of the input signal, and

[0128] The absolute value of the first feedback signal is always equal to or greater than the absolute value of the input signal.

[0129] 22. The PWM output stage of embodiment 20, wherein:

[0130] At least one integrator includes a first integrator and a second integrator serially coupled between the subtractor and the hysteresis comparator.

[0131] 23. The PWM output stage of embodiment 22, wherein:

[0132] The Σ-Δ loop includes a summer arranged serially between the first integrator and the second integrator, and a multiplier arranged on the second feedback path, between the output of the hysteresis comparator and the summer,

[0133] The multiplier is configured to generate a second feedback signal by applying a negative coefficient to the Σ-Δ PWM signal.

[0134] 24. The PWM output stage of embodiment 23, wherein:

[0135] The first integrator is configured to generate a first integration signal based on the subtracted signal,

[0136] The summer is configured to receive the first integration signal and the second feedback signal, and generate a summation signal based on the sum of the first integration signal and the second feedback signal,

[0137] The second integrator is configured to generate a second integration signal based on the summation signal, and

[0138] The hysteresis comparator is configured to receive the second integration signal as the integration signal, and generate the Σ-Δ PWM signal based on comparing the second integration signal with a first hysteresis threshold and a second hysteresis threshold.

[0139] 25. The PWM output stage of embodiment 20, further comprising:

[0140] A controller arranged on a forward control path coupled to the input of the Σ-Δ loop, wherein the controller is configured to receive the input signal and adjust the first hysteresis threshold and the second hysteresis threshold based on the value of the input signal.

[0141] 26. A pulse width modulation (PWM) output stage, comprising:

[0142] A Σ-Δ loop, comprising:

[0143] A loop filter configured to receive an input signal and a feedback signal derived from an output signal, and to generate a loop filter output signal based on a difference between the input signal and the feedback signal;

[0144] A hysteresis comparator arranged at an output of a Σ-Δ loop, wherein the hysteresis comparator is configured to receive the loop filter output signal and to generate a Σ-Δ PWM signal based on comparing the loop filter output signal with a first hysteresis threshold and a second hysteresis threshold; and

[0145] A feedback path coupled between an output of the hysteresis comparator and the loop filter, wherein the loop filter is configured to receive the Σ-Δ PWM signal as the feedback signal via the feedback path.

[0146] 27. The PWM output stage of embodiment 26, wherein:

[0147] The hysteresis comparator has a hysteresis level greater than a maximum amplitude of the input signal, and

[0148] An absolute value of the feedback signal is always equal to or greater than an absolute value of the input signal.

[0149] 28. The PWM output stage of embodiment 26, further comprising:

[0150] A controller arranged on a forward control path coupled to an input of the Σ-Δ loop, wherein the controller is configured to receive the input signal and to adjust the first hysteresis threshold and the second hysteresis threshold based on a value of the input signal.

[0151] Although various embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention that will achieve some of the advantages of the concepts disclosed herein. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the invention. It should be noted that features explained with reference to a particular drawing can be combined with features of other drawings, even for those features not explicitly mentioned. Such modifications to the overall inventive concept are intended to be covered by the appended claims and their legal equivalents.

[0152] In addition, the appended claims are hereby incorporated into the detailed description, where each claim can stand on its own as a separate exemplary embodiment. While each claim can stand on its own as a separate exemplary embodiment, it should be noted that although a dependent claim can recite a specific combination with one or more other claims in the claims, other exemplary embodiments can also include combinations of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are presented herein unless the statement is not intended to be a specific combination. In addition, the features of a claim that are intended to also include any other independent claim, even if that claim does not directly depend on an independent claim.

[0153] It should also be noted that the methods disclosed in the specification or claims can be implemented by a device having means for performing each of the corresponding acts of these methods. For example, the techniques described in this disclosure can be implemented at least in part in hardware, software, firmware, or any combination thereof, including any combination of a computing system, an integrated circuit, and a computer program on a non-transitory computer-readable recording medium. By way of example, various aspects of the described techniques can be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic circuitry, and any combination of such components.

[0154] Furthermore, it should be understood that the disclosure of multiple acts or functions in the specification or claims may not be construed as being in a particular order. Thus, the disclosure of multiple acts or functions does not limit these acts or functions to a particular order unless these acts or functions are not interchangeable for technical reasons. In addition, in some embodiments, a single act may include or may be decomposed into multiple sub-acts. Such sub-acts may be included in the disclosure of that single act and as part of the disclosure of that single act unless explicitly excluded.

Claims

1. A Σ-Δ pulse width modulation loop, comprising: A loop filter that implements a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal, and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; And A hysteresis comparator coupled to the output of the loop filter, the hysteresis comparator being configured to receive the loop filter signal and generate a Σ-Δ pulse width modulation signal based on the loop filter signal, wherein the first feedback signal is derived from the Σ-Δ pulse width modulation signal, and wherein the loop filter comprises: A combiner circuit configured to receive the input signal and the Σ-Δ pulse width modulation signal and generate a combined signal, the combined signal having a combined value that is always equal to subtracting the Σ-Δ pulse width modulation signal from the input signal; and An integrator configured to receive the combined signal and generate the loop filter signal based on the integration of the combined signal, wherein the hysteresis comparator is configured to receive the loop filter signal and generate the Σ-Δ pulse width modulation signal based on comparing the loop filter signal with a first hysteresis threshold and a second hysteresis threshold, wherein the first hysteresis threshold is greater than the maximum amplitude of the input signal.

2. The Σ-Δ pulse width modulation loop according to claim 1, wherein the loop filter comprises at least one of the following: At least one integrator; At least one register; At least one coefficient multiplier; At least one inverter; At least one adder, or At least one subtractor.

3. The Σ-Δ pulse width modulation loop according to claim 1, wherein the loop filter and the hysteresis comparator are digital.

4. The Σ-Δ pulse width modulation loop according to claim 1, wherein: The loop filter includes an input and a summer disposed at the input, the summer being configured to receive the input signal and the first feedback signal and generate the combined signal based on the sum of the input signal and the first feedback signal, wherein the first feedback signal is the inversion of the Σ-Δ pulse width modulation signal.

5. The Σ-Δ pulse width modulation loop according to claim 1, wherein: The loop filter includes an input and a subtractor disposed at the input, the subtractor being configured to receive the input signal and the first feedback signal and generate the combined signal based on subtracting the first feedback signal from the input signal, wherein the first feedback signal is the Σ-Δ pulse width modulation signal.

6. The Σ-Δ pulse width modulation loop according to claim 1, wherein: The signals inside the loop filter are clamped to values defined for the maximum state and the minimum state to avoid overflow.

7. The Σ-Δ pulse width modulation loop according to claim 1, wherein the hysteresis comparator has a hysteresis level equal to or greater than the maximum amplitude of the input signal.

8. The Σ-Δ pulse width modulation loop according to claim 1, wherein the absolute value of the first feedback signal is always equal to or greater than the absolute value of the input signal.

9. The Σ-Δ pulse width modulation loop according to claim 1, wherein: the hysteresis comparator has a hysteresis level greater than the maximum amplitude of the input signal, and the absolute value of the first feedback signal is always equal to or greater than the absolute value of the input signal.

10. The Σ-Δ pulse width modulation loop according to claim 1, further comprising: a controller arranged on the forward control path, wherein the controller is configured to receive the input signal and adjust the first hysteresis threshold and the second hysteresis threshold of the hysteresis comparator based on the value of the input signal, such that the first hysteresis threshold and the second hysteresis threshold are dynamically adjusted when the input signal is received by the loop filter.

11. The Σ-Δ pulse width modulation loop according to claim 10, wherein: the controller is configured to increase the absolute values of the first hysteresis threshold and the second hysteresis threshold in response to a decrease in the absolute value of the input signal, and the controller is configured to decrease the absolute values of the first hysteresis threshold and the second hysteresis threshold in response to an increase in the absolute value of the input signal.

12. The Σ-Δ pulse width modulation loop according to claim 11, wherein: the Σ-Δ pulse width modulation signal has a variable pulse width modulation period, the variable pulse width modulation period having a minimum duration when the input signal is zero and a maximum duration when the input signal is at the maximum amplitude or the minimum amplitude of the input signal, and the controller is configured to dynamically set the absolute values of the first hysteresis threshold and the second hysteresis threshold such that the difference between the minimum duration and the maximum duration of the variable pulse width modulation period is reduced.

13. The Σ-Δ pulse width modulation loop according to claim 10, wherein: the controller is configured to set the absolute values of the first hysteresis threshold and the second hysteresis threshold to a maximum value in response to the value of the input signal being zero, and the controller is configured to set the absolute values of the first hysteresis threshold and the second hysteresis threshold to a minimum value in response to the value of the input signal having the maximum amplitude or the minimum amplitude.

14. The Σ-Δ pulse width modulation loop according to claim 1, wherein the Σ-Δ pulse width modulation signal has a variable pulse width modulation period, the variable pulse width modulation period having a minimum duration when the input signal is zero and a maximum duration when the input signal is at the maximum amplitude or the minimum amplitude of the input signal.

15. The Σ-Δ pulse width modulation loop according to claim 1, wherein: the loop filter includes at least one control input configured to receive a control signal, wherein at least one of the control signals is configured to modify the state of the loop filter.

16. The Σ-Δ pulse width modulation loop according to claim 15, wherein: The state of the loop filter includes at least one of the following states: keeping the value constant, resetting the value to the initial state, or rewriting the value with a new value.

17. The Σ-Δ pulse width modulation loop according to claim 1, wherein: The loop filter includes at least one control input configured to receive a control signal, wherein at least one of the control signals is configured to modify the linear transfer function of the loop filter.

18. The Σ-Δ pulse width modulation loop according to claim 17, wherein: At least one of the control signals is configured to modify the linear transfer function by changing filter coefficients of the loop filter, disabling elements of the loop filter, or bypassing elements of the loop filter.

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