Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a semiconductor substrate, the semiconductor substrate comprises a plurality of chip regions and a cutting path for separating the chip regions; a test structure is formed in the cutting path, the test structure comprises an active region and a connection structure, the active region is formed in the semiconductor substrate, the connection structure is located at the end of the active region, and the plurality of active regions located in the same column are sequentially connected end to end through the connection structure; the test structure is used for bit line contact resistance testing. In this embodiment, the semiconductor device is provided with a test structure for testing the bit line contact resistance in the cutting path, and the plurality of active regions located in the same column are sequentially connected end to end through the connection structure located at the end of the active region, thereby obtaining the sum of the plurality of bit line contact resistances located in the same column and the resistance value of the active region, thereby solving the problem of inaccurate measurement caused by abnormal shallow trench isolation structure, improving the test accuracy, and thereby improving the product quality.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory devices, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As semiconductor devices shrink in size, the 17nm Dynamic Random Access Memory (DRAM) process is equivalent to the 19nm DRAM. The sizes of transistors in the memory cell array area and the peripheral circuit area are getting smaller and smaller, and the process complexity is getting higher and higher. In order to monitor the manufacturing process of semiconductor devices to ensure the reliability of semiconductor devices, it is usually practiced to form a test structure (testkey) in the semiconductor device for testing and simulating some key parameters of the semiconductor device to ensure the quality of the semiconductor device before leaving the factory.

[0003] The test of key parameters of semiconductor devices includes the test of resistance of semiconductor devices, etc. For example, by performing a bit line contact resistance test, it can be tested whether the contact between the bit line contact plug and the substrate is good. However, since there is a shallow trench isolation structure between the active areas during the current bit line contact resistance test structure test, when the shallow trench isolation structure in the substrate in the middle of the active area is abnormal, it will also cause the BLC resistance to be abnormally high, so it is impossible to accurately reflect the contact between the bit line plug and the substrate. Summary of the invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, so as to solve the problem that the test structure in the current semiconductor device cannot accurately reflect the contact situation.

[0005] An embodiment of the present invention provides a semiconductor device, including:

[0006] A semiconductor substrate, comprising a plurality of chip regions and dicing lanes for separating the chip regions;

[0007] Wherein, a test structure is formed in the cutting path, and the test structure includes:

[0008] an active region formed in a semiconductor substrate; and

[0009] The connection structure is located at the end of the active area, and the multiple active areas located in the same column are connected end to end in sequence through the connection structure.

[0010] The test structure is used for bit line contact resistance test.

[0011] In one embodiment, the connection structure includes:

[0012] A first connecting plug is located at the head of the active area;

[0013] a second connecting plug located at a tail portion of the active region; and

[0014] The metal layer is located above the first connecting plug and the second connecting plug, and connects the first connecting plug with the second connecting plug.

[0015] In one embodiment, the connection structure further includes a metal barrier layer, wherein the metal barrier layer is located between the first connection plug and the metal layer and between the second connection plug and the metal layer.

[0016] In one embodiment, the plurality of active regions and the plurality of connection structures located in the same column together form a “Z”-shaped test structure.

[0017] In one embodiment, every two adjacent active regions are connected in a direction along which the active regions extend.

[0018] In one embodiment, the test structure is one of a plurality of test structures within the scribe line.

[0019] In one embodiment, the chip area is a semiconductor memory chip.

[0020] Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, comprising:

[0021] providing a semiconductor substrate;

[0022] Forming a plurality of chip regions and cutting paths on the semiconductor substrate; wherein the cutting paths have a plurality of active regions formed synchronously with the chip regions;

[0023] A plurality of connection structures are formed, wherein the connection structures are located at the ends of the active regions, and the plurality of active regions located in the same column are sequentially connected end to end through the connection structures.

[0024] In one embodiment, the step of forming the connection structure comprises:

[0025] forming an insulating layer above the active area;

[0026] forming a first connecting plug and a second connecting plug penetrating the insulating layer, wherein the first connecting plug is located at the head of the active region, and the second connecting plug is located at the tail of the active region;

[0027] A metal layer is formed, the metal layer covers the first connecting plug and the second connecting plug, and the first connecting plug is connected to the second connecting plug through the metal layer.

[0028] In one embodiment, the plurality of active regions and the plurality of connection structures located in the same column together form a “Z”-shaped test structure.

[0029] In summary, an embodiment of the present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device includes a semiconductor substrate, the semiconductor substrate includes multiple chip areas and a cutting path for separating the chip areas; wherein a test structure is formed in the cutting path, the test structure includes an active area and a connection structure, the active area is formed in the semiconductor substrate, the connection structure is located at the end of the active area, and the multiple active areas located in the same column are connected end to end in sequence through the connection structure. In this embodiment, the semiconductor device is provided with a test structure for testing the bit line contact resistance in the cutting path, and the multiple active areas located in the same column are connected end to end in sequence through the connection structure located at the end of the active area, thereby obtaining the sum of the multiple bit line contact resistances located in the same column and the resistance of the active area, and by subtracting the test result of the active area resistance obtained by other test methods, the sum of the resistance of the bit line contact hole can be accurately obtained, thereby solving the problem of inaccurate measurement caused by abnormal shallow trench isolation structure, improving the test accuracy, and thus improving the product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A top view of a semiconductor device including a chip area and a dicing road;

[0031] Figure 2 A top view of a semiconductor device provided by an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of the arrangement of an active region of an exemplary semiconductor device;

[0033] Figure 4 For along Figure 2 A cross-sectional view of the semiconductor device at the middle dotted line L2;

[0034] Figure 5 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0035] Description of Figure Numbers:

[0036] Chip region-10, cutting road-20, test structure-200, active area-210, connection structure-220, first connection plug-221, second connection plug-222, metal layer-223, metal barrier layer 224, insulation layer-230, filling layer-240, shallow trench isolation structure 250, semiconductor substrate-30. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0040] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] The present invention provides a semiconductor device including a semiconductor substrate. Figure 1 and Figure 2 The semiconductor substrate 30 includes a plurality of chip regions 10 and a cutting road 20 for separating the chip regions 10; wherein a test structure 200 is formed in the cutting road, and the test structure 200 includes an active area 210 and a connection structure 220, wherein the active area 210 is formed in the semiconductor substrate 30, and the connection structure 220 is located at the end of the active area 210, and the plurality of active areas 210 located in the same column are sequentially connected end to end through the connection structure 220, and the test structure 200 is used for bit line contact resistance testing.

[0042] It can be understood that the test structure 200 of the semiconductor device is usually manufactured in the same process as the semiconductor device in the wafer, and the test structure 200 of the semiconductor device has a mutual correspondence with the semiconductor device: each layer of interconnection lines in the semiconductor device corresponds to the test line located at the same layer in the test structure 200 of the semiconductor device, and each bit line contact plug in the semiconductor device corresponds to a connection plug located at the same layer in the test structure 200 of the semiconductor device. Therefore, in this embodiment, when forming the bit line contact plug and the bit line connection line, the test structure 200 is formed synchronously in the cutting road 20, and the test structure 200 includes an active area 210 and a connection structure 220, the active area 210 is formed in the semiconductor substrate 30, and the connection structure 220 is located at the end of the active area 210, and the multiple active areas 210 located in the same column are sequentially connected end to end through the connection structure 220.

[0043] In this embodiment, the multiple active regions 210 located in the same column are connected end to end in sequence through the connection structure 220 located at the end of the active region 210. Figure 2As shown by the black dotted line in the figure, the bit line contact hole is connected in series with the active area, and finally the test obtains the sum of the resistance values ​​of the multiple bit line contact resistances located in the same column and the active area. By subtracting the test results of the active area resistance obtained by other test methods, the sum of the resistance values ​​of the bit line contact holes can be accurately obtained. Other test methods include connecting the active areas in series and testing to obtain the sum of the resistances of the active areas, which will not be repeated here. Therefore, the technical solution effectively solves the problem of inaccurate bit line contact resistance measurement caused by abnormal shallow trench isolation structure, thereby improving the test accuracy and further improving product quality.

[0044] In one embodiment, the connection structure 220 includes a first connection plug 221, a second connection plug 222 and a metal layer 223. The first connection plug 221 is located at the head of the active area 210; the second connection plug 222 is located at the tail of the active area 210; the metal layer 223 is located above the first connection plug 221 and the second connection plug 222 to connect the first connection plug 221 with the second connection plug 222.

[0045] It can be understood that the substrate includes a base and a shallow trench structure (not shown) formed in the base, and a plurality of active regions 210 arranged in parallel and staggered are defined by the shallow trench structure, and the shallow trench structure is filled with insulating material to form a shallow trench isolation structure 250, such as Figure 3 As shown. The substrate also includes a word line structure (not shown) and a bit line structure (not shown), wherein the word line structure is a buried word line structure, and the extension method of the buried word line structure intersects with the extension direction of the bit line structure. The bit line structure includes a bit line contact plug, a bit line and an insulating layer stacked from bottom to top, and the bottom of the bit line contact plug is on the substrate and directly in contact with the substrate; and after the bit line structure is formed, multiple bit lines are connected through a bit line connection structure 220.

[0046] In order to facilitate the testing of the bit line contact resistance, the test structure 200 is formed in the cutting path 20 while the bit line structure and the bit line connection structure 220 are formed. Figure 4As shown. The test structure 200 includes an active area 210 and a connection structure 220. The first connection plug 221 is located at the head of the active area 210; the second connection plug 222 is located at the tail of the active area 210. The first connection plug 221 and the second connection plug 222 have the same structure and both include a non-metallic conductive layer. In this embodiment, the metal layer 223 can be formed by stacking any one of titanium nitride, titanium, copper, tungsten silicide, tungsten nitride or any combination thereof and tungsten; the non-metallic conductive layer is formed by polysilicon, semiconductor conductive materials, etc. In this embodiment, a plurality of active areas 210 are arranged in an interlaced manner, and the extension direction of the active areas 210 has a certain angle with the row direction and is aligned in the column direction. For the plurality of active areas 210 located in the same column, each of the head and the tail closest thereto are connected to the metal layer 223 through the first contact plug or the second contact plug, and the metal layer 223 is the test line of the test structure of the bit line contact resistance.

[0047] Typically, the first connection plug 221 and the second connection plug 222 are formed of polysilicon, and the metal layer 223 is formed of metal tungsten. In one embodiment, in order to prevent metal atoms from diffusing into the polysilicon material layer, the connection structure further includes a metal barrier layer 224, and the metal barrier layer 224 is located between the first connection plug and the metal layer and between the second connection plug and the metal layer. In this embodiment, titanium nitride is used to form the metal barrier layer, and the metal barrier layer 224 prevents metal atoms from diffusing into the polysilicon layer.

[0048] In one embodiment, the plurality of active regions 210 and the plurality of connection structures 220 located in the same row together form a “Z”-shaped test structure 200 .

[0049] Please continue to see Figure 2 In this embodiment, the angle between the extension direction of the active area 210 and the row direction is within the range of 60° to 80°, so that multiple active areas 210 can be aligned in the column direction without affecting the number and size of the active area 210, and the distance between the head and the tail of two adjacent active areas 210 in the column direction is the shortest, and the corresponding connection structure 220 is also arranged along the y direction, thereby simplifying the manufacturing process. In this embodiment, the contact resistors located on the same column are connected in series through the test structure 200, thereby solving the problem of reduced test accuracy caused by abnormal shallow trench isolation structure.

[0050] In one embodiment,

[0051] Every two adjacent active regions are connected in a direction along which the active regions extend.

[0052] It can be understood that generally, a large-sized active area (mainly referring to the length of the active area) is first formed in the semiconductor substrate in parallel and staggered arrangement, and then the large-sized active area is divided using two layers of cutting mask plates to form a plurality of small-sized active areas at intervals. However, only one layer of cutting mask plates can be used in the cutting path, so the small-sized active areas to be formed cannot be completely separated, so every two adjacent active areas are connected in the direction along which the active areas extend.

[0053] In one embodiment, the test structure 200 is one of the multiple test structures 200 in the cutting path 20. It can be understood that the test structure 200 of the semiconductor device and the semiconductor device in the wafer are manufactured in the same process, and the test structure 200 of the semiconductor device has a mutual correspondence with the semiconductor device, so each layer of interconnection lines in the semiconductor device will correspond to a test structure 200. The test of the key parameters of the semiconductor device includes the test of the resistance of the semiconductor device, the test of the thickness of the dielectric layer, and the test of the relative position between semiconductor devices. Therefore, there are multiple test structures 200 in the cutting path 20, and the test structure 200 including the active area 210 and the connection structure 220 is only one of the multiple test structures 200 in the cutting path 20.

[0054] In one embodiment, the chip area 10 is a semiconductor memory chip. In this embodiment, the chip area 10 is a semiconductor memory chip, the semiconductor device is a semiconductor memory, and the test structure 200 is used to test the bit line contact resistance in the semiconductor memory, and then detect the quality of the semiconductor memory according to the measured bit line contact circuit. Since the multiple active areas 210 located on the same column are connected end to end in sequence through the test structure 200 in this embodiment, the sum of the resistance values ​​of the multiple bit line contact resistances and the active area is obtained. By subtracting the test results of the active area resistance obtained by other test methods, the sum of the resistance values ​​of the bit line contact holes can be accurately obtained, thereby avoiding the problem of reduced test accuracy caused by abnormal shallow trench isolation structure, improving test accuracy, and improving device quality.

[0055] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device. Figure 5 , the method for manufacturing the semiconductor device comprises:

[0056] Step S410, providing a semiconductor substrate 30;

[0057] Step S420, forming a plurality of chip regions 10 and cutting paths on the semiconductor substrate 30; wherein the cutting paths have a plurality of active regions 210 formed synchronously with the chip regions 10;

[0058] Step S430 , forming a plurality of connection structures 220 , wherein the connection structures 220 are located at the ends of the active regions 210 , and the plurality of active regions 210 located in the same column are sequentially connected end to end through the connection structures 220 .

[0059] Since the test structure 200 of the semiconductor device is usually manufactured in the same process as the semiconductor device in the wafer, and the test structure 200 of the semiconductor device has a mutual correspondence with the semiconductor device: each layer of interconnection lines in the semiconductor device corresponds to the test line located at the same layer in the test structure 200 of the semiconductor device (i.e., the metal layer 223 in the above semiconductor structure), and each bit line contact plug in the semiconductor device corresponds to a connection plug located at the same layer in the test structure 200 of the semiconductor device (i.e., the first connection plug or the second connection plug in the above semiconductor structure). Therefore, in this embodiment, when forming the bit line contact plug and the bit line connection line, the test structure 200 is formed synchronously in the cutting road 20, and the test structure 200 includes an active area 210 and a connection structure 220, wherein the active area 210 is formed in the semiconductor substrate 30, and the connection structure 220 is located at the end of the active area 210, and the multiple active areas 210 located in the same column are sequentially connected end to end through the connection structure 220.

[0060] In this embodiment, a plurality of active areas 210 located in the same column are connected end to end in sequence through a connection structure 220 located at the end of the active area 210, thereby obtaining the sum of the resistance values ​​of the plurality of bit line contact resistances located in the same column and the active area. By performing a subtraction operation with the active area resistance test result obtained by adopting other test methods, the sum of the resistance values ​​of the bit line contact holes can be accurately obtained, thereby effectively solving the problem of inaccurate bit line contact resistance measurement caused by abnormal shallow trench isolation structure, thereby improving test accuracy and further improving product quality.

[0061] In one embodiment, the steps of forming the connection structure 220 include:

[0062] forming an insulating layer 230 above the active area;

[0063] forming a first connecting plug 221 and a second connecting plug 222 penetrating the insulating layer 230 , wherein the first connecting plug 221 is located at the head of the active region 210 , and the second connecting plug 222 is located at the tail of the active region 210 ;

[0064] A metal layer 223 is formed, and the metal layer 223 covers the first connecting plug 221 and the second connecting plug 222 . The first connecting plug 221 and the second connecting plug 222 are connected through the metal layer 223 .

[0065] The semiconductor device described in this embodiment is a semiconductor memory. The substrate includes a base and a shallow trench structure (not shown) formed in the base, and a plurality of active areas 210 arranged in parallel and staggered are defined by the shallow trench structure, and the shallow trench structure is filled with insulating material to form a shallow trench isolation structure. In one embodiment, every two adjacent active areas are connected in the direction along which the active area extends. It can be understood that generally, a parallel and staggered active area with a larger specification (mainly referring to the length of the active area) is formed in the semiconductor substrate first, and then the active area with a larger specification is divided using two layers of cutting mask plates to form a plurality of spaced small-sized active areas. However, in the cutting path, only one layer of cutting mask plate can be used, and the small-sized active area to be formed cannot be completely separated, so every two adjacent active areas are connected in the direction along which the active area extends.

[0066] The substrate further includes a word line structure (not shown) and a bit line structure (not shown), wherein the word line structure is a buried word line structure, and the extension method of the buried word line structure intersects with the extension direction of the bit line structure. The bit line structure includes a bit line contact plug, a bit line and an insulating layer 230 stacked from bottom to top, and the bottom of the bit line contact plug is on the substrate and directly in contact with the substrate; and after the bit line structure is formed, multiple bit lines are connected through a bit line connection structure 220. The test structure 200 is formed synchronously with the bit line structure and the bit line connection structure 220, and the specific formation process includes:

[0067] Step 1: deposit insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride by a deposition process to form an insulating layer 230 covering the surface of the substrate (including the active area 210 and the shallow trench isolation structure 250). The deposition process may include chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), and plasma enhanced ALD (PEALD).

[0068] Step 2: When forming the bit line contact hole, a through hole for forming the first connecting plug 221 and the second connecting plug 222 is simultaneously formed in the cutting street 20 by an etching process, and the through hole exposes the active area 210 .

[0069] Then, polysilicon material is sequentially deposited by a deposition process to form a polysilicon material layer, wherein the polysilicon material layer covers the insulating layer 230 and fills the through hole.

[0070] Step three, the polysilicon material layer is etched to remove the polysilicon material layer located in the insulating layer 230, and the remaining polysilicon material layer forms a first connecting plug and a second connecting plug in the cutting road 20. In this embodiment, the non-first connecting plug and the second connecting plug are both located in the through hole and fill the through hole.

[0071] Step 4: forming a bit line connection structure in the chip region 10 through a PC (Periphery Contact) process, connecting the metal layers in the bit line structure together through the bit line connection structure; and simultaneously forming a metal layer 223 connecting the first connection plug and the second connection plug. Step 4 specifically includes:

[0072] First, after forming the bit line structure, a bit line isolation structure covering the side of the bit line structure is first formed by a deposition and etching process; this step specifically includes: first, an isolation material layer covering the surface of the bit line structure and the surface of the substrate is formed by depositing an insulating material. In this embodiment, silicon nitride is used to make the isolation material layer. Then, the isolation material layer is etched by an etching process to remove the isolation material layer located on the top of the bit line structure and the surface of the substrate, and the isolation material layer located on the side wall of the bit line structure is retained as the bit line isolation structure (not shown).

[0073] Next, after forming the bit line isolation structure, a deposition process and an etching / chemical mechanical polishing process are used to form a filling layer 240. In this embodiment, the filling layer 240 is formed by depositing a silicon nitride material.

[0074] Then, the metal layer 223 is formed by a PC process to connect the first connecting plug 221 and the second connecting plug 222, and the first connecting plug 221 and the second connecting plug 222 are connected through the metal layer 223. In some other embodiments, before forming the metal layer, a step of forming a metal barrier layer is also included, and the metal barrier layer is located between the first connecting plug and the metal layer and between the second connecting plug and the metal layer. In this embodiment, titanium nitride is used to form the metal barrier layer, and the metal barrier layer 224 blocks metal atoms from diffusing into the polysilicon layer.

[0075] In one embodiment, the multiple active areas 210 and the multiple connection structures 220 located in the same column together constitute a "Z"-shaped test structure 200. In this embodiment, the angle between the extension direction of the active area 210 and the row direction is within the range of 60° to 80°, so that the multiple active areas 210 can be aligned in the column direction without affecting the number and size of the active area 210, and the distance between the head and the tail of the two adjacent active areas 210 in the column direction is the shortest, and the corresponding connection structure 220 is also arranged along the y direction, thereby simplifying the manufacturing process. In this embodiment, the contact resistance and the active area located in the same column are connected in series through the test structure 200, and then the sum of the resistance values ​​of the multiple bit line contact resistances and the active area located in the same column is obtained by testing. By subtracting the test results of the active area resistance obtained by other test methods, the sum of the resistance values ​​of the bit line contact holes can be accurately obtained, thereby solving the problem of decreased accuracy of the bit line contact resistance test caused by the abnormality of the shallow trench isolation structure.

[0076] In summary, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device includes a semiconductor substrate 30, the semiconductor substrate 30 includes a plurality of chip regions 10 and a cutting path 20 for separating the chip regions 10; wherein a test structure 200 is formed in the cutting path, the test structure 200 includes an active area 210 and a connection structure 220, the active area 210 is formed in the semiconductor substrate 30, the connection structure 220 is located at the end of the active area 210, and the plurality of active areas 210 located in the same column are connected end to end in sequence through the connection structure 220. In the present embodiment, the semiconductor device is provided with a test structure 200 for testing the bit line contact resistance in the cutting path 20, and the multiple active areas 210 located in the same column are connected end to end in sequence through the connection structure 220 located at the end of the active area 210, that is, the bit line contact hole and the active area are connected in series, and then the sum of the multiple bit line contact resistances located in the same column is obtained, and the sum of the resistance values ​​of the bit line contact holes can be accurately obtained by subtracting the test results of the active area resistance obtained by adopting other test methods, and the sum of the resistance values ​​of the bit line contact holes can be accurately obtained, which solves the problem of inaccurate bit line contact resistance measurement caused by abnormal shallow trench isolation structure, improves test accuracy, and thus improves product quality.

[0077] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, comprising a plurality of chip regions and dicing lanes for separating the chip regions; Wherein, a test structure is formed in the cutting path, and the test structure includes: An active region is formed in a semiconductor substrate, wherein a plurality of the active regions are arranged in parallel and staggered, and an angle between an extension direction of the active region and a row direction is in a range of 60° to 80°; and A connection structure is located at the end of the active area, and multiple active areas located in the same column are connected end to end in sequence through the connection structure; multiple active areas located in the same column and multiple connection structures together constitute a "Z"-shaped test structure, and the test structure is used for bit line contact resistance testing.

2. The semiconductor device according to claim 1, wherein The connection structure comprises: a first connecting plug located at the head of the active region; a second connecting plug located at the tail of the active region; and The metal layer is located above the first connecting plug and the second connecting plug, and connects the first connecting plug with the second connecting plug.

3. The semiconductor device according to claim 2, wherein: The connection structure further includes a metal barrier layer located between the first connection plug and the metal layer and between the second connection plug and the metal layer.

4. The semiconductor device according to claim 1, wherein Every two adjacent active regions are connected in a direction along which the active regions extend.

5. The semiconductor device according to claim 1, wherein: The test structure is one of a plurality of the test structures within the scribe line.

6. The semiconductor device according to claim 1, wherein: The chip area is a semiconductor storage chip.

7. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; A plurality of chip regions and cutting paths are formed on the semiconductor substrate; wherein the cutting paths have a plurality of active regions formed synchronously with the chip regions, the plurality of active regions are arranged in parallel and staggered, and the angle between the extension direction of the active regions and the row direction is in the range of 60° to 80°; A plurality of connection structures are formed, wherein the connection structures are located at the ends of the active regions, and the plurality of active regions located in the same column are sequentially connected end to end through the connection structures, and the plurality of active regions located in the same column and the plurality of connection structures together constitute a "Z"-shaped test structure.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The steps of forming the connection structure include: forming an insulating layer above the active area; forming a first connecting plug and a second connecting plug penetrating the insulating layer, wherein the first connecting plug is located at the head of the active region, and the second connecting plug is located at the tail of the active region; A metal layer is formed, the metal layer covers the first connecting plug and the second connecting plug, and the first connecting plug is connected to the second connecting plug through the metal layer.

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