Monolithic integrated VCSEL chip

Abstract

The present application relates to a monolithic integrated VCSEL chip, which includes a first VCSEL sub-chip, and the first VCSEL chip includes a plurality of first VCSEL units arranged in a first array; and a second VCSEL sub-chip monolithically integrated with the first VCSEL sub-chip, and the second VCSEL sub-chip includes a plurality of second VCSEL units arranged in a second array; wherein, the first VCSEL sub-chip and the second VCSEL sub-chip share an N-DBR structure in terms of structure. In this way, the monolithic integrated VCSEL chip realizes the monolithic integration of multiple VCSEL chips at the wafer level, so that it can combine the respective advantages of different VCSEL chips and has a relatively small overall size.

Description

Technical Field

[0001] This application relates to the field of VCSELs, and particularly to a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip integrates two or more VCSEL sub-chips at the wafer level. Background Art

[0002] With the development of VCSEL (Vertical-Cavity Surface-Emitting Laser) technology, VCSEL chips adapted to different application scenarios have gradually emerged in the market. For example, TOF (Time of Flight) VCSEL chips, structured light VCSEL chips, etc.

[0003] Different types of VCSEL chips have different performance characteristics. Structured light VCSEL chips have the advantages of high light transmittance and low energy consumption, but they are easily affected by the environment and are only suitable for short-distance application scenarios; TOF VCSEL chips have the advantages of being less affected by the environment, etc., but their measurement accuracy is poor and the power consumption is high.

[0004] Integrated application of different types of VCSEL chips in terminal devices is the current development trend. For example, placing different models of VCSEL chips on different sides of a smart phone to serve as the front VCSEL chip of the front camera module and the rear VCSEL chip of the rear camera module to achieve different functional configurations.

[0005] Therefore, how to integrally configure two or more VCSEL chips has become a very important technical problem. Summary of the Invention

[0006] One advantage of this application is to provide a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip can integrate two or more VCSEL sub-chips on the same monolithic at the wafer level.

[0007] Another advantage of this application is to provide a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip can integrate at least two VCSEL chips of different types, so that the monolithic integrated VCSEL chip simultaneously has the characteristics of different types of VCSEL chips.

[0008] Another advantage of this application is to provide a monolithic integrated VCSEL chip, which, generally speaking, has a relatively small thickness dimension.

[0009] Another advantage of the present application is to provide a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip can selectively activate different types of chips to work based on the requirements of different application scenarios, so as to expand the application scenario compatibility of the monolithic integrated VCSEL chip.

[0010] Another advantage of the present application is to provide a monolithic integrated VCSEL chip, wherein at least two VCSEL sub-chips are monolithically integrated at the wafer level by means of a common N-DBR layer.

[0011] To achieve at least one of the above technical advantages, a monolithic integrated VCSEL chip is provided, including:

[0012] A first VCSEL sub-chip, the first VCSEL chip including a plurality of first VCSEL units arranged in a first array; and

[0013] A second VCSEL sub-chip monolithically integrated with the first VCSEL sub-chip, the second VCSEL sub-chip including a plurality of second VCSEL units arranged in a second array;

[0014] Wherein, the laser generated by each of the first VCSEL units in the first VCSEL sub-chip exits from the first side of the VCSEL chip, and the laser generated by each of the second VCSEL units in the second VCSEL sub-chip exits from the second side of the VCSE chip opposite to the first side;

[0015] Wherein, the first VCSEL sub-chip and the second VCSEL sub-chip share an N-DBR structure in terms of structure.

[0016] In the monolithic integrated VCSEL chip according to the present application, the first VCSEL unit and the second VCSEL unit respectively include: a substrate, an N-DBR layer formed on the substrate, an active region located above the N-DBR layer, an oxidation confinement layer for restricting the light-emitting aperture, a P-DBR layer located above the active region, a positive electrode and a negative electrode for conducting the active region, wherein an electrical isolation region is provided between each of the first VCSEL units and each of the second VCSEL units, and wherein the N-DBR layers of each of the first VCSEL units and the N-DBR layers of each of the second VCSEL units are coupled to each other to form the shared N-DBR structure of the first VCSEL sub-chip and the second VCSEL sub-chip.

[0017] In the monolithic integrated VCSEL chip according to the present application, the first VCSEL unit of the first VCSEL sub-chip and the second VCSEL unit of the second VCSEL sub-chip are formed on the opposite first side and second side of the VCSEL chip in an alternating manner.

[0018] In the monolithic integrated VCSEL chip according to the present application, the first VCSEL unit of the first VCSEL sub-chip and the second VCSEL unit of the second VCSEL sub-chip are symmetrically formed on the opposite first side and second side of the VCSEL chip.

[0019] In the monolithic integrated VCSEL chip according to the present application, the second VCSEL units of the second sub-chip are continuously formed between the first VCSEL units of the first sub-chip, and the first VCSEL units of the first VCSEL sub-chip and the second VCSEL units of the second VCSEL sub-chip are formed on the opposite first side and second side of the VCSEL chip.

[0020] In the monolithic integrated VCSEL chip according to the present application, in each of the first VCSEL units, the reflectivity of the N-DBR layer is higher than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the first side of the VCSEL chip. In each of the second VCSEL units, the reflectivity of the N-DBR layer is lower than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the second side of the VCSEL chip opposite to the first side.

[0021] In the monolithic integrated VCSEL chip according to the present application, in each of the first VCSEL units, the number of layers of the P-DBR layer is greater than that of the N-DBR layer; in each of the second VCSEL units, the number of layers of the P-DBR layer is less than that of the N-DBR layer.

[0022] In the monolithic integrated VCSEL chip according to the present application, in each of the first VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR layer ranges from 15 to 45 layers; in each of the second VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR layer ranges from 15 to 45 layers.

[0023] In the monolithic integrated VCSEL chip according to the present application, in each of the first VCSEL units, the reflectivity of the N-DBR layer is higher than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the first side of the VCSEL chip. In each of the second VCSEL units, the reflectivity of the N-DBR layer is higher than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the second side of the VCSEL chip opposite to the first side.

[0024] In the monolithic integrated VCSEL chip according to the present application, in each of the first VCSEL units, the number of layers of the N-DBR layer is greater than that of the P-DBR layer; in each of the second VCSEL units, the number of layers of the N-DBR layer is greater than that of the P-DBR layer.

[0025] In the monolithic integrated VCSEL chip according to the present application, in each of the first VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR layer ranges from 15 to 45 layers; in each of the second VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR layer ranges from 15 to 45 layers.

[0026] In the monolithic integrated VCSEL chip according to the present application, the negative electrodes of each of the first VCSEL units and the negative electrodes of each of the second VCSEL units are coupled to each other to form a negative electrode conductive layer.

[0027] In the monolithic integrated VCSEL chip according to the present application, the negative electrode conductive layer is formed within the N-DBR structure.

[0028] In the monolithic integrated VCSEL chip according to the present application, the positive electrodes of each of the first VCSEL units and each of the second VCSEL units are formed on the first side of the VCSEL unit.

[0029] In the monolithic integrated VCSEL chip according to the present application, the positive electrodes of each of the first VCSEL units and each of the second VCSEL units are formed on the first side of the VCSEL unit; the negative electrodes of each of the first VCSEL units and each of the second VCSEL units are formed on the second side of the VCSEL chip.

[0030] In the monolithic integrated VCSEL chip according to the present application, the negative electrodes of each of the second VCSEL units are arranged alternately, and the laser emitted by each of the second VCSEL units is adapted to exit from the gap formed by two adjacent negative electrodes.

[0031] In the monolithic integrated VCSEL chip according to the present application, the negative electrodes of the second VCSEL units are made of a light-transmissive conductive material.

[0032] In the monolithic integrated VCSEL chip according to the present application, the negative electrodes of at least some of the second VCSEL units are coupled to each other to form a negative electrode conductive layer.

[0033] In the monolithic integrated VCSEL chip according to the present application, the first VCSEL sub-chip and the second VCSEL sub-chip are selected from any one of a TOF VCSEL chip and a structured light VCSEL chip.

[0034] In the monolithic integrated VCSEL chip according to the present application, the first VCSEL sub-chip and the second VCSEL sub-chip are of the same type of VCSEL chip and have different optical powers.

[0035] In the monolithic integrated VCSEL chip according to the present application, the first VCSEL sub-chip and the second VCSEL sub-chip are selected from any one of a TOF VCSEL chip and a structured light VCSEL chip.

[0036] In the monolithic integrated VCSEL chip according to the present application, the width range of the electrical isolation region is from 1 nm to 5 mm.

[0037] In the monolithic integrated VCSEL chip according to the present application, the width range of the electrical isolation region is from 1 μm to 10 μm.

[0038] Through the understanding of the subsequent description and the drawings, the further advantages and advantages of the present application will be fully manifested.

[0039] These and other advantages, features, and advantages of the present application are fully manifested through the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Sketches showing the application of two existing VCSEL chips to a terminal device are illustrated.

[0041] Figure 2 Another sketch showing the application of two existing VCSEL chips to a terminal device is illustrated.

[0042] Figure 3 A cross-sectional sketch of a monolithic integrated VCSEL chip according to an embodiment of the present application is illustrated.

[0043] Figure 4 Sketches of the VCSEL units in the monolithic integrated VCSEL chip according to an embodiment of the present application are illustrated.

[0044] Figure 5 The cross-sectional view of another example of the integrated VCSEL chip according to an embodiment of the present application is illustrated.

[0045] Figure 6 The cross-sectional view of yet another example of the integrated VCSEL chip according to an embodiment of the present application is illustrated.

[0046] Figure 7 The cross-sectional view of yet another example of the integrated VCSEL chip according to an embodiment of the present application is illustrated.

[0047] Figure 8 The cross-sectional view of yet another example of the integrated VCSEL chip according to an embodiment of the present application is illustrated. Detailed implementation manners

[0048] The following description is used to disclose the present application so that those skilled in the art can implement the present application. The preferred embodiments in the following description are only examples, and those skilled in the art can think of other obvious variations. The basic principles defined in the following description of the present application can be applied to other implementation manners, variations, improvements, equivalent manners, and other technical solutions that do not depart from the spirit and scope of the present application.

[0049] Those skilled in the art should understand that in the disclosure of the present application, the orientation or positional relationships indicated by the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limitations on the present application.

[0050] It can be understood that the term "one" should be understood as "at least one" or "one or more". That is, in one embodiment, the number of one element can be one, while in other embodiments, the number of this element can be multiple. The term "one" should not be construed as a limitation on the number.

[0051] Overview of the Application

[0052] As described above, the integrated application of different types of VCSEL chips to terminal devices is the current development trend. Therefore, how to combine the advantages of different types of VCSEL chips and, moreover, optimize the respective defects of different VCSEL chips has become a very important technical problem.

[0053] There are currently various technical solutions for combining different VCSEL chips. Common ones include: "light emission from the front and back sides" and "light emission from the same side". Among them, "light emission from the front and back sides" means setting two VCSEL chips back to back, and the laser emission directions of the two are opposite. Figure 1 and Figure 2 FIGs. illustrate two examples of this layout method.

[0054] As Figure 1 shown, in this solution, two VCSEL chips are placed back to back with a dislocation. Although this solution can integrate the advantages of the two VCSEL chips to a certain extent, this solution occupies too much area, that is, it occupies a relatively large volume of the terminal device, which does not conform to the current development trend of miniaturization and thinning of terminal devices. As Figure 2 shown, in this solution, two VCSEL chips are aligned and set back to back. Although this solution can integrate the advantages of the two VCSEL chips to a certain extent, the thickness dimension of this solution is relatively large, that is, it still occupies a relatively large volume of the terminal device, which does not conform to the current development trend of miniaturization and thinning of terminal devices.

[0055] "Light emission from the same side" means setting the light-emitting surfaces of two VCSEL chips on the same plane. For example, two VCSEL chips are arranged side by side (not shown in the figure). This solution occupies a relatively large area and also does not conform to the current development trend of miniaturization and thinning of terminal devices.

[0056] Moreover, looking at the existing technical solutions of "light emission from the same side" and "light emission from the front and back sides", it can be found that: whether it is the "light emission from the same side" solution or the "light emission from the front and back sides" solution, there is no structural connection between different VCSEL chips. That is, in the existing integrated application solutions of VCSEL chips, different VCSEL chips are only placed at different positions of the terminal device, but they still work and are controlled independently in essence.

[0057] Regarding the above technical problems, the basic idea of this application is to achieve monolithic integration of multiple VCSEL chips at the wafer level, so that the finally formed monolithic integrated VCSEL chip can have the respective advantages of different VCSEL chips and has a relatively small overall size.

[0058] Based on this, the present application provides a monolithic integrated VCSEL chip, which includes a first VCSEL sub-chip. The first VCSEL chip includes a plurality of first VCSEL units arranged in a first array; and a second VCSEL sub-chip monolithically integrated with the first VCSEL sub-chip. The second VCSEL sub-chip includes a plurality of second VCSEL units arranged in a second array. Wherein, the laser generated by each of the first VCSEL units in the first VCSEL sub-chip exits from the first side of the VCSEL chip, and the laser generated by each of the second VCSEL units in the second VCSEL sub-chip exits from the second side of the VCSE chip opposite to the first side. Wherein, the first VCSEL sub-chip and the second VCSEL sub-chip share an N-DBR structure in terms of structure. In this way, the monolithic integrated VCSEL chip realizes the monolithic integration of multiple VCSEL chips at the wafer level, so that it can combine the advantages of different VCSEL chips respectively and has a relatively small overall size.

[0059] After introducing the basic principle of the present application, the various non-limiting embodiments of the present application will be specifically introduced with reference to the accompanying drawings.

[0060] Example 1

[0061] The inventors of the present application studied the consistency of different VCSEL chips in terms of wafer-level structure, and conceived a technical solution for monolithically integrating different models of VCSEL chips at the wafer level, so that the formed monolithic integrated VCSEL chip can combine the advantages of different VCSEL chips respectively and has a relatively small overall thickness size, meeting the development trend of thinness of current terminal devices. Here, in the embodiments of the present application, different VCSEL chips are chips of different models, which include chips of the same type but different parameters (for example, the same type but different powers) and chips of different types. The types of the VCSEL chips include, but are not limited to, TOF VCSEL chips and structured light VCSEL chips.

[0062] The following takes the monolithic integrated VCSEL chip monolithically integrating a first VCSEL sub-chip and a second VCSEL sub-chip as an example to illustrate the monolithic integrated VCSEL chip of the embodiments of the present application, that is, taking the monolithic integrated VCSEL chip integrating two different models of sub-chips as an example.

[0063] Figure 3 The cross-sectional schematic diagram of the monolithic integrated VCSEL chip according to the embodiments of the present application is illustrated. As Figure 3As shown, the monolithic integrated VCSEL chip includes a first VCSEL sub-chip 10 and a second VCSEL sub-chip 20 monolithically integrated with the first VCSEL sub-chip 10. Among them, the first VCSEL sub-chip 10 includes a plurality of first VCSEL units 100 arranged in a first array, and the second VCSEL sub-chip 20 includes a plurality of second VCSEL units 200 arranged in a second array. An electrical isolation region 300 is provided between each of the first VCSEL units 100 and each of the second VCSEL units 200. In the embodiment of the present application, the laser emission direction of the first VCSEL sub-chip 10 is opposite to the laser emission direction of the second VCSEL sub-chip 20. For example, in a specific example of the present application, the laser generated by each of the first VCSEL units 100 in the first VCSEL sub-chip 10 emits from the first side A of the VCSEL chip, and the laser generated by each of the second VCSEL units 200 in the second VCSEL sub-chip 20 emits from the second side B of the VCSE chip opposite to the first side A.

[0064] Specifically, in the embodiment of the present application, as Figure 3 shown, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share an N-DBR structure 120 in terms of structure. In this way, the monolithic integrated VCSEL chip realizes the monolithic integration of the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 at the wafer level, so that it can combine the respective advantages of the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 and has a relatively small overall size.

[0065] In order to illustrate how the first VCSEL sub-chip 10 and the second VCSEL are monolithically integrated at the wafer level, the first VCSEL unit 100 and the second VCSEL unit 200 and their light emission principles are described.

[0066] Figure 4 The figure shows a schematic diagram of each VCSEL unit in the monolithic integrated VCSEL chip according to the embodiment of the present application. As Figure 4As shown, each of the first and second VCSEL units 100, 200 (the first VCSEL unit 100 and the second VCSEL unit 200 have the same structural configuration) includes a substrate 11 (in some embodiments, the VCSEL unit may not be configured with the substrate 11), an N-DBR layer 12 formed on the substrate 11, an active region 13 located above the N-DBR layer 12, an oxidation confinement layer 14 for restricting the light-emitting aperture, a P-DBR layer 15 located above the active region 13, a positive electrode 16 and a negative electrode 17 for conducting the active region 13. Among them, the active region 13 is sandwiched between the P-DBR layer 15 and the N-DBR layer 12 to form a resonant cavity between the P-DBR layer 15 and the N-DBR layer 12.

[0067] During the working process, as long as the following two conditions are met, the first and second VCSEL units 100, 200 can achieve laser excitation: (1) Population inversion process: When there is population inversion in the active region 13 and the gain provided by the laser medium is sufficient to exceed the loss, when current is injected through the negative electrode 17 and the positive electrode 16, the light intensity will continuously increase. When electrons at the bottom of the conduction band in the high-energy state transition to the low-energy band, as light with a specific wavelength is reflected back and forth between the P-DBR layer 15 and the N-DBR layer 12, the amplification process is continuously repeated, and laser is formed; (2) Resonant cavity: Composed of the P-DBR layer 15, the N-DBR layer 12 and the gain medium, it is one of the main conditions for generating laser. The main function of the resonant cavity is to form multiple light energy feedbacks when the light generated in the active region 13 is reflected back and forth between the P-DBR 06 and the N-DBR 03 to form laser oscillation. Finally, the laser projected by the first and second VCSEL units 100, 200 will generate a set of interference fringes in space.

[0068] It is worth mentioning that in the embodiments of the present application, the selection of materials for each layer of the first and second VCSEL units 100, 200 is not limited to the present application. For example, the substrate 11 may include but is not limited to a silicon substrate 11, a sapphire substrate 11, and a potassium arsenide substrate 11, etc.; the materials of the P-DBR layer 15 and the N-DBR layer 12 include but are not limited to: InGaAsP / InP, AlGaInAs / AlInAs, AlGaAsSb / AlAsSb, GaAs / AlGaAs, Si / MgO, and Si / Al2O3, etc.

[0069] In particular, as Figure 3As shown, in the embodiments of the present application, the N-DBR layers 12 of the first VCSEL units 100 are coupled to the N-DBR layers 12 of the second VCSEL units 200 to form the shared N-DBR structure 120 of the first VCSEL sub-chip and the second VCSEL sub-chip 20. That is, the N-DBR layers 12 of the first VCSEL units 100 and the N-DBR layers 12 of the second VCSEL units 200 are coupled to each other at the structural level of the wafer level to form a layer structure, that is, the N-DBR structure 120. Or rather, during the preparation process of the monolithic integrated VCSEL chip, the N-DBR structure 120 is not corroded or etched without being truncated, so that the N-DBR structure 120 layer remains a complete layer structure after the monolithic integrated VCSEL chip is formed.

[0070] Further, as Figure 3 shown, in the embodiments of the present application, the first VCSEL units 100 of the first VCSEL sub-chip 10 and the second VCSEL units 200 of the second VCSEL sub-chip 20 are symmetrically formed on the opposite first side A and second side B of the VCSEL chip. Therefore, when the monolithic integrated VCSEL chip is turned on, the first VCSEL sub-chip 10 can emit laser light from the first side A and the second VCSEL sub-chip 20 can emit laser light from the second side B, that is, the monolithic integrated VCSEL chip can emit light simultaneously from its opposite first side A and second side B.

[0071] Specifically, in the embodiments of the present application, in each of the first VCSEL units 100, the reflectivity of the N-DBR layer 12 is higher than that of the P-DBR layer 15, so that the laser light generated by the first VCSEL unit 100 exits from the first side A of the VCSEL chip. In each of the second VCSEL units 200, the reflectivity of the N-DBR layer 12 is higher than that of the P-DBR, so that the laser light generated by the first VCSEL unit 100 exits from the second side B of the VCSEL chip opposite to the first side A.

[0072] It should be understood that the reflectivities of the N-DBR layers 12 and the P-DBR layers 15 of the first VCSEL units 100 and the second VCSEL units 200 are determined by the number of layers of the N-DBR layers 12 and the P-DBR layers 15. Specifically, in the embodiments of the present application, in each of the first VCSEL units 100, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR; in each of the second VCSEL units 200, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR.

[0073] In the embodiments of the present application, in each of the first VCSEL units 100, the number of layers of the P-DBR layer 15 ranges from 15 layers to 45 layers, and the number of layers of the N-DBR ranges from 15 layers to 45 layers; in each of the second VCSEL units 200, the number of layers of the P-DBR layer 15 ranges from 15 layers to 45 layers, and the number of layers of the N-DBR ranges from 15 layers to 45 layers. Here, one layer of the P-DBR structure is composed of a pair of high-aluminum materials and low-aluminum materials, and one layer of the N-DBR structure is composed of a pair of high-aluminum materials and low-aluminum materials.

[0074] Further, as Figure 3 and Figure 4 shown, in the embodiments of the present application, the anodes 16 of the first VCSEL units 100 of the first VCSEL sub-chip 10 are respectively formed on the surface of the first side A of the monolithic integrated VCSEL chip; the anodes 16 of the second VCSEL units 200 of the second VCSEL sub-chip 20 are respectively formed on the surface of the second side B of the monolithic integrated VCSEL chip. That is, in the embodiments of the present application, the anodes of the monolithic integrated VCSEL chip are respectively formed on its upper surface and lower surface. Further, as Figure 3 and Figure 4 shown, in the embodiments of the present application, the cathodes 17 of the first VCSEL units 100 of the first VCSEL sub-chip 10 and the cathodes 17 of the second VCSEL units 200 of the second VCSEL sub-chip 20 are mutually coupled to form a cathode conductive layer 170. That is, in the embodiments of the application, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share the cathode conductive layer 170, or rather, the monolithic integrated VCSEL chip shares the cathode.

[0075] Particularly, in the embodiments of the present application, the cathode conductive layer 170 is formed within the N-DBR structure 120. And, as Figure 3 shown, in the embodiments of the present application, the cathode conductive layer 170 is located in the middle of the monolithic integrated VCSEL chip, that is, the cathode of the monolithic integrated VCSEL chip is located in the middle thereof.

[0076] It is worth mentioning that, in the embodiments of the present application, the anodes 16 of at least some of the first VCSEL units 100 of the first VCSEL sub-chip 10 can be electrically connected to each other to form an anode 16 conductive layer. In this way, the first VCSEL sub-chip 10 is controlled to be lit in zones, where the zone setting is determined by the pattern configuration of the anode 16 conductive layer. Similarly, in the embodiments of the present application, the anodes 16 of at least some of the second VCSEL units 200 of the second VCSEL sub-chip 20 can be electrically connected to each other to form an anode conductive layer. In this way, the second VCSEL sub-chip 20 is controlled to be lit in zones, where the zone setting is determined by the pattern configuration of the anode conductive layer.

[0077] It should be understood that, in the embodiments of the present application, by reasonably arranging the anode 16 and the cathode 17 of the first VCSEL sub-chip 10 and the anode 16 and the cathode 17 of the second VCSEL sub-chip 20, the monolithic integrated VCSEL chip can achieve different lighting modes to expand the application possibilities of the monolithic integrated VCSEL chip.

[0078] Furthermore, in the embodiments of the present application, the first VCSEL sub-chip 10 is implemented as a TOF VCSEL chip, and the multiple first VCSEL units 100 included therein are arranged in a regular array; the second VCSEL sub-chip 20 is implemented as a structured light VCSEL chip, and the multiple second VCSEL units 200 included therein are arranged in a specific coding array. That is, in the example Figure 3 shown, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 are different types of VCSEL chips. Therefore, the monolithic integrated VCSEL chip can selectively activate the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 based on the requirements of different application scenarios. For example, in an application scenario that requires high measurement accuracy, the second VCSEL sub-chip 20 can be activated and the first VCSEL sub-chip 10 can be turned off; when measuring a relatively long distance, the first VCSEL sub-chip 10 can be activated and the second VCSEL sub-chip 20 can be turned off.

[0079] That is, the monolithic integrated VCSEL chip can combine the performance advantages of different types of VCSEL chips. Moreover, since the first sub-chip and the second sub-chip are monolithically integrated at the wafer level, the monolithic integrated VCSEL chip has advantages in both its overall height dimension and its horizontal dimension, that is, the overall height dimension is small, and the occupied area in the horizontal direction is also relatively small.

[0080] It is worth mentioning that, in the embodiments of the present application, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 may also be implemented as VCSEL chips of the same type but with different parameters (for example, different optical powers), and this is not limited by the present application.

[0081] In summary, the monolithic integrated VCSEL chip based on the embodiments of the present application is elucidated, which realizes the monolithic integration of multiple VCSEL chips at the wafer level, so that it can combine the respective advantages of different VCSEL chips and has a relatively small overall size.

[0082] And, the monolithic integrated VCSEL chip as described above can be prepared by the preparation scheme described below.

[0083] First, an epitaxial structure is formed by MOCVD process (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition process) or other metal growth processes. The epitaxial structure includes a substrate 11 structure, an N-DBR layer 12, an active region 13 structure, and a P-DRB structure; then, the epitaxial structure is processed by photolithography or other etching processes to form a mesa structure; then, an oxidation process is performed to form an oxidation confinement layer 14 and the gaps between the mesa structures are filled with a transparent non-conductive material to form the electrical isolation region 300. In particular, in the embodiments of the present application, the width range of the electrical isolation region 300 is from 1 nm to 5 mm, preferably, the width range of the electrical isolation region 300 is from 1 μm to 10 μm; then, a positive electrode 16 is formed on the mesa structure to form the first VCSEL sub-chip 10; then, an epitaxial structure is formed on the N-DBR structure 120 of the first VCSEL sub-chip 10 by MOCVD process (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition process) or other metal growth processes; then, the second VCSEL sub-chip 20 is made through the process described above; then, a negative electrode conductive layer 170 is formed in the N-DBR structure 120 to form the monolithic integrated VCSEL chip.

[0084] Example 2

[0085] Figure 5 The cross-sectional view of another example of the integrated VCSEL chip according to the embodiments of the present application is illustrated.

[0086] As Figure 5As shown, in this example, the monolithic integrated VCSEL chip includes a first VCSEL sub-chip 10 and a second VCSEL sub-chip 20 monolithically integrated with the first VCSEL sub-chip 10. The first VCSEL sub-chip 10 includes a plurality of first VCSEL units 100 arranged in a first array, and the second VCSEL sub-chip 20 includes a plurality of second VCSEL units 200 arranged in a second array. In particular, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share an N-DBR structure 120 structurally.

[0087] Correspondingly, in this example, the laser generated by each of the first VCSEL units 100 in the first VCSEL sub-chip 10 exits from the first side A of the VCSEL chip, and the laser generated by each of the second VCSEL units 200 in the second VCSEL sub-chip 20 exits from the second side B of the VCSE chip opposite to the first side A.

[0088] Different from the above Embodiment 1, in the embodiment of the present application, the first VCSEL units 100 of the first VCSEL sub-chip 10 and the second VCSEL units 200 of the second VCSEL sub-chip 20 are formed on the opposite first side A and second side B of the VCSEL chip in an alternating manner. Specifically, as Figure 5 shown, in this example, the first VCSEL sub-chip 10 is formed on the first side A of the monolithic integrated VCSEL chip, and the second VCSEL sub-chip 20 is formed on the second side B of the monolithic integrated VCSEL chip. Among them, one second VCSEL unit 200 is interposed between every two first VCSEL units 100, and one first VCSEL unit 100 is interposed between every two second VCSEL units 200. In this way, the first VCSEL units 100 of the first VCSEL sub-chip 10 and the second VCSEL units 200 of the second VCSEL sub-chip 20 are formed on the opposite first side A and second side B of the VCSEL chip in an alternating manner. Therefore, when the monolithic integrated VCSEL chip is turned on, the first VCSEL sub-chip 10 can emit laser from the first side A and the second VCSEL sub-chip 20 can emit laser from the second side B, that is, the monolithic integrated VCSEL chip can emit light simultaneously from its opposite first side A and second side B.

[0089] Furthermore, as Figure 4 and Figure 5As shown, in this embodiment, the N-DBR layers 12 of the first VCSEL units 100 are coupled to each other to form a first layer structure, and the N-DBR layers 12 of the second VCSEL units 200 have a second layer structure. Moreover, the first layer structure and the second layer structure are the same layer structure (i.e., the N-DBR structure 120). That is to say, in this example, the N-DBR layers 12 of the first VCSEL units 100 and the N-DBR layers 12 of the second VCSEL units 200 share the N-DBR structure 120 at the wafer-level structural level. In other words, during the fabrication process of the monolithic integrated VCSEL chip, the N-DBR structure 120 is not etched or etched without being truncated, so that the N-DBR structure 120 layer remains a complete layer structure after the monolithic integrated VCSEL chip is formed.

[0090] Specifically, in the embodiments of the present application, as Figure 4 shown, in each of the first VCSEL units 100, the reflectivity of the N-DBR layer 12 is higher than that of the P-DBR layer 15, so that the laser generated by the first VCSEL unit 100 exits from the first side A of the VCSEL chip (as Figure 5 shown). In each of the second VCSEL units 200, the reflectivity of the N-DBR layer 12 is lower than that of the P-DBR, so that the laser generated by the first VCSEL unit 100 exits from the second side B of the VCSEL chip opposite to the first side A (as Figure 5 shown).

[0091] It should be understood that the reflectivities of the N-DBR layers 12 and the P-DBR layers 15 of the first VCSEL units 100 and the second VCSEL units 200 are determined by the number of layers of the N-DBR layers 12 and the P-DBR layers 15. Specifically, in the embodiments of the present application, in each of the first VCSEL units 100, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR; in each of the second VCSEL units 200, the number of layers of the N-DBR layer 12 is less than the number of layers of the P-DBR.

[0092] In the embodiments of the present application, in each of the first VCSEL units 100, the number of layers of the P-DBR layer 15 ranges from 15 layers to 45 layers, and the number of layers of the N-DBR ranges from 15 layers to 45 layers; in each of the second VCSEL units 200, the number of layers of the P-DBR layer 15 ranges from 15 layers to 45 layers, and the number of layers of the N-DBR ranges from 15 layers to 45 layers. Here, one layer of the P-DBR structure is composed of a pair of high-aluminum materials and low-aluminum materials, and one layer of the N-DBR structure is composed of a pair of high-aluminum materials and low-aluminum materials.

[0093] Further, as Figure 4 and 5 shown, in this example, the anodes 16 of the first VCSEL units 100 of the first VCSEL sub-chip 10 are respectively formed on the surface of the first side A of the monolithic integrated VCSEL chip; the anodes 16 of the second VCSEL units 200 of the second VCSEL sub-chip 20 are respectively formed on the surface of the first side A of the monolithic integrated VCSEL chip. That is, in the embodiments of the present application, the anode of the monolithic integrated VCSEL chip is formed on one of its side surfaces. Further, as Figure 4 and 5 shown, in the embodiments of the present application, the cathodes 17 of the first VCSEL units 100 of the first VCSEL sub-chip 10 and the cathodes 17 of the second VCSEL units 200 of the second VCSEL sub-chip 20 are coupled to each other to form a cathode conductive layer 170. That is, in the embodiments of the application, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share the cathode conductive layer 170, or rather, the monolithic integrated VCSEL chip shares the cathode.

[0094] As Figure 5 shown, in this example, the cathode conductive layer 170 is formed within the N-DBR structure 120. More specifically, the cathode conductive layer 170 is located in the middle of the monolithic integrated VCSEL chip, that is, the cathode of the monolithic integrated VCSEL chip is located in the middle thereof.

[0095] Further, in this example, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 are different types of VCSEL chips; or, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 can also be implemented as the same type but with different parameters (for example, different optical powers) of VCSEL chips, and this is not limited by the present application.

[0096] In summary, the monolithic integrated VCSEL chip according to the embodiments of the present application is described. It realizes the monolithic integration of multiple VCSEL chips at the wafer level, enabling it to combine the advantages of different VCSEL chips and having a relatively small overall size.

[0097] Moreover, the monolithic integrated VCSEL chip as described above can be prepared by the preparation scheme described below.

[0098] First, an epitaxial structure is formed by MOCVD process (Metal-organic Chemical Vapor Deposition) or other metal growth processes. The epitaxial structure includes a substrate 11 structure, an N-DBR layer 12, an active region 13 structure, and a P-DRB structure. Then, the epitaxial structure is processed by photolithography or other etching processes to form a mesa structure. Next, an oxidation process is performed to form an oxidation confinement layer 14 and the gaps between the mesa structures are filled with a transparent non-conductive material to form the electrical isolation region 300. In particular, in the embodiments of the present application, the width range of the electrical isolation region 300 is from 1 nm to 5 mm. Preferably, the width range of the electrical isolation region 300 is from 1 μm to 10 μm. Then, the N-DBR structure 120 of the epitaxial structure is further processed by photolithography or other etching processes to partially reduce the number of layers of the N-DBR structure 120 at specific positions. Also, the etched regions in the N-DBR structure 120 are filled with a transparent non-conductive material to form the electrical isolation region 300. Then, a positive electrode 16 is formed on the mesa structure by evaporation. Next, a negative conductive layer 170 is formed in the N-DBR structure 120 to obtain the monolithic integrated VCSEL chip.

[0099] Example 3

[0100] Figure 6 A cross-sectional view showing another example of the integrated VCSEL chip according to the embodiments of the present application is illustrated.

[0101] As Figure 6As shown, in this example, the monolithic integrated VCSEL chip includes a first VCSEL sub-chip 10 and a second VCSEL sub-chip 20 monolithically integrated with the first VCSEL sub-chip 10. The first VCSEL sub-chip 10 includes a plurality of first VCSEL units 100 arranged in a first array, and the second VCSEL sub-chip 20 includes a plurality of second VCSEL units 200 arranged in a second array. In particular, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share an N-DBR structure 120 in terms of structure.

[0102] Correspondingly, in this example, the laser generated by each of the first VCSEL units 100 in the first VCSEL sub-chip 10 exits from the first side A of the VCSEL chip, and the laser generated by each of the second VCSEL units 200 in the second VCSEL sub-chip 20 exits from the second side B of the VCSE chip opposite to the first side A.

[0103] Different from the above-mentioned Embodiment 1, in the embodiment of the present application, the second VCSEL units 200 of the second sub-chip are continuously formed between the first VCSEL units 100 of the first sub-chip, and the first VCSEL units 100 of the first VCSEL sub-chip 10 and the second VCSEL units 200 of the second VCSEL sub-chip 20 are formed on the opposite first side A and second side B of the VCSEL chip. Specifically, as Figure 6 shown, in this example, the first VCSEL sub-chip 10 is formed on the first side A of the monolithic integrated VCSEL chip, and the second VCSEL sub-chip 20 is formed on the second side B of the monolithic integrated VCSEL chip. Among them, the second VCSEL units 200 of the second VCSEL sub-chip 20 are continuously formed on the second side B, and the arrangement positions of the second VCSEL units 200 are located between the first VCSEL units 100 of the first sub-chip, that is, the arrangement positions of the second VCSEL units 200 are clamped between the first VCSEL units 100 of the first sub-chip.

[0104] Correspondingly, when the monolithic integrated VCSEL chip is turned on, the first VCSEL sub-chip 10 can emit laser from the first side A and the second VCSEL sub-chip 20 can emit laser from the second side B, that is, the monolithic integrated VCSEL chip can emit light simultaneously from its opposite first side A and second side B.

[0105] Furthermore, as Figure 4 and Figure 6As shown, in this embodiment, the N-DBR layers 12 of the first VCSEL units 100 are coupled to each other to form a first layer structure, and the N-DBR layers 12 of the second VCSEL units 200 have a second layer structure. Moreover, the first layer structure and the second layer structure are the same layer structure (i.e., the N-DBR structure 120). That is to say, in this example, the N-DBR layers 12 of the first VCSEL units 100 and the N-DBR layers 12 of the second VCSEL units 200 share the N-DBR structure 120 at the wafer-level structural level. In other words, during the fabrication process of the monolithic integrated VCSEL chip, the N-DBR structure 120 is not etched or etched without being truncated, so that the N-DBR structure 120 layer remains a complete layer structure after the monolithic integrated VCSEL chip is formed.

[0106] Specifically, in the embodiments of the present application, as Figure 4 shown, in each of the first VCSEL units 100, the reflectivity of the N-DBR layer 12 is higher than that of the P-DBR layer 15, so that the laser generated by the first VCSEL unit 100 exits from the first side A of the VCSEL chip (as Figure 6 shown). In each of the second VCSEL units 200, the reflectivity of the N-DBR layer 12 is lower than that of the P-DBR, so that the laser generated by the first VCSEL unit 100 exits from the second side B of the VCSEL chip opposite to the first side A (as Figure 6 shown).

[0107] It should be understood that, as Figure 4 shown, the reflectivities of the N-DBR layer 12 and the P-DBR layer 15 of the first VCSEL unit 100 and the second VCSEL unit 200 are determined by the number of layers of the N-DBR layer 12 and the P-DBR layer 15. Specifically, in the embodiments of the present application, in each of the first VCSEL units 100, the number of layers of the N-DBR layer 12 is greater than the number of layers of the P-DBR; in each of the second VCSEL units 200, the number of layers of the N-DBR layer 12 is less than the number of layers of the P-DBR.

[0108] In the embodiments of the present application, in each of the first VCSEL units 100, the number of layers of the P-DBR layer 15 ranges from 15 to 45 layers, and the number of layers of the N-DBR ranges from 15 to 45 layers; in each of the second VCSEL units 200, the number of layers of the P-DBR layer 15 ranges from 15 to 45 layers, and the number of layers of the N-DBR ranges from 15 to 45 layers.

[0109] Further, as Figure 4 and Figure 6 shown, in this example, the anodes 16 of the first VCSEL units 100 of the first VCSEL sub-chip 10 are respectively formed on the surface of the first side A of the monolithic integrated VCSEL chip; the anodes 16 of the second VCSEL units 200 of the second VCSEL sub-chip 20 are respectively formed on the surface of the first side A of the monolithic integrated VCSEL chip. That is, in the embodiments of the present application, the anode of the monolithic integrated VCSEL chip is formed on one side surface thereof. Further, as Figure 4 and Figure 6 shown, in the embodiments of the present application, the cathodes 17 of the first VCSEL units 100 of the first VCSEL sub-chip 10 and the cathodes 17 of the second VCSEL units 200 of the second VCSEL sub-chip 20 are mutually coupled to form a cathode conductive layer 170. That is, in the embodiments of the application, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 share the cathode conductive layer 170, or rather, the monolithic integrated VCSEL chip shares a cathode.

[0110] As Figure 6 shown, in this example, the cathode conductive layer 170 is formed within the N-DBR structure 120. More specifically, the cathode conductive layer 170 is located in the middle of the monolithic integrated VCSEL chip, that is, the cathode of the monolithic integrated VCSEL chip is located in the middle thereof.

[0111] Figure 7 The figure shows a cross-sectional view of another example of the integrated VCSEL chip according to the embodiments of the present application. Among them, Figure 7 The example illustrated is Figure 6 a modified implementation of. As Figure 7 shown, in this example, the cathodes 17 of the first VCSEL units 100 and the second VCSEL units 200 are formed on the second side B of the VCSEL chip, and the cathodes 17 of the first VCSEL units 100 and the second VCSEL units 200 are mutually coupled to the cathode conductive layer 170, wherein the cathode conductive layer 170 is made of a light-transmissive conductive material.

[0112] It is worth mentioning that in such as Figure 8In the illustrated example, it is only necessary that the negative electrode 17 corresponding to the second VCSEL sub-chip 20 can allow the laser generated by the second VCSEL sub-chip 20 to pass through. That is, in this example, at least the negative electrode 17 corresponding to the second VCSEL sub-chip 20 is made of a light-transmissive conductive material. In a specific implementation, the light-transmissive material is selected from any one of ITO (indium tin oxide), ATO (antimony tin oxide), FTO (fluorine-doped tin oxide), AZO (aluminum zinc oxide), GZO (gallium zinc oxide), and IZO (indium zinc oxide).

[0113] Figure 8 FIG. illustrates a cross-sectional view of another example of the integrated VCSEL chip according to an embodiment of the present application, wherein, Figure 8 The illustrated example is Figure 7 a modified implementation of. As Figure 8 shown, in this example, the negative electrodes 17 of each of the first VCSEL units 100 and each of the second VCSEL units 200 are formed on the second side B of the VCSEL chip. And, the negative electrodes 17 of each of the second VCSEL units 200 are arranged alternately, and the laser emitted by each of the second VCSEL units 200 is adapted to emit from the gap formed between two adjacent negative electrodes 17.

[0114] Furthermore, in this example, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 are different types of VCSEL chips; alternatively, the first VCSEL sub-chip 10 and the second VCSEL sub-chip 20 can also be implemented as the same type but having different parameters (for example, different optical powers) of VCSEL chips, and this is not limited by the present application.

[0115] In summary, the monolithic integrated VCSEL chip based on the embodiment of the present application is clarified, which realizes the monolithic integration of multiple VCSEL chips at the wafer level, so that it can combine the respective advantages of different VCSEL chips and has a relatively small overall size.

[0116] And, the monolithic integrated VCSEL chip as described above can be prepared by the preparation scheme described below.

[0117] First, an epitaxial structure is formed through the MOCVD process (Metal-organic Chemical Vapor Deposition) or other metal growth processes. The epitaxial structure includes a substrate 11 structure, an N-DBR layer 12, an active region 13 structure, and a P-DRB structure. Then, the epitaxial structure is processed through photolithography or other etching processes to form a mesa structure. Next, an oxidation process is performed to form an oxidation confinement layer 14, and the gaps between the mesa structures are filled with a transparent non-conductive material to form the electrical isolation region 300. The transparent non-conductive material is selected from silicon nitride, silicon oxide, etc. In particular, in the embodiments of the present application, the width range of the electrical isolation region 300 is from 1 nm to 5 mm. Preferably, the width range of the electrical isolation region 300 is from 1 μm to 10 μm. Then, the N-DBR structure 120 of the epitaxial structure is further processed through photolithography or other etching processes to partially reduce the number of layers of the N-DBR structure 120 at specific positions. Also, the etched regions in the N-DBR structure 120 are filled with the transparent non-conductive material to form the electrical isolation region 300. Then, a positive electrode 16 is formed on the mesa structure through evaporation. Next, a negative conductive layer 170 is formed in the N-DBR structure 120 to fabricate the monolithic integrated VCSEL chip.

[0118] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. Additionally, the specific details disclosed above are only for illustrative and facilitating understanding purposes and are not limitations. These details do not limit the present application to necessarily adopt these specific details for implementation.

[0119] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present application are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms meaning "including but not limited to" and can be used interchangeably with each other. The word "or" and "and" used herein refer to the word "and / or" and can be used interchangeably with it, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with it.

[0120] It should also be noted that in the devices, equipment and methods of the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations shall be regarded as equivalent solutions of the present application.

[0121] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present application. Thus, the present application is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0122] The above description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the form disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and subcombinations.

Claims

1. A monolithic integrated VCSEL chip, characterized in that, Comprising: A first VCSEL sub-chip, the first VCSEL sub-chip including a plurality of first VCSEL units arranged in a first array; And A second VCSEL sub-chip monolithically integrated with the first VCSEL sub-chip, the second VCSEL sub-chip including a plurality of second VCSEL units arranged in a second array; Wherein, the laser generated by each of the first VCSEL units in the first VCSEL sub-chip exits from a first side of the VCSEL chip, and the laser generated by each of the second VCSEL units in the second VCSEL sub-chip exits from a second side of the VCSEL chip opposite to the first side; Wherein, the first VCSEL sub-chip and the second VCSEL sub-chip share an N-DBR structure in terms of structure; Wherein, the first VCSEL units of the first VCSEL sub-chip and the second VCSEL units of the second VCSEL sub-chip are formed on the opposite first side and second side of the VCSEL chip; The first VCSEL units of the first VCSEL sub-chip and the second VCSEL units of the second VCSEL sub-chip are alternately arranged, or, the second VCSEL units of the second VCSEL sub-chip are continuously formed between the first VCSEL units of the first VCSEL sub-chip.

2. The monolithic integrated VCSEL chip according to claim 1, wherein, The first VCSEL units and the second VCSEL units respectively include: a substrate, an N-DBR layer formed on the substrate, an active region formed on the N-DBR layer, an oxidation confinement layer for restricting the light-emitting aperture, a P-DBR layer formed on the active region, a positive electrode and a negative electrode for conducting the active region. Wherein, an electrical isolation region is provided between each of the first VCSEL units and each of the second VCSEL units. Wherein, the N-DBR layers of each of the first VCSEL units and the N-DBR layers of each of the second VCSEL units are coupled to each other to form the shared N-DBR structure of the first VCSEL sub-chip and the second VCSEL sub-chip.

3. The chip-integrated VCSEL chip according to claim 2, wherein, In each of the first VCSEL units, the reflectivity of the N-DBR layer is higher than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the first side of the VCSEL chip. In each of the second VCSEL units, the reflectivity of the N-DBR layer is lower than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the second side of the VCSEL chip opposite to the first side.

4. The monolithic integrated VCSEL chip according to claim 3, wherein, In each of the first VCSEL units, the number of layers of the P-DBR layer is greater than the number of layers of the N-DBR layer; in each of the second VCSEL units, the number of layers of the P-DBR layer is less than the number of layers of the N-DBR layer.

5. The monolithic integrated VCSEL chip according to claim 4, wherein, In each of the first VCSEL units, the number of layers of the P-DBR layer ranges from 15 layers to 45 layers, and the number of layers of the N-DBR ranges from 15 layers to 45 layers; in each of the second VCSEL units, the number of layers of the P-DBR layer ranges from 15 layers to 45 layers, and the number of layers of the N-DBR ranges from 15 layers to 45 layers.

6. The monolithic integrated VCSEL chip according to claim 2, wherein, The negative electrodes of the first VCSEL units are coupled to each other, and the negative electrodes of the second VCSEL units are coupled to each other to form a negative conductive layer.

7. The monolithic integrated VCSEL chip according to claim 6, wherein, The negative conductive layer is formed within the N-DBR structure.

8. The monolithic integrated VCSEL chip according to claim 7, wherein, The positive electrodes of the first VCSEL units and the second VCSEL units are formed on the first side of the VCSEL units.

9. The monolithic integrated VCSEL chip according to any one of claims 2, wherein, The positive electrodes of the first VCSEL units and the second VCSEL units are formed on the first side of the VCSEL units; the negative electrodes of the first VCSEL units and the second VCSEL units are formed on the second side of the VCSEL chip.

10. The monolithic integrated VCSEL chip according to claim 9, wherein, The negative electrodes of the second VCSEL units are arranged alternately, and the laser emitted by each of the second VCSEL units is adapted to emit from the gap formed between two adjacent negative electrodes.

11. The monolithic integrated VCSEL chip according to claim 9, wherein, The negative electrodes of the second VCSEL units are made of a light-transmissive conductive material.

12. The monolithic integrated VCSEL chip according to claim 11, wherein, At least some of the negative electrodes of the second VCSEL units are coupled to each other to form a negative conductive layer.

13. The monolithic integrated VCSEL chip according to claim 2, wherein, The first VCSEL sub-chip and the second VCSEL sub-chip are the same type of VCSEL chips, and have different optical powers.

14. The monolithic integrated VCSEL chip according to claim 2, wherein, The first VCSEL sub-chip and the second VCSEL sub-chip are selected from any one of TOF VCSEL chips and structured light VCSEL chips.

15. The monolithic integrated VCSEL chip according to claim 2, wherein, The width range of the electrical isolation region is from 1 nm to 5 mm.

16. The monolithic integrated VCSEL chip according to claim 15, wherein, The width range of the electrical isolation region is from 1 um to 10 um.

17. A monolithic integrated VCSEL chip, characterized in that, Including: A first VCSEL sub-chip, the first VCSEL sub-chip includes a plurality of first VCSEL units arranged in a first array; And A second VCSEL sub-chip monolithically integrated with the first VCSEL sub-chip, the second VCSEL sub-chip includes a plurality of second VCSEL units arranged in a second array; Wherein, the laser generated by each of the first VCSEL units in the first VCSEL sub-chip emits from the first side of the VCSEL chip, and the laser generated by each of the second VCSEL units in the second VCSEL sub-chip emits from the second side of the VCSEL chip opposite to the first side; Wherein, the first VCSEL sub-chip and the second VCSEL sub-chip share an N-DBR structure in terms of structure; Wherein, the first VCSEL units of the first VCSEL sub-chip and the second VCSEL units of the second VCSEL sub-chip are formed on the opposite first side and second side of the VCSEL chip; The first VCSEL units of the first VCSEL sub-chip and the second VCSEL units of the second VCSEL sub-chip are symmetrical to each other.

18. The monolithic integrated VCSEL chip according to claim 17, wherein, The first VCSEL unit and the second VCSEL unit respectively include: a substrate, an N-DBR layer formed on the substrate, an active region formed on the N-DBR layer, an oxidation confinement layer for restricting the light-emitting aperture, a P-DBR layer formed on the active region, a positive electrode and a negative electrode for conducting the active region. Wherein, an electrical isolation region is provided between each of the first VCSEL units and each of the second VCSEL units. Wherein, the N-DBR layers of each of the first VCSEL units and the N-DBR layers of each of the second VCSEL units are coupled to each other to form the N-DBR structure shared by the first VCSEL sub-chip and the second VCSEL sub-chip.

19. The monolithic integrated VCSEL chip according to claim 18, wherein, In each of the first VCSEL units, the reflectivity of the N-DBR layer is higher than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the first side of the VCSEL chip. In each of the second VCSEL units, the reflectivity of the N-DBR layer is higher than that of the P-DBR layer, so that the laser generated by the first VCSEL unit exits from the second side of the VCSEL chip opposite to the first side.

20. The monolithic integrated VCSEL chip according to claim 19, wherein, In each of the first VCSEL units, the number of layers of the N-DBR layer is greater than the number of layers of the P-DBR layer; in each of the second VCSEL units, the number of layers of the N-DBR layer is greater than the number of layers of the P-DBR layer.

21. The monolithic integrated VCSEL chip according to claim 20, wherein, In each of the first VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR ranges from 15 to 45 layers; in each of the second VCSEL units, the number of layers of the P-DBR layer ranges from 15 to 45 layers, and the number of layers of the N-DBR ranges from 15 to 45 layers.

22. The monolithic integrated VCSEL chip according to claim 18, wherein, The negative electrodes of each of the first VCSEL units and the negative electrodes of each of the second VCSEL units are coupled to each other to form a negative electrode conductive layer.

23. The monolithic integrated VCSEL chip according to claim 22, wherein, The negative electrode conductive layer is formed within the N-DBR structure.

24. The monolithic integrated VCSEL chip according to claim 23, wherein, The positive electrodes of each of the first VCSEL units and each of the second VCSEL units are formed on the first side of the VCSEL unit.

25. The monolithic integrated VCSEL chip according to claim 18, wherein, The positive electrodes of each of the first VCSEL units and each of the second VCSEL units are formed on the first side of the VCSEL unit; the negative electrodes of each of the first VCSEL units and each of the second VCSEL units are formed on the second side of the VCSEL chip.

26. The monolithic integrated VCSEL chip according to claim 25, wherein, The negative electrodes of each of the second VCSEL units are arranged alternately, and the laser emitted by each of the second VCSEL units is adapted to exit from the gap formed between two adjacent negative electrodes.

27. The monolithic integrated VCSEL chip according to claim 25, wherein, The negative electrodes of each of the second VCSEL units are made of a light-transmissive conductive material.

28. The monolithic integrated VCSEL chip according to claim 27, wherein, At least some of the negative electrodes of the second VCSEL units are coupled to each other to form a negative electrode conductive layer.

29. The monolithic integrated VCSEL chip according to claim 18, wherein, The first VCSEL sub-chip and the second VCSEL sub-chip are selected from any one of TOF VCSEL chips and structured light VCSEL chips.

30. The monolithic integrated VCSEL chip according to claim 18, wherein, The width range of the electrical isolation region is from 1 nm to 5 mm.

31. The monolithic integrated VCSEL chip according to claim 30, wherein, The width range of the electrical isolation region is from 1 um to 10 um.

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