Integrated Circuit and Its Interface Control Circuit

Abstract

The present invention relates to an integrated circuit and an interface control circuit thereof. The interface control circuit includes an interface wrapper, a logic circuit, a multiplexer, and a command decoder. The interface wrapper transmits and receives a plurality of first signals in a first interface, converts the first signals into a plurality of second signals in a second interface, and generates at least one first command signal according to the first signals. The logic circuit receives the second signals and generates a second command signal according to the second signals. The multiplexer receives the first command signal and the second command signal, and generates a third command signal according to the first command signal and the second command signal. The command decoder receives the third command signal and generates a decoded command according to the third command signal.

Description

Technical Field

[0001] The present invention relates to an integrated circuit and an interface control circuit thereof, and more particularly to an interface control circuit capable of processing signals of various formats between an integrated circuit bus interface and a serial peripheral interface. Background Art

[0002] In conventional technology, an integrated circuit (I 2 C) interface and / or serial peripheral interface (SPI) to access integrated circuits with electrically erasable programmable read-only memory (EEPROM). In terms of application, I 2 The C interface not only has a lower operating speed than SPI, 2 The hardware structure of the I C interface is also simpler than that of the SPI. 2 Both the C interface and SPI have their own advantages. In addition, in order to save the cost of product mask, I 2 The combination of C interface and SPI can be a good solution. Summary of the invention

[0003] The invention provides an integrated circuit and an interface control circuit capable of processing signals in various formats.

[0004] The interface control circuit includes an interface wrapper, a logic circuit, a multiplexer, and a command decoder. The interface wrapper receives and sends a plurality of first signals in a first interface, converts the first signals into a plurality of second signals in a second interface, and generates at least one first command signal according to the first signal. The logic circuit receives the second signal, and generates a second command signal according to the second signal. The multiplexer receives the first command signal and the second command signal, and generates a third command signal according to the first command signal and the second command signal. The command decoder receives the third command signal, and generates a decoded command according to the third command signal.

[0005] The integrated circuit includes a non-volatile memory and the interface control circuit mentioned above. The interface control circuit converts a first signal to generate a plurality of access control signals for accessing the non-volatile memory.

[0006] Based on the above, in an embodiment of the present invention, the interface control circuit provides a combined interface solution, and the chip can receive signals in multiple formats through the interface control circuit.

[0007] In order to better understand the above features and advantages of the present disclosure, several embodiments are described in detail with reference to the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0009] Figure 1 It is a block diagram of an interface control circuit according to an embodiment of the present disclosure;

[0010] Figure 2A It is a waveform graph of a write operation of an interface control circuit according to an embodiment of the present disclosure;

[0011] Figure 2B It is a waveform graph of a read operation of an interface control circuit according to an embodiment of the present disclosure;

[0012] Figure 3 It is a block diagram of an integrated circuit according to an embodiment of the present disclosure.

[0013] Explanation of reference numerals in the drawings

[0014] 100, 310: Interface control circuit;

[0015] 110: Interface wrapper;

[0016] 120: Logic circuit;

[0017] 130: Multiplexer;

[0018] 140: Command decoder;

[0019] 150: Input / output buffer;

[0020] 300: Integrated circuit;

[0021] 320: Non-volatile memory;

[0022] ACK: Acknowledgment signal;

[0023] BP_addr: Bypass address signal;

[0024] BP_cmd: Bypass command signal;

[0025] BP_data: Bypass data signal;

[0026] CMD1: First command signal;

[0027] CMD2: Second command signal;

[0028] CMD3: Third command signal;

[0029] COD1, COD2: Device selection code;

[0030] CS1: Access control signal;

[0031] CSB, spi_csb: Chip select signal;

[0032] DC1: Decoded command;

[0033] I2C_MODE: Mode selection signal;

[0034] i2C_read: I2C device selection code;

[0035] i2C_sdo: I2C data output code;

[0036] LSC1: Logic state control signal;

[0037] N_addr: Address;

[0038] N_cmd: Command;

[0039] N_data: Data;

[0040] N_dummy: Dummy;

[0041] NACK: Non-acknowledgment signal;

[0042] RC: Read code;

[0043] RD / WT: Read or write mode signal;

[0044] SCL, spi_sck: Clock signal;

[0045] SDA: Bidirectional signal;

[0046] SDAI, spi_sdi: Data input signal;

[0047] SDOB, spi_sdo: Data output signal;

[0048] SG1: First signal;

[0049] SG2: Second signal;

[0050] SP: I2C stop condition;

[0051] SP_ADD: Address signal;

[0052] SP_D: Data signal;

[0053] SP_ST: Status signal;

[0054] TP1, TP2, TP3, TP4: Time intervals;

[0055] TPE1, TPE2: Time points;

[0056] WC: Write Code. Detailed Implementation Manner

[0057] Please refer to Figure 1 , which is a block diagram of an interface control circuit according to an embodiment of the present disclosure. The interface control circuit 100 includes an interface wrapper 110, a logic circuit 120, a multiplexer (MUX) 130, and a command decoder 140. The interface wrapper 110 transceives a plurality of first signals SG1 in a first interface. The interface wrapper 110 further performs a conversion operation between the first signal SG1 and a plurality of second signals SG2 in a second interface, and generates at least one first command signal CMD1 according to the first signal SG1. In this embodiment, the first interface may be an integrated circuit (I 2 C) interface, and the second interface may be a serial peripheral interface (SPI). In addition, the first signal SG1 includes a chip select signal CSB, a clock signal SCL, a data input signal SDAI, and a data output signal SDOB, where the chip select signal CSB, the clock signal SCL, the data input signal SDAI, and the data output signal SDOB are all I 2 C format signals. Here, the bidirectional signal SDA in SPI format may be coupled to an input / output (I / O) buffer 150. The data input signal SDAI may be generated according to the bidirectional signal SDA, or the bidirectional signal SDA may be obtained according to the data output signal SDOB.

[0058] The interface wrapper 110 further receives a mode selection signal I2C_MODE. If the mode selection signal I2C_MODE is at a valid logic level, then the interface wrapper 110 performs a conversion operation to convert the first signal SG1 to generate a second signal SG2 in SPI format. The valid logic level may be a logic high level or a logic low level. In this embodiment, the second signal SG2 includes a chip select signal spi_csb, a clock signal spi_sck, a data input signal spi_sdi, and a data output signal spi_sdo. The chip select signal spi_csb, the clock signal spi_sck, the data input signal spi_sdi, and the data output signal spi_sdo are all in SPI format.

[0059] On the other hand, if the mode selection signal I2C_MODE is at a non-valid logic level, then the first signal SG1 received by the interface wrapper 110 may be in SPI format, and the interface wrapper 110 may directly output the first signal SG1 as the second signal SG2.

[0060] When operating the conversion operation, the interface wrapper 110 can detect the slave address through the clock signal SCL and the data input signal SDAI. The interface wrapper 110 detects I according to the chip select signal CSB of the first signal SG1 2 C start condition and I 2 C stop condition to convert the chip select signal spi_csb of the second signal SG2 into a transition between two different logic levels. If I 2 C start condition is detected, then the interface wrapper 110 causes the chip select signal spi_csb to transition from a logic high level to a logic low level. If I 2 C stop condition is detected, then the interface wrapper 110 causes the chip select signal spi_csb to transition from a logic low level to a logic high level.

[0061] The interface wrapper 110 will be in I during the conversion operation 2 C format clock signal SCL is converted into a clock signal spi_sck in SPI format, and during the conversion operation, it will also be in I 2 C format data input signal SDAI is converted into a data input signal spi_sdi in SPI format. In one embodiment, the interface wrapper 110 can directly output the clock signal SCL and the data input signal SDAI to generate the clock signal spi_sck and the data input signal spi_sdi respectively.

[0062] During the data loading period of the conversion operation, the interface wrapper 110 converts the data output signal spi_sdo in SPI format into I 2 C format data output signal SDOB.

[0063] The interface wrapper 110 also identifies I according to the bidirectional signal SDA 2 C receive acknowledgment cycle and I 2 C transmit acknowledgment cycle. The interface wrapper 110 will 2 C receive acknowledgment cycle is converted into an SPI data read cycle, and the I 2 C transmit acknowledgment cycle is converted into an SPI data loading cycle.

[0064] The interface wrapper 110 can also detect I through the clock signal SCL and the data input signal SDAI 2 C test mode sequence, and when the I 2 C test mode sequence is detected, enable the SPI test mode. The interface wrapper 110 can generate a first command signal CMD1 to include the detected I 2 C test mode sequence, and the first command signal CMD1 can also include I with a read mode 2 C device select code, I with a write mode,2 C device selection code, I 2 C response and I 2 C mode selection signal.

[0065] The logic circuit 120 is coupled to the interface wrapper 110, the command decoder 130, and the MUX 130, receives the chip select signal spi_csb, the clock signal spi_sck, and the data input signal spi_sdi, and outputs the data output signal spi_sdo. In addition, the logic circuit 120 receives the decoded command DC1 from the command decoder 140. The logic circuit 120 can generate a second command signal CMD2 according to the second signal SG2 and the decoded command DC1. Among them, the decoded command DC1 can include multiple commands N_cmd, multiple addresses N_addr, multiple virtuals N_dummy, multiple data N_data, and a read or write mode signal RD / WT.

[0066] The logic circuit 120 further generates an access control signal CS1 according to the decoded command DC1. The access control signal CS1 includes a status signal SP_ST, an address signal SP_ADD, and a data signal SP_D, where the status signal SP_ST, the address signal SP_ADD, and the data signal SP_D are all in SPI format.

[0067] The access control signal CS1 can be provided to a device with SPI, and the access control signal CS1 can be used to communicate with the device. The device can be a memory circuit, which is placed on the same chip as the interface control circuit 100.

[0068] The MUX 130 receives the first command signal CMD1 and the second command CMD2. The MUX 130 generates a third command signal CMD3 according to the first command signal CMD1 and the second command signal CMD2, and further generates a logic state control signal LSC1 according to the first command signal CMD1. In this embodiment, the logic state control signal LSC1 includes one of a bypass command signal BP_cmd, a bypass address signal BP_addr, and a bypass data signal BP_data.

[0069] Regarding the detailed operation of the MUX 130, based on the first command signal CMD1, the MUX 130 can convert the I with a read mode 2 C device selection code into an SPI read command. The MUX 130 can also convert the I with a write mode 2 C device selection code into an SPI write command. On the other hand, the MUX 130 can generate a bypass command signal BP_cmd, a bypass address signal BP_addr, or a bypass data signal BP_data according to the first command signal CMD1. In the I for the first signal SG12 In the SPI logic of the C operation, the bypass command signal BP_cmd, the bypass address signal BP_addr, and the bypass data signal BP_data are used to skip one or more command cycles, one or more address cycles, and one or more data cycles.

[0070] The command decoder 140 receives the logic state control signal LSC1 and the third command signal CMD3, and generates a decoded command DC1 according to the logic state control signal LSC1 and the third command signal CMD3.

[0071] In this embodiment, the interface wrapper 110, the logic circuit 120, the MUX 130, and the command decoder 140 can all be constructed by logic circuit components. The logic circuit 120 can be a state machine with a counter.

[0072] Reference Figure 2A , which is a waveform diagram of the write operation of the interface control circuit according to an embodiment of the present disclosure. Please refer jointly to Figure 1 and Figure 2A , during the time interval TP1, the bidirectional signal SDA is set to an input signal and transmits the device selection code COD1 and the write code WC, where the device selection code COD1 can be the logical values 1, 0, 1, 0, X, X, X, and the write code WC is the logical value 0. The interface wrapper 110 receives the device selection code COD1 and the write code WC through the bidirectional signal SDA according to the clock signal SCL. After receiving the device selection code COD1, the interface wrapper 110 can detect the I 2 C start condition, and convert the chip select signal spi_csb from a logic high level to a logic low level. Subsequently, a low pulse on the I 2 C data output code i2C_sdo can be generated in response to the write code WC in the C mode. 2 In this way, an acknowledgment signal ACK with a logic low level can be generated on the bidirectional signal SDA.

[0073] Here, the interface wrapper 110 can identify the I 2 C transmission acknowledgment cycle according to the acknowledgment signal ACK, and convert the I 2 C transmission acknowledgment cycle into an SPI data loading cycle.

[0074] In addition, after receiving the write code WC with a logic low level, the I 2 C device selection code i2C_read can be pulled to a logic low level. The I 2 C device selection code i2C_read can be used to indicate whether the access operation of the I 2 C interface is set to the write mode or the read mode. In this embodiment, when the I 2When the C interface is set to the write mode, I 2 C device selection code i2C_read is at a logic low level, and when I 2 C interface is set to the read mode, I 2 C device selection code i2C_read is at a logic high level. I 2 C device selection code i2C_read can be included in the first command CMD1 as shown in Figure 1 . I 2 C device selection code i2C_read can be generated by interface wrapper 110 and transmitted to MUX 130.

[0075] During time interval TP2, interface wrapper 110 converts clock signal SCL into clock signal spi_sck. During time interval TP2, bidirectional signal SDA is also set to an input signal, and interface wrapper 110 can receive write data according to clock signal SCL and convert bidirectional signal SDA into data input signal spi_sdi. In this embodiment, during time interval TP2, the waveforms of clock signal SCL and clock signal spi_sck can be the same, and the waveforms of bidirectional signal SDA and data input signal spi_sdi can be the same.

[0076] Time interval TP2 can be executed one or more times depending on the number of write data. In this embodiment, write data with 8 bits can be written during one time interval TP2.

[0077] If the write operation has been completed, then I 2 C stop condition SP can be generated after time point TPE1. The interface wrapper can detect I 2 C stop condition SP and convert chip select signal spi_csb from a logic low level to a logic high level.

[0078] It should be noted here that in this embodiment, chip select signal spi_csb is a logic low enable signal. That is to say, if chip select signal spi_csb is at a logic low level, the operation of logic circuit 120 can be activated, and if chip select signal spi_csb is at a logic high level, the operation of logic circuit 120 can be stopped. In addition, in another embodiment, chip select signal spi_csb can also be defined as a high enable signal. Thus, when chip select signal spi_csb is at a logic high level, the operation of logic circuit 120 can be activated, and when chip select signal spi_csb is at a logic low level, the operation of logic circuit 120 can be stopped.

[0079] Refer to Figure 2B , which is a waveform graph of the read operation of the interface control circuit according to an embodiment of the present disclosure. Please refer to it togetherFigure 1 and Figure 2B During time interval TP3, the bidirectional signal SDA is set as an input signal and the device selection code COD2 and the read code RC are transmitted, where the device selection code COD2 can be the logical values 1, 0, 1, 0, X, X, X, and the read code RC is the logical value 1. The interface wrapper 110 receives the device selection code COD2 and the read code RC through the bidirectional signal SDA according to the clock signal SCL. After receiving the device selection code COD2, the interface wrapper 110 can detect the I 2 C start condition and convert the chip select signal spi_csb from a logical high level to a logical low level. Subsequently, the I 2 C data output code i2C_sdo can be pulled to a logical low level in response to the write code WC. Thus, an acknowledgment signal ACK with a logical low level can be generated on the bidirectional signal SDA. Here, since the read code RC is received, the I 2 C data output code i2C_sdo can be held at a logical low level.

[0080] Here, the interface wrapper 110 can identify the I 2 C receive acknowledgment cycle according to the acknowledgment signal ACK and convert the I 2 C receive acknowledgment cycle into an SPI data read cycle.

[0081] In addition, after receiving the read code RC with a logical high level, the I 2 C device selection code i2C_read can be held at a logical high level to indicate that the access operation of the I 2 C interface is set to the read mode.

[0082] During time interval TP4, the interface wrapper 110 converts the clock signal SCL into the clock signal spi_sck. During time interval TP4, the bidirectional signal SDA is also set as an output signal, and the interface wrapper 110 can receive the read data from the data input signal spi_sdo according to the clock signal spi_sck and convert the bidirectional signal SDA into the data output signal spi_sdo. In this embodiment, during time interval TP4, the waveforms of the clock signal SCL and the clock signal spi_sck can be the same, and the waveforms of the bidirectional signal SDA and the data output signal spi_sdo can be the same.

[0083] The time interval TP4 can be executed one or several times depending on the number of read data. In this embodiment, 8-bit read data can be read during one time interval TP4.

[0084] During the time interval TP5, a non-acknowledgment signal NACK with a logic high level is received from the bidirectional signal SDA. After the time point TPE2, an I 2 C stop condition SP can be detected. Accordingly, the interface wrapper converts the chip select signal spi_csb from a logic low level to a logic high level, thus completing the read operation.

[0085] Please refer to Figure 3 , which is a block diagram of an integrated circuit according to an embodiment of the present disclosure. The integrated circuit 300 includes an interface control circuit 310 and a non-volatile memory 320. The interface control circuit 310 is coupled to the non-volatile memory 320. The interface control circuit 310 can receive a first signal SG1. The first signal SG1 can be in SPI format or in I 2 C format. In this embodiment, the integrated circuit 300 also has a mode selection bit. The mode selection bit can be used to set a mode selection signal I2C_MODE, and the mode selection signal I2C_MODE can be used to set the operating mode of the interface control circuit 310. The mode selection bit can be provided by an electronic fuse or any other programmable non-volatile memory known to those skilled in the art. The mode selection bit can also be set through the I 2 C test mode to configure the integrated circuit 300 into SPI mode, and the speed of the test operation can be increased.

[0086] When the interface control circuit 310 receives the first signal SG1 in I 2 C format, the interface control circuit 310 can convert the first signal SG1 to generate an access control signal CS1 for accessing the non-volatile memory 320. The detailed operations have been described in the above embodiments and will not be repeated here.

[0087] In addition, the non-volatile memory 320 can be an electrically erasable programmable read-only memory (EEPROM), a flash memory, or any other non-volatile memory known to those skilled in the art.

[0088] In summary, the present disclosure provides an interface control circuit that can convert a signal in I 2 C format into SPI format. Thus, both SPI and I 2 C format signals can be used in the integrated circuit, and the I 2 C interface and SPI combined design in a single chip can be realized.

[0089] It will be apparent to those skilled in the art that various modifications and changes can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of the present invention provided that such modifications and variations are within the scope of the appended claims and their equivalents.

Claims

1. An interface control circuit, comprising: An interface wrapper that transmits and receives a plurality of first signals in a first interface, converts the first signals into a plurality of second signals in a second interface, and generates at least one first command signal based on the first signals; A logic circuit coupled to the interface wrapper and receiving the second signals, generating second command signals based on the second signals; A multiplexer coupled to the interface wrapper and the logic circuit, receiving the first command signals and the second command signals, and generating third command signals based on the first command signals and the second command signals; And A command decoder coupled to the multiplexer and the logic circuit, receiving the third command signals and generating decoded commands based on the third command signals, wherein the first interface is an integrated circuit interface and the second interface is a serial peripheral interface.

2. The interface control circuit according to claim 1, wherein the interface wrapper detects an integrated circuit start condition and an integrated circuit stop condition according to the first signal, so as to convert the chip select signal of the second signal into a transition between two different logic levels.

3. The interface control circuit according to claim 1, wherein the interface wrapper converts an integrated circuit receive acknowledge cycle into a serial peripheral interface data read cycle based on the first signal, and converts an integrated circuit transmit acknowledge cycle into a serial peripheral interface data load cycle.

4. The interface control circuit according to claim 1, wherein the interface wrapper enables a serial peripheral interface test mode by detecting an integrated circuit test mode sequence based on the first signal.

5. The interface control circuit according to claim 1, wherein the multiplexer generates a logic state control signal according to the first command signal, and the logic state control signal is one of a bypass command signal, a bypass address signal, and a bypass data signal.

6. The interface control circuit according to claim 5, wherein the command decoder is configured to: Generate a decoded command according to the bypass command signal to skip a command cycle in the serial peripheral interface logic operation; Generate a decoded command according to the bypass address signal to skip an address cycle in the serial peripheral interface logic operation; or Generate a decoded command according to the bypass data signal to skip a data cycle in the serial peripheral interface logic operation.

7. The interface control circuit according to claim 1, wherein the multiplexer converts an integrated circuit bus device select code with a read mode into a serial peripheral interface read command based on the first command signal.

8. The interface control circuit according to claim 1, wherein the multiplexer converts an integrated circuit bus device select code with a write mode into a serial peripheral interface write command based on the first command signal.

9. The interface control circuit according to claim 1, wherein the logic circuit is a finite state machine and further generates an access control signal according to the decoded command.

10. An integrated circuit, comprising: A non-volatile memory; And The interface control circuit according to claim 1, wherein the interface control circuit is coupled to the non-volatile memory and converts the first signals to generate a plurality of access control signals for accessing the non-volatile memory.

11. The integrated circuit according to claim 10, wherein the logic circuit is coupled to the non-volatile memory, and the logic circuit is a finite state machine and further generates an access control signal for accessing the non-volatile memory according to the decoded command.

12. The integrated circuit according to claim 10, further comprising a mode selection bit, wherein the mode selection bit is set through an integrated circuit bus test mode to configure the integrated circuit into a serial peripheral interface mode.

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