Semiconductor integrated circuit and its test method

Abstract

Embodiments of the present invention provide a semiconductor integrated circuit and a test method thereof that can reduce the cost of test steps. The semiconductor integrated circuit according to the embodiment includes a storage area, a selection area, a setting register, and a setting circuit. The storage area stores a plurality of setting conditions. The selection circuit selects a specific setting condition from the plurality of setting conditions and reads it out from the storage area. The setting register stores the specific setting condition read out from the storage area. The setting circuit sets the operation condition with reference to the specific setting condition stored in the setting register.

Description

[0001] [Related Application Cases]

[0002] This application claims priority based on Japanese Patent Application No. 2020-149574 (filing date: September 7, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor integrated circuit and a test method thereof. Background Art

[0004] When the requirement specifications of each user for a semiconductor integrated circuit are different, it is necessary to prepare the setting of the test steps before shipping the semiconductor integrated circuit according to the types of requirement specifications. Therefore, the cost of constructing and managing the test system used for the test steps increases. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor integrated circuit and a test method thereof that can reduce the cost of test steps.

[0006] The semiconductor integrated circuit according to the embodiment includes a storage area, a selection area, a setting register, and a setting circuit. The storage area stores a plurality of setting conditions. The selection circuit selects a specific setting condition from the plurality of setting conditions and reads it out from the storage area. The setting register stores the specific setting condition read out from the storage area. The setting circuit sets the operation condition with reference to the specific setting condition stored in the setting register. Brief Description of the Drawings

[0007] Figure 1 It is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the first embodiment.

[0008] Figure 2 It is a table showing an example of the correspondence between the signal level of the setting signal and the address of the storage area.

[0009] Figure 3 It is a graph showing an example of the setting signal input to the setting pin.

[0010] Figure 4 It is a flowchart for explaining the test method of the semiconductor integrated circuit according to the first embodiment.

[0011] Figure 5 It is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the second embodiment.

[0012] Figure 6 It is a table showing an example of the correspondence between the potential of the setting pad and the storage method.

[0013] Figure 7 It is a graph showing an example of setting the potential of a setting pad.

[0014] Figure 8 It is a schematic diagram showing an example of setting the signal level of a setting signal according to the potential of a setting pad.

[0015] Figure 9 It is a graph showing another example of setting the potential of a setting pad.

[0016] Figure 10 It is a schematic diagram showing another example of setting the signal level of a setting signal according to the potential of a setting pad. Detailed implementation mode

[0017] Hereinafter, the implementation mode will be described with reference to the accompanying drawings. In the description of the accompanying drawings, the same reference numerals are added to the same parts and the description is omitted.

[0018] (First implementation mode)

[0019] As Figure 1 shown, the semiconductor integrated circuit 10 of the first implementation mode of the present invention includes a storage area 100, a selection circuit 110, a voltage generation circuit 120, and a logic circuit 130. The logic circuit 130 includes a setting register 131 and a setting circuit 132.

[0020] The storage area 100 stores various setting conditions regarding the semiconductor integrated circuit 10. The selection circuit 110 selects a specific setting condition from the various setting conditions and reads out the selected setting condition from the storage area 100. The setting register 131 stores the specific setting condition read out from the storage area 100. The setting circuit 132 refers to the specific setting condition stored in the setting register 131 and sets the operation condition of the semiconductor integrated circuit 10. The semiconductor integrated circuit 10 operates according to the operation condition set by the setting circuit 132.

[0021] The operation specifications of the semiconductor integrated circuit 10 may be different for each user at the place where the semiconductor integrated circuit 10 is shipped. The storage area 100 stores, for example, various setting conditions corresponding to multiple specifications that the user may require. The setting register 131 stores the setting condition referred to for setting the operation condition of the semiconductor integrated circuit 10.

[0022] Figure 1The case where the semiconductor integrated circuit 10 of the first embodiment is a NAND (Not-AND) flash memory is shown. When the semiconductor integrated circuit 10 is a NAND flash memory, the setting conditions stored in the storage area 100 include, for example, at least any one of the voltages for the write operation, read operation, and erase operation of the NAND flash memory; or the conditions for setting the timing for executing these operations. Hereinafter, the write operation, read operation, and erase operation performed by the NAND flash memory are also collectively referred to as the "operations of the NAND flash memory".

[0023] The setting conditions stored in the storage area 100 may also include the storage method of the NAND flash memory, etc. For example, in the quadruple level cell (QLC) method where one memory cell can store 4-bit information and the triple level cell (TLC) method where one memory cell can store 3-bit information, the number of data bits written is different. Therefore, the operation settings of the NAND flash memory are different between the QLC method and the TLC method. Therefore, various setting conditions for setting the operations of the NAND flash memory that are most suitable for the adopted storage method may be stored in the storage area 100.

[0024] The NAND flash memory may also adopt the pseudo triple level cell (pTLC) method. The NAND flash memory of the pTLC method is a product of the QLC method, but has a product mode that can also simulate the operations of the TLC method.

[0025] Figure 1 The semiconductor integrated circuit 10 shown is a NAND flash memory having a first memory cell array 140A and a second memory cell array 140B. The storage area 100 is set in a part of the first memory cell array 140A.

[0026] The semiconductor integrated circuit 10 has a peripheral circuit 150A that controls the operation of the first memory cell array 140A and a peripheral circuit 150B that controls the operation of the second memory cell array 140B. The peripheral circuit 150A and the peripheral circuit 150B each include a row counter 151, a sense amplifier 152, an XDL 153, and a YLOG 154.

[0027] The row counter 151 controls the word line. The sense amplifier 152 controls the bit line. The XDL 153 temporarily stores the data written to the memory cell array or the data read from the memory cell array. The YLOG 154 controls the flow of data in the memory cell array during the write operation or read operation, etc.

[0028] The voltage generation circuit 120 generates a power supply voltage supplied to each circuit included in the semiconductor integrated circuit 10. The logic circuit 130 controls the peripheral circuit 150A, the peripheral circuit 150B, and the voltage generation circuit 120, and performs the operation of the NAND flash memory. Inside the semiconductor integrated circuit 10, signals are transmitted between circuits via the bus 160.

[0029] The semiconductor integrated circuit 10 is controlled by the controller 20. Data transmission and reception between the controller 20 and the semiconductor integrated circuit 10 or power supply to the semiconductor integrated circuit 10 are performed via the interface circuit 170 of the semiconductor integrated circuit 10. The memory system 1 including the semiconductor integrated circuit 10 and the controller 20 can be connected to a host machine (not shown). The memory system 1 is, for example, an SSD (Solid State Disk).

[0030] The controller 20 may include a circuit such as a system-on-a-chip (SoC). The controller 20 comprehensively controls the operation of the memory system 1. Each function of the controller 20 can be realized by the controller 20 executing firmware. Each function of the controller 20 can also be realized by using dedicated hardware within the controller 20.

[0031] The controller 20 controls the communication between the host machine and the semiconductor integrated circuit 10. The controller 20 controls the semiconductor integrated circuit 10 to receive an instruction from the host machine and perform a write operation or a read operation. For example, the controller 20 controls the semiconductor integrated circuit 10 to write data specified by a write instruction. In addition, the controller 20 transmits the data read from the address of the semiconductor integrated circuit 10 specified by a read instruction to the host machine. Alternatively, the controller 20 controls the semiconductor integrated circuit 10 to perform an erase operation for erasing the stored data.

[0032] The state of the semiconductor integrated circuit 10 is initialized using the setting conditions stored in the setting register 131, for example, at power-on reset (POR). The logic circuit 130 controls the operation of the semiconductor integrated circuit 10 at the time of POR.

[0033] At the time of POR, the logic circuit 130 reads information (skip flag information) of a storage area that cannot be used due to defects from a specific storage area of, for example, the NAND flash memory. In addition, the logic circuit 130 reads the operation conditions stored in the setting register 131. And, the logic circuit 130 sequentially sets specific setting parts of the internal circuits of the semiconductor integrated circuit 10 based on the operation conditions. Thus, the semiconductor integrated circuit 10 is initialized to a state for receiving signals from the controller 20.

[0034] As described above, when power-on reset (POR) occurs, the setting circuit 132 sets the operation conditions with reference to specific setting conditions stored in the setting register 131. Figure 1 An example is shown in which the setting register 131 is arranged inside the logic circuit 130. However, the setting register 131 can also be arranged at a position different from the logic circuit 130 inside the semiconductor integrated circuit 10.

[0035] Figure 1 The semiconductor integrated circuit 10 shown is provided with a first setting pin 201, a second setting pin 202, and a third setting pin 203 for inputting a setting signal for allowing the selection circuit 110 to select setting conditions. Hereinafter, the first setting pin 201, the second setting pin 202, and the third setting pin 203 are also collectively referred to as "setting pins 200".

[0036] The first setting signal S1 is input to the first setting pin 201, the second setting signal S2 is input to the second setting pin 202, and the third setting signal S3 is input to the third setting pin 203. Hereinafter, the first setting signal S1 to the third setting signal S3 are also collectively referred to as "setting signals S". For example, the setting signal S output from the controller 20 is input to the setting pins 200.

[0037] The setting signal S input to the setting pins 200 is input to the selection circuit 110. The selection circuit 110 selects the setting conditions stored in the setting register 131 according to the signal level of the setting signal S.

[0038] Figure 2 An example showing the correspondence between the signal level of the setting signal S and the addresses respectively storing various setting conditions in the storage area 100 is shown. Here, the signal level of the setting signal S is either a high level (H level) or a low level (L level). Figure 2 In this case, a signal of the H level is set to "1", and a signal of the L level is set to "0" (the same applies hereinafter).

[0039] For example, when the signal levels of the first setting signal S1 to the third setting signal S3 are all "0", the selection circuit 110 selectively reads out the setting conditions stored in the area specified by block "0" and word line (WL) "34" of the storage area 100 from the storage area 100. In this way, the signal level of the setting signal S is made to correspond to the address of the memory cell 100 storing specific setting conditions.

[0040] Figure 3 An example of the setting signal S input to the setting pins 200 is shown. As Figure 3As shown, in a state where the setting signal S is set on the setting pin 200, the signal level of the ready / busy (R / B) pin changes from the H level to the L level. During the period when the R / B pin is at the low level, the signal level of the setting signal S set on the setting pin 200 is input to the selection circuit 110.

[0041] Figure 3 In the example shown, the signal level of the first setting signal S1 is "0" (L level), the signal level of the second setting signal S2 is "1" (H level), and the signal level of the third setting signal S3 is "0" (L level). In this case, Figure 2 In the corresponding example shown, the selection circuit 110 selectively reads out the setting conditions stored in the area specified by block "0" and word line (WL) "8" of the storage area 100. The selection circuit 110 stores the read setting conditions in the setting register 131. After that, the R / B pin returns from the L level to the H level.

[0042] As described above, the semiconductor integrated circuit 10 stores different setting conditions in multiple areas of the storage area 100. When setting the operation conditions of the semiconductor integrated circuit 10, the setting circuit 132 reads out specific setting conditions corresponding to the setting of the setting pin 200 from the storage area 100. The setting circuit 132 stores the read setting conditions in the setting register 131. Thereby, the operation conditions of the semiconductor integrated circuit 10 are set.

[0043] In order to set the operation conditions of the semiconductor integrated circuit 10, as described above, the number of pins of the setting pin 200 is regarded as the number of bits. Therefore, according to the type of setting conditions stored in the storage area 100, the number of pins of the setting pin 200 is prepared. For example, when there are 3 setting pins 200, up to 1 setting condition can be selected from 8 setting conditions.

[0044] The setting of the operation conditions with reference to the setting conditions stored in the setting register 131 can also be performed, for example, in a test step (hereinafter referred to as "shipment test") before the shipment of the semiconductor integrated circuit 10 product. For example, the shipment test is performed on the semiconductor integrated circuit 10 in the wafer state or the semiconductor integrated circuit 10 in the state of being cut and mounted in a package.

[0045] In the shipment test, various inspections such as detection of initial product defects are performed. In addition, in the shipment test of the NAND flash memory, characteristics such as the setting value of the voltage when the NAND flash memory operates or the timing of execution of the operation are adjusted for each product. The characteristics adjusted by the shipment test are stored in a register or a specific temporary storage area for each product.

[0046] With respect to the semiconductor integrated circuit 10 of the first embodiment, the semiconductor integrated circuit of the comparative example in which the content of the register storing the setting conditions cannot be changed after the manufacturing process is completed has the following problem.

[0047] In the semiconductor integrated circuit of the comparative example, before the manufacturing process is completed, the register storing the setting conditions of the semiconductor integrated circuit is set according to the specifications required by the user. Therefore, when different specifications are required for each shipping location, it is necessary to prepare and use a shipping test according to the type of setting conditions set for each user. In addition, regarding the storage method of the NAND flash memory, it is also necessary to prepare a shipping test according to each specification such as the QLC method or the pTLC method. Therefore, the semiconductor integrated circuit of the comparative example has an increased cost for the construction and management of the test system for the shipping test.

[0048] In addition, in the case of the semiconductor integrated circuit of the comparative example, when shipping is performed by only changing the register settings or when the shipping destination is changed, it is necessary to perform the shipping test again and rewrite the register settings according to the specifications required by the shipping destination. As a result, the cost or time of the shipping test increases, and also affects the operation of equipment such as testers. In addition, in the semiconductor integrated circuit of the comparative example, when the shipping destination is changed or the storage method is changed after the shipping test is completed, it is sometimes necessary to entrust the user to perform multi-parameter loading (MPL). "MPL" is the action of reading the setting conditions of the registers written in the storage area of the NAND flash memory into the NAND flash memory before the product is shipped, and storing the settings in the registers.

[0049] On the other hand, the semiconductor integrated circuit 10 of the first embodiment stores all the setting conditions for each shipping destination in the storage area 100 at the time of implementing the shipping test. Furthermore, the semiconductor integrated circuit 10 selects a setting condition corresponding to the user's specification or the like from the plurality of setting conditions stored in the storage area 100 during the shipping test, and stores the selected setting condition in the setting register 131. Therefore, the shipping test prepared for the semiconductor integrated circuit 10 can be set to one type.

[0050] As a result, the cost of constructing and managing a test system can be reduced according to the semiconductor integrated circuit 10. Therefore, the semiconductor integrated circuit 10 does not need to implement MPL according to the user's desired specifications or the storage method of the NAND flash memory after the shipment test is completed.

[0051] As described above, the semiconductor integrated circuit 10 of the first embodiment has a storage area 100 that stores various setting conditions, and stores a specific setting condition read from the storage area 100 in the setting register 131. Therefore, according to the semiconductor integrated circuit 10, it is easy to switch the setting conditions stored in the setting register 131. For example, according to the semiconductor integrated circuit 10, it is possible to change the POR target page even after the shipment test is completed.

[0052] In addition, in the semiconductor integrated circuit 10, it is not necessary to prepare and operate a variety of shipment tests corresponding to the user's specifications. Therefore, it is possible to reduce the types of shipment tests prepared for the semiconductor integrated circuit 10 and make the shipment tests efficient.

[0053] Hereinafter, with reference to Figure 4 the flowchart, an example of the test method of the semiconductor integrated circuit 10 will be described. Hereinafter, the test method of the semiconductor integrated circuit 10 in a state where the semiconductor integrated circuit 10 and the controller 20 constitute the memory system 1 will be described. The semiconductor integrated circuit 10 is in a state of being mounted in a package.

[0054] In step S10, the controller 20 inputs a setting signal S having a specific signal level to the setting pin 200 of the semiconductor integrated circuit 10. The signal level of the setting signal S is set according to the specifications required by the semiconductor integrated circuit 10.

[0055] In step S20, the selection circuit 110 selects a specific setting condition stored in the area corresponding to the signal level of the setting signal S in the storage area 100 that stores various setting conditions. The selection circuit 110 refers to, for example, Figure 2 the correspondence between the signal level of the setting signal S shown and the address of the storage area 100, etc., and selects a specific setting condition.

[0056] In step S30, the semiconductor integrated circuit 10 executes POR. For example, the controller 20 sends an instruction to start POR to the semiconductor integrated circuit 10.

[0057] In step S40, the selection circuit 110 reads out the specific setting condition selected by the selection circuit 110 from the storage area 100. The selection circuit 110 stores the read specific setting condition in the setting register 131.

[0058] In step S50, the setting circuit 132 sets the operation conditions of the semiconductor integrated circuit 10 with reference to the specific setting conditions stored in the setting register 131.

[0059] In step S60, a test step is performed on the semiconductor integrated circuit 10 that operates according to the operation conditions set by the setting circuit 132. In the test step, various inspections such as initial defect detection of the semiconductor integrated circuit 10 are performed, or characteristics such as adjusting the set value of the voltage when the NAND flash memory operates or the timing of operation are performed for each product.

[0060] In the above, the case where the controller 20 sets the signal level of the setting signal S input to the setting pin 200 has been described. In the test of the semiconductor integrated circuit 10 in the wafer state, for example, a setting signal S with a specific signal level can also be input from the tester to the setting pin 200 via a probe in contact with the semiconductor integrated circuit 10.

[0061] (Second Embodiment)

[0062] As Figure 5 shown, the semiconductor integrated circuit 10a of the second embodiment has a setting pad 210. In the semiconductor integrated circuit 10a, the selection circuit 110 selects the setting conditions stored in the setting register 131 according to the potential of the setting pad 210. That is, Figure 5 the semiconductor integrated circuit 10a shown has a setting pad 210 instead of the setting pin 200, which is different from the semiconductor integrated circuit 10 shown in Figure 1 .

[0063] The setting pad 210 is set to a specific potential in order to select a specific setting condition stored in the setting register 131 from among various setting conditions stored in the storage area 100. For example, the setting pad 210 set to the H level can be connected to the power supply line VCC set to the positive potential. Alternatively, the setting pad 210 set to the L level can be connected to the ground line GND.

[0064] For example Figure 6 shown, when the potential Vs of the setting pad 210 is "0" (L level), the semiconductor integrated circuit 10a can also set the QLC mode as the storage mode of the NAND flash memory. Also, when the potential Vs of the setting pad 210 is "1" (H level), the semiconductor integrated circuit 10a can also set the pTLC mode as the storage mode of the NAND flash memory.

[0065] Figure 7 An example of setting the potential Vs of the setting pad 210 to the L level is shown. In the state where the potential Vs of the setting pad 210 is set, the signal level of the ready / busy pin (R / B pin) changes from the H level to the L level. During the period when the R / B is at the low level, a setting signal of "0" corresponding to the L level of the potential Vs of the setting pad 210 is input to the selection circuit 110.

[0066] At this time, for example Figure 8 As shown, the setting pad 210 can also be electrically connected to the ground wire GND. Thereby, the potential Vs of the setting pad 210 becomes the L level. The comparator 220 compares the potential Vs of the setting pad 210 with a preset reference potential, and determines whether the potential Vs of the setting pad 210 is the H level or the L level. The data of the determination result of the comparator 220 is sent to the encoder 230. The encoder 230 performs encoding (encoding) of the data sent from the comparator 220. When the potential Vs of the setting pad 210 is the L level, the encoder 230 sends "0" to the selection circuit 110 as a setting signal.

[0067] Figure 9 An example of setting the potential Vs of the setting pad 210 to the H level is shown. During the period when the R / B pin is at the low level, a setting signal of "1" corresponding to the H level of the potential Vs of the setting pad 210 is input to the selection circuit 110.

[0068] At this time, for example Figure 10 As shown, the setting pad 210 can also be electrically connected to the power supply line VCC. Thereby, the potential Vs of the setting pad 210 becomes the H level. The comparator 220 determines that the potential Vs of the setting pad 210 is the H level. Also, the encoder 230 sends "1" to the selection circuit 110 as a setting signal.

[0069] The electrical connection between the setting pad 210 and the power supply line or the like can also be achieved using bonding wires or the like. The connection using bonding wires can be implemented, for example, in the wire bonding step or the like during the assembly of mounting the semiconductor integrated circuit 10 on the package. That is, at the assembly stage of the semiconductor integrated circuit 10a, the type of the power supply line electrically connected to the setting pad 210 can also be allocated according to the specifications of the shipping destination.

[0070] As described above, in order to set the operation conditions of the semiconductor integrated circuit 10a, the potential of the setting pad 210 is regarded as a bit. In the above description, the case where there is one setting pad 210 has been described, but the number of setting pads 210 corresponding to the number of types of setting conditions stored in the storage area 100 can also be prepared.

[0071] For example, when three setting pads 210 are arranged in the semiconductor integrated circuit 10a, the potentials of the setting pads 210 are the H level, the H level, and the L level respectively. For the potential Vs of each setting pad 210, the comparator 220 determines the H level and the L level. Also, the encoder 230 sends the digital signal "110" to the selection circuit 110 as a setting signal.

[0072] In the semiconductor integrated circuit 10a of the second embodiment, for example, in the wire bonding step during packaging, the potential Vs of the setting pad 210 is set. Therefore, in the semiconductor integrated circuit 10a, no preparatory operations such as MPL are required during shipping tests or user use. Here, "preparatory operations" are operations such as changing the setting conditions stored in the setting register 131 of the semiconductor integrated circuit 10a using a controller 20 or the like. Therefore, according to the semiconductor integrated circuit 10a, the efficiency during shipping tests or user use is improved.

[0073] In addition, in the semiconductor integrated circuit 10a, for products after shipping tests are performed, for example, the storage mode of the NAND flash memory can be changed by setting the potential Vs of the setting pad 210 during packaging. Therefore, there is no need to perform shipping tests accompanying a change in the shipping location.

[0074] Furthermore, the semiconductor integrated circuit 10a of the second embodiment is substantially the same as the semiconductor integrated circuit 10 of the first embodiment, and repeated descriptions are omitted. For example, according to the semiconductor integrated circuit 10a, the test system for shipping test preparation can be made into one type, so the cost of constructing and managing the test system can be reduced.

[0075] In addition, Figure 5 Although an example in which the semiconductor integrated circuit 10a does not have a setting pin 200 is shown, the semiconductor integrated circuit 10a may also have both a setting pad 210 and a setting pin 200. For example, either the setting pad 210 or the setting pin 200 can be used to set the voltage during the operation of the NAND flash memory or the conditions for setting the operation timing. Also, the storage mode of the NAND flash memory can be set using the other of the setting pad 210 and the setting pin 200.

[0076] When both the setting pad 210 and the setting pin 200 are provided in the semiconductor integrated circuit 10a, after packaging in which the setting of the setting pad 210 has been determined, the operation conditions of the semiconductor integrated circuit 10a can be selected by setting the setting pin 200. For example, after selecting the storage mode of the NAND flash memory by setting the setting pad 210, the setting conditions desired by the setting register 131 can be stored by setting the setting pin 200.

[0077] (Other Embodiments)

[0078] In the above description, the setting pin 200 for inputting the setting signal S is set as a dedicated pin, but a dedicated pin may not be prepared for the setting pin 200. For example, a pin of the semiconductor integrated circuit 10 that is not used during POR can also be used as the setting pin 200.

[0079] In addition, in the above description, although the semiconductor integrated circuit 10 is described as a NAND flash memory, the semiconductor integrated circuit 10 may also be other types of memory devices. In addition, the semiconductor integrated circuit 10 may also be a device other than a memory device.

[0080] As mentioned above, although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other ways and various omissions, substitutions, and changes can be made without departing from the gist of the invention. The embodiments and their variations are included in the scope and gist of the invention and are included in the invention described in the claims and its equivalents.

[0081] [Description of Symbols]

[0082] 1 Memory system

[0083] 10 Semiconductor integrated circuit

[0084] 20 Controller

[0085] 100 Storage area

[0086] 110 Selection circuit

[0087] 130 Logic circuit

[0088] 131 Setting register

[0089] 132 Setting circuit

[0090] 140A First memory cell array

[0091] 140B Second memory cell array

[0092] 201 First setting pin

[0093] 202 Second setting pin

[0094] 203 Third setting pin

[0095] 210 Setting pin.

Claims

1. A semiconductor integrated circuit, comprising: A setting pad; A storage area for storing a plurality of setting conditions; A selection circuit that selects a specific setting condition from the plurality of setting conditions according to the potential of the setting pad, and reads out the specific setting condition from the storage area; A setting register for storing the specific setting condition read out from the storage area; A setting circuit that sets an operating condition with reference to the specific setting condition stored in the setting register; A comparator that compares the potential of the setting pad with a reference potential to determine the potential of the setting pad; And An encoder that encodes data based on the result determined by the comparator; And The selection circuit selects the specific setting condition from the plurality of setting conditions corresponding to the result according to the potential of the setting pad; The setting pad does not include a pin. When the potential of the setting pad is set to a first potential, it is connected to a first line, and when the potential of the setting pad is set to a second potential different from the first potential, it is connected to a second line different from the first line.

2. The semiconductor integrated circuit according to claim 1, wherein the setting circuit sets the operating condition with reference to the specific setting condition stored in the setting register at power-on reset.

3. The semiconductor integrated circuit according to claim 1, wherein the setting pad is connected to a power supply line of the semiconductor integrated circuit.

4. The semiconductor integrated circuit according to claim 1, wherein the storage area is set in a part of a memory cell array of a NAND flash memory.

5. The semiconductor integrated circuit according to claim 4, wherein the setting condition includes at least one of conditions of voltages for respective write operations, read operations, and erase operations of the NAND flash memory; and conditions for setting timings of executing the write operation, the read operation, and the erase operation.

6. The semiconductor integrated circuit according to claim 4, wherein the setting condition includes a condition for setting an operation most suitable for a storage mode of the NAND flash memory.

7. The semiconductor integrated circuit according to claim 1, wherein The first potential is higher than the second potential; The first line is a power supply line; The second line is a ground line.

8. The semiconductor integrated circuit according to claim 1, wherein the selection circuit inputs data corresponding to the potential of the setting pad during a period when the signal is at the second potential.

9. A method for testing a semiconductor integrated circuit, comprising: Setting the potential of a setting pad included in the semiconductor integrated circuit; Selecting a specific setting condition from a storage area storing a plurality of setting conditions according to the potential of the setting pad; Reading out the selected specific setting condition from the storage area and storing it in a setting register; Setting an operating condition of the semiconductor integrated circuit with reference to the specific setting condition stored in the setting register; Comparing the potential of the setting pad with a reference potential; and Encode data based on the result of comparing the potential of the set pad with the reference potential; and In the storage area storing the multiple sets of conditions, the specific set of conditions is selected according to the potential of the set pad by the encoded data; The set pad does not include pins. When the potential of the set pad is set to the first potential, it is connected to the first line. When the potential of the set pad is set to the second potential different from the first potential, it is connected to the second line different from the first line.

10. The test method of the semiconductor integrated circuit according to claim 9, wherein when power is turned on and reset, the operating conditions are set with reference to the specific set of conditions stored in the set register.

11. The test method of the semiconductor integrated circuit according to claim 9, wherein a test step is performed on the semiconductor integrated circuit operating according to the set operating conditions.

12. The test method of the semiconductor integrated circuit according to claim 11, wherein the test step is performed on the semiconductor integrated circuit in the wafer state or the semiconductor integrated circuit mounted in the package.

13. The test method of the semiconductor integrated circuit according to claim 9, wherein the set pad: is connected to the power supply line of the semiconductor integrated circuit when set to the first potential, and is connected to the ground line of the semiconductor integrated circuit when set to the second potential.

14. The test method of the semiconductor integrated circuit according to claim 9, wherein the storage area is set in a part of the memory cell array of the NAND flash memory.

15. The test method of the semiconductor integrated circuit according to claim 14, wherein the set conditions include at least any one of the conditions of the voltages of the write operation, read operation, and erase operation of the NAND flash memory; and the conditions for setting the timing of executing the write operation, read operation, and erase operation.

16. The test method of the semiconductor integrated circuit according to claim 14, wherein the set conditions include the conditions for setting the operation most suitable for the storage mode of the NAND flash memory.

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