A method for preparing a floating gate split-gate flash memory device and the device

Abstract

The present invention provides a method for preparing a floating-gate split-gate flash memory device, comprising: providing a substrate; forming a select gate structure on the substrate at a position corresponding to a P-type well region; and forming a first control gate structure above the select gate structure; forming symmetrical "L"-shaped floating gate structures with outward depressions on both sides of the select gate structure and the first control gate structure; forming second control gate structures at the depressions of the floating gate structures; and forming sidewall structures at the bottoms of the second control gate structure and the floating gate structure, facing one side of the first control gate structure. The beneficial effect of the technical solution of the present invention is that the inner and outer first control gate structures and the second control gate structures form overlapping surfaces on the three most important surfaces of the "L"-shaped floating gate structure, thereby greatly improving the coupling coefficient between the first control gate structure and the second control gate structure and the floating gate structure, while simultaneously reducing the coupling coefficient between the select gate structure and the floating gate structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a preparation method and device of a floating gate split-gate flash memory device. Background Art

[0002] Floating-gate split-gate flash memory devices have two floating gates, allowing them to store two bits of data in a single device. A select gate selects the floating gate currently being read or written. This device structure can reduce the number of devices in a memory array and increase storage density.

[0003] Through the experiment of size change of floating gate split gate flash memory device in the prior art, such as Figure 1 and Figure 2 As shown in FIG, due to the reduction in the overlapping area between the control gate 115 and the floating gate 113, the coupling coefficient from the control gate 115 to the floating gate 113 is greatly reduced, while the coupling coefficient from the select gate 118 to the floating gate 113 is rapidly increased from the original 13.7% to 24.6%. The rapid increase in the coupling coefficient of the select gate 118 causes the turn-off capability of the control gate 115 of the device to deteriorate, and the leakage is very serious, as shown in FIG. Figure 3 As shown in the graph, the relationship between the current on the bit line and the voltage on the control gate 115 shows that the subthreshold swing reaches 800mV / decade. Therefore, increasing the overlap area between the control gate 115 and the floating gate 113 and reducing the coupling coefficient of the select gate 118 are crucial for further scaling of floating gate split-gate flash memory devices. Summary of the Invention

[0004] In order to solve the above problems in the prior art, a method for manufacturing a floating gate split-gate flash memory device and a device are provided. The specific technical solution is as follows:

[0005] A method for preparing a floating gate split-gate flash memory device, characterized in that it comprises the following steps:

[0006] Step S1, providing a substrate, wherein a P-type well region separated by a shallow trench isolation structure is provided on the top of the substrate;

[0007] Step S2, forming a select gate structure at a position corresponding to the P-type well region on the substrate, and forming a first control gate structure above the select gate structure;

[0008] Step S3, forming symmetrical “L”-shaped outward-recessed floating gate structures on both sides of the select gate structure and the first control gate structure;

[0009] Step S4, forming a second control gate structure at the recessed positions of the floating gate structure;

[0010] In step S5 , a spacer structure is formed on the bottom of the second control gate structure and the floating gate structure, respectively, on a side facing away from the first control gate structure.

[0011] Preferably, the step S2 includes:

[0012] Step S21, forming a select gate dielectric layer on the upper surface of the substrate;

[0013] Step S22, forming a select gate polysilicon layer on the upper surface of the select gate dielectric layer;

[0014] Step S23, forming a first oxide layer, a first nitride layer, an etch stop layer and a second nitride layer in sequence on the upper surface of the select gate polysilicon layer;

[0015] Step S24, etching the second nitride layer and the etch stop layer to form a groove corresponding to the position of the first control gate structure and exposing the first nitride layer;

[0016] Step S25, forming a second oxide layer on the surface of the second nitride layer, the wall and the bottom of the groove, and filling the groove to form a first control gate polysilicon layer;

[0017] Step S26, etching the first control gate polysilicon layer to remove the first control gate polysilicon layer on the surface of the second nitride layer, and making the height of the first control gate polysilicon layer in the groove lower than the notch of the groove, and forming inner sidewall structures respectively attached to the inner walls on both sides of the groove;

[0018] Step S27, filling the groove opening with an isolation dielectric layer, and polishing the isolation dielectric layer to remove the second oxide layer on the upper surface of the second nitride layer;

[0019] Step S28, etching and removing the second nitride layer, the etch stop layer, the first nitride layer, the first oxide layer, the select gate polysilicon layer, the select gate dielectric layer, retaining the second oxide layer on the groove wall and the bottom of the groove, and retaining the select gate dielectric layer, the select gate polysilicon layer, the first oxide layer, and the first nitride layer between the second oxide layer at the bottom of the groove and the upper surface of the substrate.

[0020] Preferably, the step S3 includes:

[0021] Step S31, forming a floating gate dielectric layer on the upper surface of the substrate, on both sides of the select gate structure, on both sides of the first control gate structure and on the upper surface;

[0022] Step S32, forming a floating gate polysilicon layer on the upper surface of the floating gate dielectric layer;

[0023] Step S33, trimming the morphology of the floating gate polysilicon layer so that the floating gate polysilicon layer forms an outwardly recessed "L"-shaped structure on the upper surface of the substrate, on both sides of the select gate structure, and on both sides of the first control gate structure, and removing the floating gate polysilicon layer above the shallow trench isolation structure in the width direction to divide the floating gate polysilicon layer into independent blocks;

[0024] Step S34 , forming a composite dielectric layer on the upper surface of the floating gate polysilicon layer and the upper surface of the floating gate dielectric layer on the exposed upper surface of the shallow trench isolation structure.

[0025] Preferably, in step S33, the floating gate polysilicon layer forms an outwardly recessed "L"-shaped structure on the upper surface of the substrate, on both sides of the selection gate structure, and on both sides of the first control gate structure, and the floating gate polysilicon layer is divided into independent blocks in the width direction through selective photolithography and etching.

[0026] Preferably, in step S34, the composite dielectric layer includes:

[0027] a bottom oxide layer;

[0028] an intermediate nitride layer covering the bottom oxide layer;

[0029] A top oxide layer covers the middle nitride layer.

[0030] Preferably, the step S4 includes:

[0031] Step S41, forming a second control gate polysilicon layer on the upper surface of the composite dielectric layer;

[0032] Step S42: etching the second control gate polysilicon layer, the composite dielectric layer, the floating gate polysilicon layer, the dielectric isolation layer, the second oxide layer, and the floating gate dielectric layer to form the floating gate structure and the second control gate structure, removing the composite structure dielectric layer on top of the floating gate structure and the first control gate structure, and thinning the floating gate dielectric layer on the substrate surface and the second oxide layer and the isolation dielectric layer on top of the first control gate.

[0033] In step S43 , source and drain regions are defined on the substrate, and the source and drain regions are lightly doped.

[0034] Preferably, after step S42 is performed, the heights of the top of the first control gate structure, the top of the floating gate structure, and the top of the second control gate structure gradually decrease from the middle to both sides.

[0035] Preferably, the step S5 includes:

[0036] Step S51, forming a first spacer on the exposed side surfaces of the second control gate polysilicon layer and the floating gate polysilicon layer, respectively, wherein the first spacer also covers the exposed side surface of the composite structure dielectric layer between the second control gate structure and the floating gate structure;

[0037] Step S52, forming a second spacer material layer on the exposed floating gate dielectric layer, the first spacer, the top of the composite structure dielectric layer, the floating gate polysilicon layer, the second oxide layer, and the isolation dielectric layer;

[0038] Step S53, etching the second spacer material layer and the floating gate dielectric layer to expose the heavily doped regions of the source and drain regions;

[0039] Step S54, performing ion implantation into the heavily doped region using the remaining second spacer material layer as a mask to form the source and drain regions;

[0040] In step S55, the remaining second sidewall material layer is etched to expose the floating gate polysilicon layer, the second oxide layer, the floating gate dielectric layer, and the top of the composite structure dielectric layer to form an outwardly recessed "L"-shaped second sidewall outside the first sidewall.

[0041] Also included is a structure of a floating gate split-gate flash memory device, which includes:

[0042] A substrate having a P-type well region separated by a shallow trench isolation structure provided on the top of the substrate;

[0043] a select gate structure, disposed on the substrate at a position corresponding to the P-type well region;

[0044] A first control gate structure is provided above the select gate structure

[0045] a pair of mirror-symmetrical L-shaped floating gate structures with outward depressions, respectively disposed on both sides of the select gate structure and the first control gate structure;

[0046] a pair of second control gate structures, respectively disposed at recessed positions of the floating gate structure;

[0047] The sidewall structure is arranged on a side of the second control gate structure facing away from the first control gate structure.

[0048] Preferably, the select gate structure includes:

[0049] a select gate dielectric layer, disposed on the upper surface of the substrate;

[0050] A select gate polysilicon layer is disposed on the upper surface of the select gate dielectric layer.

[0051] Preferably, the first control gate structure includes

[0052] A first composite structure dielectric layer is disposed on the upper surface of the select gate structure;

[0053] a first control gate polysilicon layer, disposed on the upper surface of the first composite structure dielectric layer;

[0054] An oxide layer is provided on both sides of the first control gate polysilicon layer, completely covering the sidewalls of the first control gate polysilicon layer. The sum of the width of the first control gate polysilicon layer and the thickness of the two oxide layers is equal to the width of the select gate structure. The height of the first control gate polysilicon layer is lower than the height of the oxide layer, and the first control gate polysilicon layer forms an inner sidewall structure respectively attached to the oxide layers on both sides.

[0055] An isolation dielectric layer is disposed on top of the first control gate polysilicon layer and fills the gap of the inner sidewall structure, and the upper surface of the isolation dielectric layer is flush with the top of the oxide layer.

[0056] Preferably, the first composite medium layer comprises:

[0057] a bottom oxide layer;

[0058] an intermediate nitride layer covering the bottom oxide layer;

[0059] A top oxide layer covers the middle nitride layer.

[0060] Preferably, the floating gate structure includes:

[0061] a floating gate dielectric layer covering both side walls of the select gate structure, both side walls of the first control gate structure, and the lightly doped regions on the upper surface of the substrate corresponding to the source and drain regions;

[0062] a floating gate polysilicon layer covering the surface of the floating gate dielectric layer except for the area above the shallow trench isolation structure, and forming a mirror-symmetrical "L" shape that is recessed outward and is divided into independent blocks in the width direction;

[0063] Part of the floating gate dielectric layer extends out from the floating gate polysilicon layer on both sides, and a thickness of the floating gate dielectric layer extending out from the floating gate polysilicon layer is lower than that of the floating gate dielectric layer below the floating gate polysilicon layer.

[0064] Preferably, the second control gate structure includes:

[0065] a second composite dielectric layer disposed on the inner wall surface of the recess of the L-shaped floating gate polysilicon layer and the upper surface of the gate dielectric layer above the shallow trench isolation structure;

[0066] A second control gate polysilicon layer is disposed on the second composite structure dielectric layer.

[0067] Preferably, the side wall structure includes:

[0068] a first spacer covering side surfaces of the floating gate structure and the second control gate structure;

[0069] A second sidewall spacer covers a lower half of the second sidewall spacer and an upper surface of the floating gate dielectric layer extending out of the floating gate polysilicon layer.

[0070] The beneficial effect of the technical solution of the present invention is that the first control gate structure and the second control gate structure on the inner and outer sides form overlapping surfaces on the three most important surfaces of the "L"-shaped floating gate structure, thereby greatly improving the coupling coefficient of the first control gate structure and the second control gate structure to the floating gate structure, while reducing the coupling coefficient of the selection gate structure to the floating gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The embodiments of the present invention will be described more fully with reference to the accompanying drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0072] Figure 1 It is a structural diagram of a floating gate split-gate flash memory device in the prior art;

[0073] Figure 2 A diagram showing the relationship between word line and bit line voltage and device size of a floating gate split-gate flash memory device in the prior art;

[0074] Figure 3 A diagram showing the relationship between the bit line current and the control gate voltage of a floating gate split-gate flash memory device in the prior art;

[0075] Figure 4 A flowchart of an embodiment of a method for preparing a floating gate split-gate flash memory device of the present invention;

[0076] Figure 5 FIG4 is a flowchart of step S2 of an embodiment of a method for preparing a floating gate split-gate flash memory device of the present invention;

[0077] Figure 6 FIG3 is a flowchart of step S3 of an embodiment of a method for preparing a floating gate split-gate flash memory device of the present invention;

[0078] Figure 7 FIG4 is a flowchart of step S4 of an embodiment of a method for preparing a floating gate split-gate flash memory device of the present invention;

[0079] Figure 8 FIG4 is a flowchart of step S5 of an embodiment of a method for preparing a floating gate split-gate flash memory device of the present invention;

[0080] Figures 9-19A schematic diagram of structural state changes of an embodiment of a method for preparing a floating gate split-gate flash memory device of the present invention;

[0081] Figure 20 Schematic diagram of the structure of the active area in the width direction of an embodiment of a floating gate split-gate flash memory device of the present invention;

[0082] Figure 21 The figure is a schematic structural diagram of a cross section of a shallow trench isolation structure portion in the width direction of an embodiment of a floating gate split-gate flash memory device of the present invention. DETAILED DESCRIPTION

[0083] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0084] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0085] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0086] like Figure 4 , Figure 20 As shown, the technical solution of the present invention includes a method for preparing a floating gate split-gate flash memory device, which includes the following steps:

[0087] Step S1, providing a substrate, with a P-type well region 101 disposed on top of the substrate and separated by a shallow trench isolation structure in the device width direction;

[0088] Step S2, forming a select gate structure at a position corresponding to the P-type well region on the substrate, and forming a first control gate structure above the select gate structure;

[0089] Step S3, forming symmetrical “L”-shaped outward-recessed floating gate structures on both sides of the select gate structure and the first control gate structure;

[0090] Step S4, forming a second control gate structure at the recessed positions of the floating gate structure;

[0091] In step S5 , a spacer structure is formed at the bottom of the second control gate structure and the floating gate structure, respectively, on a side facing away from the first control gate structure.

[0092] In the above technical solution, an L-shaped floating gate structure is used to achieve both inner and outer lateral coupling and outer longitudinal coupling with the first and second control gate structures. The inner first control gate structure and the outer second control gate structure are laterally coupled along the long sides of the L-shaped floating gate structure. Furthermore, the outer second control gate structure is laterally coupled along the long sides of the L-shaped floating gate structure while being longitudinally coupled along the short sides of the L-shaped floating gate structure. The inner and outer first and second control gate structures overlap on the three most important surfaces of the L-shaped floating gate structure, significantly increasing the coupling coefficients between the first and second control gate structures and the floating gate structure while reducing the coupling coefficient between the select gate structure and the floating gate structure. Furthermore, the overlap between the inner and outer first and second control gate structures and the floating gate structure significantly increases the coupling area, thereby facilitating a reduction in the device control gate height and improving compatibility with advanced CMOS (Complementary Metal Oxide Semiconductor) devices without affecting the control gate-floating gate coupling effect.

[0093] Based on the above technical solution, it is further preferred that the P-type well region 101 can be a medium-high voltage P-type well region.

[0094] Based on the above technical solution, preferably, Figure 5 As shown, step S2 includes,

[0095] Step S21, forming a select gate dielectric layer 102 on the upper surface of the substrate;

[0096] Step S22 , forming a select gate polysilicon layer 103 on the upper surface of the select gate dielectric layer 102 ;

[0097] Step S23 , forming a first oxide layer 104 - 1 , a first nitride layer 104 - 2 , an etch stop layer 501 and a second nitride layer 502 in sequence on the upper surface of the select gate polysilicon layer 103 ;

[0098] Step S24, etching the second nitride layer 502 and the etch stop layer 501 to form a groove corresponding to the first control gate structure position and exposing the first nitride layer 104-2;

[0099] Step S25, combining Figure 9 As shown, a second oxide layer 104-3 is formed on the surface 502 of the second nitride layer, the wall and bottom of the groove, and a first control gate polysilicon layer 105-1 is formed in the groove.

[0100] Step S26, etching the first control gate polysilicon layer 105-1 to remove the first control gate polysilicon layer 105-1 on the surface of the second nitride layer 502, and making the height of the first control gate polysilicon layer 105-1 in the groove lower than the notch of the groove, and forming inner sidewall structures respectively attached to the inner walls on both sides of the groove; preferably, the first control gate polysilicon layer 105-1 can be formed in the groove by filling polysilicon and anisotropically etching back;

[0101] Step S27, combining Figure 10 As shown, an isolation dielectric layer 106 is filled in the groove opening, and the isolation dielectric layer 106 is polished to remove the second oxide layer 104-3 on the upper surface of the second nitride layer 502, so that the upper surface of the isolation dielectric layer 106 is flush with the upper surface of the second nitride layer 502;

[0102] Step S28, combining Figure 11 As shown, the second nitride layer 502 on the upper surface of the substrate, the etch stop layer 501, the first nitride layer 104-2, the first oxide layer 104-1, the select gate polysilicon layer 103, the select gate dielectric layer 102 are etched away, and the second oxide layer 104-3 at the groove wall and the groove bottom is retained, as well as the select gate dielectric layer 102, the select gate polysilicon layer 103, the first oxide layer 104-1, and the first nitride layer 104-2 between the second oxide layer 104-3 at the groove bottom and the upper surface of the substrate are retained.

[0103] Based on the above technical solution, further preferably, the thickness of the select gate polycrystalline layer 103 may be less than 500 angstroms.

[0104] Based on the above technical solution, preferably, the second oxide layer 104 - 3 and the isolation dielectric layer 106 can be used as etching mask layers to remove the second nitride layer 502 by wet etching.

[0105] More preferably, after the second nitride layer 502 is removed, the second oxide layer 104-3 and the isolation dielectric layer 106 may be used as masks to sequentially etch the etch stop layer 501, the first nitride layer 104-2, the first oxide layer 104-1 and the select gate polysilicon layer 103 in a self-aligned manner.

[0106] On this basis, further preferably, a thermal oxidation layer 503 may be formed on the side of the remaining select gate polysilicon layer 103 through a thermal oxidation process, and then the select gate dielectric layer 102 may be etched away.

[0107] Based on the above technical solution, it is further preferred that in step S27, the second nitride layer 502 can be used as a grinding stop layer to remove the second oxide layer 104-3 on the surface of the second nitride layer 502 through chemical mechanical grinding, and make the upper surface of the isolation dielectric layer 106 flush with the upper surface of the second nitride layer 502.

[0108] Based on the above technical solution, preferably, Figure 6 、 Figure 12 、 Figure 13 As shown, step S3 includes,

[0109] Step S31 , forming a floating gate dielectric layer 107 on the upper surface of the substrate, on both sides of the selected gate structure, both sides of the first control gate structure and the upper surface;

[0110] Step S32, forming a floating gate polysilicon layer 108 on the upper surface of the floating gate dielectric layer 107;

[0111] In step S33, the morphology of the floating gate polysilicon layer 108 is trimmed so that the floating gate polysilicon layer 108 forms an outwardly recessed "L"-shaped structure on both sides of the select gate structure and the first control gate structure on the upper surface of the substrate. The floating gate polysilicon layer 108 above the shallow trench isolation structure 504 is removed in the width direction of the device to divide the floating gate polysilicon layer 108 into independent blocks. Figure 13 A cross-sectional view showing the morphology of the floating gate polysilicon layer 108 removed above the shallow trench isolation structure 504;

[0112] In step S34 , a composite dielectric layer is formed on the upper surface of the floating gate polysilicon layer 108 and the upper surface of the floating gate dielectric layer 107 on the upper surface of the exposed shallow trench isolation structure 504 .

[0113] Based on the above technical solution, it is further preferred that in step S33, the floating gate polysilicon layer 108 is formed on the upper surface of the substrate, on both sides of the selection gate structure and on both sides of the first control gate structure to form an "L"-shaped structure that is recessed outward, and the floating gate polysilicon layer 108 can be divided into independent blocks in the width direction of the device by selective photolithography and etching.

[0114] Based on the above technical solution, it is further preferred that in step S34, the composite medium layer may include:

[0115] a bottom oxide layer 1104-1;

[0116] an intermediate nitride layer 1104-2 covering the bottom oxide layer;

[0117] A top oxide layer 1104-3 covers the middle nitride layer.

[0118] The composite dielectric layer forms an ONO (oxide layer-nitride layer-oxide layer) structure.

[0119] Based on the above technical solution, preferably, Figure 7 、 Figure 14 、 Figure 15 、 Figure 16 As shown, Figure 15Showing a cross-sectional view of the shallow trench isolation structure, step S4 includes,

[0120] Step S41, forming a second control gate polysilicon layer 105-2 on the upper surface of the composite dielectric layer;

[0121] Step S42: etching the second control gate polysilicon layer 105-2, the composite dielectric layer, the floating gate polysilicon layer 108, the dielectric isolation layer 106, the second oxide layer 104-3, and the floating gate dielectric layer 107 to form a floating gate structure and a second control gate structure. The composite dielectric layer on top of the floating gate structure and the first control gate structure is removed, and the floating gate dielectric layer 107 exposed on the substrate surface and the second oxide layer 104-3 and the isolation dielectric layer 106 on top of the first control gate structure are thinned.

[0122] In step S43 , source and drain regions 109 are defined on the substrate and lightly doped.

[0123] Based on the above technical solution, preferably, in step S42, the second control gate polysilicon layer 105-2 can be etched using an anisotropic etching process to form the second control gate polysilicon layer 105-2 of the outer wall structure. Furthermore, the composite structure dielectric layer between the second control gate polysilicon layer 105-2 and the floating gate polysilicon layer 108 can be etched using an anisotropic etching process. When the composite structure dielectric layer is etched, a portion of the isolation dielectric layer 106 and the floating gate dielectric layer 107 are also etched away. Furthermore, when the floating gate polysilicon layer 108 is etched using an anisotropic etching process, a portion of the second control gate polysilicon layer 105-2 is also etched away.

[0124] Based on the above technical solution, it is further preferred that after step S42 is executed, the heights of the top of the first control gate structure, the top of the floating gate structure and the top of the second control gate structure gradually decrease from the middle to both sides.

[0125] Based on the above technical solution, it is further preferred that the height of the control gate polysilicon layer 1105 can be greater than 1000 angstroms.

[0126] In a preferred embodiment, when the thickness of the select gate polysilicon layer 103 is less than 500 angstroms and the thickness of the control gate polysilicon layer 1105 is greater than 1000 angstroms, the coupling coefficient between the select gate structure and the floating gate structure can be effectively reduced while increasing the coupling coefficient between the control gate structure and the floating gate structure, thereby improving the turn-off capability of the control gate structure.

[0127] Based on the above technical solution, preferably, Figure 8 、 Figure 17 、 Figure 18 、 Figure 19 As shown, Figure 17 、 Figure 19 Showing a cross-sectional view of the shallow trench isolation structure, step S5 includes,

[0128] Step S51: forming a first spacer 110-1 on the exposed sides of the second control gate polysilicon layer 105-2 and the floating gate polysilicon layer 108. The first spacer 110-1 also covers the exposed side of the composite structure dielectric layer between the second control gate structure and the floating gate structure. Preferably, the first spacer 110-1 may be an oxide layer.

[0129] Step S52, forming a second spacer material layer on the exposed floating gate dielectric layer 107, the first spacer 110-1, the top of the composite structure dielectric layer, the floating gate polysilicon layer 108, the second oxide layer 104-3, and the isolation dielectric layer 106; preferably, the second spacer material layer can be a nitride layer;

[0130] Step S53 , etching the second spacer material layer and the floating gate dielectric layer 107 to expose the heavily doped region 111 of the source and drain regions;

[0131] Step S54 , using the remaining second spacer material layer as a mask, ion implantation is performed on the heavily doped region to form source and drain regions 109 ;

[0132] In step S55, the remaining second spacer material layer is etched to expose the floating gate polysilicon layer 108, the second oxide layer 104-3, the floating gate dielectric layer 107, and the top of the composite structure dielectric layer to form an outwardly recessed "L"-shaped second spacer 110-2 outside the first spacer 110-1.

[0133] In the above technical solution, the second control gate structure and the floating gate structure are both sidewall-type polysilicon, which can achieve self-aligned etching of the second control gate structure and the floating gate structure, which is conducive to reducing the size of the device.

[0134] The technical solution of the present invention also includes a structure of a floating gate split gate flash memory device, such as Figure 20 、 Figure 21 As shown, Figure 21 Shows a cross-sectional view of a shallow trench isolation structure, including:

[0135] A substrate, with a P-type well region 101 separated by a shallow trench isolation structure provided on the top of the substrate;

[0136] a select gate structure, disposed on the substrate at a position corresponding to the P-type well region 101;

[0137] A first control gate structure is disposed above the select gate structure

[0138] like Figure 20 As shown, a pair of mirror-symmetrical "L"-shaped floating gate structures with outward depressions are respectively arranged on both sides of the select gate structure and the first control gate structure. Figure 21 The shallow trench isolation structure shown does not have an "L"-shaped floating gate structure;

[0139] like Figure 20 As shown, a pair of second control gate structures are respectively arranged at the recessed positions of the floating gate structure. Figure 21 In the embodiment, a pair of second control gate structures are respectively disposed on the floating gate dielectric layer 107 above the shallow trench isolation structure 504;

[0140] The sidewall structure is arranged on a side of the second control gate structure facing away from the first control gate structure.

[0141] In the above technical solution, an L-shaped floating gate structure is used to achieve both inner and outer lateral coupling and outer longitudinal coupling with the first and second control gate structures. The inner first control gate structure and the outer second control gate structure are laterally coupled along the long sides of the L-shaped floating gate structure. Furthermore, the outer second control gate structure is laterally coupled along the long sides of the L-shaped floating gate structure while being longitudinally coupled along the short sides of the L-shaped floating gate structure. The inner and outer first and second control gate structures overlap on the three most important surfaces of the L-shaped floating gate structure, significantly increasing the coupling coefficients between the first and second control gate structures and the floating gate structure while reducing the coupling coefficient between the select gate structure and the floating gate structure. Furthermore, the overlap between the inner and outer first and second control gate structures and the floating gate structure significantly increases the coupling area, thereby facilitating a reduction in the device control gate height and improving compatibility with advanced CMOS (Complementary Metal Oxide Semiconductor) devices without affecting the control gate-floating gate coupling effect. Based on the above technical solution, preferably, in a subsequent process, the first control gate and the second control gate can be short-circuited by using a contact hole to form an integrated control.

[0142] Based on the above technical solution, preferably, the select gate structure includes:

[0143] A select gate dielectric layer 102 is disposed on the upper surface of the substrate;

[0144] A select gate polysilicon layer 103 is disposed on the upper surface of the select gate dielectric layer 102 .

[0145] Based on the above technical solution, preferably, the first control gate structure includes:

[0146] A first composite structure dielectric layer is disposed on the upper surface of the select gate structure;

[0147] a first control gate polysilicon layer 105 - 1 , disposed on the upper surface of the first composite structure dielectric layer;

[0148] An oxide layer 104-3 is provided on both sides of the first control gate polysilicon layer 105-1, completely covering the sidewalls of the first control gate polysilicon layer 105-1. The sum of the width of the first control gate polysilicon layer 105-1 and the thickness of the two oxide layers 104-3 is equal to the width of the select gate structure. The height of the first control gate polysilicon layer 105-1 is lower than the height of the oxide layer 104-3, and the first control gate polysilicon layer 105-1 forms an inner sidewall structure attached to the oxide layers 104-3 on both sides.

[0149] An isolation dielectric layer 106 is disposed on top of the first control gate polysilicon layer 105 - 1 and fills the gaps of the inner sidewall structure. The upper surface of the isolation dielectric layer 106 is flush with the top of the oxide layer 104 - 3 .

[0150] Based on the above technical solution, preferably, the first composite dielectric layer includes:

[0151] a first bottom oxide layer 104 - 1 ;

[0152] a first middle nitride layer 104-2 covering the bottom oxide layer;

[0153] A first top oxide layer 104 - 3 covering the middle nitride layer.

[0154] Based on the above technical solution, preferably, the floating gate structure includes:

[0155] A floating gate dielectric layer 107 covering both sidewalls of the select gate structure, both sidewalls of the first control gate structure and the position of the lightly doped region 109 corresponding to the source and drain region 111 on the upper surface of the substrate;

[0156] A floating gate polysilicon layer 108 covers the surface of the floating gate dielectric layer 107 except for the surface above the shallow trench isolation structure 504 and is in a mirror-symmetrical "L" shape that is recessed outward and is divided into independent blocks in the width direction;

[0157] Part of the floating gate dielectric layer 107 extends out of the floating gate polysilicon layer 108 from both sides. The thickness of the floating gate dielectric layer 107 extending out of the floating gate polysilicon layer 108 is lower than that of the floating gate dielectric layer 107 below the floating gate polysilicon layer 108 .

[0158] Based on the above technical solution, preferably, the second control gate structure includes:

[0159] a second composite dielectric layer disposed on the inner wall surface of the recess of the L-shaped floating gate polysilicon layer 108;

[0160] A second control gate polysilicon layer 105 - 2 is disposed on the second composite structure dielectric layer.

[0161] Based on the above technical solution, it is further preferred that the second composite dielectric layer includes:

[0162] a second bottom oxide layer 1104 - 1 ;

[0163] a second middle nitride layer 1104-2 covering the bottom oxide layer;

[0164] A second top oxide layer 1104 - 3 covering the middle nitride layer.

[0165] Based on the above technical solution, preferably, the side wall structure includes:

[0166] A first spacer 110 - 1 covers the side surfaces of the floating gate structure and the second control gate structure; more preferably, the first spacer 110 - 1 may be an oxide layer.

[0167] A second spacer 110 - 2 covers the lower half of the second spacer and the upper surface of the floating gate dielectric layer extending out of the floating gate polysilicon layer. Further preferably, the second spacer 110 - 2 may be a nitride layer.

[0168] In the above technical solution, the second control gate structure and the floating gate structure are both sidewall-type polysilicon, which can achieve self-aligned etching of the second control gate structure and the floating gate structure, which is conducive to reducing the size of the device.

[0169] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a floating gate split-gate flash memory device, characterized in that: The following steps are included: Step S1, providing a substrate, wherein a P-type well region separated by a shallow trench isolation structure is provided on the top of the substrate; Step S2, forming a select gate structure at a position corresponding to the P-type well region on the substrate, and forming a first control gate structure above the select gate structure; Step S2 includes the following steps: Step S21, forming a select gate dielectric layer on the upper surface of the substrate; Step S22, forming a select gate polysilicon layer on the upper surface of the select gate dielectric layer; Step S23, forming a first oxide layer, a first nitride layer, an etch stop layer and a second nitride layer in sequence on the upper surface of the select gate polysilicon layer; Step S24, etching the second nitride layer and the etch stop layer to form a groove corresponding to the position of the first control gate structure and exposing the first nitride layer; Step S25, forming a second oxide layer on the surface of the second nitride layer, the wall and the bottom of the groove, and filling the groove to form a first control gate polysilicon layer; Step S26, etching the first control gate polysilicon layer to remove the first control gate polysilicon layer on the surface of the second nitride layer, and making the height of the first control gate polysilicon layer in the groove lower than the notch of the groove, and forming inner sidewall structures respectively attached to the inner walls on both sides of the groove; Step S27, filling the groove opening with an isolation dielectric layer, and polishing the isolation dielectric layer to remove the second oxide layer on the upper surface of the second nitride layer; Step S28, etching away the second nitride layer, the etch-stop layer, the first nitride layer, the first oxide layer, the select gate polysilicon layer, and the select gate dielectric layer on the upper surface of the substrate, leaving the second oxide layer on the groove wall and the groove bottom, and leaving the select gate dielectric layer, the select gate polysilicon layer, the first oxide layer, and the first nitride layer between the second oxide layer at the groove bottom and the upper surface of the substrate; Step S3, forming symmetrical "L"-shaped outward-recessed floating gate structures on both sides of the select gate structure and the first control gate structure; Step S4, forming a second control gate structure at the recessed positions of the floating gate structure; In step S5 , a spacer structure is formed on the bottom of the second control gate structure and the floating gate structure, respectively, on a side facing away from the first control gate structure.

2. The preparation method according to claim 1, wherein The step S3 includes: Step S31, forming a floating gate dielectric layer on the upper surface of the substrate, on both sides of the select gate structure, on both sides of the first control gate structure and on the upper surface; Step S32, forming a floating gate polysilicon layer on the upper surface of the floating gate dielectric layer; Step S33, trimming the morphology of the floating gate polysilicon layer so that the floating gate polysilicon layer forms an outwardly recessed "L"-shaped structure on the upper surface of the substrate, on both sides of the select gate structure, and on both sides of the first control gate structure, and removing the floating gate polysilicon layer above the shallow trench isolation structure in the width direction to divide the floating gate polysilicon layer into independent blocks; Step S34 , forming a composite dielectric layer on the upper surface of the floating gate polysilicon layer and the upper surface of the floating gate dielectric layer on the exposed upper surface of the shallow trench isolation structure.

3. The preparation method according to claim 2, wherein In the step S33, the floating gate polysilicon layer is formed into an outwardly recessed "L"-shaped structure on the upper surface of the substrate, on both sides of the select gate structure and on both sides of the first control gate structure, and the floating gate polysilicon layer is divided into independent blocks by selective photolithography in the width direction.

4. The preparation method according to claim 2, wherein In step S34, the composite dielectric layer includes: a bottom oxide layer; an intermediate nitride layer covering the bottom oxide layer; A top oxide layer covers the middle nitride layer.

5. The preparation method according to claim 2, wherein The step S4 includes: Step S41, forming a second control gate polysilicon layer on the upper surface of the composite dielectric layer; Step S42: etching the second control gate polysilicon layer, the composite dielectric layer, the floating gate polysilicon layer, the isolation dielectric layer, the second oxide layer, and the floating gate dielectric layer to form the floating gate structure and the second control gate structure, removing the composite dielectric layer on top of the floating gate structure and the first control gate structure, and thinning the floating gate dielectric layer on the substrate surface and the second oxide layer and the isolation dielectric layer on top of the first control gate. In step S43 , source and drain regions are defined on the substrate, and the source and drain regions are lightly doped.

6. The preparation method according to claim 5, wherein After step S42 is performed, the heights of the top of the first control gate structure, the top of the floating gate structure, and the top of the second control gate structure gradually decrease from the middle to both sides.

7. The preparation method according to claim 5, wherein The step S5 includes: Step S51, forming a first spacer on the exposed side surfaces of the second control gate polysilicon layer and the floating gate polysilicon layer, respectively, wherein the first spacer also covers the exposed side surface of the composite dielectric layer between the second control gate structure and the floating gate structure; Step S52, forming a second spacer material layer on the exposed floating gate dielectric layer, the first spacer, the top of the composite dielectric layer, the floating gate polysilicon layer, the second oxide layer, and the isolation dielectric layer; Step S53, etching the second spacer material layer and the floating gate dielectric layer to expose the heavily doped regions of the source and drain regions; Step S54, performing ion implantation into the heavily doped region using the remaining second spacer material layer as a mask to form the source and drain regions; In step S55, the remaining second sidewall spacer material layer is etched to expose the floating gate polysilicon layer, the second oxide layer, the floating gate dielectric layer, and the top of the composite dielectric layer, thereby forming an outwardly recessed "L"-shaped second sidewall spacer outside the first sidewall spacer.

8. A structure of a floating gate split-gate flash memory device, characterized in that: include, A substrate having a P-type well region separated by a shallow trench isolation structure provided on the top of the substrate; a select gate structure, disposed on the substrate at a position corresponding to the P-type well region; A first control gate structure is provided above the select gate structure; the first control gate structure includes A first composite dielectric layer is disposed on the upper surface of the select gate structure; a first control gate polysilicon layer, disposed on the upper surface of the first composite dielectric layer; An oxide layer is provided on both sides of the first control gate polysilicon layer, completely covering the sidewalls of the first control gate polysilicon layer. The sum of the width of the first control gate polysilicon layer and the thickness of the two oxide layers is equal to the width of the select gate structure. The height of the first control gate polysilicon layer is lower than the height of the oxide layer, and the first control gate polysilicon layer forms an inner sidewall structure respectively attached to the oxide layers on both sides. an isolation dielectric layer, disposed on top of the first control gate polysilicon layer and filling the gap of the inner sidewall structure, with an upper surface flush with the top of the oxide layer; a pair of mirror-symmetrical L-shaped floating gate structures with outward depressions, respectively disposed on both sides of the select gate structure and the first control gate structure; a pair of second control gate structures, respectively disposed at recessed positions of the floating gate structure; The sidewall structure is arranged on a side of the second control gate structure facing away from the first control gate structure.

9. The structure according to claim 8, characterized in that The select gate structure includes: a select gate dielectric layer, disposed on the upper surface of the substrate; A select gate polysilicon layer is disposed on the upper surface of the select gate dielectric layer.

10. The structure according to claim 8, wherein The first composite dielectric layer includes: a bottom oxide layer; an intermediate nitride layer covering the bottom oxide layer; A top oxide layer covers the middle nitride layer.

11. The structure according to claim 8, wherein The floating gate structure includes: a floating gate dielectric layer covering both side walls of the select gate structure, both side walls of the first control gate structure, and the lightly doped regions on the upper surface of the substrate corresponding to the source and drain regions; a floating gate polysilicon layer covering the surface of the floating gate dielectric layer except for the area above the shallow trench isolation structure, and forming a mirror-symmetrical "L" shape that is recessed outward and is divided into independent blocks in the width direction; Part of the floating gate dielectric layer extends out from the floating gate polysilicon layer on both sides, and a thickness of the floating gate dielectric layer extending out from the floating gate polysilicon layer is lower than that of the floating gate dielectric layer below the floating gate polysilicon layer.

12. The structure according to claim 11, wherein The second control gate structure includes, a second composite dielectric layer disposed on the inner wall surface of the recess of the L-shaped floating gate polysilicon layer and the upper surface of the floating gate dielectric layer above the shallow trench isolation structure; A second control gate polysilicon layer is disposed on the second composite dielectric layer.

13. The structure according to claim 11, wherein The side wall structure includes: a first spacer covering side surfaces of the floating gate structure and the second control gate structure; A second sidewall spacer covers a lower half of the second sidewall spacer and an upper surface of the floating gate dielectric layer extending out of the floating gate polysilicon layer.

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