Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device can include a cell wafer including a source plate, a plurality of first word lines, and a plurality of second word lines, the plurality of first word lines being stacked apart from each other along a plurality of first vertical channels protruding in a vertical direction from a bottom surface of the source plate, the plurality of second word lines being stacked apart from each other along a plurality of second vertical channels protruding in the vertical direction from a top surface of the source plate; a first peripheral wafer bonded to the bottom surface of the cell wafer and including a first row decoder unit that transfers an operating voltage to the plurality of first word lines; and a second peripheral wafer bonded to the top surface of the cell wafer and including a second row decoder unit that transfers an operating voltage to the plurality of second word lines.

Description

Technical Field

[0001] The various implementations generally relate to semiconductor technology, and more specifically, to three-dimensional semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices with two-dimensional or planar structures have been developed using fine patterning processes to store more data in the same area. However, as the linewidth of circuits narrows due to the need for high integration, interference between memory cells becomes severe, causing various limitations such as performance degradation. Of course, in addition to these structural limitations, the need to introduce expensive equipment to pattern fine linewidths inevitably increases manufacturing costs.

[0003] As an alternative to overcoming the limitations of two-dimensional semiconductor memory devices, three-dimensional semiconductor memory devices have been proposed. The advantages of three-dimensional semiconductor memory devices are that by increasing the number of stacked layers through vertically stacking memory cells, larger capacity can be achieved within the same area, thus providing high performance and excellent power efficiency. Summary of the Invention

[0004] Various implementations relate to three-dimensional semiconductor memory devices with improved integration and performance.

[0005] In one embodiment, a three-dimensional semiconductor memory device may include: a cell wafer including a source plate, a plurality of first word lines and a plurality of second word lines, the plurality of first word lines being stacked spaced apart from each other along a plurality of first vertical channels projecting from the bottom surface of the source plate in a vertical direction, and the plurality of second word lines being stacked spaced apart from each other along a plurality of second vertical channels projecting from the top surface of the source plate in a vertical direction; a first peripheral wafer bonded to the bottom surface of the cell wafer and including a first row decoder unit that delivers operating voltages to the plurality of first word lines; and a second peripheral wafer bonded to the top surface of the cell wafer and including a second row decoder unit that delivers operating voltages to the plurality of second word lines.

[0006] In one embodiment, a three-dimensional semiconductor memory device may include: a cell wafer including a source plate, a first memory block, and a second memory block, the first memory block including a plurality of first cell strings extending vertically from the bottom surface of the source plate, and the second memory block including a plurality of second cell strings extending vertically from the top surface of the source plate; a first peripheral wafer bonded to the bottom surface of the cell wafer and including a first row decoder unit that supplies an operating voltage to the first memory block; and a second peripheral wafer bonded to the top surface of the cell wafer and including a second row decoder unit that supplies an operating voltage to the second memory block. The first memory block and the second memory block may be configured to be erased independently of each other.

[0007] In one embodiment, a three-dimensional semiconductor memory device may include: a cell wafer including a source plate, a first sub-memory cell array disposed below the source plate, and a second sub-memory cell array disposed above the source plate; a first peripheral wafer bonded to the bottom surface of the cell wafer and including a first logic circuit unit that transmits an operating voltage to the first sub-memory cell array; and a second peripheral wafer bonded to the top surface of the cell wafer and including a second logic circuit unit that transmits an operating voltage to the second sub-memory cell array. Attached Figure Description

[0008] Figure 1 This is a block diagram that schematically illustrates a representation of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a schematic cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 3 This is a diagram illustrating a schematic layout of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 4 This is an example Figure 3 The diagram shows a cross-sectional view of a semiconductor memory device.

[0012] Figure 5 This is a diagram illustrating a schematic layout of a semiconductor memory device according to another embodiment of the present disclosure.

[0013] Figure 6 This is an example Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device.

[0014] Figure 7 This is a cross-sectional view illustrating the structure of a first sub-memory cell array and a second sub-memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 8 This is a diagrammatic representation used to assist in comparing the structure of the vertical channel related to this disclosure with the structure of the vertical channel according to an embodiment of this disclosure.

[0016] Figure 9 This is a block diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 10 This is a block diagram illustrating a computing system including a semiconductor memory device according to an embodiment of the present disclosure. Detailed Implementation

[0018] The advantages and features of this disclosure, as well as methods of implementing them, will become apparent from the following description of exemplary embodiments, taken with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0019] Because the figures, dimensions, ratios, angles, and quantities of elements given in the accompanying drawings describing embodiments of this disclosure are merely exemplary, this disclosure is not limited to what is shown. Throughout the specification, similar reference numerals refer to similar components. In describing this disclosure, detailed descriptions of related technologies will be omitted where it is determined that such detailed descriptions may obscure the gist or clarity of the disclosure. It should be understood that terms such as “comprising,” “having,” “including,” etc., as used in the specification and claims should not be construed as limiting to the means listed thereafter, unless explicitly stated otherwise. When referring to singular nouns using indefinite or definite articles (e.g., “a,” “an,” or “the”), the article may include the plural form of the noun unless explicitly stated otherwise.

[0020] When interpreting the elements in the embodiments of this disclosure, they should be interpreted as including tolerances, even if not explicitly mentioned.

[0021] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only for distinguishing one component from another and do not limit the substance, order, sequence, or quantity of the components. Additionally, the components in embodiments of this disclosure are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, as used herein, within the spirit of this disclosure, a first component may be a second component.

[0022] If a component is described as "connected," "linked," or "attached" to another component, it can mean that the component is not only directly "connected," "linked," or "attached," but also indirectly "connected," "linked," or "attached" via a third component. When describing positional relationships, such as "component A on component B," "component A above component B," "component A below component B," and "component A next to component B," one or more other components may be placed between component A and B unless the terms "directly" or "immediately adjacent" are explicitly used.

[0023] The features of the various exemplary embodiments of this disclosure can be joined, combined, or separated, in part or in whole. Technically, various interactions and operations are also possible. The various exemplary embodiments can be practiced individually or in combination.

[0024] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram that schematically illustrates a representation of a semiconductor memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1 The semiconductor memory device 100 according to embodiments of the present disclosure may include a memory cell array 110 and logic circuitry 120. Logic circuitry 120 may include a row decoder (X-DEC) 121, a page buffer circuitry 122, and peripheral circuitry (PERI circuitry) 123.

[0027] The memory cell array 110 may include a first sub-memory cell array 110A and a second sub-memory cell array 110B. Each of the first sub-memory cell array 110A and the second sub-memory cell array 110B may include a plurality of memory blocks BLK.

[0028] A memory block (BLK) may include multiple memory cells. For example, a memory cell may be a non-volatile memory cell, and more specifically, a memory cell may be a non-volatile memory cell based on a charge-fetching device.

[0029] Each memory block BLK of the first sub-memory cell array 110A can be connected to the row decoder 121 via multiple first word lines WL1. Each memory block BLK of the second sub-memory cell array 110B can be connected to the row decoder 121 via multiple second word lines WL2.

[0030] The row decoder 121 can select any one of the memory blocks included in the first sub-memory cell array 110A and the second sub-memory cell array 110B in response to the row address X_A provided from the peripheral circuit 123.

[0031] The row decoder 121 may include a first row decoder unit 121A and a second row decoder unit 121B. The first row decoder unit 121A is connected to the first sub-memory cell array 110A through multiple first word lines WL1, and the second row decoder unit 121B is connected to the second sub-memory cell array 110B through multiple second word lines WL2.

[0032] The first row decoder unit 121A can transmit the operating voltage X_V provided from the peripheral circuit 123 to a first word line WL1 connected to a memory block BLK selected from the memory blocks BLK included in the first sub-memory cell array 110A. The second row decoder unit 121B can transmit the operating voltage X_V provided from the peripheral circuit 123 to a second word line WL2 connected to a memory block BLK selected from the memory blocks BLK included in the second sub-memory cell array 110B. Although not shown, each of the first row decoder unit 121A and the second row decoder unit 121B may include multiple transmission transistors for transmitting the operating voltage X_V.

[0033] Page buffer circuit 122 may include multiple page buffers PB connected to memory cell array 110 via multiple bit lines BL.

[0034] Page buffer PB can receive page buffer control signal PB_C from peripheral circuit 123, and can send and receive data signal DATA from peripheral circuit 123. Page buffer PB can control bit line BL in response to page buffer control signal PB_C. For example, page buffer PB can detect data stored in memory cells of memory cell array 110 by sensing the signal of bit line BL in response to page buffer control signal PB_C, and can send data signal DATA to peripheral circuit 123 based on the detected data. Page buffer PB can apply a signal to bit line BL based on data signal DATA received from peripheral circuit 123 in response to page buffer control signal PB_C, thereby writing data to memory cells of memory cell array 110. Page buffer PB can write data to or read data from memory cells connected to active word lines.

[0035] Peripheral circuit 123 can receive command signals CMD, address signals ADD, and control signals CTRL from devices outside the semiconductor memory device 100 (e.g., a memory controller), and can send data DATA to and receive data DATA from such devices. Peripheral circuit 123 can output signals for writing data to or reading data from the memory cell array 110 based on the command signals CMD, ADD, and CTRL, such as row address X_A, page buffer control signal PB_C, etc. Peripheral circuit 123 can generate various voltages required in the semiconductor memory device 100, including the operating voltage X_V.

[0036] As the size of electronic products (especially mobile products) in which semiconductor memory devices 100 are installed decreases, there is a growing demand to reduce the size of semiconductor memory devices 100. As the number of word lines stacked increases due to the need for high capacity, the number of transmission transistors included in the line decoder 121 also increases, thus increasing the area occupied by the line decoder 121. For this reason, it is difficult to manufacture semiconductor memory devices 100 in a small size.

[0037] The embodiments of this disclosure can provide measures that can suppress the increase in size of the semiconductor memory device 100 and improve the integration density.

[0038] In the following figures, the direction projecting vertically from the top surface of the substrate is defined as the vertical direction VD, and two directions parallel to the top surface of the substrate and intersecting each other are defined as the first direction FD and the second direction SD, respectively. For example, the first direction FD may correspond to the extension direction of word lines and / or the arrangement direction of bit lines, while the second direction SD may correspond to the extension direction of bit lines and / or the arrangement direction of word lines. The first direction FD and the second direction SD may intersect each other substantially perpendicularly. In the figures, the direction indicated by the arrow and the opposite direction represent the same direction.

[0039] Figure 2 This is a schematic cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0040] Reference Figure 2 The semiconductor memory device 100 according to embodiments of the present disclosure may include a cell wafer CW and a first peripheral wafer PW1 and a second peripheral wafer PW2 bonded to the bottom and top surfaces of the cell wafer CW by a bonding technique such as hybrid bonding.

[0041] Semiconductor memory device 100 may be a non-monolithic three-dimensional memory device. The term non-monolithic means that the unit wafer CW, the first peripheral wafer PW1, and the second peripheral wafer PW2 constituting the semiconductor memory device 100 are manufactured separately on different substrates and then interconnected with each other by bonding technology.

[0042] For ease of understanding, Figure 2 , Figure 3 and Figure 5 The illustration shows that the bottom surface of the unit wafer CW and the top surface of the first peripheral wafer PW1 are separated from each other, and the top surface of the unit wafer CW and the bottom surface of the second peripheral wafer PW2 are separated from each other. However, it should be understood that the bottom surface of the unit wafer CW and the top surface of the first peripheral wafer PW1 are in contact with each other, and the top surface of the unit wafer CW and the bottom surface of the second peripheral wafer PW2 are in contact with each other.

[0043] The first sub-memory cell array 110A can be disposed on the bottom surface of the source plate 10 of the cell wafer CW, while the second sub-memory cell array 110B can be disposed on the top surface of the source plate 10 of the cell wafer CW. The cell wafer CW can be a double-sided memory including the first sub-memory cell array 110A and the second sub-memory cell array 110B disposed on the two surfaces of the source plate 10.

[0044] The logic circuit 120 can be divided into a first logic circuit unit 120A and a second logic circuit unit 120B. The first logic circuit unit 120A and the second logic circuit unit 120B can be respectively disposed in the first peripheral wafer PW1 and the second peripheral wafer PW2.

[0045] Figure 3 This is a diagram illustrating a schematic layout of a semiconductor memory device according to an embodiment of the present disclosure.

[0046] Reference Figure 3 The cell region CR and the thinning region SR can be defined on the first direction FD.

[0047] The first sub-memory cell array 110A and the second sub-memory cell array 110B can be disposed in the cell region CR of the cell wafer CW so as to overlap each other in the vertical direction VD.

[0048] Multiple first word lines WL1 and multiple first bit lines BL1 connected to the first sub-memory cell array 110A can be disposed on one side of the cell wafer CW where the first sub-memory cell array 110A is located. The multiple first word lines WL1 can extend in the first direction FD and be arranged in the second direction SD, and the multiple first bit lines BL1 can extend in the second direction SD and be arranged in the first direction FD.

[0049] Multiple second word lines WL2 and multiple second bit lines BL2 connected to the second sub-memory cell array 110B can be disposed on the other side of the cell wafer CW where the second sub-memory cell array 110B is located. The multiple second word lines WL2 can extend in the first direction FD and be arranged in the second direction SD, and the multiple second bit lines BL2 can extend in the second direction SD and be arranged in the first direction FD.

[0050] The first row decoder unit (X-DEC unit 1) 121A can be disposed in the thinned region SR of the first peripheral wafer PW1. In order to reduce the delay of the signal provided from the first row decoder unit 121A to the first word line WL1, the first row decoder unit 121A can be configured to have a shape extending in a second direction SD, which is the arrangement direction of the first word line WL1, and can have a length in the second direction SD that is substantially the same as or similar to that of the first sub-memory cell array 110A.

[0051] The second row decoder unit (X-DEC unit 2) 121B can be located in the thinned region SR of the second peripheral wafer PW2, and can overlap with the first row decoder unit 121A in the vertical direction VD.

[0052] Similar to the first row decoder unit 121A, the second row decoder unit 121B can be configured to have a shape extending in a second direction SD, which is the arrangement direction of the second word line WL2, and can have a length in the second direction SD that is substantially the same as or similar to that of the second sub-memory cell array 110B.

[0053] The page buffer circuit 122 may include a first page buffer circuit unit (PB circuit unit 1) 122A and a second page buffer circuit unit (PB circuit unit 2) 122B.

[0054] The first page buffer circuit unit 122A may be disposed in the cell region CR of the first peripheral wafer PW1, and may include multiple page buffers (not shown) respectively connected to multiple first bit lines BL1. In order to reduce the delay of the signal applied from the first page buffer circuit unit 122A to the first bit line BL1 or the signal received from the first bit line BL1 in the first page buffer circuit unit 122A, the first page buffer circuit unit 122A may be configured to have a shape extending in a first direction FD which is the arrangement direction of the first bit line BL1, and may have a length in the first direction FD that is substantially the same as or similar to that of the first sub-memory cell array 110A.

[0055] The second page buffer circuit unit 122B can be disposed in the cell region CR of the second peripheral wafer PW2, and can overlap with the first page buffer circuit unit 122A in the vertical direction VD. The second page buffer circuit unit 122B may include multiple page buffers (not shown) respectively connected to multiple second bit lines BL2.

[0056] Similar to the first page buffer circuit unit 122A, the second page buffer circuit unit 122B can be configured to have a shape extending in a first direction FD, which is the arrangement direction of the second bit line BL2, and can have a length in the first direction FD that is substantially the same as or similar to that of the second sub-memory cell array 110B.

[0057] Although not shown, the peripheral circuit ( Figure 1 123) can be located in the first peripheral wafer PW1 and / or the second peripheral wafer PW2. For example, the peripheral circuit can be located in the area of ​​the first peripheral wafer PW1 where the first row decoder unit 121A and the first page buffer circuit unit 122A are not located, and in the area of ​​the second peripheral wafer PW2 where the second row decoder unit 121B and the second page buffer circuit unit 122B are not located.

[0058] The first row decoder unit 121A, the first page buffer circuit unit 122A, and a portion of the peripheral circuitry (not shown) disposed in the first peripheral wafer PW1 can constitute the first logic circuit unit. Figure 2 (120A). The second row decoder unit 121B, the second page buffer circuit unit 122B, and another part of the peripheral circuit (not shown) disposed in the second peripheral wafer PW2 can constitute the second logic circuit unit ( Figure 2 (120B).

[0059] Multiple external connection pads (PADs) can be arranged in a row at one edge of the second peripheral wafer PW2. Through these external connection pads, the semiconductor memory device 100 can receive electrical signals (e.g., command signals, address signals, and control signals) from external devices such as memory controllers, and can exchange data with these external devices. Power supply voltage can be supplied to the semiconductor memory device 100 from the outside through at least one external connection pad (PAD).

[0060] Figure 4 This is an example Figure 3 The diagram shows a cross-sectional view of a semiconductor memory device.

[0061] Reference Figure 4 The source plate 10 may include semiconductor materials, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), or gallium arsenide (GaAs).

[0062] The first sub-memory cell array 110A may include a plurality of first vertical channels Cha protruding from the bottom surface of the source plate 10 along the vertical direction VD, and a plurality of first electrode layers 20a and a plurality of first interlayer dielectric layers 22a alternately stacked on the bottom surface of the source plate 10 along the plurality of first vertical channels Cha.

[0063] The first electrode layer 20a may include a conductive material. For example, the first electrode layer 20a may include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The first interlayer dielectric layer 22a may include silicon oxide.

[0064] In the first electrode layer 20a, at least one first electrode layer 20a starting from the uppermost first electrode layer 20a may be configured with a source select line. In the first electrode layer 20a, at least one first electrode layer 20a starting from the lowermost first electrode layer 20a may be configured with a drain select line. The first electrode layer 20a between the source select line and the drain select line may be configured with a first word line.

[0065] Although not shown in detail, each of the first vertical channels Cha may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon and may include p-type impurities such as boron (B) in some regions therein. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer stacked sequentially from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stacked structure in which oxide layers, nitride layers, and oxide layers are stacked sequentially.

[0066] The source select transistor can be configured in a region or area surrounding the first vertical channel CHa with the source select line. The memory cell can be configured in a region or area surrounding the first vertical channel CHa with the first word line. The drain select transistor can be configured in a region or area surrounding the first vertical channel CHa with the drain select line.

[0067] A source selection transistor, multiple memory cells, and a drain selection transistor disposed along a first vertical channel Cha in the vertical direction VD can be configured into a first cell string CSTR1. The first sub-memory cell array 110A may include multiple first cell strings CSTR1 corresponding to multiple first vertical channels CHa.

[0068] Multiple first-position lines BL1 can be positioned below the first vertical channel Cha. Each of the first-position lines BL1 can be connected to the corresponding first vertical channel CHa via a contact element.

[0069] The dielectric layer ILD1 can be defined on the bottom surface of the source plate 10 to cover multiple first electrode layers 20a, multiple first interlayer dielectric layers 22a, multiple first vertical channels CHa, and multiple first first lines BL1. The bottom surface of the dielectric layer ILD1 can form a bonding layer between the unit wafer CW and the bottom surface of the first peripheral wafer PW1. The unit wafer CW can include multiple first bonding pads BP1 on its bottom surface that are connected to the multiple first electrode layers 20a and the multiple first first lines BL1.

[0070] For the sake of simplicity in the illustration, Figure 4 Only a few of the multiple first bonding pads BP1 are shown, which are connected to some first electrode layers 20a and some first bit lines BL1. However, it should be understood that the multiple first bonding pads BP1 are respectively connected to multiple first electrode layers 20a and multiple first bit lines BL1.

[0071] Similar to the first sub-memory cell array 110A, the second sub-memory cell array 110B may include a plurality of second vertical channels CHb protruding in the vertical direction VD from the top surface of the source plate 10, and a plurality of second electrode layers 20b and a plurality of second interlayer dielectric layers 22b alternately stacked on the top surface of the source plate 10 along the plurality of second vertical channels CHb. For example, the second sub-memory cell array 110B may have a structure that is a symmetrical mirror image of the structure of the first sub-memory cell array 110A with respect to the source plate 10.

[0072] In the second electrode layer 20b, at least one second electrode layer 20b, starting from the bottommost second electrode layer 20b, may be configured with a source select line. In the second electrode layer 20b, at least one second electrode layer 20b, starting from the topmost second electrode layer 20b, may be configured with a drain select line. The second electrode layer 20b between the source select line and the drain select line may be configured with a second word line.

[0073] The source-select transistor can be configured in the region or area surrounding the second vertical channel CHb with the source-select line. The memory cell can be configured in the region or area surrounding the second vertical channel CHb with the second word line. The drain-select transistor can be configured in the region or area surrounding the second vertical channel CHb with the drain-select line.

[0074] A source selection transistor, multiple memory cells, and a drain selection transistor disposed along a second vertical channel CHb in the vertical direction VD can be configured into a second cell string CSTR2. The second sub-memory cell array 110B may include multiple second cell strings CSTR2 corresponding to multiple second vertical channels CHb.

[0075] Multiple second bit lines BL2 can be positioned above the second vertical channel CHb. Each of the second bit lines BL2 can be connected to the corresponding second vertical channel CHb via a contact element.

[0076] The dielectric layer ILD2 can be defined on the top surface of the source plate 10 to cover multiple second electrode layers 20b, multiple second interlayer dielectric layers 22b, multiple second vertical channels CHb, and multiple second bit lines BL2. The top surface of the dielectric layer ILD2 can form the top surface of the bonding between the unit wafer CW and the second peripheral wafer PW2. The unit wafer CW can include multiple second bonding pads BP2 on its top surface, which are connected to the multiple second electrode layers 20b and the multiple second bit lines BL2. For the sake of simplicity, Figure 4 Only some of the multiple second bonding pads BP2 are illustrated, which are connected to some second electrode layers 20b and some second bit lines BL2. However, it should be understood that the multiple second bonding pads BP2 are respectively connected to multiple second electrode layers 20b and multiple second bit lines BL2.

[0077] The first peripheral wafer PW1 may include a substrate 30 and a first logic circuit unit 120A defined on the substrate 30, and the second peripheral wafer PW2 may include a substrate 40 and a second logic circuit unit 120B defined below the substrate 40. The first logic circuit unit 120A and the second logic circuit unit 120B can be fabricated using CMOS (Complementary Metal-Oxide-Semiconductor) technology.

[0078] The dielectric layer ILD3 can be defined on the top surface of the substrate 30 of the first peripheral wafer PW1 to cover the first logic circuit cell 120A. The top surface of the dielectric layer ILD3 can form the top surface of the first peripheral wafer PW1 bonded to the cell wafer CW. The first peripheral wafer PW1 can include a plurality of third bonding pads BP3 connected to the first logic circuit cell 120A on its top surface. The first sub-memory cell array 110A and the first logic circuit cell 120A can be electrically connected by bonding the plurality of third bonding pads BP3 to the plurality of first bonding pads BP1 respectively.

[0079] The dielectric layer ILD4 can be defined on the bottom surface of the substrate 40 of the second peripheral wafer PW2 to cover the second logic circuit cell 120B. The bottom surface of the dielectric layer ILD4 can form the bottom surface of the second peripheral wafer PW2 bonded to the cell wafer CW. The second peripheral wafer PW2 can include a plurality of fourth bonding pads BP4 on its bottom surface, which are connected to the second logic circuit cell 120B. The second sub-memory cell array 110B and the second logic circuit cell 120B can be electrically connected by bonding the plurality of fourth bonding pads BP4 to the plurality of second bonding pads BP2 respectively.

[0080] As referenced above Figures 1 to 3 As described, a first row decoder unit 121A, connected to a first word line WL1 of the first sub-memory cell array 110A, is disposed in the first peripheral wafer PW1, and a second row decoder unit 121B, connected to a second word line WL2 of the second sub-memory cell array 110B, is disposed in the second peripheral wafer PW2. Therefore, a connection between the first word line WL1 and the first row decoder unit 121A is provided at the bonding surface between the cell wafer CW and the first peripheral wafer PW1 (see [link to documentation]). Figure 3 The bonding pads of the unit wafer CW and the second peripheral wafer PW2 are provided, and the second word line WL2 and the second line decoder unit 121B are provided at the bonding surface between the unit wafer CW and the second peripheral wafer PW2 (see Figure 3 The bonding pads of ) are connected. That is, the word lines WL1 and WL2 are connected to the line decoder 121 (see Figure 3The bonding pads of the interconnect word lines WL1 and WL2 are distributed above two separate top and bottom bonding surfaces shared by the cell wafer CW. Therefore, compared to the case where all bonding pads for the interconnect word lines WL1 and WL2 and the line decoder 121 are located on a single bonding surface, the number of bonding pads on each bonding surface is reduced in the disclosed embodiment, thus allowing for an increase in the size of each pad. As a result, alignment margins during wafer bonding can be increased, which suppresses or reduces the occurrence of pad bonding failures.

[0081] Refer again Figure 4 External connection pads (PADs) may be disposed on the top surface of the substrate 40 of the second peripheral wafer PW2. Although not shown, a dielectric layer for insulating the external connection pads (PADs) from the substrate 40 may be additionally formed on the top surface of the substrate 40. The external connection pads (PADs) may be connected to at least one of the first logic circuit unit 120A and the second logic circuit unit 120B.

[0082] To facilitate the electrical connection between the external connection pad PAD and the first logic circuit unit 120A, each of the first peripheral wafer PW1, the second peripheral wafer PW2, and the unit wafer CW can have a vertical connection structure.

[0083] The vertical interconnect structure of the first peripheral wafer PW1 may include a plurality of contacts CNT1 and CNT2, wiring W1, and bonding pad BP3′ disposed in the vertical direction VD. For example, the bonding pad BP3′ may be disposed on the top surface of the first peripheral wafer PW1, and the plurality of contacts CNT1 and CNT2 and wiring W1 may be disposed through the dielectric layer ILD3 in the vertical direction VD to connect the bonding pad BP3′ and the first logic circuit unit 120A.

[0084] The vertical interconnect structure of the cell wafer CW may include multiple contacts CNT3 to CNT7, multiple wirings W2 and W3, and bonding pads BP1′ and BP2′ disposed in the vertical direction VD. For example, bonding pads BP1′ and BP2′ may be disposed on the bottom and top surfaces of the cell wafer CW, respectively, while the multiple contacts CNT3 to CNT7 and multiple wirings W2 and W3 may be disposed in the vertical direction VD through dielectric layer ILD1, source plate 10, and dielectric layer ILD2 to connect bonding pads BP1′ and BP2′.

[0085] The vertical interconnect structure of the second peripheral wafer PW2 may include a plurality of contacts CNT8 to CNT10, wiring W4, and bonding pad BP4′ disposed in the vertical direction VD. For example, the bonding pad BP4′ may be disposed on the bottom surface of the second peripheral wafer PW2, and the plurality of contacts CNT8 to CNT10 and wiring W4 may be disposed in the vertical direction VD through the dielectric layer ILD4 and the substrate 40 to connect the bonding pad BP4′ to the external interconnect pad PAD.

[0086] Since the bonding pad BP3′ of the first peripheral wafer PW1 and the bonding pad BP1′ of the unit wafer CW are bonded to each other, and the bonding pad BP2′ of the unit wafer CW and the bonding pad BP4′ of the second peripheral wafer PW2 are bonded to each other, the electrical path connecting the first logic circuit unit 120A and the external connection pad PAD can be configured.

[0087] Figure 5 This is a diagram illustrating a schematic layout of a semiconductor memory device according to another embodiment of the present disclosure.

[0088] Reference Figure 5 The page buffer circuit (PB circuit) 122 can be disposed in the cell region CR of the second peripheral wafer PW2. In this embodiment, each page buffer included in the page buffer circuit 122 can be connected to one of the multiple first bit lines BL1 and one of the multiple second bit lines BL2.

[0089] Page buffer circuit 122 can be configured to have a shape extending in a first direction FD which is the arrangement direction of the first bit line BL1 and the second bit line BL2, and can have a length in the first direction FD that is substantially the same as or similar to that of the first sub-memory cell array 110A and the second sub-memory cell array 110B.

[0090] Although not shown, the peripheral circuit ( Figure 1 123) can be located in the first peripheral wafer PW1 and / or the second peripheral wafer PW2. For example, the peripheral circuit can be located in the area of ​​the first peripheral wafer PW1 where the first row decoder unit (X-DEC unit 1) 121A is not located, and in the area of ​​the second peripheral wafer PW2 where the second row decoder unit (X-DEC unit) 121B and the page buffer circuit (PB circuit) 122 are not located.

[0091] The first row decoder unit (X-DEC unit 1) 121A can be disposed in the thinned region SR of the first peripheral wafer PW1. The first row decoder unit 121A disposed in the first peripheral wafer PW1 and a portion of the peripheral circuitry (not shown) can constitute the first logic circuit unit ( Figure 2(120A). The second row decoder unit (X-DEC unit 2) 121B can be disposed in the thinned region SR of the second peripheral wafer PW2. The second row decoder unit 121B disposed in the second peripheral wafer PW2, the page buffer circuit 122, and another part of the peripheral circuit (not shown) can constitute the second logic circuit unit ( Figure 2 (120B).

[0092] Figure 6 This is an example Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device.

[0093] Reference Figure 6 ,and Figure 3 and Figure 4 Compared to the semiconductor memory device shown, the cell wafer CW may include multiple vertical wiring TSVs connecting multiple first bit lines BL1 and multiple second bit lines BL2. The multiple first bit lines BL1 and multiple second bit lines BL2 can correspond to each other on a one-to-one basis. The corresponding first bit lines BL1 and second bit lines BL2 can be configured to overlap each other in the vertical direction VD. The vertical wiring TSVs can extend in the vertical direction VD and can connect the corresponding first bit lines BL1 and second bit lines BL2.

[0094] For example, a vertical wiring TSV can pass through multiple first electrode layers 20a, multiple first interlayer dielectric layers 22a, source plate 10, multiple second electrode layers 20b, and multiple second interlayer dielectric layers 22b in the vertical direction VD. Although not shown, the dielectric layer surrounding the outer wall of the vertical wiring TSV can be formed to isolate the vertical wiring TSV from the multiple first electrode layers 20a, source plate 10, and multiple second electrode layers 20b.

[0095] According to this embodiment, the first sub-memory cell array 110A and the second sub-memory cell array 110B share a page buffer, thus reducing the number of page buffers and the area occupied by the page buffer circuit. Furthermore, since no page buffer circuit is provided in the first peripheral wafer PW1, the area of ​​the first peripheral wafer PW1 that can be used to provide peripheral circuits can be increased.

[0096] Figure 7 This is a cross-sectional view taken in the second direction SD, illustrating the structure of the first sub-memory cell array and the second sub-memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0097] Reference Figure 7The system can define a plurality of first slits SLT1 that divide the alternately stacked first electrode layer 20a and the first interlayer dielectric layer 22a. Each of the plurality of first slits SLT1 can have a flat plate shape that is parallel or substantially parallel to a plane defined by a first direction FD and a vertical direction VD.

[0098] A first memory block BLK1 can be configured by a plurality of first electrode layers 20a, a plurality of first interlayer dielectric layers 22a, and a plurality of first vertical channels CHa disposed between a pair of adjacent first slits SLT1. Since a plurality of first slits SLT1 are arranged on the second direction SD, a plurality of first memory blocks BLK1 can be disposed on the second direction SD.

[0099] Similarly, multiple second slits SLT2 can be defined, which divide the alternately stacked second electrode layer 20b and the interlayer dielectric layer 22b into cells of memory blocks, so that the second sub-memory cell array 110B can be divided into multiple second memory blocks BLK2.

[0100] During the erase operation, an erase voltage can be applied to the source plate 10. Figure 1 The first row decoder unit 121A and the second row decoder unit 121B shown can apply an erase enable voltage to the word lines of memory blocks selected from a plurality of first memory blocks BLK1 and a plurality of second memory blocks BLK2, and can apply an erase disable voltage with a higher level than the erase enable voltage to the word lines of the remaining unselected memory blocks. Therefore, the first memory blocks BLK1 included in the first sub-memory cell array 110A and the second memory blocks BLK2 included in the second sub-memory cell array 110B can be erased independently of each other.

[0101] In the disclosed embodiment, by separately disposing electrode layers 20a and 20b on the top and bottom surfaces of the source plate 10, the lengths of the vertical channels CHa and CHb can be reduced compared to a comparative example where the electrode layers are disposed on only one surface of the source plate 10. Therefore, the number of memory cells included in a single cell string CSTR1 or CSTR2 can be reduced, and the number of memory cells included in a single memory block BLK1 or BLK2 can be reduced, thereby reducing the size of the memory block.

[0102] As is commonly known in the art, semiconductor memory devices are configured with multiple memory blocks, and each memory block is configured with multiple pages. Semiconductor memory devices perform write and read operations on a page-by-page basis and erase operations on a block-by-block basis. The speeds of the various operations are different. For example, a read operation takes approximately 25 microseconds (μs), a write operation takes approximately 250 μs, and an erase operation takes approximately 2,000 μs; therefore, the speeds of the operations are asymmetrical. Specifically, the erase operation is much slower than the read and write operations. The speed of the erase operation decreases as the size of the memory block increases. The slow erase operation is a major cause of performance degradation in semiconductor memory devices.

[0103] According to embodiments of this disclosure, by reducing the size of the memory block, the speed of the erase operation can be increased, thereby helping to improve the performance of the semiconductor memory device.

[0104] Figure 8 This is a diagrammatic representation that aids in comparing the structure of a vertical channel related to this disclosure with the structure of a vertical channel according to an embodiment of this disclosure. Figure 8 (a) illustrates the structure of a vertical channel relevant to this disclosure, while Figure 8 (b) illustrates the structure of a vertical channel according to this disclosure.

[0105] like Figure 8 As shown in (a), in a comparative example where all electrode layers 20 are stacked on only one surface of the source plate 10, the vertical channel CH has a relatively long length that extends through all electrode layers 20. Due to this fact, as the current amplitude on the vertical channel CH decreases, the amount of cell current can decrease, and data sensing accuracy may deteriorate. Furthermore, as the difference between the top CD (critical dimension) and the bottom CD of the vertical channel CH increases, the threshold voltage distribution of the electrode layers 20 may deteriorate.

[0106] The capacity of the pump circuit can be increased to compensate for the current consumed in the vertical channel (CH), and tuning schemes can be introduced to compensate for the degradation of the threshold voltage distribution. However, increasing the capacity of the pump circuit increases the size of the semiconductor memory device, and requires significant time and effort to develop the tuning scheme.

[0107] like Figure 8As shown in (b) of this disclosure, according to an embodiment of the present disclosure, electrode layers 20a and 20b are distributed on the top and bottom surfaces of the source plate 10, and the vertical channel CHa or CHb can be configured to have a relatively short length passing through the electrode layer 20b stacked on the top surface of the source plate 10 or the electrode layer 20a stacked on the bottom surface of the source plate 10. Therefore, as the current amplitude in the vertical channels CHa and CHb decreases, the amount of cell current increases, thereby improving data sensing accuracy. In addition, since the difference between the top CD and the bottom CD of the vertical channels CHa and CHb is reduced, the threshold voltage distribution can be improved.

[0108] Figure 9 This is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0109] Reference Figure 9 The memory system 600 according to the embodiment may include a non-volatile memory device (NVM device) 610 and a memory controller 620.

[0110] The non-volatile memory device 610 can be constructed from the memory device described above and can operate in the manner described above. The memory controller 620 can be configured to control the non-volatile memory device (NVM device) 610. The combination of the non-volatile memory device (NVM device) 610 and the memory controller 620 can be configured as a memory card or a solid-state drive (SSD). SRAM 621 serves as the working memory for the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol for the host connected to the memory system 600.

[0111] Error correction code block (ECC) 624 detects and corrects errors included in data read from non-volatile memory device (NVM device) 610.

[0112] The memory interface (memory I / F) 625 is interfaced with the non-volatile memory device 610 of this embodiment. The processing unit (CPU) 622 performs general control operations for data exchange with the memory controller 620.

[0113] Although not shown in the accompanying drawings, it will be apparent to those skilled in the art that the memory system 600 according to the embodiment may additionally include a ROM storing code data for interfacing with a host. The non-volatile memory device (NVM device) 610 may be configured as a multi-chip package comprising multiple flash memory chips.

[0114] As described above, the memory system 600 according to this embodiment can be configured as a highly reliable storage medium with a low probability of error. Specifically, the non-volatile memory device of this embodiment can be included in memory systems such as solid-state drives (SSDs), which are currently under active research. In this case, the memory controller 620 can be configured to communicate with an external (e.g., a host) via one of various interface protocols such as USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI-E (Rapid Peripheral Component Interconnect) protocol, SATA (Serial Advanced Technology Attached) protocol, PATA (Parallel Advanced Technology Attached) protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Data Center Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

[0115] Figure 10 This is a block diagram illustrating a computing system including a memory device according to an embodiment of the present disclosure.

[0116] Reference Figure 10 The computing system 700 according to an embodiment may include a memory system 710, a microprocessor (CPU) 720, RAM 730, a user interface 740, and a modem 750 (such as a baseband chipset) electrically connected to a system bus 760. In the case where the computing system 700 according to an embodiment is a mobile device, a battery (not shown) may be additionally provided for supplying the operating voltage of the computing system 700. Although not shown in the figures, it will be apparent to those skilled in the art that the computing system 700 according to this embodiment may additionally include an application chipset, a camera image processor (CIS), mobile DRAM, etc. For example, the memory system 710 may be configured to use a non-volatile memory SSD (solid-state drive / disk) to store data. Alternatively, the memory system 710 may be configured as converged flash memory (e.g., OneNAND flash memory).

[0117] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in a descriptive sense only and not as limiting the scope of the technology. The scope of this disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of this disclosure can be interpreted in conjunction with the appended claims and cover all equivalents falling within the scope of the appended claims.

[0118] Cross-references to related applications

[0119] This application claims priority to Korean Patent Application No. 10-2020-0114975, filed with the Korean Intellectual Property Office on September 8, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: A unit wafer comprising: a source plate; a plurality of first word lines stacked at intervals along a plurality of first vertical channels projecting from the bottom surface of the source plate in a vertical direction; a plurality of second word lines stacked at intervals along a plurality of second vertical channels projecting from the top surface of the source plate in the vertical direction; a plurality of first bit lines connected to the plurality of first vertical channels; and a plurality of second bit lines connected to the plurality of second vertical channels. A first peripheral wafer is bonded to the bottom surface of the unit wafer and includes a first row decoder unit that transmits operating voltages to the plurality of first word lines. A second peripheral wafer, bonded to the top surface of the unit wafer, includes: a second row decoder unit that transmits operating voltages to the plurality of second word lines; and a page buffer circuit comprising a plurality of page buffers, wherein each of the plurality of page buffers is commonly connected to one of the plurality of first bit lines and one of the plurality of second bit lines; and Multiple vertical contact structures are respectively connected to the multiple first word lines and pass through the multiple first word lines, the source plate, and the multiple second word lines. The plurality of first position lines are respectively connected to the plurality of second position lines through the plurality of vertical contact structures.

2. The three-dimensional semiconductor memory device according to claim 1, in, The first peripheral wafer also includes a first page buffer circuit unit, which includes multiple first page buffers connected to the plurality of first bit lines, and The second peripheral wafer also includes a second page buffer circuit unit, which includes a plurality of second page buffers connected to the plurality of second bit lines.

3. The three-dimensional semiconductor memory device according to claim 2, further comprising: Peripheral circuits The peripheral circuit is located in the region of the first peripheral wafer where the first row decoder unit and the first page buffer circuit unit are not located, and is located in the region of the second peripheral wafer where the second row decoder unit and the second page buffer circuit unit are not located.

4. The three-dimensional semiconductor memory device according to claim 1, further comprising: Peripheral circuits The peripheral circuit is located in the region of the first peripheral wafer where the first row decoder unit is not located, and in the region of the second peripheral wafer where the second row decoder unit and the page buffer circuit are not located.

5. The three-dimensional semiconductor memory device according to claim 1, wherein, The unit wafer, the first peripheral wafer, and the second peripheral wafer are each divided into a unit region and a thinning region. The plurality of first word lines and the plurality of second word lines are disposed in the unit region, and the first row decoder unit and the second row decoder unit are disposed in the thinning region. The cell region and the thinning region are arranged to minimize the delay of the operating voltage transmitted from the first row decoder unit to the plurality of first word lines.

6. The three-dimensional semiconductor memory device according to claim 2, wherein, The structure above the top surface of the source plate in the unit wafer and the structure below the bottom surface of the source plate in the unit wafer are mirror images of each other.

7. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: A unit wafer, comprising: a source plate; a first memory block including a plurality of first cell strings extending in a vertical direction from the bottom surface of the source plate; a second memory block including a plurality of second cell strings extending in the vertical direction from the top surface of the source plate; a plurality of first bit lines connected to the plurality of first cell strings; and a plurality of second bit lines connected to the plurality of second cell strings. A first peripheral wafer is bonded to the bottom surface of the unit wafer and includes a first row decoder unit that transmits an operating voltage to the first memory block. A second peripheral wafer, bonded to the top surface of the unit wafer, includes: a second row decoder unit that transmits an operating voltage to the second memory block; and a page buffer circuit comprising a plurality of page buffers, wherein each of the plurality of page buffers is commonly connected to one of the plurality of first bit lines and one of the plurality of second bit lines; and Multiple vertical contact structures are respectively connected to the multiple first word lines and pass through the multiple first word lines, the source plate, and the multiple second word lines. The plurality of first position lines are respectively connected to the plurality of second position lines through the plurality of vertical contact structures, and The first storage block and the second storage block are configured to be erased independently of each other.

8. The three-dimensional semiconductor memory device according to claim 7, in, The first peripheral wafer also includes a first page buffer circuit unit, which includes multiple first page buffers connected to the plurality of first bit lines, and The second peripheral wafer also includes a second page buffer circuit unit, which includes a plurality of second page buffers connected to the plurality of second bit lines.

9. The three-dimensional semiconductor memory device according to claim 8, further comprising: Peripheral circuits The peripheral circuit is located in the region of the first peripheral wafer where the first row decoder unit and the first page buffer circuit unit are not located, and is located in the region of the second peripheral wafer where the second row decoder unit and the second page buffer circuit unit are not located.

10. The three-dimensional semiconductor memory device according to claim 7, further comprising: Peripheral circuits The peripheral circuit is located in the region of the first peripheral wafer where the first row decoder unit is not located, and in the region of the second peripheral wafer where the second row decoder unit and the page buffer circuit are not located.

11. The three-dimensional semiconductor memory device according to claim 7, wherein, The unit wafer, the first peripheral wafer, and the second peripheral wafer are each divided into a unit region and a thinning region, and the plurality of first unit strings and the plurality of second unit strings are disposed in the unit region, while the first row decoder unit and the second row decoder unit are disposed in the thinning region. The cell region and the thinning region are arranged to minimize the delay of the operating voltage transmitted from the first row decoder unit to the plurality of first cell strings.

12. The three-dimensional semiconductor memory device according to claim 8, wherein, The structure above the top surface of the source plate in the unit wafer and the structure below the bottom surface of the source plate in the unit wafer are mirror images of each other.

13. The three-dimensional semiconductor memory device according to claim 7, wherein, The first storage block is defined by a plurality of first slits extending in the vertical direction from the bottom surface of the source plate, and the second storage block is defined by a plurality of second slits extending in the vertical direction from the top surface of the source plate.

14. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: A unit wafer, comprising a source plate, a first sub-memory cell array disposed below the source plate, and a second sub-memory cell array disposed above the source plate; A first peripheral wafer is bonded to the bottom surface of the unit wafer and includes a first logic circuit unit that transmits an operating voltage to the first sub-memory cell array. as well as A second peripheral wafer, bonded to the top surface of the unit wafer, and including a second logic circuit unit that supplies operating voltages to the second sub-memory cell array, The unit wafer, the first peripheral wafer, and the second peripheral wafer are each divided into a unit region and a thinning region. The first sub-memory cell array and the second sub-memory cell array are disposed in the unit region, and the first logic circuit unit and the second logic circuit unit are disposed in the thinning region. The cell region and the thinned region are arranged to minimize the delay of the operating voltage supplied from the first logic circuit cell to the first sub-memory cell array.

15. The three-dimensional semiconductor memory device of claim 14, further comprising: Multiple external connection pads are connected to the first logic circuit unit and the second logic circuit unit and are configured to interface with external devices.

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