Substrate selection circuit

Abstract

The present invention discloses a substrate selection circuit, comprising: a selection circuit and a positive feedback amplifier circuit. The selection circuit includes a first switching transistor and a second switching transistor connected in series. The first switching transistor is connected to a first voltage and an output terminal, and the second switching transistor is connected to a second voltage and the output terminal. The positive feedback amplifier circuit compares the first voltage and the second voltage and correspondingly outputs a first signal that is amplified through positive feedback and used to control the conduction of the first switching transistor or a second signal that is used to control the conduction of the second switching transistor. The output terminal outputs an output voltage corresponding to the first voltage or the second voltage through the conduction of the first switching transistor or the second switching transistor. According to the substrate selection circuit of the embodiment of the present invention, through the positive feedback effect and the relatively high amplification factor of the positive feedback amplifier circuit, when the first voltage and the second voltage are close to each other, the larger voltage can still be correctly selected, and at the same time, it has a strong driving ability and a small leakage current at this time.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a substrate selection circuit. Background Art

[0002] Substrate selection circuits are widely used in analog circuit modules, especially in circuits with dual power supplies, such as charger circuits, DC / DC boost circuits, and boost charge pump circuits. Secondly, they are used in the field of driving GPIO ports to prevent leakage current when VCC drops or VCC < GPIO voltage.

[0003] Figure 1 FIG. is a circuit schematic diagram of a substrate selection circuit in the prior art. This substrate selection circuit has a simple structure. As Figure 1 shown, PMOS transistor PM1 and PMOS transistor PM2 are selection and driving transistors. The source of PMOS transistor PM1 is connected to voltage V1, and the gate of PMOS transistor PM1 is connected to voltage V2. The source of PMOS transistor PM2 is connected to voltage V2, and the gate of PMOS transistor PM2 is connected to voltage V1. The drains of PMOS transistor PM1 and PMOS transistor PM2 are connected together and connected to the substrates of PMOS transistor PM1 and PMOS transistor PM2. For this substrate selection circuit, if V1 > V2, PMOS transistor PM1 conducts, PMOS transistor PM2 cuts off, and the output voltage VOUT at the output terminal NW is V1; if V2 > V1, then PMOS transistor PM1 cuts off, PMOS transistor PM2 conducts, and the output voltage VOUT at the output terminal NW is V2. It can be seen that VOUT is the higher one selected from V1 and V2.

[0004] Although the above substrate selection circuit has a simple structure, it has the following disadvantages: The above substrate selection circuit can make a correct selection when V1 and V2 differ greatly, but when V1 and V2 do not differ much and driving ability is required, since neither PMOS transistor PM1 nor PMOS transistor PM2 can conduct fully, VOUT cannot make a correct selection, and there will be leakage current at this time, especially having a low leakage current in the non-working state, and it cannot meet the requirement of having strong driving ability in the working state.

[0005] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0006] An object of the present invention is to provide a substrate selection circuit that can reduce leakage and has strong driving ability.

[0007] To achieve the above object, an embodiment of the present invention provides a substrate selection circuit, including: a selection circuit and a positive feedback amplifier circuit. The selection circuit includes a first switching transistor and a second switching transistor connected in series. The first switching transistor is connected to a first voltage V1 and an output terminal NW, and the second switching transistor is connected to a second voltage V2 and the output terminal NW. The first input terminal and the second input terminal of the positive feedback amplifier circuit are respectively connected to the first voltage V1 and the second voltage V2, and the first output terminal and the second output terminal are respectively connected to the first switching transistor and the second switching transistor. The positive feedback amplifier circuit compares the first voltage V1 and the second voltage V2 and correspondingly outputs a first signal for controlling the first switching transistor to conduct or a second signal for controlling the second switching transistor to conduct through positive feedback amplification. The output terminal NW outputs an output voltage corresponding to the first voltage V1 or the second voltage V2 through the conduction of the first switching transistor or the second switching transistor.

[0008] In one or more embodiments of the present invention, the first switching transistor is a PMOS transistor PM3. The drain of the PMOS transistor PM3 is connected to the first voltage V1, the source and the substrate of the PMOS transistor PM3 are connected and connected to the output terminal NW, and the gate of the PMOS transistor PM3 is connected to the first output terminal of the positive feedback amplifier circuit. The second switching transistor is a PMOS transistor PM4. The drain of the PMOS transistor PM4 is connected to the second voltage V2, the source and the substrate of the PMOS transistor PM4 are connected and connected to the output terminal NW, and the gate of the PMOS transistor PM4 is connected to the second output terminal of the positive feedback amplifier circuit.

[0009] In one or more embodiments of the present invention, the positive feedback amplifier circuit includes a PMOS transistor PM5 and a PMOS transistor PM6. The drain of the PMOS transistor PM5 forms the first input terminal, the gate of the PMOS transistor PM5 is connected to the source and the substrate of the PMOS transistor PM6 and forms the first output terminal, the source and the substrate of the PMOS transistor PM5 are connected and connected to the gate of the PMOS transistor PM6 and form the second output terminal, and the drain of the PMOS transistor PM6 forms the second input terminal.

[0010] In one or more embodiments of the present invention, the positive feedback amplifier circuit further includes a first NMOS transistor connected to the PMOS transistor PM5 and the first output terminal, and a second NMOS transistor connected to the PMOS transistor PM6 and the second output terminal. The drain of the first NMOS transistor is connected to the source of the PMOS transistor PM5, the gate of the first NMOS transistor is connected to the first output terminal, and the source and substrate of the first NMOS transistor are both grounded. The drain of the second NMOS transistor is connected to the source of the PMOS transistor PM6, the gate of the second NMOS transistor is connected to the second output terminal, and the source and substrate of the second NMOS transistor are both grounded. One or a plurality of the first NMOS transistors are provided in sequence, and one or a plurality of the second NMOS transistors are provided in sequence.

[0011] In one or more embodiments of the present invention, current limiting devices are connected between the drain of the PMOS transistor PM3 and the first voltage V1, and between the drain of the PMOS transistor PM4 and the second voltage V2.

[0012] In one or more embodiments of the present invention, current limiting devices are connected between the drain of the PMOS transistor PM5 and the first input terminal, and between the drain of the PMOS transistor PM6 and the second input terminal.

[0013] The present invention also discloses a substrate selection circuit, including: a selection circuit and a current comparator.

[0014] The selection circuit includes a first switching transistor and a second switching transistor connected in series. The first switching transistor is connected to the first voltage V1 and the output terminal NW, and the second switching transistor is connected to the second voltage V2 and the output terminal NW. When the difference between the first voltage V1 and the second voltage V2 is large, the conduction or cutoff of the first switching transistor or the second switching transistor is controlled by comparing the first voltage V1 and the second voltage V2, so as to output an output voltage corresponding to the first voltage V1 or the second voltage V2 through the output terminal NW.

[0015] The current comparator includes: a third switching transistor, a fourth switching transistor, a bias circuit, a first current generating circuit, a second current generating circuit, a first current comparing circuit, and a second current comparing circuit.

[0016] The third switching transistor is connected to the first voltage V1 and the output terminal NW, and the fourth switching transistor is connected to the second voltage V2 and the output terminal NW; a bias circuit is used to provide a bias voltage NW1; a first current generation circuit and a second current generation circuit are respectively connected to the first voltage V1 and the second voltage V2, and simultaneously receive the bias voltage NW1 and respectively generate a current NBIS_IO and a current NBIS_VCC; a first current comparison circuit and a second current comparison circuit both compare the current NBIS_IO and the current NBIS_VCC and respectively output corresponding control signals to control the conduction and cutoff of the third switching transistor and the fourth switching transistor; when the difference between the first voltage V1 and the second voltage V2 is large or relatively close, the output terminal NW outputs an output voltage corresponding to the first voltage V1 or the second voltage V2 according to the conduction of the third switching transistor or the fourth switching transistor.

[0017] In an embodiment further disclosed in the present invention, the bias circuit includes a PMOS transistor PM17 and an NMOS transistor NM10. The substrate and the source of the PMOS transistor PM17 are connected and connected to the output terminal NW. The gate and the drain of the PMOS transistor PM17 are connected and connected to the drain of the NMOS transistor NM10 and simultaneously output the bias voltage NW1. The substrate, the source and the gate of the NMOS transistor NM10 are connected and grounded simultaneously.

[0018] In an embodiment further disclosed in the present invention, the first current generation circuit includes a PMOS transistor PM7 and an NMOS transistor NM5. The substrate of the PMOS transistor PM7 is connected to the output terminal NW. The source of the PMOS transistor PM7 is connected to the first voltage V1. The gate of the PMOS transistor PM7 receives the bias voltage NW1. The drain of the PMOS transistor PM7 is connected to the drain and the gate of the NMOS transistor NM5 and outputs the current NBIS_IO. The substrate and the source of the NMOS transistor NM5 are grounded.

[0019] In an embodiment further disclosed in the present invention, a current limiting device is connected between the source of the PMOS transistor PM7 and the first voltage V1.

[0020] In an embodiment further disclosed in the present invention, the third switching transistor is a PMOS transistor PM15, and the fourth switching transistor is a PMOS transistor PM16. The drain of the PMOS transistor PM15 is connected to the first voltage V1. The gate of the PMOS transistor PM15 is connected to the first current comparison circuit. The substrate and the source of the PMOS transistor PM15 are connected to the output terminal NW. The drain of the PMOS transistor PM16 is connected to the second voltage V2. The substrate and the source of the PMOS transistor PM16 are connected to the output terminal NW. The gate of the PMOS transistor PM16 is connected to the second current comparison circuit.

[0021] In an embodiment further disclosed by the present invention, a current limiting device is connected between the drain of the PMOS transistor PM15 and the first voltage V1, and between the drain of the PMOS transistor PM16 and the second voltage V2.

[0022] In an embodiment further disclosed by the present invention, the first current comparison circuit includes a PMOS transistor PM11, a PMOS transistor PM12, an NMOS transistor NM7, and an NMOS transistor NM9;

[0023] The substrate and the source of the PMOS transistor PM11 are connected and connected to the output terminal NW. The gate and the drain of the PMOS transistor PM11 are connected and connected to the gate of the PMOS transistor PM12 and the drain of the NMOS transistor NM7. The substrate and the source of the NMOS transistor NM7 are grounded. The gate of the NMOS transistor NM7 is used to receive the current NBIS_VCC. The source and the substrate of the PMOS transistor PM12 are connected to the output terminal NW. The drain of the PMOS transistor PM12 is connected to the drain of the NMOS transistor NM9 and outputs a control signal to control the PMOS transistor PM15 to conduct or turn off. The substrate and the source of the NMOS transistor NM9 are grounded. The gate of the NMOS transistor NM9 is used to receive the current NBIS_IO.

[0024] In an embodiment further disclosed by the present invention, the first current comparison circuit further includes an NMOS transistor NM8. The gate, the source, and the substrate of the NMOS transistor NM8 are all grounded. The drain of the NMOS transistor NM8 is connected to the drain of the NMOS transistor NM7.

[0025] In an embodiment further disclosed by the present invention, the circuit structures of the first current generation circuit and the second current generation circuit are the same, and the circuit structures of the first current comparison circuit and the second current comparison circuit are the same.

[0026] In an embodiment further disclosed by the present invention, the first switching transistor is a PMOS transistor PM10, and the second switching transistor is a PMOS transistor PM9. The source of the PMOS transistor PM10 is connected to the first voltage V1 and the gate of the PMOS transistor PM9. The substrate and the drain of the PMOS transistor PM10 are connected to the output terminal NW. The gate of the PMOS transistor PM10 is connected to the second voltage V2 and the source of the PMOS transistor PM9. The substrate and the drain of the PMOS transistor PM9 are connected to the output terminal NW.

[0027] In an embodiment further disclosed by the present invention, a current limiting device is connected between the connection point of the source of the PMOS transistor PM10 and the gate of the PMOS transistor PM9 and the first voltage V1, and between the connection point of the gate of the PMOS transistor PM10 and the source of the PMOS transistor PM9 and the second voltage V2.

[0028] Compared with the prior art, the substrate selection circuit according to the embodiment of the present invention, through the positive feedback effect of the positive feedback amplifier circuit and the relatively high amplification factor, can still correctly select the larger voltage when the first voltage V1 and the second voltage V2 are close to each other, and at the same time has a strong driving ability, and the leakage current at this time is small. Description of the Drawings

[0029] Figure 1 is the circuit schematic diagram of the substrate selection circuit in the prior art;

[0030] Figure 2 is the circuit schematic diagram of the substrate selection circuit according to an embodiment of the present invention;

[0031] Figure 3 is the first waveform diagram of the DC scan simulation according to an embodiment of the present invention;

[0032] Figure 4 is the second waveform diagram of the DC scan simulation according to an embodiment of the present invention;

[0033] Figure 5 is the circuit schematic diagram of the substrate selection circuit according to another embodiment of the present invention;

[0034] Figure 6 is the waveform diagram of the DC scan simulation according to another embodiment of the present invention. Detailed Embodiments

[0035] The following will describe in detail the specific embodiments of the present invention with reference to the drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0036] Unless otherwise clearly stated, throughout the specification and claims, the term "comprising" or its variations such as "comprises" or "including" etc. will be understood to include the stated elements or components, without excluding other elements or other components.

[0037] Example 1

[0038] As Figure 2As shown in the figure, a substrate selection circuit includes a selection circuit and a positive feedback amplifier circuit. Among them, the selection circuit includes a first switching transistor and a second switching transistor connected in series. The first switching transistor is connected to the first voltage V1 and the output terminal NW, and the second switching transistor is connected to the second voltage V2 and the output terminal NW. The first input terminal and the second input terminal of the positive feedback amplifier circuit are respectively connected to the first voltage V1 and the second voltage V2, and the first output terminal and the second output terminal are respectively connected to the first switching transistor and the second switching transistor. The positive feedback amplifier circuit compares the first voltage V1 and the second voltage V2 and correspondingly outputs a first signal that is amplified through positive feedback and used to control the conduction of the first switching transistor or a second signal that is used to control the conduction of the second switching transistor. The output terminal NW outputs an output voltage corresponding to the first voltage V1 or the second voltage V2 through the conduction of the first switching transistor or the second switching transistor.

[0039] In this embodiment, the first switching transistor is the PMOS transistor PM3, and the drain of the PMOS transistor PM3 is connected to the first voltage V1. A current limiting device is connected between the drain of the PMOS transistor PM3 and the first voltage V1, and the current limiting device is the resistor R1. Of course, in other embodiments, the current limiting device can be other devices. The source and the substrate of the PMOS transistor PM3 are connected and connected to the output terminal NW, and the gate of the PMOS transistor PM3 is connected to the first output terminal of the positive feedback amplifier circuit.

[0040] In this embodiment, the second switching transistor is the PMOS transistor PM4, and the drain of the PMOS transistor PM4 is connected to the second voltage V2. A current limiting device is connected between the drain of the PMOS transistor PM4 and the second voltage V2, and the current limiting device is the resistor R4. Of course, in other embodiments, the current limiting device can be other devices. The source and the substrate of the PMOS transistor PM4 are connected and connected to the output terminal NW, and the gate of the PMOS transistor PM4 is connected to the second output terminal of the positive feedback amplifier circuit.

[0041] As Figure 2As shown, the positive feedback amplifier circuit includes PMOS transistor PM5 and PMOS transistor PM6. The drain of PMOS transistor PM5 forms a first input terminal and is connected to the first voltage V1 through the first input terminal. A current limiting device is connected between the drain of PMOS transistor PM5 and the first input terminal. The current limiting device is resistor R2. Of course, in other embodiments, the current limiting device can be other devices. The gate of PMOS transistor PM5 is connected to the source and substrate of PMOS transistor PM6 and forms a first output terminal connected to the gate of PMOS transistor PM3. The source and substrate of PMOS transistor PM5 are connected and connected to the gate of PMOS transistor PM6 and form a second output terminal connected to the gate of PMOS transistor PM4. The drain of PMOS transistor PM6 forms a second input terminal and is connected to the second voltage V2 through the second input terminal. A current limiting device is connected between the drain of PMOS transistor PM6 and the second input terminal. The current limiting device is resistor R3. Of course, in other embodiments, the current limiting device can be other devices. In this embodiment, the positive feedback amplifier circuit has a relatively high amplification factor.

[0042] As Figure 2 shown, the positive feedback amplifier circuit further includes a first NMOS transistor connected to PMOS transistor PM5 and the first output terminal and a second NMOS transistor connected to PMOS transistor PM6 and the second output terminal. Both the first NMOS transistor and the second NMOS transistor are used to reduce power consumption. Therefore, the number of the first NMOS transistor and the second NMOS transistor can be set according to needs, and one or a plurality of them connected in sequence can be set.

[0043] For example, two first NMOS transistors are provided, which are the first NMOS transistor NM1 and the first NMOS transistor NM2 respectively. Two second NMOS transistors are provided, which are the second NMOS transistor NM3 and the second NMOS transistor NM4 respectively. The drain of the first NMOS transistor NM2 is connected to the source of PMOS transistor PM5. The gate of the first NMOS transistor NM2 is connected to the first output terminal and the gate of PMOS transistor PM3. The substrate of the first NMOS transistor NM2 is grounded. The drain of the first NMOS transistor NM1 is connected to the source of the first NMOS transistor NM2. The gate of the first NMOS transistor NM1 is connected to the first output terminal and the gate of PMOS transistor PM3. The source and substrate of the first NMOS transistor NM1 are both grounded. The drain of the second NMOS transistor NM4 is connected to the source of PMOS transistor PM6. The gate of the second NMOS transistor NM4 is connected to the second output terminal and the gate of PMOS transistor PM4. The substrate of the second NMOS transistor NM4 is grounded. The drain of the second NMOS transistor NM3 is connected to the source of the second NMOS transistor NM4. The source and substrate of the second NMOS transistor NM3 are both grounded.

[0044] It can be seen that when multiple first NMOS transistors are connected, the drain of the first first NMOS transistor is connected to the source of PMOS transistor PM5, the gate of the first first NMOS transistor is connected to the first output terminal, the gate of the last first NMOS transistor is connected to the first output terminal, the source is grounded, the sources and drains of adjacent two first NMOS transistors are connected while the gates are connected to each other and to the first output terminal, and the substrates of all first NMOS transistors are grounded. When multiple second NMOS transistors are connected, the drain of the first second NMOS transistor is connected to the source of PMOS transistor PM6, and the gate of the last second NMOS transistor is connected to the second output terminal. The gate of the last second NMOS transistor is connected to the second output terminal, the source of the last second NMOS transistor is grounded, the sources and drains of adjacent two second NMOS transistors are connected while the gates are connected to each other and to the second output terminal, and the substrates of all second NMOS transistors are grounded.

[0045] In this embodiment, initially, the voltages of the source terminal and the drain terminal of PMOS transistor PM5 are close, and the voltage difference between them is only Vth5. The potentials of the source terminal and the drain terminal of PMOS transistor PM6 are close, and the voltage difference between them is only Vth6. It is generally considered that Vth5≈Vth6 = Vth. The positive feedback amplifier circuit has a first flip threshold VT1 and a second flip threshold VT2. It is generally considered that the first flip threshold VT1≈V1 + 0.5Vth, and the second flip threshold VT2≈V1 - 0.5Vth.

[0046] It is preset that the first flip threshold VT1 is greater than the second flip threshold VT2, and the first voltage V1 is a fixed voltage. When the second voltage V2 is greater than the first flip threshold VT1, V2>>V1. At this time, the gate-source voltage VSG6 of PMOS transistor PM6 is V2, and the second voltage V2 is greater than Vth6. While the gate-source voltage VSG5 of PMOS transistor PM5 is V1 - V2, and V1 - V2 is less than Vth5, making PMOS transistor PM6 conduct and PMOS transistor PM5 turn off. Furthermore, PMOS transistor PM3 turns off and PMOS transistor PM4 conducts, and the output terminal NW selects to output the second voltage V2. When the second voltage V2 is less than the second flip threshold VT2, V2<<V1, the gate-source voltage VSG6 of PMOS transistor PM6 = V2 - V1, V2 - V1 < Vth6, while the gate-source voltage VSG5 of PMOS transistor PM5 is V1, and V1 > Vth5, making PMOS transistor PM5 conduct and PMOS transistor PM6 turn off. Furthermore, PMOS transistor PM3 conducts and PMOS transistor PM4 turns off, and the output terminal NW selects to output the first voltage V1.

[0047] When VT2 < V2 < VT1, the substrate selection circuit still cannot select the larger second voltage V2 at this time. The reason is that due to the existence of the hysteresis region, only when the voltage difference between the second voltage V2 and the first voltage V1 exceeds the first flip threshold VT1 of the positive feedback amplifier circuit, the positive feedback amplifier circuit will respond. When the voltage difference between the second voltage V2 and the first voltage V1 is less than the second flip threshold VT2 of the positive feedback amplifier circuit, the positive feedback amplifier circuit can flip to the opposite level again. Therefore, when VT2 < V2 < VT1, PMOS transistor PM3 and PMOS transistor PM4 are turned on simultaneously, but the driving ability is enhanced compared with the traditional substrate selection circuit, and the static leakage current is in the pA order of magnitude.

[0048] However, when V2 = VT1 or V2 = VT2, the positive feedback amplifier circuit is in the critical state of flipping and non-flipping, and the voltage difference between the second voltage V2 and the first voltage V1 is large. The static leakage current in this state is large, about in the μA order of magnitude.

[0049] As Figure 3 shown, the first voltage V1 is set to 5V, and the second voltage V2 gradually increases from 0V to 7V. As can be seen from Figure 3 , when the second voltage V2 is less than 5V, the output terminal NW outputs the first voltage V1; when the second voltage V2 > 5.4V (that is, the first threshold voltage VT1 is 5.4V at this time), the output terminal NW will select to output the second voltage V2. Moreover, it can be seen that when the second voltage V2 = 5.4V, the leakage current is relatively large, about 5μA, and before this inflection point, the leakage current is small, in the pA order of magnitude.

[0050] Another example is Figure 4 shown. The first voltage V1 is set to 5V, and the second voltage V2 gradually decreases from 7V to 0V. As can be seen from Figure 4 , when the second voltage V2 is greater than 5V, the output terminal NW outputs the second voltage V2; when the second voltage V2 < 4.54V (that is, the second threshold voltage VT2 is 4.54V at this time), the output terminal NW will select to output the first voltage V1. Moreover, it can be seen that when the second voltage V2 = 4.54V, the leakage current is relatively large, about 5μA, and before this inflection point, the leakage current is small, in the pA level.

[0051] Embodiment 2

[0052] As Figure 5 shown, to solve the remaining defects in Embodiment 1, this embodiment also provides a substrate selection circuit, including: a selection circuit and a current comparator.

[0053] The selection circuit includes a first switching transistor and a second switching transistor connected in series. The first switching transistor is connected to a first voltage V1 and an output terminal NW, and the second switching transistor is connected to a second voltage V2 and the output terminal NW. When the difference between the first voltage V1 and the second voltage V2 is relatively large, the conduction or cutoff of the first switching transistor or the second switching transistor is controlled by comparing the first voltage V1 and the second voltage V2, so that an output voltage corresponding to the first voltage V1 or the second voltage V2 is output through the output terminal NW.

[0054] In this embodiment, the first switching transistor is a PMOS transistor PM10, and the second switching transistor is a PMOS transistor PM9. The source of the PMOS transistor PM10 is connected to the first voltage V1 and the gate of the PMOS transistor PM9. The substrate and the drain of the PMOS transistor PM10 are connected to the output terminal NW. The gate of the PMOS transistor PM10 is connected to the second voltage V2 and the source of the PMOS transistor PM9. The substrate and the drain of the PMOS transistor PM9 are connected to the output terminal NW.

[0055] A current limiting device for current limiting protection is connected between the connection point of the source of the PMOS transistor PM10 and the gate of the PMOS transistor PM9 and the first voltage V1. The current limiting device is a resistor R6. Of course, in other embodiments, the current limiting device can be other devices. A current limiting device for current limiting protection is connected between the connection point of the gate of the PMOS transistor PM10 and the source of the PMOS transistor PM9 and the second voltage V2. The current limiting device is a resistor R9. Of course, in other embodiments, the current limiting device can be other devices.

[0056] The current comparator includes: a third switching transistor, a fourth switching transistor, a bias circuit 10, a first current generation circuit 20, a second current generation circuit 30, a first current comparison circuit 40, and a second current comparison circuit 50.

[0057] Among them, the third switching transistor is connected to the first voltage V1 and the output terminal NW, and the fourth switching transistor is connected to the second voltage V2 and the output terminal NW. In this embodiment, the third switching transistor is the PMOS transistor PM15, and the fourth switching transistor is the PMOS transistor PM16. The drain of the PMOS transistor PM15 is connected to the first voltage V1, and a current limiting device for current limiting protection is connected between the drain of the PMOS transistor PM15 and the first voltage V1. The current limiting device is the resistor R5. Of course, in other embodiments, the current limiting device can be other devices. The gate of the PMOS transistor PM15 is connected to the first current comparison circuit, and the substrate and source of the PMOS transistor PM15 are connected to the output terminal NW. The drain of the PMOS transistor PM16 is connected to the second voltage V2, the drain of the PMOS transistor PM15 is connected to the first voltage V1, and a current limiting device for current limiting protection is connected between the drain of the PMOS transistor PM16 and the second voltage V2. The current limiting device is the resistor R10. Of course, in other embodiments, the current limiting device can be other devices. The substrate and source of the PMOS transistor PM16 are connected to the output terminal NW, and the gate of the PMOS transistor PM16 is connected to the second current comparison circuit.

[0058] The bias circuit 10 is used to provide the bias voltage NW1. Specifically, the bias circuit 10 includes a PMOS transistor PM17 and an NMOS transistor NM10. The substrate and source of the PMOS transistor PM17 are connected and connected to the output terminal NW. The gate and drain of the PMOS transistor PM17 are connected and connected to the drain of the NMOS transistor NM10 and output the bias voltage NW1 at the same time. The substrate, source and gate of the NMOS transistor NM10 are connected and grounded at the same time.

[0059] As Figure 5 shown, the circuit structures of the first current generation circuit and the second current generation circuit are the same. They are respectively connected to the first voltage V1 and the second voltage V2, receive the bias voltage NW1 at the same time, and generate the current NBIS_IO and the current NBIS_VCC respectively.

[0060] Specifically, the first current generation circuit includes a PMOS transistor PM7 and an NMOS transistor NM5. The substrate of the PMOS transistor PM7 is connected to the output terminal NW, and the source of the PMOS transistor PM7 is connected to the first voltage V1. A current limiting device for current limiting protection is connected between the source of the PMOS transistor PM7 and the first voltage V1. The current limiting device is the resistor R7. Of course, in other embodiments, the current limiting device can be other devices. The gate of the PMOS transistor PM7 receives the bias voltage NW1. The drain of the PMOS transistor PM7 is connected to the drain and gate of the NMOS transistor NM5 and outputs the current NBIS_IO. The substrate and source of the NMOS transistor NM5 are grounded.

[0061] The second current generation circuit includes PMOS transistor PM8 and NMOS transistor NM6. The substrate of PMOS transistor PM8 is connected to the output terminal NW, and the source of PMOS transistor PM8 is connected to the second voltage V2. A current limiting device for current limiting protection is connected between the source of PMOS transistor PM8 and the second voltage V2. The current limiting device is resistor R8. Of course, in other embodiments, the current limiting device can be other devices. The gate of PMOS transistor PM8 receives the bias voltage NW1. The drain of PMOS transistor PM8 is connected to the drain and gate of NMOS transistor NM6 and outputs the current NBIS_VCC. The substrate and source of NMOS transistor NM6 are grounded.

[0062] As Figure 5 shown, the circuit structures of the first current comparison circuit and the second current comparison circuit are the same. Both compare the current NBIS_IO and the current NBIS_VCC and respectively output corresponding control signals to control the conduction and cutoff of the third switching transistor and the fourth switching transistor. When the difference between the first voltage V1 and the second voltage V2 is relatively large or relatively close, the output terminal NW outputs an output voltage corresponding to the first voltage V1 or the second voltage V2 according to the conduction of the third switching transistor or the fourth switching transistor.

[0063] Specifically, the first current comparison circuit includes PMOS transistors PM11, PM12, NMOS transistors NM7 and NM9.

[0064] The substrate and source of PMOS transistor PM11 are connected and connected to the output terminal NW and the source of PMOS transistor PM10. The gate and drain of PMOS transistor PM11 are connected and connected to the gate of PMOS transistor PM12 and the drain of NMOS transistor NM7. The substrate and source of NMOS transistor NM7 are grounded. The gate of NMOS transistor NM7 is used to receive the current NBIS_VCC. The source and substrate of PMOS transistor PM12 are connected and connected to the output terminal NW and the source of PMOS transistor PM10. The drain of PMOS transistor PM12 is connected to the drain of NMOS transistor NM9 and the gate of PMOS transistor PM15 and outputs a control signal to control the conduction or cutoff of PMOS transistor PM15. The substrate and source of NMOS transistor NM9 are grounded. The gate of NMOS transistor NM9 is used to receive the current NBIS_IO.

[0065] The first current comparison circuit further includes NMOS transistor NM8. The gate, source and substrate of NMOS transistor NM8 are all grounded. The drain of NMOS transistor NM8 is connected to the drain of NMOS transistor NM7.

[0066] The second current comparison circuit includes PMOS transistors PM13, PM14, NMOS transistors NM11 and NM13.

[0067] The substrate and source of PMOS transistor PM14 are connected and connected to the output terminal NW and the source of PMOS transistor PM16. The gate and drain of PMOS transistor PM14 are connected and connected to the gate of PMOS transistor PM13 and the drain of NMOS transistor NM13. The substrate and source of NMOS transistor NM13 are grounded. The gate of NMOS transistor NM13 is used to receive the current NBIS_IO. The source and substrate of PMOS transistor PM13 are connected and connected to the output terminal NW and the source of PMOS transistor PM16. The drain of PMOS transistor PM13 is connected to the drain of NMOS transistor NM11 and the gate of PMOS transistor PM16 and outputs a control signal to control the conduction or turn-off of PMOS transistor PM16. The substrate and source of NMOS transistor NM11 are grounded. The gate of NMOS transistor NM11 is used to receive the current NBIS_VCC.

[0068] The first current comparison circuit further includes an NMOS transistor NM12, and the gate, source, and substrate of the NMOS transistor NM12 are all grounded. The drain of the NMOS transistor NM12 is connected to the drain of the NMOS transistor NM13.

[0069] The NMOS transistors NM8 and NM12 are protection transistors, which are used to ensure the turn-off of the PMOS transistors PM15 and PM16 when the current comparator fails.

[0070] When the voltage difference between the first voltage V1 and the second voltage V2 is large, if the first voltage V1 is greater than the second voltage V2, the PMOS transistor PM10 conducts, and the output terminal NW outputs the first voltage V1. If the first voltage V1 is less than the second voltage V2, the PMOS transistor PM9 conducts, and the output terminal NW outputs the second voltage V2. The corresponding current comparator will also respond, causing one of the PMOS transistors PM15 and PM16 to conduct and the other to turn off.

[0071] When the first voltage V1 and the second voltage V2 are close, especially when |V1 - V2| < |Vth|, the role of the current comparator becomes particularly important. At this time, the PMOS transistors PM10 and PM9 conduct simultaneously, and the driving ability is weak. Wherein, Vth is the voltage between the source and drain of the PMOS transistor PM10, and the voltage between the source and drain of the PMOS transistor PM9 is equal to the voltage between the source and drain of the PMOS transistor PM10.

[0072] The bias circuit 10 provides a bias voltage NW1. After receiving the bias voltage NW1, the first current generation circuit and the second current generation circuit can amplify the input signals thereof, and respectively output a current NBIS_IO and a current NBIS_VCC. The first current comparison circuit receives the current NBIS_IO and the current NBIS_VCC, and performs comparison through a mirror circuit composed of a PMOS transistor PM11 and a PMOS transistor PM12. The second current comparison circuit receives the current NBIS_IO and the current NBIS_VCC, and performs comparison through a mirror circuit composed of a PMOS transistor PM13 and a PMOS transistor PM14. Finally, the PMOS transistor PM15 and the PMOS transistor PM16 are respectively controlled to drive the gate voltage of the PMOS transistor PM15 or the PMOS transistor PM16 to the output terminal NW or the ground, so that the PMOS transistor PM15 or the PMOS transistor PM16 is turned on or off, thereby enabling the output terminal NW to correctly select and output a first voltage V1 or a first voltage V2, and having a very strong driving ability. Because the gate terminal voltage of the PMOS transistor PM15 or the PMOS transistor PM16 can be as low as the ground potential at this time and is in a strong conduction state.

[0073] In this embodiment, by providing a current comparator, there is no hysteresis interval and the sensitivity is higher; in addition, the path from the output terminal NW to the ground is a high-impedance path, that is, the NMOS transistor NM10 is a reverse-biased NMOS transistor, and the conduction current is in the pA order of magnitude, so low power consumption is achieved. And when the voltage difference between the first voltage V1 and the second voltage V2 is large, the PMOS transistor PM10 and the PMOS transistor PM15 are turned on simultaneously or the PMOS transistor PM9 and the PMOS transistor PM16 are turned on simultaneously. When the voltage of the first voltage V1 and the second voltage V2 is very close, the PMOS transistor PM15 or the PMOS transistor PM16 is strongly turned on, so the driving ability is very strong.

[0074] As Figure 6 shown, the first voltage V1 is set to 5V, and the second voltage V2 gradually increases from 0V to 7V. As can be seen from Figure 6 , regardless of whether the second voltage V2 is less than 5V, equal to 5V or greater than 5V, the NW output terminal can always select the higher voltage between the first voltage V1 and the second voltage V2. At the same time, the corresponding leakage current is very small and is in the nA order of magnitude.

[0075] The foregoing description of specific exemplary embodiments of the present invention is for purposes of illustration and exemplification. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many modifications and variations are possible in light of the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the invention and its practical applications, so that those skilled in the art can implement and utilize the various different exemplary embodiments of the invention, as well as various different selections and modifications. The scope of the present invention is intended to be defined by the claims and their equivalents.

Claims

1. A substrate selection circuit, characterized in that Comprising: A selection circuit and a positive feedback amplifier circuit. The selection circuit includes a first switching transistor and a second switching transistor connected in series. The first switching transistor is connected to a first voltage V1 and an output terminal NW. The second switching transistor is connected to a second voltage V2 and the output terminal NW. The first input terminal and the second input terminal of the positive feedback amplifier circuit are respectively connected to the first voltage V1 and the second voltage V2, and the first output terminal and the second output terminal are respectively connected to the first switching transistor and the second switching transistor. The positive feedback amplifier circuit compares the first voltage V1 and the second voltage V2 and correspondingly outputs a first signal that is amplified through positive feedback and used to control the conduction of the first switching transistor or a second signal that is used to control the conduction of the second switching transistor. The output terminal NW outputs an output voltage corresponding to the first voltage V1 or the second voltage V2 through the conduction of the first switching transistor or the second switching transistor. The positive feedback amplifier circuit includes a PMOS transistor PM5 and a PMOS transistor PM6. The drain of the PMOS transistor PM5 forms the first input terminal. The gate of the PMOS transistor PM5 is connected to the source and the substrate of the PMOS transistor PM6 and forms the first output terminal. The source and the substrate of the PMOS transistor PM5 are connected and connected to the gate of the PMOS transistor PM6 and form the second output terminal. The drain of the PMOS transistor PM6 forms the second input terminal. The positive feedback amplifier circuit further includes a first NMOS transistor connected to the PMOS transistor PM5 and the first output terminal and a second NMOS transistor connected to the PMOS transistor PM6 and the second output terminal. The drain of the first NMOS transistor is connected to the source of the PMOS transistor PM5. The gate of the first NMOS transistor is connected to the first output terminal. The source and the substrate of the first NMOS transistor are both grounded. The drain of the second NMOS transistor is connected to the source of the PMOS transistor PM6. The gate of the second NMOS transistor is connected to the second output terminal. The source and the substrate of the second NMOS transistor are both grounded. One or a plurality of the first NMOS transistors are arranged in series. One or a plurality of the second NMOS transistors are arranged in series.

2. The substrate selection circuit according to claim 1, wherein The first switching transistor is a PMOS transistor PM3. The drain of the PMOS transistor PM3 is connected to the first voltage V1. The source and the substrate of the PMOS transistor PM3 are connected and connected to the output terminal NW. The gate of the PMOS transistor PM3 is connected to the first output terminal of the positive feedback amplifier circuit. The second switching transistor is a PMOS transistor PM4. The drain of the PMOS transistor PM4 is connected to the second voltage V2. The source and the substrate of the PMOS transistor PM4 are connected and connected to the output terminal NW. The gate of the PMOS transistor PM4 is connected to the second output terminal of the positive feedback amplifier circuit.

3. The substrate selection circuit according to claim 2, wherein Current limiting devices are connected between the drain of the PMOS transistor PM3 and the first voltage V1 and between the drain of the PMOS transistor PM4 and the second voltage V2.

4. The substrate selection circuit according to claim 1, wherein Current limiting devices are connected between the drain of the PMOS transistor PM5 and the first input terminal and between the drain of the PMOS transistor PM6 and the second input terminal.

5. A substrate selection circuit, characterized in that, Comprising: Selection circuit and current comparator; The selection circuit includes a first switching transistor and a second switching transistor connected in series. The first switching transistor is connected to a first voltage V1 and an output terminal NW, and the second switching transistor is connected to a second voltage V2 and the output terminal NW. When the difference between the first voltage V1 and the second voltage V2 is large, by comparing the first voltage V1 and the second voltage V2, the conduction or cutoff of the first switching transistor or the second switching transistor is controlled, so that an output voltage corresponding to the first voltage V1 or the second voltage V2 is output through the output terminal NW; The current comparator includes: A third switching transistor and a fourth switching transistor. The third switching transistor is connected to the first voltage V1 and the output terminal NW, and the fourth switching transistor is connected to the second voltage V2 and the output terminal NW; A bias circuit for providing a bias voltage NW1; A first current generation circuit and a second current generation circuit, which are respectively connected to the first voltage V1 and the second voltage V2, receive the bias voltage NW1 at the same time and respectively generate a current NBIS_IO and a current NBIS_VCC; and A first current comparison circuit and a second current comparison circuit, both of which compare the current NBIS_IO and the current NBIS_VCC and respectively output corresponding control signals to control the conduction and cutoff of the third switching transistor and the fourth switching transistor; when the difference between the first voltage V1 and the second voltage V2 is large or relatively close, the output terminal NW outputs an output voltage corresponding to the first voltage V1 or the second voltage V2 according to the conduction of the third switching transistor or the fourth switching transistor.

6. The substrate selection circuit according to claim 5, wherein The bias circuit includes a PMOS transistor PM17 and an NMOS transistor NM10. The substrate and the source of the PMOS transistor PM17 are connected and connected to the output terminal NW. The gate and the drain of the PMOS transistor PM17 are connected and connected to the drain of the NMOS transistor NM10 to output the bias voltage NW1 at the same time. The substrate, the source and the gate of the NMOS transistor NM10 are connected and grounded at the same time.

7. The substrate selection circuit according to claim 5, wherein The first current generation circuit includes a PMOS transistor PM7 and an NMOS transistor NM5. The substrate of the PMOS transistor PM7 is connected to the output terminal NW. The source of the PMOS transistor PM7 is connected to the first voltage V1. The gate of the PMOS transistor PM7 receives the bias voltage NW1. The drain of the PMOS transistor PM7 is connected to the drain and the gate of the NMOS transistor NM5 and outputs the current NBIS_IO. The substrate and the source of the NMOS transistor NM5 are grounded.

8. The substrate selection circuit according to claim 7, wherein A current limiting device is connected between the source of the PMOS transistor PM7 and the first voltage V1.

9. The substrate selection circuit according to claim 5, wherein The third switching transistor is a PMOS transistor PM15, and the fourth switching transistor is a PMOS transistor PM16. The drain of the PMOS transistor PM15 is connected to the first voltage V1. The gate of the PMOS transistor PM15 is connected to the first current comparison circuit. The substrate and the source of the PMOS transistor PM15 are connected to the output terminal NW. The drain of the PMOS transistor PM16 is connected to the second voltage V2. The substrate and the source of the PMOS transistor PM16 are connected to the output terminal NW. The gate of the PMOS transistor PM16 is connected to the second current comparison circuit.

10. The substrate selection circuit according to claim 9, wherein A current-limiting device is connected between the drain of the PMOS transistor PM15 and the first voltage V1, and between the drain of the PMOS transistor PM16 and the second voltage V2.

11. The substrate selection circuit according to claim 9, characterized in that, The first current comparison circuit includes a PMOS transistor PM11, a PMOS transistor PM12, an NMOS transistor NM7, and an NMOS transistor NM9. The substrate and source of the PMOS transistor PM11 are connected and connected to the output terminal NW. The gate and drain of the PMOS transistor PM11 are connected and connected to the gate of the PMOS transistor PM12 and the drain of the NMOS transistor NM7. The substrate and source of the NMOS transistor NM7 are grounded. The gate of the NMOS transistor NM7 is used to receive the current NBIS_VCC. The source and substrate of the PMOS transistor PM12 are connected to the output terminal NW. The drain of the PMOS transistor PM12 is connected to the drain of the NMOS transistor NM9 and outputs a control signal to control the conduction or cutoff of the PMOS transistor PM15. The substrate and source of the NMOS transistor NM9 are grounded. The gate of the NMOS transistor NM9 is used to receive the current NBIS_IO.

12. The substrate selection circuit according to claim 11, wherein The first current comparison circuit further includes an NMOS transistor NM8. The gate, source, and substrate of the NMOS transistor NM8 are all grounded. The drain of the NMOS transistor NM8 is connected to the drain of the NMOS transistor NM7.

13. The substrate selection circuit according to claim 5, characterized in that, The circuit structures of the first current generation circuit and the second current generation circuit are the same, and the circuit structures of the first current comparison circuit and the second current comparison circuit are the same.

14. The substrate selection circuit according to claim 5, characterized in that The first switching transistor is a PMOS transistor PM10, and the second switching transistor is a PMOS transistor PM9. The source of the PMOS transistor PM10 is connected to the first voltage V1 and the gate of the PMOS transistor PM9. The substrate and drain of the PMOS transistor PM10 are connected to the output terminal NW. The gate of the PMOS transistor PM10 is connected to the second voltage V2 and the source of the PMOS transistor PM9. The substrate and drain of the PMOS transistor PM9 are connected to the output terminal NW.

15. The substrate selection circuit according to claim 14, wherein, A current-limiting device is connected between the connection point of the source of the PMOS transistor PM10 and the gate of the PMOS transistor PM9 and the first voltage V1, and between the connection point of the gate of the PMOS transistor PM10 and the source of the PMOS transistor PM9 and the second voltage V2.

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