A decoding method and device applied to semi-parallel LDPC decoder

Abstract

The present invention discloses a decoding method and device applied to a semi-parallel LDPC decoder, including: obtaining LDPC decoding associated parameters, and configuring the associated parameters to the semi-parallel LDPC decoder; obtaining first information of the data to be decoded, and using the first information to perform check node update processing to obtain updated check node values; and performing variable node update processing on variable nodes based on the updated check node values, row weight information, and index position information of valid check nodes to obtain updated variable nodes; performing decoding check processing based on the updated variable nodes to obtain decoding results. The present invention realizes the configurability of decoder associated parameters, and the independence of check node updates and variable node updates makes row and column updates synchronized, thereby achieving the purpose of reducing resource overhead and having a wider application scenario.

Description

Technical Field

[0001] The present invention relates to the technical field of digital information transmission, and in particular to a decoding method and device applied to a semi-parallel LDPC decoder. Background Art

[0002] LDPC (low density parity check) can achieve error performance close to the Shannon limit and is widely used in deep space communication, satellite digital video, mobile wireless communication and other fields.

[0003] There are many types of LDPC code decoding algorithms, most of which are essentially based on the message passing decoding algorithm of Tanner graph. According to the different forms of message transmission during the message iteration process, the decoding methods of LDPC codes can be divided into hard decision decoding and soft decision decoding. The main hard decision decoding algorithms include bit flipping algorithm (BF), weighted bit flipping algorithm (WBF), etc.; the soft decoding algorithms mainly include iterative structured belief propagation algorithm (BP), also known as sum-product algorithm (SPA). The LDPC decoder structure can choose to adopt full serial, full parallel or semi-parallel structure. Among them, the full serial LDPC decoder uses a check node update unit and a variable node update unit to traverse all nodes respectively. Its advantages are low resource consumption, low power consumption, and simple connection between the operation unit and the storage; the disadvantage is that the decoding time is extended, which is not suitable for occasions with high-speed decoding requirements. In the full parallel decoder, the traversal process of all check nodes and variable nodes occurs at the same time, the decoding speed is fast, and the resource consumption is also large. It is only suitable for decoding of medium and short code lengths with extremely high requirements for decoding speed. Summary of the invention

[0004] In view of the above problems, the present invention provides a decoding method and device applied to a semi-parallel LDPC decoder, which achieves the purpose of reducing resource overhead and expanding application scenarios.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A decoding method applied to a semi-parallel LDPC decoder, comprising:

[0007] Acquire LDPC decoding associated parameters, and configure the associated parameters to a semi-parallel LDPC decoder, so that the semi-parallel LDPC decoder enters a working state of executing data to be decoded;

[0008] Acquire first information of the data to be decoded, and use the first information to perform check node update processing to obtain updated check node values, wherein the first information includes row multiplicity information of each row and column address parameters and variable node values ​​of valid variable nodes of each row;

[0009] And, based on the updated check node value, the row multiplicity information and the index position information of the valid check node, the variable node update processing is performed on the variable node to obtain an updated variable node;

[0010] A decoding check process is performed based on the updated variable node to obtain a decoding result.

[0011] Optionally, the associated parameters include:

[0012] One or more of the maximum row multiplicity configuration parameter, the maximum column multiplicity configuration parameter, the row multiplicity configuration parameter for each row, the column multiplicity configuration parameter for each row, the valid variable node position configuration parameter for each row, the valid check node position parameter for each column, the code length configuration parameter and the check equation configuration parameter.

[0013] Optionally, the performing check node update processing using the first information to obtain an updated check node value includes:

[0014] According to the row multiplicity information and the valid node information of each row, query and obtain the variable node probability information of each round of each row corresponding to the updated check node information;

[0015] Subtract the decoded soft byte data from the variable node probability information to obtain an intermediate signal;

[0016] Performing cumulative multiplication processing on the intermediate signal to obtain a first result, and obtaining a minimum value based on the intermediate signal to obtain a second result;

[0017] The first result and the second result are multiplied, and the multiplication result is multiplied by a correction factor to obtain an updated check node value.

[0018] Optionally, it also includes:

[0019] The updated check node values ​​are stored to obtain storage information of valid nodes in the target matrix corresponding to the data to be decoded.

[0020] Optionally, performing variable node update processing on the variable node based on the updated check node value, the row multiplicity information and the index position information of the valid check node to obtain the updated variable node includes:

[0021] Based on the updated check node value, the row multiplicity information and the index position information of the valid check node, performing an accumulation operation on the variable node to obtain an accumulation result;

[0022] The data to be decoded is added to the corresponding variable node index position, and the variable node update operation is performed based on the accumulated result to obtain an updated variable node.

[0023] Optionally, it also includes:

[0024] The updated variable nodes are stored in a data storage medium for storing variable node probability information after each round of iteration update to obtain variable node probability information.

[0025] Optionally, performing decoding verification processing based on the updated variable node to obtain a decoding result includes:

[0026] Obtain the variable node probability information value of the previous input corresponding to the updated variable node, and convert the variable node probability information value less than 0 to 1, and convert the remaining to 0, to obtain the converted variable node probability information;

[0027] If the valid identification signal corresponding to the converted variable node probability information is pulled high, the column weight of each column and the index value of the row position of each column are obtained for each beat update;

[0028] Reading out the internal cached data according to the index value of each column and row position, performing calculations with the corresponding input probability information, and writing the obtained index information back to the corresponding index position;

[0029] When all the input data are calculated in response to the corresponding processing based on the index writeback, the internal cache data is verified. If all are 0, a decoding success signal is output, and the converted valid data of the cache is output;

[0030] If not all 0, check whether the current iteration number is equal to the set iteration number. If so, output a decoding success signal and output the cached converted valid data;

[0031] If it is not equal to the set number of iterations, only a decoding success signal is output.

[0032] A decoding device applied to a semi-parallel LDPC decoder, comprising:

[0033] A configuration unit, configured to obtain LDPC decoding associated parameters, and configure the associated parameters to a semi-parallel LDPC decoder, so that the semi-parallel LDPC decoder enters a working state of executing data to be decoded;

[0034] A first processing unit is used to obtain first information of the data to be decoded, and use the first information to perform check node update processing to obtain updated check node values, wherein the first information includes row multiplicity information of each row and column address parameters and variable node values ​​of valid variable nodes of each row;

[0035] Furthermore, a second processing unit is used to perform variable node update processing on the variable node based on the updated check node value, the row multiplicity information and the index position information of the valid check node to obtain an updated variable node;

[0036] The decoding unit is used to perform decoding verification processing based on the updated variable node to obtain a decoding result.

[0037] A storage medium stores executable instructions, and when the instructions are executed by a processor, the decoding method applied to a semi-parallel LDPC decoder as described in any one of the above items is implemented.

[0038] An electronic device, comprising:

[0039] Memory, used to store programs;

[0040] A processor is used to execute the program, wherein the program is specifically used to implement the decoding method applied to the semi-parallel LDPC decoder as described in any one of the above.

[0041] Compared with the prior art, the present invention provides a decoding method and device for a semi-parallel LDPC decoder, including: obtaining LDPC decoding associated parameters, and configuring the associated parameters to the semi-parallel LDPC decoder, so that the semi-parallel LDPC decoder enters a working state of executing data to be decoded; obtaining first information of the data to be decoded, and using the first information to update the check node to obtain an updated check node value, the first information includes row multiplicity information of each row and column address parameters and variable node values ​​of the valid variable nodes of each row; and, based on the updated check node value, row multiplicity information and index position information of the valid check node, the variable node is updated to obtain an updated variable node; based on the updated variable node, a decoding check is performed to obtain a decoding result. The present invention realizes the configurability of decoder associated parameters, and the independence of check node update and variable node update makes row and column updates synchronized, thereby achieving the purpose of reducing resource overhead and having a wider application scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0043] Figure 1 A flowchart of a decoding method applied to a semi-parallel LDPC decoder provided by an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a decoding effect under different conditions provided by an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of the structure of a decoding device applied to a semi-parallel LDPC decoder provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The terms "first" and "second" and the like in the specification and claims of the present invention and the above drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0048] In an embodiment of the present invention, a decoding method applied to a semi-parallel LDPC decoder is provided. The method is implemented based on a sum-product algorithm (SPA). In the embodiment of the present invention, the check matrix H of the LDPC decoding is a quasi-circular matrix with M rows and N columns, and is composed of J*K (J=M / Z, K=N / Z) block Z*Z circulant sub-matrices.

[0049] In order to facilitate the iterative structure of the belief propagation algorithm (BP), the following symbols are defined:

[0050] H ji represents the element in the jth row and ith column of the check matrix H;

[0051] V j All the j-th check nodes f j The combination of connected variable nodes;

[0052] V j\i Except for variable nodes c i , all the nodes with the jth check node f j The combination of connected variable nodes;

[0053] C i All nodes c with the i-th variable i The combination of connected check nodes;

[0054] C i\j Except for the check nodes j , all nodes c with the i-th variable iThe combination of connected check nodes;

[0055] P i b =Pr(c i =b|y i ) represents c obtained based on the received signal value y and channel characteristics i The probability of taking the value b, where b∈{0,1}; it is easy to know that P i 0 +P i 1 =1,P i b Can be regarded as variable node c i The prior probability of

[0056] q ij (b) represents the check node set C i\j The i-th variable node c is obtained i = the probability of b, obviously q ij (0)+q ij (1) = 1, q ij (b) can be regarded as variable node c i To the check node f j the message delivered;

[0057] r ji (b) means that given c i =b and the probability distribution of other variable nodes {q i'j (b):i'∈V j\i}, the conditional probability that the jth verification equation is true. ji (b) can be regarded as a check node f j To variable node c i The message delivered.

[0058] The SPA algorithm in the frequency domain can be divided into the following steps:

[0059] (1) Initialization: preset the prior probability of information bits for a specific channel:

[0060]

[0061] (2) Horizontal iteration process (updating check nodes), calculation:

[0062]

[0063] r ji (1) = 1-r ji (0)

[0064] By observing the expression of the check equation, we can find that the condition for the check equation corresponding to a row of the check matrix to be valid is that there must be an even number of "1"s in the variable nodes participating in the check equation. i = 0, in order to satisfy the jth check equation, then {c i' :i'∈V j\i} must contain an even number of "1".

[0065] (3) Vertical iteration process (update variable nodes), calculate:

[0066]

[0067] Among them, K ij To make q ij (0)+q ij (1) = coefficient of 1.

[0068] (4) Calculate the posterior probability of the i-th variable node:

[0069]

[0070] Among them, K i To make Q i (0)+Q i (1) = coefficient of 1.

[0071] (5) Hard decision and iterative stop check:

[0072]

[0073] For each bit c i ,i=1,2,…,N,if Q i (0)>0.5, then otherwise Calculate the syndrome If s=0, it means the decoding is successful, then the decoding is stopped and The value of is output as the decoding result; otherwise, go to step (2) to continue iterating. If the number of iterations has reached the maximum number of iterations set in advance and the decoding has not been successfully completed, the decoding ends and the decoding fails. value as output.

[0074] If the probability message is represented by the log-likelihood ratio (LLR), the log-domain SPA decoding algorithm can be obtained from the probability domain SPA algorithm. Decoding in the logarithmic domain has two advantages: first, a large number of multiplication operations in the probability domain can be converted into addition operations in the logarithmic domain; second, the coefficient normalization step is omitted, which improves the stability of the calculation.

[0075] Furthermore, the present invention proposes a parameter-configurable semi-parallel LDPC decoder structure, which can reduce resource overhead and support flexible configuration of multiple matrix H generation matrix types under certain conditions, making the application scenarios broader.

[0076] See also Figure 1 , which is a flowchart of a decoding method applied to a semi-parallel LDPC decoder provided by an embodiment of the present invention, may include the following steps:

[0077] S101, obtaining LDPC decoding associated parameters, and configuring the associated parameters to a semi-parallel LDPC decoder.

[0078] According to the actual application scenario, the LDPC decoding related parameters can be configured to the semi-parallel LDPC decoder. The related parameters include: a maximum row multiplicity configuration parameter, a maximum column multiplicity configuration parameter, a row multiplicity configuration parameter for each row, a column multiplicity configuration parameter for each row, a valid variable node position configuration parameter for each row, a valid check node position parameter for each column, a code length configuration parameter, and a check equation configuration parameter. One or more.

[0079] Assuming that the code length is H matrix, the dimension is NxK, and the block quasi-cyclic matrix is ​​an LxL square matrix, if the design multiplexing index is L, K / L horizontal operation units (HPUs) and N / L vertical operation units (VPUs) are required. Since in the embodiment of the present invention, the configuration of the semi-parallel LDPC decoder can be realized based on the selected associated parameters, so that the semi-parallel LDPC decoder enters the working state of executing the data to be decoded. Specifically, it can be realized: support the maximum row weight to be configurable (the maximum value is less than or equal to K); support the maximum column weight to be configurable (the maximum value is less than or equal to J); support the row weight of each row to be configurable; support the column weight of each column to be configurable; support the valid variable node position of each row to be configurable; support the valid check node position of each column to be configurable; support the code length N to be configurable; support the number of check equations M to be configurable.

[0080] It should be noted that the decoder structure in the embodiment of the present invention needs to save the index position information of its valid nodes for a specific check matrix: the column address with a value of 1 in the corresponding row and the row address with a value of 1 in the corresponding column, and allocate storage space (RAM depth is Z) for each cyclic sub-matrix separately. According to the characteristics of the quasi-cyclic matrix, there will be no address conflict; in addition, it is necessary to save the column weight indication of the code length N and the row weight indication of the number of check equations M. According to the characteristics of the quasi-cyclic matrix, the node information used for the current check node update calculation can be determined from which position of the check matrix. It is similar when updating the variable node.

[0081] For example, for a 2 / 3 code rate, code length 3072, number of check equations 1024, and quasi-circular matrix 128*128 LDPC code, the decoder is configured in combination with the characteristics of the LDPC code matrix. The row weight of each row can be configured (supporting different row weights for each row), the column weight of each column can be configured (supporting different column weights for each column), the position of each row's valid variable node, and the position of each column's valid check node. The code length N is configured to 3072, and the number of check equations M is configured to 1024.

[0082] After configuring a certain LDPC code parameter, the decoding process under this H generation matrix can be started; after each decoding data comes in, the decoder will enter the initialization state and initialize the prior probability information of the variable node; and store the data to be decoded into the rx_data_buf module at the same time, where the rx_data_buf module mainly completes the caching of the input decoding soft bit data.

[0083] S102: Acquire first information of the data to be decoded, and use the first information to perform check node update processing to obtain updated check node values.

[0084] The first information includes row multiplicity information of each row, column address parameters of valid variable nodes of each row, and variable node values.

[0085] In one implementation of the embodiment of the present invention, the use of the first information to perform check node update processing to obtain an updated check node value includes: querying and obtaining the variable node probability information of each row and each round corresponding to the updated check node information according to the row multiplicity information and the valid node information of each row; subtracting the decoded soft byte data from the variable node probability information to obtain an intermediate signal; performing cumulative multiplication processing on the intermediate signal to obtain a first result, and obtaining a minimum value based on the intermediate signal to obtain a second result; multiplying the first result and the second result, and multiplying the multiplication result by a correction factor to obtain an updated check node value. Among them, the first result is the cumulative multiplication result of the intermediate signal, and the second result is the result after taking the minimum value.

[0086] Specifically, after the decoder configuration is completed, it enters the check node update state. In this state, first read out the row weight row_weight_rd_data of each row and the column index address parameter row_vp_index_rd_data of the valid variable node of each row and the variable node value rx_rd_data (the input soft bit information cached by the rx_data_buf module); use the row weight information and the valid variable node information of each row to find out the variable node probability information vp_data of each row in each round that is needed to update the check node information this time; then use vp_data to subtract the soft bit data to be decoded to obtain the intermediate signal vp_sub_lq, and for the vp_sub_lq signal, take the sign bit for cumulative multiplication (XOR implementation) all the way to find the minimum value β i'j (i'∈V j\i ); supports up to N / Z paths to be performed simultaneously, multiplying the output of each minimum value module with the output of the sign accumulation module of its corresponding node (no multiplier is required for implementation), and then multiplying it by the alpha correction factor to obtain the updated check node value, that is, completing the horizontal iteration process (the check node update calculation is mainly completed in the check_point_calc module, among which the check_point_calc module is used to complete the horizontal iteration process, that is, to complete the check node update calculation).

[0087] Correspondingly, the updated check node value is stored to obtain the storage information of the valid node in the target matrix corresponding to the data to be decoded. The updated value is written back to the cp_vp_memory module and given to the vertical iteration (updating variable nodes) calculation module. The cp_vp_memory module is used to complete the storage of valid node information in the H matrix.

[0088]

[0089] α mn =sgn(q mn );β mn =abs(q mn )

[0090] S103 , performing variable node update processing on the variable node based on the updated check node value, the row multiplicity information and the index position information of the valid check node to obtain an updated variable node.

[0091] While the check nodes are updated row by row, the update operation of the variable nodes can be performed in parallel in a pipeline manner. In one implementation of the embodiment of the present invention, the variable node update processing is performed on the variable node based on the updated check node value, the row multiplicity information and the index position information of the valid check node to obtain the updated variable node, including: based on the updated check node value, the row multiplicity information and the index position information of the valid check node, the variable node is accumulated to obtain the accumulation result; the data to be decoded is added to the corresponding variable node index position, and the variable node update operation is performed based on the accumulation result to obtain the updated variable node.

[0092] Specifically, after receiving the updated check node value, the varient_point_calc module (the varient_point_calc module is used to complete the return value iteration process, that is, to complete the variable node update calculation.) can perform accumulation operations on the variable nodes in combination with the row multiplicity information and the index position signal of the valid check node, and then add the original data to be decoded (rx_data_buf) to the corresponding variable node index position, thereby completing the variable node update operation; the updated variable node is stored in the variable node probability information for storing each round of iterative updates, and the variable node probability information is obtained, that is, written to the variable node probability information vp_data for storing each round of iterative updates, and sent all the way to the decoding module (the decode_out module is used to complete the decoding decision processing).

[0093] S104: Perform decoding processing based on the updated variable node to obtain a decoding result.

[0094] The decoding process performed in the embodiment of the present application is mainly to complete the final decoding verification process of the result of this round of iteration.

[0095] Correspondingly, in a possible implementation, the decoding verification processing is performed based on the updated variable node to obtain the decoding result, including: obtaining the variable node probability information value of the previous stage input corresponding to the updated variable node, and converting the variable node probability information value less than 0 to 1, and converting the remaining to 0, to obtain the converted variable node probability information; if the valid identification signal corresponding to the converted variable node probability information is pulled high, obtaining the column weight of each column and the index value of each column row position for each beat update; reading out the internal cached data according to the index value of each column row position, and comparing it with the corresponding Input probability information for calculation, write the obtained index information back to the corresponding index position; in response to the corresponding processing based on the index write back, when all the input data are calculated, verify the internal cache data, if all are 0, output the decoding success signal, and output the cached converted valid data; if not all are 0, check whether the current iteration round number is equal to the set number of iterations, if so, output the decoding success signal, and output the cached converted valid data; if not equal to the set number of iterations, only output the decoding success signal, do not output the cached converted valid data, and the decoder ends the decoding. Among them, "one beat" refers to a cycle of the clock in the digital circuit, also known as each clock cycle. When the valid identification signal corresponding to the converted variable node probability information is pulled high, it means that the valid identification signal corresponding to the variable node probability information is at a high level 1.

[0096] The present invention stores row multiplicity information, index position signals of valid check nodes, and index position signals of valid variable nodes. That is, independent address storage space is allocated for check node update and variable node accumulation, and the design ensures that check node update and variable node accumulation can be performed in parallel. The accumulation of variable nodes is performed in the corresponding vertical direction after the calculation of the previous check node is completed, avoiding the time of waiting for all variable nodes to be updated and then updating the check node. The time of one decoding iteration is only M+N beats. Moreover, compared with storing the original matrix information, only storing the valid check node information greatly reduces the storage amount and can save a lot of storage resources, so that the decoder can also be applied in some low-end devices of FPGA. In addition, based on the independent storage of the index position signal of the valid check node and the index position signal of the valid variable node, the parameter configuration of the decoder is very flexible by allocating the storage space in units of sub-circular matrices, and under certain conditions, it can be dynamically hot-configured according to the new H matrix without powering off. The application scenario is relatively wide.

[0097] See also Figure 2 , is a schematic diagram of a decoding effect under different conditions provided by an embodiment of the present invention. Figure 2In the embodiment, M=1024, N=3072. In the actual application scenario, for example, for a certain LDPC code with a code rate of 2 / 3, a code length of 3072, a number of check equations of 1024, and a quasi-cyclic matrix of 128*128. Compared with the comparative scheme, the present invention will reduce the RAM consumption by about 50%. In addition, through the optimization design scheme of independently storing the node values ​​in the calculation process, the present invention supports the flexible switching of LDPC decoding of multiple generation matrices. For example, after the circuit is implemented according to the indicators of code length N, number of check equations M, and quasi-cyclic matrix Z*Z, only parameter configuration is required to adapt to any LDPC decoding requirements that meet the LDPC coding rules with any code length less than or equal to N, number of check equations less than or equal to M, and quasi-cyclic matrix dimension less than or equal to Z. There is no need to carry out repeated targeted development for different check matrices H, which is very flexible and convenient in engineering applications, greatly saving costs and reducing development time.

[0098] In another embodiment of the present invention, a decoding device for semi-parallel LDPC decoder is provided. Figure 3 ,include:

[0099] The configuration unit 10 is used to obtain LDPC decoding associated parameters and configure the associated parameters to the semi-parallel LDPC decoder so that the semi-parallel LDPC decoder enters a working state of executing the data to be decoded; the associated parameters include: a maximum row multiplicity configuration parameter, a maximum column multiplicity configuration parameter, a row multiplicity configuration parameter for each row, a column multiplicity configuration parameter for each row, a valid variable node position configuration parameter for each row, a valid check node position parameter for each column, a code length configuration parameter, and a check equation configuration parameter. One or more;

[0100] A first processing unit 20 is used to obtain first information of the data to be decoded, and use the first information to perform check node update processing to obtain updated check node values, wherein the first information includes row multiplicity information of each row and column address parameters and variable node values ​​of valid variable nodes of each row;

[0101] Furthermore, the second processing unit 30 is used to perform variable node update processing on the variable node based on the updated check node value, the row multiplicity information and the index position information of the valid check node to obtain an updated variable node;

[0102] A decoding unit 40, configured to perform decoding verification processing based on the updated variable node to obtain a decoding result;

[0103] The first processing unit is specifically configured to:

[0104] According to the row multiplicity information and the valid node information of each row, query and obtain the variable node probability information of each round of each row corresponding to the updated check node information;

[0105] Subtract the decoded soft byte data from the variable node probability information to obtain an intermediate signal;

[0106] Performing cumulative multiplication processing on the intermediate signal to obtain a first result, and obtaining a minimum value based on the intermediate signal to obtain a second result;

[0107] Multiplying the first result and the second result, and multiplying the multiplication result by a correction factor to obtain an updated check node value;

[0108] The second processing unit is specifically used for:

[0109] Based on the updated check node value, the row multiplicity information and the index position information of the valid check node, performing an accumulation operation on the variable node to obtain an accumulation result;

[0110] The data to be decoded is added to the corresponding variable node index position, and the variable node is updated based on the accumulated result to obtain an updated variable node. Optionally, it also includes:

[0111] The first storage unit is used to store the updated check node value to obtain storage information of valid nodes in the target matrix corresponding to the data to be decoded.

[0112] Optionally, it also includes:

[0113] The second storage unit is used to store the updated variable nodes into a storage unit for storing variable node probability information after each round of iteration update to obtain variable node probability information.

[0114] Furthermore, the decoding unit is specifically used for:

[0115] Obtain the variable node probability information value of the previous input corresponding to the updated variable node, and convert the variable node probability information value less than 0 to 1, and convert the remaining to 0, to obtain the converted variable node probability information;

[0116] If the valid identification signal corresponding to the converted variable node probability information is pulled high, the column weight of each column and the index value of the row position of each column are obtained for each beat update;

[0117] Reading out the internal cached data according to the index value of each column and row position, performing calculations with the corresponding input probability information, and writing the obtained index information back to the corresponding index position;

[0118] When all the input data are calculated in response to the corresponding processing based on the index writeback, the internal cache data is verified. If all are 0, a decoding success signal is output, and the converted valid data of the cache is output;

[0119] If not all 0, check whether the current iteration number is equal to the set iteration number. If so, output a decoding success signal and output the cached converted valid data;

[0120] If it is not equal to the set number of iterations, only a decoding success signal is output.

[0121] Based on the above embodiments, an embodiment of the present application provides a storage medium, wherein the storage medium stores executable instructions, and when the instructions are executed by a processor, the decoding method applied to a semi-parallel LDPC decoder as described in any one of the above embodiments is implemented. .

[0122] An embodiment of the present invention further provides an electronic device, including:

[0123] Memory, used to store programs;

[0124] A processor is used to execute the program, wherein the program is specifically used to implement the decoding method applied to the semi-parallel LDPC decoder as described in any one of the above.

[0125] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0126] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A decoding method applied to a semi-parallel LDPC decoder, characterized in that: include: Acquire LDPC decoding associated parameters, and configure the associated parameters to a semi-parallel LDPC decoder, so that the semi-parallel LDPC decoder enters a working state of executing data to be decoded; The associated parameters include: one or more of a maximum row multiplicity configuration parameter, a maximum column multiplicity configuration parameter, a row multiplicity configuration parameter for each row, a column multiplicity configuration parameter for each row, a valid variable node position configuration parameter for each row, a valid check node position parameter for each column, a code length configuration parameter, and a check equation configuration parameter; Acquire first information of the data to be decoded, and use the first information to perform check node update processing to obtain updated check node values, wherein the first information includes row multiplicity information of each row and column address parameters and variable node values ​​of valid variable nodes of each row; Furthermore, based on the updated check node value, the row multiplicity information and the index position information of the valid check node, a variable node update process is performed on the variable node to obtain an updated variable node; Perform decoding verification processing based on the updated variable node to obtain a decoding result; The using the first information to perform check node update processing to obtain an updated check node value includes: According to the row multiplicity information and the valid node information of each row, query and obtain the variable node probability information of each round of each row corresponding to the updated check node information; Subtract the decoded soft byte data from the variable node probability information to obtain an intermediate signal; Performing cumulative multiplication processing on the intermediate signal to obtain a first result, and obtaining a minimum value based on the intermediate signal to obtain a second result; Multiplying the first result and the second result, and multiplying the multiplication result by a correction factor to obtain an updated check node value; The performing variable node update processing on the variable node based on the updated check node value, the row multiplicity information and the index position information of the valid check node to obtain the updated variable node includes: Based on the updated check node value, the row multiplicity information and the index position information of the valid check node, performing an accumulation operation on the variable node to obtain an accumulation result; The data to be decoded is added to the corresponding variable node index position, and the variable node update operation is performed based on the accumulated result to obtain an updated variable node.

2. The method according to claim 1, characterized in that Also includes: The updated check node values ​​are stored to obtain storage information of valid nodes in the target matrix corresponding to the data to be decoded.

3. The method according to claim 1, characterized in that Also includes: The updated variable nodes are stored in a data structure for storing variable node probability information after each round of iteration update to obtain variable node probability information.

4. The method according to claim 3, characterized in that The decoding verification process is performed based on the updated variable node to obtain a decoding result, including: Obtain the variable node probability information value of the previous input corresponding to the updated variable node, and convert the variable node probability information value less than 0 to 1, and convert the remaining to 0, to obtain the converted variable node probability information; If the valid identification signal corresponding to the converted variable node probability information is pulled high, the column weight of each column and the index value of the row position of each column are obtained for each beat update; Reading out the internal cached data according to the index value of each column and row position, performing calculations with the corresponding input probability information, and writing the obtained index information back to the corresponding index position; When all the input data are calculated in response to the corresponding processing based on the index writeback, the internal cache data is verified. If all are 0, a decoding success signal is output, and the converted valid data of the cache is output; If not all 0, check whether the current iteration number is equal to the set iteration number. If so, output a decoding success signal and output the cached converted valid data; If it is not equal to the set number of iterations, only a decoding success signal is output.

5. A decoding device applied to a semi-parallel LDPC decoder, characterized in that: include: A configuration unit, configured to obtain LDPC decoding associated parameters, and configure the associated parameters to a semi-parallel LDPC decoder, so that the semi-parallel LDPC decoder enters a working state of executing data to be decoded; The associated parameters include: one or more of a maximum row multiplicity configuration parameter, a maximum column multiplicity configuration parameter, a row multiplicity configuration parameter for each row, a column multiplicity configuration parameter for each row, a valid variable node position configuration parameter for each row, a valid check node position parameter for each column, a code length configuration parameter, and a check equation configuration parameter; A first processing unit is used to obtain first information of the data to be decoded, and use the first information to perform check node update processing to obtain updated check node values, wherein the first information includes row multiplicity information of each row and column address parameters and variable node values ​​of valid variable nodes of each row; Furthermore, a second processing unit is used to perform variable node update processing on the variable node based on the updated check node value, the row multiplicity information and the index position information of the valid check node to obtain an updated variable node; A decoding unit, used for performing decoding verification processing based on the updated variable node to obtain a decoding result; The first processing unit is specifically configured to: According to the row multiplicity information and the valid node information of each row, query and obtain the variable node probability information of each round of each row corresponding to the updated check node information; Subtract the decoded soft byte data from the variable node probability information to obtain an intermediate signal; Performing cumulative multiplication processing on the intermediate signal to obtain a first result, and obtaining a minimum value based on the intermediate signal to obtain a second result; Multiplying the first result and the second result, and multiplying the multiplication result by a correction factor to obtain an updated check node value; The second processing unit is specifically configured to: Based on the updated check node value, the row multiplicity information and the index position information of the valid check node, performing an accumulation operation on the variable node to obtain an accumulation result; The data to be decoded is added to the corresponding variable node index position, and the variable node update operation is performed based on the accumulated result to obtain an updated variable node.

6. A storage medium, characterized in that: The storage medium stores executable instructions, and when the instructions are executed by the processor, the decoding method applied to the semi-parallel LDPC decoder as described in any one of claims 1 to 4 is implemented.

7. An electronic device, characterized in that: include: Memory, used to store programs; A processor is used to execute the program, wherein the program is specifically used to implement the decoding method applied to a semi-parallel LDPC decoder as described in any one of claims 1 to 4.

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