Wafer inspection task processing method, device, system and storage medium

Abstract

The present application provides a method, device, system and storage medium for processing wafer detection tasks. The method includes: a resource management node receives a wafer detection task from a storage server, selects a target working node from a plurality of working nodes according to the weight value of each working node connected to the resource management node, and assigns the wafer detection task to the target working node. The target working node selects an idle GPU from the resource pool and assigns the wafer detection task to the idle GPU for execution. The GPU pre-processes the wafer image in the wafer detection task, inputs the processed wafer image into the wafer detection model, and obtains the detection result. Through the above-mentioned two-level task scheduling, the wafer detection task is distributed to the GPUs of each working node for execution, and load balancing between working nodes and GPUs is achieved, which can meet the real-time requirements for defect detection of massive wafer images and improve the throughput of the system for processing wafer detection tasks.

Description

Technical Field

[0001] The present application relates to the field of information processing technology, and in particular to a method, device, system and storage medium for processing wafer inspection tasks. Background Art

[0002] Wafers are the basic raw materials for manufacturing semiconductor devices. High-purity semiconductors are prepared into wafers through processes such as crystal pulling and slicing. Wafers undergo a series of semiconductor manufacturing processes to form extremely small circuit structures, which are then cut, packaged, and tested to become chips, which are widely used in various electronic devices.

[0003] In the case of mass production of wafers, it is completely impossible to rely on manual appearance inspection. Therefore, wafer appearance inspection equipment is often used for quality inspection. The intelligent defect detection algorithm based on deep learning can effectively improve the accuracy of wafer inspection compared with traditional image recognition detection algorithms.

[0004] However, the algorithm based on deep learning is highly complex, and the wafer appearance inspection equipment that relies on the central processing unit (CPU) to provide computing power can no longer meet the real-time requirements of wafer defect detection. Especially with the continuous increase in factory production capacity, there are a large number of wafer images to be inspected every day. The current equipment has limited detection capabilities and low detection efficiency. Summary of the invention

[0005] The present application provides a method, device, system and storage medium for processing wafer inspection tasks to improve the inspection efficiency of the wafer inspection system.

[0006] In a first aspect, an embodiment of the present application provides a method for processing a wafer inspection task, which is applied to a resource management node, wherein the resource management node is connected to a plurality of working nodes, and the method includes:

[0007] Receiving a wafer inspection task from a storage server, wherein the wafer inspection task includes at least one wafer image;

[0008] Determine a target working node according to the weight value of each working node; wherein the target working node is a working node with the largest weight value among the multiple working nodes, and the weight value of each working node is a parameter for allocating wafer inspection tasks determined according to the load information of each working node;

[0009] Send the wafer inspection task to the target working node.

[0010] In one embodiment of the present application, before determining the target working node according to the weight value of each working node, the method further includes:

[0011] Obtaining a load value of each of the working nodes, where the load value is used to indicate the load size of the working node within a preset time period;

[0012] According to the multiple load values ​​of the multiple working nodes, the weight value of each working node is determined; wherein the load size of the working node is negatively correlated with the weight value of the working node.

[0013] In one embodiment of the present application, obtaining the load value of each working node includes:

[0014] Receiving a set of working parameters from each of the working nodes, the set of working parameters including at least one of GPU utilization and available video memory of multiple GPUs of the working node, and CPU utilization and available memory of a central processing unit of the working node;

[0015] According to the working parameter set of each working node, a load value of each working node is determined.

[0016] In one embodiment of the present application, obtaining the load value of each working node includes:

[0017] A load value is received from each of the working nodes, where the load value of each of the working nodes is determined by each of the working nodes according to a set of working parameters.

[0018] In one embodiment of the present application, determining the load value of each working node according to the working parameter set of each working node includes:

[0019] The load value of each working node is determined according to a preset weight value set and a working parameter set of each working node; wherein the preset weight value set includes weight coefficients for indicating the GPU utilization, the available video memory, the CPU utilization and the available memory.

[0020] In one embodiment of the present application, the receiving a set of working parameters from each of the working nodes includes:

[0021] Periodically receiving a set of working parameters from each of the working nodes; or

[0022] When the wafer inspection task of each working node starts or ends execution, a working parameter set is received from each working node.

[0023] In one embodiment of the present application, determining the weight value of each of the working nodes according to the multiple load values ​​of the multiple working nodes includes:

[0024] Obtaining multiple load values ​​of the multiple working nodes;

[0025] Determine a load threshold according to the multiple load values, where the load threshold is used to indicate an average load size of the multiple working nodes;

[0026] A weight value of each of the working nodes is determined according to the load threshold and multiple load values ​​of the multiple working nodes.

[0027] In one embodiment of the present application, determining the weight value of each of the working nodes according to the load threshold and the multiple load values ​​of the multiple working nodes includes:

[0028] Setting the weight value of the working node whose load value is greater than the load threshold to 1; or

[0029] The weight value of the working node whose load value is less than or equal to the load threshold is set to the number of GPUs connected to the working node.

[0030] In a second aspect, an embodiment of the present application provides a processing device for a wafer inspection task, wherein the processing device is connected to a plurality of working nodes, and the processing device includes:

[0031] A receiving module, configured to receive a wafer inspection task from a storage server, wherein the wafer inspection task includes at least one wafer image;

[0032] A processing module, used to determine a target working node according to the weight value of each working node; wherein the target working node is a working node with the largest weight value among the multiple working nodes, and the weight value of each working node is a parameter for allocating wafer inspection tasks determined according to the load information of each working node;

[0033] A sending module is used to send the wafer inspection task to the target working node.

[0034] In a third aspect, an embodiment of the present application provides a processing device for a wafer inspection task, comprising:

[0035] at least one processor; and

[0036] a memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the processing device to perform any method according to the first aspect.

[0038] In a fourth aspect, an embodiment of the present application provides a wafer inspection system, including:

[0039] At least one resource management node, and a plurality of working nodes connected to the resource management node; each of the working nodes comprises a plurality of graphics processing units (GPUs);

[0040] The resource management node is used to execute the method as described in any one of the first aspects.

[0041] In one embodiment of the present application, after receiving the wafer inspection task sent by the resource management node, each of the working nodes selects an idle GPU from multiple GPUs in the working node and assigns the wafer inspection task to the idle GPU for execution.

[0042] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the processor is enabled to execute any one of the methods described in the first aspect.

[0043] The embodiment of the present application provides a method, device, system and storage medium for processing wafer detection tasks. The method includes: a resource management node receives a wafer detection task from a storage server, selects a target working node from a plurality of working nodes according to the weight value of each working node connected to the resource management node, and assigns the wafer detection task to the target working node. The target working node selects an idle GPU from the resource pool, and assigns the received wafer detection task to the idle GPU for execution. The GPU pre-processes the wafer image in the wafer detection task, inputs the processed wafer image into the wafer detection model, and obtains the detection result. Through the above-mentioned two-level task scheduling, the wafer detection task is distributed to the GPUs of each working node for execution, and load balancing between working nodes and GPUs is achieved, which can meet the real-time requirements for defect detection of massive wafer images and improve the throughput of the system for processing wafer detection tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0045] Figure 1 A schematic diagram of the architecture of a wafer inspection system provided in an embodiment of the present application;

[0046] Figure 2 An execution flow chart of a resource management node provided in an embodiment of the present application;

[0047] Figure 3 An execution flow chart of a working node provided in an embodiment of the present application;

[0048] Figure 4 An interactive schematic diagram of a method for processing a wafer inspection task provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of a wafer inspection model training method provided in an embodiment of the present application;

[0050] Figure 6 An interactive schematic diagram of a method for processing a wafer inspection task provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of the structure of a processing device for a wafer inspection task provided in an embodiment of the present application;

[0052] Figure 8 A hardware schematic diagram of a device for processing wafer inspection tasks provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example.

[0055] In addition, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus.

[0056] The technical solution provided in the embodiments of the present application relates to the field of semiconductor wafer production, and in particular to the field of defect detection in the wafer production process.

[0057] The chip (i.e. integrated circuit) industry is a strategic, basic and leading industry for the national economy and social development, and plays a key role in several major fields such as computers, consumer electronics, network communications, and automotive electronics. The chip production and manufacturing process is very complicated. Among them, the surface defects of wafers, which are the main material for manufacturing chips, are the main obstacle affecting product yield. By detecting surface defects on wafers, not only can defective grains be found, but also faults in the process can be judged based on the distribution pattern of defective grains, so that engineers can make process improvements.

[0058] At present, wafer defect detection is mainly divided into two categories: one is to detect the electrical properties of the grains through probe testing, and the other is to detect defects on the surface of the wafer through manual visual inspection. Both methods require experienced engineers to analyze and judge, which is manpower-consuming, labor-intensive and prone to errors. With the continuous increase in factory production capacity, the efficiency of manual detection is low.

[0059] With the continuous development of detection technology, detection methods based on image recognition have emerged, which can improve the efficiency and accuracy of wafer detection to a certain extent. This detection method mainly includes the following steps: first, feature extraction of wafer images is performed, and then the extracted features are input into the machine learning model for judgment, and the wafer defects in the wafer images are classified and identified. Subsequently, a detection method based on deep learning emerged. As the hottest machine learning method at present, deep learning requires a large amount of training data. Compared with the above-mentioned image recognition detection method, it can further improve the accuracy of wafer detection and reduce the false alarm rate. However, the detection method based on deep learning has a higher algorithm complexity, and the equipment that relies on the central processing unit CPU to provide computing power cannot meet the real-time requirements of the algorithm. As the factory production capacity increases, the detection machine will generate a large number of wafer images every day. The current equipment has limited detection capabilities and low detection efficiency.

[0060] In response to the above technical problems, an embodiment of the present application provides a distributed solution based on a GPU cluster, which distributes the detection of wafer images to the GPUs of each working node in the cluster, improves the throughput of intelligent defect detection, and meets the real-time requirements of intelligent defect detection for massive wafer images. The powerful computing power of the GPU is used to perform hardware acceleration on the wafer intelligent defect detection process to reduce latency. In addition, an embodiment of the present application also provides a distributed system architecture based on a GPU cluster, which optimizes the resource utilization of the GPU and improves the throughput of wafer intelligent defect detection through a customized GPU cluster scheduling algorithm for the characteristics of wafer intelligent defect detection.

[0061] Before introducing the processing method of the wafer inspection task provided in the embodiment of the present application, the system architecture of the method is briefly introduced first.

[0062] Figure 1 The schematic diagram of the structure of the wafer inspection system provided in the embodiment of the present application is as follows: Figure 1 As shown, the wafer inspection system provided in this embodiment includes: multiple image acquisition devices, a storage server, and at least one resource management node ( Figure 1 A resource management node is shown), and multiple working nodes. Each image acquisition device is connected to a storage server, the storage server is connected to a resource management node, and the resource management server is connected to multiple working nodes respectively. Each working node includes multiple GPUs, and the GPU is used to actually perform wafer inspection tasks.

[0063] The image acquisition device of this embodiment is used to acquire images of each wafer on the production line, and the image acquisition device stores the acquired wafer images on a storage server. As an example, the image acquisition device can be set on a detection machine on the production line.

[0064] The storage server of this embodiment is used to store wafer images from different image acquisition devices, and trigger the GPU cluster to perform intelligent defect detection on the wafer images. Among them, the GPU cluster includes a resource management node (RMN) and a work node (WN). The resource management node is responsible for the scheduling of wafer detection tasks, and the work node is responsible for the execution of wafer detection tasks.

[0065] In one embodiment of the present application, the storage server sends a wafer inspection task to the resource management node. Through a two-level scheduling algorithm, the wafer inspection task is sent to the GPU that actually executes the task. Specifically, the resource management node assigns the wafer inspection task to the working node, and the working node then assigns the wafer inspection task to the GPU.

[0066] In one embodiment of the present application, the resource management node may use a dynamic weight-based polling algorithm to assign wafer inspection tasks to working nodes, and periodically check the health status of each working node connected to the resource management node.

[0067] For example, Figure 2 The execution flow chart of the resource management node provided in the embodiment of the present application is as follows: Figure 2 As shown, after receiving the wafer inspection task from the storage server, the resource management node first determines whether it is necessary to update the weight of the working node. If it is necessary to update the weight of the working node, the load of the working node is calculated and the weight of the working node is updated. Based on the updated weight, a working node is selected from multiple working nodes and the wafer inspection task is assigned to the selected working node.

[0068] As an example, the resource management node can update the weight of the working node regularly, for example, once every 5 minutes. As an example, the resource management node can update the weight of the working node upon receiving the load information reported by the working node (usually when the load information of the working node changes). The load information of the working node can be the load value of the working node (characterizing the load size of the working node), or it can be a working parameter set of the working node, and the working parameter set includes at least one of the following: the utilization rate of the working node CPU, the available memory, the utilization rate of each GPU of the working node, and the available video memory.

[0069] In one embodiment of the present application, the working node includes multiple GPUs, and the wafer inspection tasks are assigned to the idle GPUs by maintaining the task queue (TaskQueue) and the resource pool (Resource Pool). Among them, the task queue is responsible for maintaining the wafer inspection tasks that need to be executed, and the wafer inspection tasks are executed in the task queue in a "first in, first out" order. The resource pool is responsible for maintaining the GPU in an idle / busy state, and the resource pool includes an idle GPU.

[0070] For example, Figure 3 The execution flow chart of the working node provided in the embodiment of the present application is as follows: Figure 3 As shown, the working node includes two parts, the CPU and the GPU, and the execution process of the working node will run on two hardware devices, the CPU and the GPU. Among them, the CPU part is responsible for the scheduling of wafer inspection tasks from the working node to the GPU, and the wafer inspection tasks are executed in a first-in-first-out order. The GPU part is responsible for the defect detection task of the wafer image in the wafer inspection task, including the preprocessing of the wafer image, the wafer defect detection based on the wafer inspection model, and the post-processing of the inspection results. As an example, the inspection result includes a label value for indicating whether there is a wafer defect in the wafer image, a variety of defect categories, the confidence corresponding to each defect category, and the defect location. The post-processing of the inspection results can be to eliminate the defect categories with lower confidence and retain only the defect categories with the highest confidence and the defect locations of the defect categories.

[0071] As an example, the working node obtains the wafer inspection task from the task queue and determines whether there is an idle GPU in the resource pool. If there is an idle GPU in the resource pool, the working node randomly selects an idle GPU from the resource pool, assigns the wafer inspection task to the idle GPU, and updates the GPU status to busy. After the wafer inspection task is completed, the GPU status is updated to idle. If there is no idle GPU in the resource pool, wait until there is an idle GPU in the resource pool.

[0072] As an example, a wafer inspection model is pre-set in the GPU, and the model can be trained based on any deep learning model. Using the wafer inspection model to detect defects in wafer images requires a lot of computing resources. By performing hardware acceleration on the GPU, the performance can be improved by more than 10 times compared to the CPU, meeting the real-time requirements of wafer inspection.

[0073] The above describes the Figure 1 The information processing process of the system architecture shown in the figure is described in detail below with specific embodiments of the technical solution of the present application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0074] Figure 4 An interactive schematic diagram of a method for processing a wafer inspection task provided in an embodiment of the present application, such as Figure 4 As shown, the processing method provided in this embodiment includes the following steps:

[0075] Step 101: The storage server sends a wafer inspection task to a resource management node, where the wafer inspection task includes at least one wafer image.

[0076] The storage server may be connected to one resource management node or multiple resource management nodes. The steps of this embodiment are described by taking one resource management node as an example.

[0077] In some embodiments, the storage server may send different wafer inspection tasks to multiple resource management nodes at the same time, and each resource management node is responsible for assigning the received wafer inspection task to a working node connected to it.

[0078] Optionally, the storage server may be a network storage server, such as a Network Attached Storage (NAS) server.

[0079] Step 102: The resource management node determines a target working node according to the weight value of each working node.

[0080] Among them, the target working node is the working node with the largest weight value among multiple working nodes, and the weight value of each working node is a parameter used to allocate wafer detection tasks determined according to the load information of each working node.

[0081] The load information of the working node may be a load value, which is used to indicate the load size of the working node within a preset period of time, or a working parameter used to indicate the load status of the working node, and the working parameter includes at least one of the CPU utilization rate, available memory, GPU utilization rate of multiple GPUs, and available video memory of the working node. Among them, available memory refers to the available memory of the CPU, and available video memory refers to the available video memory of the GPU.

[0082] The larger the weight value of the working node in this embodiment, the greater the probability of being assigned to the wafer inspection task; the smaller the weight value of the working node, the smaller the probability of being assigned to the wafer inspection task; if the weight value of the working node is 0, it will not be assigned to the wafer inspection task.

[0083] Optionally, the default weight value of the worker node can be set to the number of GPUs of the worker node, expressed as Where x∈(1,2,…,n), n is a positive integer greater than or equal to 2, and n corresponds to Figure 1 The number of worker nodes in .

[0084] Step 103: The resource management node sends the wafer inspection task to the target working node.

[0085] Step 104: The target working node determines an idle GPU.

[0086] Step 105: The target working node sends a wafer inspection task to the GPU.

[0087] The target working node receives the wafer inspection task sent by the resource management node, determines whether there is an idle GPU in the resource pool, and if so, assigns the wafer inspection task to the idle GPU. If there is no idle GPU in the resource pool, waits for an idle GPU to appear in the resource pool, and then assigns the wafer inspection task to the idle GPU.

[0088] As an example, if there are multiple idle GPUs in the resource pool, the target working node can randomly assign the wafer inspection task to one of the idle GPUs. As another example, if there are multiple idle GPUs in the resource pool, the target working node can assign the wafer inspection task to the idle GPU with the largest video memory based on the video memory size of the GPU.

[0089] Step 106: The GPU executes the wafer detection task.

[0090] The GPU receives the wafer inspection task sent by the working node, and first preprocesses the wafer image in the wafer inspection task to obtain the processed wafer image. Among them, the preprocessing includes at least one of rotation, cropping, scaling, and numerical normalization of the wafer image. Data normalization refers to normalizing the RGB value and position information of each pixel of the wafer image to [0,1]. The advantage of normalizing to [0,1] is that data values ​​of different dimensions (RGB value, position) can be compared through the same dimension, so that the contribution value of each feature to the result is the same. The processed wafer image meets the requirements of the wafer inspection model for input images.

[0091] Then, the processed wafer image is input into a pre-trained wafer detection model to obtain a detection result. The wafer detection model is trained using any deep learning model. The detection result output by the model includes: a label indicating whether there is a wafer defect in the wafer image, a defect category, and at least one of the defect location.

[0092] Exemplarily, the label can be a label value, for example, 0 indicates that there is no wafer defect in the wafer image, and 1 indicates that there is a wafer defect in the wafer image. The defect category can be indicated by the ID of the defect category. Exemplarily, wafer defects include scratch defects, particle defects, poor coating, poor edge coverage and other defects. The defect position indicates the area of ​​the wafer defect, which can be a rectangular area. Accordingly, the rectangular area can be represented by diagonal vertex coordinates or four vertex coordinates.

[0093] Optionally, the detection result also includes the confidence level corresponding to the defect category (which can be understood as a probability value).

[0094] The processing method of the wafer detection task provided in this embodiment is that the resource management node receives the wafer detection task from the storage server, selects the target working node from multiple working nodes according to the weight value of each working node connected to the resource management node, and assigns the wafer detection task to the target working node. The target working node selects an idle GPU from the resource pool and assigns the received wafer detection task to the idle GPU for execution. The GPU pre-processes the wafer image in the wafer detection task, inputs the processed wafer image into the wafer detection model, and obtains the detection result. Through the above-mentioned two-level task scheduling, the wafer detection task is distributed to the GPU of each working node for execution, and load balancing between the working nodes and between the GPUs is achieved, which can meet the real-time requirements for defect detection of massive wafer images and improve the throughput of the system for processing wafer detection tasks.

[0095] In the above embodiment, each GPU of the working node includes a wafer detection model. The training process of the wafer detection model is briefly introduced below with reference to the accompanying drawings. Figure 5The flowchart of the wafer inspection model training process provided in the embodiment of the present application is as follows: Figure 5 As shown, the training method of the wafer inspection model includes the following steps:

[0096] Step 201: Establish an initial wafer inspection model.

[0097] Step 202, obtaining image samples and annotation results of the image samples, wherein the image samples include first image samples of different wafer defect categories and second image samples without wafer defects, and the annotation results include labels for indicating whether there are wafer defects in the image samples, defect category IDs, and defect locations.

[0098] In this embodiment, the first image samples include wafer images at different shooting angles, different wafer defect categories, different wafer defect locations, different surfaces (front and back of the wafer), and different environmental conditions (such as lighting conditions, temperature environment, humidity environment, etc.). Similarly, the second image samples include wafer images without wafer defects at different shooting angles, different surfaces, and different environmental conditions.

[0099] Step 203: Use the image sample as the input of the wafer detection model, use the annotation result of the image sample as the output of the wafer detection model, train the initial wafer detection model, and obtain the wafer detection model.

[0100] The GPU of this embodiment uses the above-mentioned wafer inspection model to perform defect inspection on wafer images, which can greatly improve the inspection accuracy and inspection efficiency.

[0101] Based on the above embodiments, the processing method of the wafer inspection task is described in detail below with reference to the accompanying drawings. Figure 6 An interactive schematic diagram of a method for processing a wafer inspection task provided in an embodiment of the present application, such as Figure 6 As shown, the processing method provided in this embodiment includes the following steps:

[0102] Step 301: The storage server sends a wafer inspection task to a resource management node, where the wafer inspection task includes at least one wafer image.

[0103] Step 302: The resource management node obtains the load value of each working node, where the load value is used to indicate the load size of the working node within a preset time period.

[0104] In one embodiment of the present application, the above step 302 includes: the resource management node receives a set of working parameters from each working node; and determines the load value of each working node according to the set of working parameters of each working node. The set of working parameters includes the GPU utilization and available video memory of multiple GPUs of the working node, and the CPU utilization and available memory of the working node.

[0105] The resource management node can receive the working parameter set from the working node in the following ways:

[0106] In a possible implementation, the resource management node periodically receives a set of working parameters from each working node.

[0107] Optionally, the resource management node may periodically send a query request to multiple working nodes, the query request being used to request the current working status of the working node. In response to the query request, each working node sends a query response to the resource management node, the query response including the current working parameter set of the working node.

[0108] Optionally, the resource management node and the working node agree on a reporting period for the working parameter set, and each working node actively reports the working parameter set to the resource management node according to the reporting period.

[0109] In a possible implementation, when the wafer inspection task of each working node starts or ends execution, the resource management node receives the working parameter set from each working node. For example, when working node 1 assigns the wafer inspection task to GPU1, and GPU1 starts to execute the wafer inspection task, working node 1 reports the working parameter set of working node 1 to the resource management node. For another example, when GPU1 of working node 1 ends execution of the wafer inspection task, working node 1 reports the working parameter set of working node 1 to the resource management node.

[0110] As an example, the resource management node determines the load value of each working node according to the working parameter set of each working node, including: the resource management node determines the load value of each working node according to the preset weight value set and the working parameter set of each working node. The preset weight value set includes weight coefficients for indicating GPU utilization, available video memory, CPU utilization, and available memory.

[0111] Specifically, the resource management node can determine the load value of each working node through the following formula:

[0112]

[0113] Where, L xRepresents the load value of the x-th working node, where x∈(1,2,…,n) and n is a positive integer greater than or equal to 2.

[0114] represents the GPU utilization of the i-th GPU of the x-th worker node, represents the average GPU utilization of all GPUs of the x-th worker node, where i∈(1,2,…,k) and k is a positive integer greater than or equal to 2.

[0115] represents the available video memory capacity of the i-th GPU of the x-th worker node, U CPU Indicates the CPU utilization of the xth worker node, A RAM Indicates the available memory capacity of the xth worker node.

[0116] f GPU Represents the weight coefficient of GPU utilization, f VRAM Represents the weight coefficient of available video memory, f CPU Indicates the weight coefficient of CPU utilization, f RAM Indicates the weight factor of available memory.

[0117] In one embodiment of the present application, the above step 302 includes: the resource management node receives a load value from each working node, and the load value of each working node is determined by each working node according to a set of working parameters. The working node of the above example directly reports its load value to the resource management node, which can reduce the amount of calculation of the resource management node, save some computing resources, and improve the processing performance of the resource management node.

[0118] Step 303: The resource management node determines the weight value of each working node according to the multiple load values ​​of the multiple working nodes. The load value of the working node is negatively correlated with the weight value of the working node, that is, the larger the load value of the working node, the smaller the weight value of the working node, and the smaller the load value of the working node, the larger the weight value of the working node.

[0119] In one embodiment of the present application, the above step 303 includes: the resource management node obtains multiple load values ​​of multiple working nodes, determines a load threshold according to the multiple load values, and determines a weight value of each working node according to the load threshold and the multiple load values ​​of the multiple working nodes. The load threshold is used to indicate the average load size of the multiple working nodes. The load threshold is a dynamically changing threshold, and the resource management node can calculate the load threshold T by the following formula:

[0120]

[0121] Where λ is a coefficient, λ∈[1,+∞), and λ is set to 2 by default.

[0122] In one possible scenario, the resource management node determines that the load value of a working node is greater than the load threshold. The weight value of the working node is set to 1. The probability of the working node being assigned to a task is reduced to The working node in the above situation is identified as a sub-healthy state, indicating that the load of the working node is too large. Therefore, try not to assign new tasks to the working node, which can reduce the probability of the working node being assigned a new task.

[0123] In one possible scenario, the resource management node determines that the load value of a working node is less than or equal to the load threshold. The weight value of the worker node is set to the number of GPUs of the worker node. The probability of the working node being assigned to the task is increased to The working node in the above situation is identified as healthy, indicating that the load of the working node is small. Therefore, the new task is assigned to the working node first, which can increase the probability of the working node being assigned to the new task.

[0124] In addition to the above two situations, there is a special situation: there was originally a connection relationship between a work node and a resource management node, but due to network problems or equipment problems, the work node and the resource management node are disconnected. The work node is considered to be unhealthy, and the resource management node no longer considers assigning new tasks to the work node. The weight value of the work node can be set to 0.

[0125] In a possible implementation, the resource management node can periodically calculate the load threshold, obtain the latest load threshold, and adjust the weight value of each working node based on the load threshold. This method occupies less resources of the resource management node, but the weight value of each working node is not updated in a timely manner.

[0126] In another possible implementation, after receiving the load information reported by the working node (as long as one working node reports updated load information), the resource management node recalculates the load threshold, obtains an updated load threshold, and adjusts the weight value of each working node based on the load threshold. In this way, the weight value of each working node is updated in time, but the resource usage is high.

[0127] Step 304: The resource management node determines a target working node according to the weight value of each working node.

[0128] Step 305: The resource management node sends the wafer inspection task to the target working node.

[0129] Step 306: The target working node determines an idle GPU.

[0130] Step 307: The target working node sends the wafer inspection task to the GPU.

[0131] Step 308: The GPU executes the wafer detection task.

[0132] Steps 304 to 308 of this embodiment are the same as steps 102 to 106 of the above embodiment. For details, please refer to the above embodiment and will not be repeated here.

[0133] The processing method of the wafer detection task provided in the present embodiment, the resource management node receives the wafer detection task from the storage server, obtains the weight value of each working node and the current load threshold, and adjusts the weight value of each working node by comparing the size relationship between the weight value of each working node and the current load threshold. According to the weight value of each working node, the target working node is selected from multiple working nodes, and the wafer detection task is assigned to the target working node. The target working node selects an idle GPU from multiple GPUs and assigns the wafer detection task to the idle GPU for execution. Through the above-mentioned two-level task scheduling, the wafer detection task is distributed to the GPUs of each working node for execution, and load balancing between working nodes and GPUs is achieved, which can meet the real-time requirements for defect detection of massive wafer images and improve the throughput of the system for processing wafer detection tasks.

[0134] The embodiment of the present application can divide the functional modules of the processing device according to the above method embodiment. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The following is an example of using each functional module divided according to each function.

[0135] Figure 7 A schematic diagram of the structure of a processing device for wafer inspection tasks provided in an embodiment of the present application. Figure 7 As shown, the processing device 400 of the wafer inspection task of this embodiment is connected to multiple working nodes, and the processing device 400 includes:

[0136] A receiving module 401 is used to receive a wafer inspection task from a storage server, wherein the wafer inspection task includes at least one wafer image;

[0137] Processing module 402, used to determine a target working node according to the weight value of each working node; wherein the target working node is a working node with the largest weight value among the multiple working nodes, and the weight value of each working node is a parameter for allocating wafer inspection tasks determined according to the load information of each working node;

[0138] The sending module 403 is used to send the wafer inspection task to the target working node.

[0139] In one embodiment of the present application, before determining the target working node according to the weight value of each working node, the processing module 402 is further configured to:

[0140] Obtaining a load value of each of the working nodes, where the load value is used to indicate the load size of the working node within a preset time period;

[0141] According to the multiple load values ​​of the multiple working nodes, the weight value of each working node is determined; wherein the load size of the working node is negatively correlated with the weight value of the working node.

[0142] In one embodiment of the present application, the receiving module 401 is further used to receive a set of working parameters from each of the working nodes, wherein the set of working parameters includes at least one of GPU utilization and available video memory of multiple GPUs of the working node, and CPU utilization and available memory of the central processing unit of the working node;

[0143] The processing module 402 is further configured to determine a load value of each of the working nodes according to a set of working parameters of each of the working nodes.

[0144] In one embodiment of the present application, the receiving module 401 is further used to receive a load value from each of the working nodes, where the load value of each of the working nodes is determined by each of the working nodes according to a set of working parameters.

[0145] In one embodiment of the present application, the processing module 402 is specifically configured to:

[0146] The load value of each working node is determined according to a preset weight value set and a working parameter set of each working node; wherein the preset weight value set includes weight coefficients for indicating the GPU utilization, the available video memory, the CPU utilization and the available memory.

[0147] In one embodiment of the present application, the receiving module 401 is specifically configured to:

[0148] Periodically receiving a set of working parameters from each of the working nodes; or

[0149] When the wafer inspection task of each working node starts or ends execution, a working parameter set is received from each working node.

[0150] In one embodiment of the present application, the processing module 402 is specifically configured to:

[0151] Obtaining multiple load values ​​of the multiple working nodes;

[0152] Determine a load threshold according to the multiple load values, where the load threshold is used to indicate an average load size of the multiple working nodes;

[0153] A weight value of each of the working nodes is determined according to the load threshold and multiple load values ​​of the multiple working nodes.

[0154] In one embodiment of the present application, the processing module 402 is specifically configured to:

[0155] Setting the weight value of the working node whose load value is greater than the load threshold to 1; or

[0156] The weight value of the working node whose load value is less than or equal to the load threshold is set to the number of GPUs of the working node.

[0157] The processing device provided in the embodiment of the present application is used to execute each step of the resource management node in any of the aforementioned method embodiments. Its implementation principle and technical effects are similar and will not be repeated here.

[0158] Figure 8 A hardware schematic diagram of a processing device for wafer inspection tasks provided in an embodiment of the present application. Figure 8 As shown, the processing device 500 for wafer inspection tasks in this embodiment includes:

[0159] At least one processor 501 ( Figure 8 Only one processor is shown); and

[0160] A memory 502 is communicatively connected to the at least one processor; wherein,

[0161] The memory 502 stores instructions that can be executed by the at least one processor 501. The instructions are executed by the at least one processor 501 so that the processing device 500 can execute each step of the resource management node in any of the above method embodiments.

[0162] Optionally, the memory 502 may be independent or integrated with the processor 501 .

[0163] When the memory 502 is a device independent of the processor 501 , the processing device 500 further includes: a bus 503 for connecting the memory 502 and the processor 501 .

[0164] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the technical solution of the resource management node in any of the aforementioned method embodiments.

[0165] The present application also provides a wafer inspection system, which can be referred to as Figure 1 The system comprises:

[0166] At least one resource management node, and multiple working nodes connected to the resource management node, wherein each working node includes multiple graphics processing units (GPUs), and the resource management node is used to execute each step of the resource management node in any of the aforementioned method embodiments.

[0167] In one embodiment of the present application, after receiving the wafer inspection task sent by the resource management node, each working node selects an idle GPU from multiple GPUs in the working node and assigns the wafer inspection task to the idle GPU for execution. The GPU is used to execute the wafer inspection task.

[0168] In one embodiment of the present application, the GPU includes a wafer inspection model, which is trained using a deep learning model and is used to detect whether there are defects in each wafer image in a wafer inspection task, the defect category, and the defect location.

[0169] The wafer inspection system provided in the embodiment of the present application is an inspection system with a distributed architecture based on a GPU cluster, which can realize real-time inspection of massive wafer images generated by defect inspection machines, and can assist the production department to quickly lock in problematic defect inspection machines, thereby helping to find process problems early, respond to process deviations in a timely manner, and significantly reduce the cost of finding problematic machines for inspection, thereby improving process yield and reducing production costs.

[0170] It should be understood that the processor mentioned in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0171] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0172] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0173] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0174] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0175] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for processing a wafer inspection task, characterized in that: Applied to a resource management node, the resource management node is connected to a plurality of working nodes, the method comprises: Receiving a wafer inspection task from a storage server, wherein the wafer inspection task includes at least one wafer image; Determine a target working node according to the weight value of each working node; wherein the target working node is a working node with the largest weight value among the multiple working nodes, and the weight value of each working node is a parameter for allocating wafer inspection tasks determined according to the load information of each working node; Sending the wafer inspection task to the target working node; Before determining the target working node according to the weight value of each working node, the method further includes: Obtaining a load value of each of the working nodes, the load value being used to indicate the load size of the working node within a preset time period; determining a weight value of each of the working nodes according to the multiple load values ​​of the multiple working nodes; wherein the load size of the working node is negatively correlated with the weight value of the working node; wherein obtaining the load value of each of the working nodes includes determining the load value of the working node by the following formula: in, Represents the load value of the xth working node, where , n is a positive integer greater than or equal to 2; represents the GPU utilization of the i-th GPU of the x-th worker node, represents the average GPU utilization of all GPUs of the x-th worker node, where , k is a positive integer greater than or equal to 2; represents the available video memory capacity of the i-th GPU of the x-th worker node, Indicates the CPU utilization of the xth worker node. Indicates the available memory capacity of the xth worker node; Represents the weight coefficient of GPU utilization, Represents the weight coefficient of available video memory, Indicates the weight coefficient of CPU utilization. Indicates the weight factor of available memory.

2. The method according to claim 1, characterized in that The obtaining of the load value of each working node comprises: Receiving a set of working parameters from each of the working nodes, the set of working parameters including at least one of GPU utilization and available video memory of multiple GPUs of the working node, and CPU utilization and available memory of a central processing unit of the working node; According to the working parameter set of each working node, the load value of each working node is determined.

3. The method according to claim 2, characterized in that The receiving a set of working parameters from each working node includes: Periodically receiving a set of working parameters from each of the working nodes; or When the wafer inspection task of each working node starts or ends execution, a working parameter set is received from each working node.

4. The method according to any one of claims 1 to 3, characterized in that The step of determining a weight value of each of the working nodes according to the multiple load values ​​of the multiple working nodes includes: Obtaining multiple load values ​​of the multiple working nodes; Determine a load threshold according to the multiple load values, where the load threshold is used to indicate an average load size of the multiple working nodes; A weight value of each of the working nodes is determined according to the load threshold and multiple load values ​​of the multiple working nodes.

5. The method according to claim 4, characterized in that Determining the weight value of each of the working nodes according to the load threshold and the multiple load values ​​of the multiple working nodes includes: Setting the weight value of the working node whose load value is greater than the load threshold to 1; or The weight value of the working node whose load value is less than or equal to the load threshold is set to the number of GPUs of the working node.

6. A processing device for wafer inspection tasks, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the processing device to perform the method according to any one of claims 1 to 5.

7. A wafer inspection system, characterized in that: include: At least one resource management node, and a plurality of working nodes connected to the resource management node; each of the working nodes comprises a plurality of graphics processing units (GPUs); The resource management node is used to execute the method according to any one of claims 1 to 5.

8. The system according to claim 7, characterized in that After receiving the wafer inspection task sent by the resource management node, each of the working nodes selects an idle GPU from multiple GPUs in the working node and assigns the wafer inspection task to the idle GPU for execution.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the processor is enabled to execute the method according to any one of claims 1 to 5.

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