A ferroelectric memory and a writing operation method thereof

Abstract

The present invention discloses a write operation method of a ferroelectric memory, which receives data to be written through a serial data interface, and starts to pre-read data when a specified data bit is received, and each data pre-read reads data in a storage unit of N bytes, wherein the value of N is equal to the number of bytes of the minimum operation unit of the ferroelectric memory, and after the data pre-read is completed or a rising edge appears on a chip selection signal, 0 is written in the N-byte storage unit for the data pre-read operation, and after the N-byte data is received, 1 is written back in the N-byte storage unit, and then the next N-byte storage unit is pre-read and written back according to the same method until all data are written.

Description

Technical Field

[0001] The present invention relates to the technical field of ferroelectric memory, and in particular to a ferroelectric memory and a writing operation method thereof. Background Art

[0002] In recent years, ferroelectric memory has attracted more and more attention as a new type of memory with high writing speed and high read and write times. Ferroelectric memory is a non-volatile memory with a special process. When an electric field is applied to a ferroelectric transistor, the central atom stays in the first low energy state along the electric field, and when the electric field is reversed and applied to the same ferroelectric transistor, the central atom moves in the crystal along the direction of the electric field and stays in the second low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of the electric field. The polarized charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarized charge formed by the non-reversal of the ferroelectric domain under the electric field is lower. This binary stable state of ferroelectric materials allows ferroelectrics to be used as memory.

[0003] When the electric field is removed, the central atom remains in a low energy state, and the state of the memory is preserved and will not disappear. Therefore, the high polarization charge formed by the reversal of the ferroelectric domain under the electric field or the low polarization charge formed by no reversal can be used to determine whether the memory cell is in the "1" or "0" state. The reversal of the ferroelectric domain does not require a high electric field, but only a normal operating voltage can change the "1" or "0" state of the memory cell; there is no need for a charge pump to generate a high voltage for data erasure, so there is no erase delay. This feature allows the ferroelectric memory to continue to save data after power failure, and it has a fast write speed and an unlimited write life, and is not easy to be damaged. Moreover, compared with existing non-volatile memory technology, ferroelectric memory has a higher write speed and a longer read and write life.

[0004] In the existing ferroelectric memory array design, IO is used as the minimum operation unit, and one IO includes multiple bytes. However, in the actual write operation, data is written byte by byte. This means that every time a byte of data is written, it is necessary to perform a read and write operation on all the bytes in the IO where it is located, which greatly increases the number of write cycles and reduces the stability of the product. Summary of the invention

[0005] In view of some or all of the problems in the prior art, the present invention provides a write operation method for a ferroelectric memory, comprising the steps of:

[0006] receiving data to be written via a serial data interface;

[0007] When receiving the designated data bit, data pre-reading is started, wherein the data pre-reading reads data in N bytes of storage units, wherein the value of N is equal to the number of bytes of the minimum operation unit of the ferroelectric memory;

[0008] After the data pre-reading is completed, writing 0 in the storage unit of the N bytes;

[0009] When N bytes of data are received or a rising edge appears on the chip select signal, write 1 back to the storage unit of the N bytes; and

[0010] The next N bytes of storage units are pre-read and written back until all data are written.

[0011] Furthermore, pre-reading and writing back data for the next N bytes of storage units includes the following steps:

[0012] When the designated time is extended or the designated data bit is received, data pre-reading is started, wherein the data pre-reading reads data in the storage unit of N bytes;

[0013] After the data pre-reading is completed, writing 0 in the storage unit of the N bytes; and

[0014] After receiving N bytes of data, or when a rising edge appears on the chip select signal, 1 is written back to the storage unit of the N bytes.

[0015] Furthermore, the designated data bit is the third or fourth data bit of the first byte of the N bytes.

[0016] Furthermore, the write operation method also includes: after writing back 1, delaying for a specified period of time, and pre-reading and writing back data for the next N bytes of storage units.

[0017] Furthermore, the value of N is 4.

[0018] Furthermore, the data pre-reading includes:

[0019] Applying a voltage to the word line connected to the N bytes of storage cells so that the word line changes from a low level to a high level;

[0020] Applying a voltage to the plate lines connected to the N bytes of storage cells so that the plate lines change from a low level to a high level; and

[0021] By comparing the voltages of the connected bit lines of the memory cells in the N bytes with a reference voltage, it is determined whether the data in the memory cells is "0" or "1".

[0022] Furthermore, the data pre-reading further includes: before applying a voltage to the plate line, clearing and discharging the bit line of the storage unit in the IO.

[0023] Further, writing 0 in the N bytes of storage units includes:

[0024] Controlling the voltage of the bit lines connected to the storage cells in the N bytes to become a low level through the driving circuit, so as to write the data "0"; and

[0025] The plate line voltage connected to the storage cells in the N bytes is controlled to become a low level.

[0026] Furthermore, the write-back 1 includes:

[0027] The voltages of the bit lines connected to the memory cells in the N bytes are controlled to become high level, so that the data "1" is written.

[0028] Another aspect of the present invention provides a ferroelectric memory capable of performing the write operation as described above, the ferroelectric memory comprising:

[0029] A register for storing data pre-read from a storage unit; and

[0030] The counting unit is coupled to the driving circuit and is used for counting the received data bits and sending word line, plate line and bit line driving signals to control the voltages of the word line, plate line and bit line when the count reaches a preset value.

[0031] Furthermore, the counting unit includes a plurality of D flip-flops.

[0032] The present invention provides a ferroelectric memory and a write operation method thereof, based on the inventor's insight that the minimum operation unit of the write operation of the ferroelectric memory usually includes multiple bytes. Therefore, in the existing write operation method, each time a byte of data is written, it is necessary to perform a pre-read and write-back operation on all bytes in the minimum operation unit where the byte is located. This means that when continuous writing is required, each storage unit needs to undergo multiple read and write operations, which is likely to reduce the stability of the ferroelectric memory in the long run. In order to improve product stability and thus ensure product life, it should be considered to reduce the number of read and write times of the storage unit. The inventor further found that, assuming that the minimum operation unit includes N bytes, when the N bytes all need to write new data, it is necessary to perform N pre-read and write-back operations on all storage units in the minimum operation unit, wherein each write-back writes new data in a storage unit of one byte, and the other bytes write back the pre-read data. Therefore, it can be considered to merge them into one time, and write new data in all bytes that need to be updated in the minimum unit at one time. Based on this, the inventor proposes a write operation method, which improves the write operation timing so that data pre-reading and write-back are performed only once in a minimum operation unit. Specifically, data pre-reading is performed after receiving the specified data bit, and after the pre-reading is completed, 0 is first written to all storage cells in the minimum operation unit, and then 1 is written back after receiving all the data in the minimum operation unit. With the write operation method, each storage cell of the ferroelectric memory will only be read and written once, which greatly reduces the number of write cycles and improves the stability of the ferroelectric memory. At the same time, since the writing of 0 has been completed in the process of receiving data, only 1 needs to be written when writing back, which shortens the write-back cycle, thereby ensuring that the input timing of subsequent data is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0034] Figure 1 A schematic diagram of the circuit structure of a 2T2C ferroelectric memory is shown;

[0035] Figure 2 A schematic diagram showing the pre-reading and write-back time nodes of a write operation method of a ferroelectric memory in the prior art;

[0036] Figure 3 A schematic diagram showing the pre-reading and write-back time nodes of a write operation method of a ferroelectric memory in one embodiment of the present invention;

[0037] Figure 4 A schematic flow chart showing a write operation method of a ferroelectric memory according to an embodiment of the present invention;

[0038] Figure 5 A pulse timing diagram showing a write operation method of a ferroelectric memory in one embodiment of the present invention; and

[0039] Figure 6 A schematic structural diagram of a counting unit of a ferroelectric memory according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0040] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0041] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0042] It should be noted that the embodiments of the present invention describe the process steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0043] The present invention may be related to a memory, in particular to a ferroelectric memory. In the present invention, the term "minimum operation unit" refers to a set of storage cells that can be operated at a time in a ferroelectric memory. For example, currently, a common ferroelectric memory can read and write 4 bytes of data at a time, and the minimum operation unit includes a total of 32-bit storage cells corresponding to the 4 bytes of data and a corresponding sensing circuit.

[0044] Figure 1 FIG. 2 shows a schematic diagram of the circuit structure of a 2T2C ferroelectric memory. Figure 1 As shown in FIG. 1 , in a 2T2C structured ferroelectric memory, each bit includes two opposite capacitors that reference each other. Figure 1As shown, each storage unit of the 2T2C ferroelectric memory includes two transistors and two ferroelectric capacitors, wherein the transistor is a CMOS transistor, which includes a gate, a source and a drain, and the source or drain of the transistor is connected to a plate of the ferroelectric capacitor. Each storage unit of the 2T2C ferroelectric memory also includes 4 signal lines connected to the outside. Among them, WL is a word line, which is connected to the gates of the two transistors and is used to control the switches of the two transistors. When WL is at a high level, the two ferroelectric capacitors are turned on with the bit lines, BL and BL_bar are bit lines, which are used to write or read data into the storage unit, and PL is a plate line, which is connected to the other plate of the two ferroelectric capacitors and is used to charge the ferroelectric capacitors to polarize them.

[0045] In an embodiment of the present invention, the ferroelectric memory may include a plurality of storage areas, wherein each storage area includes a plurality of storage blocks, each storage block may include a plurality of bytes, and each byte includes 8 identical storage cells arranged in an array. In actual products, storage cells in different rows and columns may be set according to the capacity of the memory. Among them, the gates of the transistors of the storage cells in the same horizontal row are connected to the same word line WL, the sources of the transistors of the storage cells in the same vertical column are connected to the same bit line BL or BL_bar, and the plates of the ferroelectric capacitors of the storage cells away from the transistors are connected to the same common plate line PL.

[0046] When performing data read and write operations, first, the read and write control circuit of the storage unit controls the word line WL connected to the selected storage unit to become a high level, and WL is connected to the gate of the transistor of the storage unit. Because WL becomes a high level, the transistor is turned on. At this time, one plate of the capacitor of the storage unit is connected to the bit line BL or BL_bar through the turned-on transistor, and the other plate of the capacitor is connected to the plate line PL. In this way, by applying different voltages to the bit line and the plate line, different electric fields can be applied to both ends of the ferroelectric capacitor. The applied electric fields are different, and the polarization degree of the ferroelectric capacitor is different. Therefore, by utilizing the different polarization of the ferroelectric capacitor, different data can be stored in the ferroelectric capacitor.

[0047] In the existing write operation method, such as Figure 2 As shown in the figure, each time a byte of data is written, all bytes in the minimum operation unit where this byte is located need to be pre-read and written back once. This means that when continuous writing is required, each storage unit needs to undergo multiple read and write operations. In the long run, it is very likely to reduce the stability of the ferroelectric memory. In order to improve product stability, the inventor proposes a write operation method that improves the write operation timing so that only one data pre-read and write back are performed in a minimum operation unit. Figure 3As shown, the write operation method performs data pre-reading after receiving the specified data bit, and after the pre-reading is completed, first writes 0 to all storage units in the minimum operation unit, and then writes back 1 after receiving all the data in the minimum operation unit. The scheme of the present invention is further described below in conjunction with the accompanying drawings of the embodiments.

[0048] Figure 4 and Figure 5 The flowchart and pulse timing diagram of the write operation method of the ferroelectric memory according to one embodiment of the present invention are respectively shown. Figure 4 As shown, a write operation method of a ferroelectric memory includes:

[0049] First, in step 401, data is received. Data is received via a serial data interface, and the data includes a write instruction, address information, and valid data. The write operation of the ferroelectric memory is controlled by a write instruction, such as Figure 5 As shown, when receiving a write instruction, the chip select signal CSB generates a falling edge, so that data can be input to the serial data interface. One serial clock Clock cycle can complete the input of 1 bit of data; during the period when the write operation code and address information are input to the serial data interface SI, the word line WL and the plate line PL are both low level;

[0050] Next, in step 402, data is pre-read. When the designated data bit is received, data pre-reading begins, and the data pre-reading reads the data in the N-byte storage unit, wherein the value of N is equal to the number of bytes of the minimum operation unit of the ferroelectric memory. Usually, the value of N is 4, but it should be understood that in other embodiments of the present invention, the value of N can be determined according to the number of storage units that can be operated at a single time in the ferroelectric memory. In one embodiment of the present invention, the designated data bit is the third or fourth bit of the first byte of the N bytes. In one embodiment of the present invention, the data obtained by the data pre-reading is stored in a register. Taking the ferroelectric memory of 2T2C structure as an example, Figure 5 As shown, data pre-reading includes:

[0051] First, a voltage is applied to the word line WL connected to the N bytes of storage cells, so that the word line WL changes from a low level to a high level, at which time the transistors in the storage cells are turned on;

[0052] Next, a voltage is applied to the plate lines PL connected to the N bytes of storage cells, so that the plate lines change from a low level to a high level, and the ferroelectric capacitor is charged to polarize it. In one embodiment of the present invention, before applying the voltage to the plate lines, the bit lines of the N bytes of storage cells may be cleared and discharged; and

[0053] Finally, by comparing the voltages of the bit lines BL and BL_bar connected to the memory cells in the N bytes, it is determined whether the data in the memory cells is "0" or "1";

[0054] Next, in step 403, "0" is written. After the data pre-reading is completed, 0 is written in the N-byte storage unit. Taking the ferroelectric memory of 2T2C structure as an example, Figure 5 As shown, writing 0 in the N-byte storage unit includes:

[0055] Controlling the voltages of the bit lines BL and BL_bar connected to the storage cells in the N bytes to become low level through the driving circuit, so as to write the data "0"; and

[0056] Controlling the plate line voltage connected to the memory cells in the N bytes to become a low level, so as to reduce the stress time of the ferroelectric memory cells and reduce fatigue and imprinting effects;

[0057] Next, in step 404, write "1". When N bytes of data are received or the chip select signal CSB has a rising edge, write 1 in the storage unit of the N bytes. Specifically, if the total number of bytes of data to be written M is less than or equal to N, the write 1 operation is performed when the chip select signal CSB has a rising edge and after all the data to be written is received; and if the total number of bytes of data to be written M is greater than N, the write 1 operation is performed after N bytes of data are received. Taking the ferroelectric memory of the 2T2C structure as an example, Figure 5 As shown, the write 1 includes controlling the voltage of the bit line BL_bar connected to the storage unit in the N bytes to become a high level to realize the writing of data "1". It should be understood that if the total number of bytes of data to be written M is less than N, the writing of data "1" includes: writing "1" in the storage units of M bytes according to the received data to be written, and writing "1" back in the remaining NM bytes of storage units according to the data obtained by data pre-reading; it should be understood that during the operation of data pre-reading and writing 1, the reception of data is not interrupted; and

[0058] Finally, return to step 402 to pre-read and write back the data of the next N bytes of storage units until all data are written. In one embodiment of the present invention, since the cycle required for writing 1 is usually 1 to 2 serial port clock cycles, the data pre-read and write back operations of the next N bytes of storage units can be performed immediately after writing 1 is completed, or the data pre-reading can be started after a delay of a period of time at the third or fourth bit of the first byte of the next N bytes. Specifically, it includes:

[0059] After the first N bytes are written as 1, or when the specified time is extended, or when a specified data bit is received, data pre-reading begins, wherein the data pre-reading reads data in the storage unit of N bytes;

[0060] After the data pre-reading is completed, writing 0 in the storage unit of the N bytes; and

[0061] After receiving N bytes of data, write 1 back to the storage units of the N bytes. Since the data to be written is not necessarily an integer multiple of N, the final number of bytes K remaining may be less than N. At this time, the write 1 operation is performed when the chip select signal CSB has a rising edge, that is, when all data reception is completed. At this time, the write 1 operation includes: writing "1" in the storage units of K bytes according to the received data to be written, and writing "1" back in the remaining NK bytes of storage units according to the data obtained by pre-reading the data.

[0062] According to the write operation method described above, when the total number of bytes M of the data to be written is a multiple of N, a total of M / N data pre-read and write-back operations are required, and when the total number of bytes M of the data to be written is not a multiple of N, |M / N|+1 data pre-read and write-back operations are required. Compared with the prior art, the number of write cycles is greatly reduced.

[0063] Next, taking N as 4 and M as 2 and 5 as examples, the process of the write operation method is described in detail.

[0064] When the minimum operation unit of the ferroelectric memory is 4 bytes and 2 bytes need to be written continuously, according to the write operation method described above, the specific write process includes:

[0065] First, data is received through the serial data interface, and the data includes a write instruction, address information, and valid data. When a write instruction is received, the chip select signal CSB generates a falling edge, so that the data can be input to the serial data interface. During the period when the write operation code and address information are input to the serial data interface SI, the word line WL and the plate line PL are both at a low level;

[0066] Next, when a designated data bit, such as the third or fourth bit of data, is received, data pre-reading is started, wherein the data pre-reading reads data in a 4-byte storage unit and stores the data obtained by the data pre-reading in a register. During this process, the word line WL and the plate line PL change from a low level to a high level.

[0067] Next, after the data pre-reading is completed, 0 is written in the 4-byte storage unit, and after completion, the board line voltage is controlled to become a low level; and

[0068] Finally, when the 2 bytes of data are received, the chip select signal CSB has a rising edge, and at this time, 1 is written to the 4-byte storage unit. Specifically, "1" is written to the 2-byte storage unit according to the received data to be written, and "1" is written back to the remaining 2-byte storage unit according to the data obtained by pre-reading the data.

[0069] When the minimum operation unit of the ferroelectric memory is 4 bytes and 5 bytes need to be written continuously, according to the write operation method described above, the specific write process includes:

[0070] First, data is received through the serial data interface, and the data includes a write instruction, address information, and valid data. When a write instruction is received, the chip select signal CSB generates a falling edge, so that the data can be input to the serial data interface. During the period when the write operation code and address information are input to the serial data interface SI, the word line WL and the plate line PL are both at a low level;

[0071] Next, when a designated data bit, such as the third or fourth bit of data, is received, data pre-reading is started, wherein the data pre-reading reads data in a 4-byte storage unit and stores the data obtained by the data pre-reading in a register. During this process, the word line WL and the plate line PL change from a low level to a high level.

[0072] Next, after the data pre-reading is completed, 0 is written in the 4-byte storage unit, and after completion, the board line voltage is controlled to become a low level;

[0073] Next, after receiving 4 bytes of data, writing 1 in the storage unit of the 4 bytes according to the received data to be written; and

[0074] Finally, after the write 1 operation of the first 4 bytes is completed, or the specified time is delayed, or the specified data bit is received, the data of the next 4 bytes of storage units are pre-read, and after the data pre-read is completed, 0 is written in the storage units of the 4 bytes, and when the remaining one byte of data is received, the chip select signal CSB has a rising edge, and at this time, 1 is written in the storage units of the 4 bytes. Specifically, "1" is written in one of the byte storage units according to the received data to be written, and "1" is written back in the remaining 3 bytes of storage units according to the data obtained by data pre-reading.

[0075] Another aspect of the present invention provides a ferroelectric memory capable of performing the write operation as described above, the ferroelectric memory comprising:

[0076] A register is used to store data read from a storage unit in a data pre-read operation and temporarily store the data in the register. As mentioned above, after the data pre-read is completed, 0 will be written to all storage units in the minimum operation unit, and when writing back, only 1 needs to be written back. Therefore, when the data to be written is less than the number of bytes of the minimum operation unit, it is necessary to write back the part of the data that is 1 to the corresponding storage unit according to the data stored in the register, and the data 0 stored in the register does not need to be written back; and

[0077] The counting unit is coupled to the driving circuit and is used for counting the received data bits and sending word line, plate line and bit line driving signals to control the voltages of the word line, plate line and bit line when the count reaches a preset value.

[0078] Furthermore, the counting unit includes a plurality of D flip-flops.

[0079] The write operation method in the embodiment of the present invention optimizes the timing of the write operation compared to the existing ferroelectric memory write operation. When receiving the specified data bit, the pre-read operation is started first, and after receiving the specified data bit, write 1 is performed. Based on this, in order to accurately start the pre-read and write 1 operations at a preset time point, compared to the existing ferroelectric memory, the ferroelectric memory in the embodiment of the present invention should also include a counting unit and / or a timing unit to determine the number of data bits received or the timing. The counting unit and / or the timing unit are coupled to the driving circuit of the ferroelectric memory. When the count value of the counting unit and / or the timing unit reaches the preset value, a driving signal is generated to drive the word line, plate line, and bit line in the IO, thereby starting the pre-read or write-back operation. Figure 6 FIG. 2 is a schematic diagram showing the structure of a counting unit of a ferroelectric memory according to an embodiment of the present invention. Figure 6 As shown, the counting unit can be composed of a D flip-flop, for example. The counting unit described in the figure can realize the counting of 0-7, and the length of one counting cycle is equal to 8 serial clock cycles. Specifically, the initial value of the count value qcnt is 0, that is, the output value qcnt of each D flip-flop is <2> 、qcnt <1> 、qcnt <0> The values ​​of are all 0, and the first D flip-flop in the counting unit is triggered by the rising edge of SCK, and its positive output value is qcnt <0> The second D flip-flop uses the inverted output of the first D flip-flop The rising edge triggers the positive output value to be qcnt <1> , and the third D flip-flop uses the inverted output of the second D flip-flop The rising edge triggers the positive output value to be qcnt <2> , then according to the output value qcnt of the three D flip-flops <2> 、qcnt <1> 、qcnt <0> The currently received data bit can be determined. When more count values ​​are required, the number of D flip-flops can be increased accordingly. Meanwhile, in other embodiments of the present invention, other counter or timer circuits known to those skilled in the art can also be used to implement this function.

[0080] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A write operation method for a ferroelectric memory, characterized in that: Includes steps: receiving data to be written via a serial data interface; When receiving the designated data bit, data pre-reading is started, wherein the data pre-reading reads data in N bytes of storage units, wherein the value of N is equal to the number of bytes of the minimum operation unit of the ferroelectric memory; After the data pre-reading is completed, writing 0 in the storage unit of the N bytes; When a rising edge appears on the chip select signal, or after receiving N bytes of data, write 1 back to the storage unit of the N bytes; and If there is still data that has not been written, the data of the next N bytes of storage units are pre-read and written back until all the data are written.

2. The write operation method according to claim 1, characterized in that: The data pre-reading and writing back of the next N bytes of storage units includes the following steps: After the first N bytes are written as 1, or the specified time is extended, or a specified data bit is received, data pre-reading is performed, wherein the data pre-reading reads the data in the next N bytes of storage units; After the data pre-reading is completed, writing 0 in the storage unit of the next N bytes; as well as After receiving the next N bytes of data, or when a rising edge appears on the chip select signal, 1 is written back to the storage unit of the next N bytes.

3. The write operation method according to claim 1, characterized in that: The designated data bit is the third or fourth data bit of the first byte of the N bytes.

4. The write operation method according to claim 1, characterized in that: The value of N is 4.

5. The write operation method according to claim 1, characterized in that: The data pre-reading includes: Applying a voltage to the word line connected to the N bytes of storage cells so that the word line changes from a low level to a high level; Applying a voltage to the plate lines connected to the N bytes of storage cells so that the plate lines change from a low level to a high level; and The data in the memory cells in the N bytes are determined according to the voltages of the connected bit lines of the memory cells.

6. The write operation method according to claim 5, characterized in that: The data pre-reading further includes: before applying a voltage to the plate line, clearing and discharging the bit lines of the N bytes of storage cells.

7. The write operation method according to claim 1, characterized in that: Writing 0 in the N bytes of storage cells includes: Controlling the voltage of the bit line connected to the storage unit in the N bytes to become a low level through the driving circuit, thereby writing the data "0", and controlling the voltage of the plate line connected to the storage unit in the N bytes to become a low level; and The write-back 1 includes: The voltage of the bit line connected to the memory cells in the N bytes is controlled to become a high level, so as to realize the writing of data "1".

8. A write operation method for a ferroelectric memory, characterized in that: Includes steps: receiving data to be written via a serial data interface; When receiving the designated data bit, data pre-reading is started, wherein the data pre-reading reads data in N bytes of storage units, wherein the value of N is equal to the number of bytes of the minimum operation unit of the ferroelectric memory; After the data pre-reading is completed, writing 0 in the storage unit of the N bytes; When the number of bytes M of the data to be written is less than the number of bytes N of the minimum operation unit, when the data transmission of the aforementioned serial data interface is completed and a rising edge appears on the chip select signal, 1 is written back to the storage unit of the N bytes; When the number of bytes M of data to be written is greater than the number of bytes N of the minimum operation unit, for storage units that are integer multiples of M / N, after receiving N bytes of data, 1 is written back to the N-byte storage unit; for storage units that are integer multiples of M / N + 1, 1 is written back to the N-byte storage unit when the data transmission of the aforementioned serial data interface is completed and a rising edge appears in the chip select signal.

9. A ferroelectric memory, characterized in that: It is configured to perform a write operation according to the write operation method according to any one of claims 1 to 8, and the ferroelectric memory comprises: a register configured to register data pre-read from a memory cell; and The counting unit is coupled to the driving circuit and is configured to count the received data bits and send word line, plate line and bit line driving signals to control the voltages of the word line, plate line and bit line when the count reaches a preset value.

10. The ferroelectric memory according to claim 9, wherein: The counting unit includes a D flip-flop.

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