Flash memory test method and device, electronic equipment and storage medium

Abstract

The invention provides a Flash memory testing method and device, electronic equipment and a storage medium, and relates to the technical field of testing. The method comprises the following steps: writing first test data into a Flash memory through data read-write software of an upper computer; reading the first storage data in the Flash memory through the data read-write software, verifying the write-in condition of the first test data according to the first storage data to obtain a write-in verification result, and controlling the relay to be disconnected when the data is successfully written in; controlling the relay to be closed after a first preset time is continued, reading second storage data in the Flash memory through the data read-write software, and verifying the reading condition of the first test data according to the second storage data to obtain a read verification result; and circulating the steps for multiple times, and evaluating the read-write stability of the Flash memory according to the obtained write-in verification results and read verification results for multiple times, thereby realizing the read-write stability test of the Flash memory with low cost.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a Flash memory testing method, device, electronic equipment and storage medium. Background Art

[0002] Flash memory is widely used in many fields, especially in the field of medical equipment, due to its long life, high reliability and fast reading performance. As a key storage medium for electronic devices, Flash memory carries the core programs and parameters that control the operation of the device. During the device startup phase, these programs and parameters stored in the Flash memory must be accurately read to ensure the accurate execution of the device functions. However, in actual applications, incomplete chip initialization or program defects at power-on may affect the correct reading of parameters, thus posing a potential threat to the safety of medical operations.

[0003] To solve these problems, an automated test system is currently used to test the read and write stability of Flash memory, and the power-on and power-off processes of the device are controlled by a programmable power supply to improve the accuracy and efficiency of parameter reading. However, this method has obvious limitations: using a programmable power supply to control the power on and off of the device not only significantly increases the cost of the device, but also increases the complexity of the system. Summary of the invention

[0004] The problem solved by the invention is how to realize the read-write stability test of the Flash memory at a low cost.

[0005] In order to solve the above problems, the present invention provides a Flash memory testing method, device, electronic equipment and storage medium.

[0006] In a first aspect, the present invention provides a Flash memory test method, based on a test system, the test system includes a host computer, a single-chip microcomputer, a relay and a power supply, the host computer is communicatively connected to the single-chip microcomputer, the single-chip microcomputer is connected to the relay, the relay is used to control the power supply of the power supply to the Flash memory, the Flash memory test method includes:

[0007] S100: Writing the first test data into the Flash memory through the data reading and writing software of the host computer;

[0008] S200: reading the first storage data in the Flash memory by the data reading and writing software, verifying the writing status of the first test data according to the first storage data, and obtaining a writing verification result; when the writing verification result is that the data is written successfully, controlling the relay to be disconnected so that the power supply stops supplying power to the Flash memory;

[0009] S300: After a first preset time, the relay is controlled to be closed so that the power supply continues to supply power to the Flash memory, the second storage data in the Flash memory is read by the data reading and writing software, and the reading of the first test data is verified according to the second storage data to obtain a reading verification result;

[0010] S400: looping S100 to S300 for multiple times, and evaluating the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

[0011] Optionally, verifying the writing status of the first test data according to the first storage data to obtain a writing verification result includes:

[0012] Determining whether the first test data is equal to the first stored data;

[0013] When the first test data is equal to the first stored data, the write verification result is that the data is written successfully;

[0014] When the first test data is not equal to the first stored data, the write verification result is data write failure, the number of write failures is increased by one, and the process returns to execute S100.

[0015] Optionally, the verifying the reading of the first test data according to the second stored data to obtain a reading verification result includes:

[0016] When the first test data is equal to the second storage data, the read verification result is that the data is read successfully, and the number of cycles is increased by one;

[0017] When the first test data is not equal to the second storage data, the read verification result is data read failure, the number of cycles is increased by one and the number of read failures is increased by one.

[0018] Optionally, during the cycles S100 to S300 , the first test data taken in each cycle is different.

[0019] Optionally, the cycle S100 to S300 is repeated multiple times, and the read and write stability of the Flash memory is evaluated according to the multiple write verification results and the read verification results obtained, including:

[0020] When the number of cycles is equal to or greater than the preset number, the number of write failures, the number of read failures and the number of cycles are output;

[0021] Determine a ratio of the number of write failures to the number of cycles as a first coefficient;

[0022] Determine the ratio of the number of read failures to the number of cycles as a second coefficient;

[0023] The read and write stability of the Flash memory is evaluated according to the first coefficient and the second coefficient.

[0024] Optionally, the evaluating the read and write stability of the Flash memory according to the first coefficient and the second coefficient includes:

[0025] When the first coefficient is greater than a first preset threshold, determining that a write stability problem occurs in the Flash memory;

[0026] When the second coefficient is greater than a second preset threshold, it is determined that a read stability problem occurs in the Flash memory.

[0027] Optionally, the Flash memory testing method further includes:

[0028] When the first test data is not equal to the first stored data or the first test data is not equal to the second stored data, triggering an exception handling mechanism, and returning to execute S100, wherein the exception handling mechanism includes at least one of data backup, memory replacement, and system restart;

[0029] The data backup includes backing up the first test data to other storage media;

[0030] The memory replacement includes replacing the original Flash memory with the spare Flash memory;

[0031] The system restart includes restarting the electronic device to restore the Flash memory to a stable state.

[0032] In a second aspect, the present invention provides a Flash memory test device, based on a test system, the test system includes a host computer, a single-chip microcomputer, a relay and a power supply, the host computer is communicatively connected to the single-chip microcomputer, the single-chip microcomputer is connected to the relay, the relay is used to control the power supply of the power supply to the Flash memory, and the Flash memory test device includes:

[0033] An acquisition module, used for writing the first test data into a Flash memory through the data reading and writing software of the host computer;

[0034] A write verification module, used for reading the first storage data in the Flash memory through the data reading and writing software, verifying the writing status of the first test data according to the first storage data, and obtaining a write verification result; when the write verification result is that the data is written successfully, controlling the relay to be disconnected so that the power supply stops supplying power to the Flash memory;

[0035] a reading verification module, used for controlling the relay to close after a first preset time, so that the power supply continues to supply power to the Flash memory, reading the second storage data in the Flash memory through the data reading and writing software, and verifying the reading of the first test data according to the second storage data to obtain a reading verification result;

[0036] An evaluation module is used to cycle from the acquisition module to the read verification module for multiple times, and evaluate the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

[0037] In a third aspect, the present invention provides an electronic device, including a memory and a processor;

[0038] The memory is used to store computer programs;

[0039] The processor is used to implement the Flash memory testing method as described in the first aspect when executing the computer program.

[0040] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the Flash memory testing method as described in the first aspect is implemented.

[0041] The Flash memory test method, device, electronic device and storage medium of the present invention have the beneficial effects of: writing the first test data into the Flash memory by data reading and writing software, backing up the first test data, and providing data support for the subsequent verification process. Then, read the first storage data in the Flash memory (i.e., the first test data stored in the Flash memory after the previous write operation), verify whether the written data is correct, and ensure the integrity and accuracy of the data. When the written data is correct, the power supply of the Flash memory is cut off by communicating with the single-chip microcomputer to control the relay, so that it enters the power-off state. After waiting for the first preset time, the power supply of the Flash memory is restored by communicating with the single-chip microcomputer to control the relay again, so that it is powered on again, avoiding the use of a high-cost program-controlled power supply, thereby reducing the cost of the Flash memory test. In addition, since the program-controlled power supply not only requires a complex software program, but also requires high-power components such as conduction diodes, switches and relays, not using a program-controlled power supply can also significantly reduce the complexity of the system. Subsequently, the second stored data in the Flash memory (i.e., the first test data previously stored in the Flash memory through the write operation) is read through the same data read-write software to verify whether the read data is correct, and to ensure the integrity and accuracy of the data after the power-off and power-on process. Whether verifying the correctness of the Flash memory write or the correctness of its read, data comparison is performed directly, which can not only timely discover and locate errors that may occur during the data reading process (such as data damage or loss), but also simplify the data verification process, without the need for complex detection mechanisms, and reduce the difficulty and cost of development and implementation. By cyclically executing the above-mentioned write and read operations, and evaluating the Flash memory read-write stability based on the results of multiple verifications, the stability and durability of the Flash memory under long-term and multiple operations can be comprehensively evaluated, ensuring that the electronic equipment can maintain a high degree of reliability and safety under various circumstances, and can also save the cost of testing the Flash memory and reduce the complexity of the Flash memory test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the principle of a Flash memory testing device according to an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of a Flash memory testing method according to an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of a specific flow chart of a Flash memory testing method according to an embodiment of the present invention;

[0045] Figure 4A system architecture diagram of a Flash memory test device according to an embodiment of the present invention;

[0046] Figure 5 4 is a system architecture diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0048] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0049] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to"; the term "based on" means "based at least in part on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments"; the term "optionally" means "optional embodiments". The relevant definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc. mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0050] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0051] The names of the messages or information exchanged between multiple devices in the embodiments of the present invention are only used for illustrative purposes, and are not used to limit the scope of these messages or information.

[0052] In the related art, an automated test system is used to test the Flash memory. These systems control the power-on and power-off process of the device through a programmable power supply to improve the accuracy and efficiency of parameter reading. However, this method has obvious limitations:

[0053] First, programmable power control equipment requires additional hardware and software support, including sophisticated power management chips, control circuits, and related interfaces and communication protocols. The introduction of these components will significantly increase hardware costs. In addition, in order to achieve precise power control, some advanced functions such as overcurrent protection and overvoltage protection may need to be added, which will further increase costs.

[0054] Secondly, the introduction of programmable power control equipment makes system design more complicated. On the one hand, it is necessary to design and implement power control algorithms, which involve real-time monitoring and adjustment of parameters such as voltage and current; on the other hand, it is also necessary to ensure the coordination of power control with other parts of the system (such as data reading and writing, error correction, etc.) to ensure the stability and reliability of the system. These requirements increase the workload of design and testing and increase the complexity of the system.

[0055] In addition, due to the complexity of programmable power control equipment, its maintenance and debugging have become more difficult. Any power control-related failure may require professional technical support to resolve, which not only increases maintenance costs, but may also lead to extended system downtime.

[0056] In view of the problems existing in the above-mentioned related technologies, the present embodiment provides a Flash memory testing method, device, electronic device and storage medium.

[0057] like Figure 1 As shown, a Flash memory test method provided by an embodiment of the present invention is based on a test system, the test system includes a host computer, a single-chip microcomputer, a relay and a power supply, the host computer is communicatively connected to the single-chip microcomputer, the single-chip microcomputer is connected to the relay, and the relay is used to control the power supply of the power supply to the Flash memory. The Flash memory test method is as shown in Figure 2 As shown, including:

[0058] S100: Writing the first test data into the Flash memory through the data reading and writing software of the host computer;

[0059] It should be noted that the host computer includes Python software and data reading and writing software, wherein the Python software and the data reading and writing software communicate with each other through the Automation Device Specification (ADS) protocol. Therefore, by writing a Python program, the data reading and writing software can be controlled to write and read the Flash memory.

[0060] Among them, the ADS protocol is used to achieve efficient data exchange between the host computer and the slave computer (such as PLC), and is widely used in the TwinCAT automation software platform. Through the ADS protocol, the host computer can communicate seamlessly with the data reading and writing software to achieve operations such as monitoring, control and data reading of the equipment. In practical applications, the ADS protocol is often used in conjunction with the EtherCAT bus to achieve high-speed, real-time data transmission. This combination not only improves the speed of data transmission, but also ensures the accuracy and reliability of the data. For example, in the "Software Design of the Host Computer of the Carpet Tufting Machine Based on ADS Communication" project, the ADS protocol is used to achieve communication between the host computer and the slave computer of the carpet tufting machine. Through the TwinCAT system architecture, the ADS protocol makes information transmission faster and more stable, thereby significantly improving the performance and response speed of the entire system.

[0061] Specifically, the host computer sends the first test data to the data reading and writing software, and writes the first test data to the Flash memory through the data reading and writing software Ethernet for Control Automation Technology (EtherCAT) communication. At the same time, the host computer saves the first test data in the form of a file on a hard disk or solid-state drive, or saves it in a database, such as SQLite, MySQL, etc. This first test data saved in the host computer is used as a reference benchmark for subsequent data verification processes to ensure that the data written and read from the Flash memory is completely consistent with the original data.

[0062] The first test data is a set of predefined data used to test the Flash memory, aiming to comprehensively evaluate its performance and reliability under various conditions. The data can be randomly generated or in a specific pattern or sequence to cover various possible data types and formats. For example, randomly generated data can be used to detect the Flash memory's ability to handle disordered data to ensure that each byte can be written and read correctly. Specific patterns or sequences can be used to detect specific types of errors. Common specific patterns include all 0 (e.g., 0x00 0x00 0x00...), all 1 (e.g., 0xFF 0xFF 0xFF...), and alternating 01 (e.g., 0x00 0xFF 0x00 0xFF...). These patterns can help detect bit flip errors, adjacent bit interference, and other hardware faults in the Flash memory.

[0063] In addition, EtherCAT is an industrial fieldbus technology based on Ethernet, which is designed to provide a high-speed, low-latency, synchronous and deterministic communication method for industrial automation applications that require real-time control and data exchange. The core advantage of EtherCAT lies in its extremely high real-time and synchronization. EtherCAT achieves efficient data transmission through "flying read and write" technology. This technology allows data to be inserted and extracted directly when the data frame passes, rather than using the traditional store-and-forward method, which significantly reduces transmission delays.

[0064] S200: reading the first storage data in the Flash memory by the data reading and writing software, verifying the writing status of the first test data according to the first storage data, and obtaining a writing verification result; when the writing verification result is that the data is written successfully, controlling the relay to be disconnected so that the power supply stops supplying power to the Flash memory;

[0065] Specifically, in the previous step, the data reading and writing software has written the first test data into the Flash memory. Now the host computer hopes to verify the writing status by obtaining these first test data. To this end, the host computer will send a request to the data reading and writing software through the ADS protocol. After receiving the request, the data reading and writing software reads the first storage data (the first test data written in the previous step) from the Flash memory through EtherCAT communication. Subsequently, the read first storage data is verified by the first test data backed up in the host computer. If the host computer obtains a verification result of write failure, it means that the data reading operation has failed, which may be due to data damage or loss caused by hardware failure, software error or other reasons. On the contrary, if the host computer obtains a verification result of successful writing, it means that the data reading operation is successful and no errors have occurred. In this case, an instruction is sent to the microcontroller through serial communication to control the IO port of the microcontroller to disconnect the relay, thereby cutting off the power supply of the Flash memory and putting it into a power-off state, such as Figure 1 shown.

[0066] Hardware failures include damage to the Flash memory chip, power fluctuations, or signal interference. Software errors include logical errors in the data reading and writing software or communication protocol problems. Other reasons include external factors such as electromagnetic interference and unstable power supply. Data corruption refers to data being damaged by some external influence during the writing or reading process. Data loss refers to the loss of part of the data during the transmission process, resulting in incomplete read data.

[0067] S300: After a first preset time, the relay is controlled to be closed so that the power supply continues to supply power to the Flash memory, the second storage data in the Flash memory is read by the data reading and writing software, and the reading of the first test data is verified according to the second storage data to obtain a reading verification result;

[0068] Specifically, after power failure, wait for a preset time (i.e., the first preset time) to ensure that the Flash memory is completely powered off and in a stable state. Then, send a command to the microcontroller through serial communication to control the relay to close, thereby restoring the power supply of the Flash memory and powering it on again. Figure 1 As shown. Next, the second storage data (the first test data written after power-off and power-on processing) is read from the Flash memory using data read and write software, and these data are compared with the first test data backed up in the host computer to verify the correctness of the read operation. Finally, the read verification result is obtained based on the comparison result to confirm whether the data remains complete and accurate. This process simulates the power outage that the Flash memory may encounter in actual use, and is intended to detect its data retention ability and stability after power outage.

[0069] The first preset time can be set to 5S or 10S, which is suitable for simulating short power outages, such as momentary power outages or quick restarts. The first preset time can also be set to 120S or 360S to simulate longer power outages, such as restarting after a device is shut down or a long power outage. By setting different power outage times, various situations in actual applications can be simulated more comprehensively, the data retention capability of the Flash memory in different time periods can be evaluated, and its reliability and durability in various power outage situations can be verified to ensure that its performance in actual applications meets expectations.

[0070] In addition, the power on and off of the Flash memory can be realized by controlling the opening and closing of the relay by the single-chip microcomputer, which can simulate the power on and off conditions in actual use, and is helpful to detect the data storage capacity of the Flash memory after powering on again. Specifically: In terms of hardware selection, common single-chip microcomputers (such as Arduino, STM32, etc.) and relay modules on the market are used, and the cost of these components is relatively low. In terms of hardware design, the relay can be controlled by sending simple instructions through serial communication, without the need for complex hardware design. In terms of the first preset time setting, it can be achieved through a simple delay function or timer, and no additional hardware support is required. Therefore, realizing the power on and off of the Flash memory by controlling the opening and closing of the relay by the single-chip microcomputer not only simplifies the system design, but also significantly reduces the cost of Flash memory testing.

[0071] S400: looping S100 to S300 for multiple times, and evaluating the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

[0072] Specifically, the above-mentioned write and read operations are repeated many times. Each cycle records the verification results of write and read, including success and failure. Based on the results of multiple verifications, the stability of the Flash memory can be comprehensively evaluated. If the number of failures is relatively large compared to the number of successes, this indicates that the stability of the Flash memory is poor. In this case, the causes of failures (such as hardware failures, software errors, or environmental factors) can be analyzed in detail to identify and fix the existing problems, thereby significantly improving the overall quality and reliability of the Flash memory. If the number of failures is relatively small compared to the number of successes, this indicates that the stability of the Flash memory is good. In this case, it can be ensured that the Flash memory meets the needs and expectations of customers, especially in applications with high reliability requirements, such as medical equipment and industrial automation systems. Stable Flash memory not only provides reliable performance, but also enhances user trust and satisfaction.

[0073] In this embodiment, while writing the first test data into the Flash memory by the data reading and writing software, the first test data is backed up to provide data support for the subsequent verification process. Then, the first storage data in the Flash memory (i.e., the first test data stored in the Flash memory after the write operation) is read to verify whether the written data is correct and to ensure the integrity and accuracy of the data. When the written data is correct, the power supply of the Flash memory is cut off by communicating with the single-chip microcomputer to control the relay, so that it enters the power-off state. After waiting for the first preset time, the power supply of the Flash memory is restored by communicating with the single-chip microcomputer to control the relay again, so that it is powered on again, avoiding the use of a high-cost program-controlled power supply, thereby reducing the cost of the Flash memory test. In addition, since the program-controlled power supply not only requires complex software programs, but also requires high-power conducting diodes, switches, relays and other components, not using the program-controlled power supply can also significantly reduce the complexity of the system. Subsequently, the second storage data in the Flash memory (i.e., the first test data stored in the Flash memory after the write operation) is read by the same data reading and writing software to verify whether the read data is correct and to ensure the integrity and accuracy of the data after power-off and power-on again. Whether verifying the correctness of writing to the Flash memory or verifying the correctness of reading it, data comparison is performed directly, which can not only timely discover and locate errors that may occur during the data reading process (such as data corruption or loss), but also simplify the data verification process, without the need for complex detection mechanisms, and reduce the difficulty and cost of development and implementation. By cyclically executing the above-mentioned writing and reading operations and evaluating the Flash memory read and write stability based on the results of multiple verifications, the stability and durability of the Flash memory under long-term and multiple operations can be comprehensively evaluated to ensure that electronic equipment can maintain a high degree of reliability and safety under various circumstances. It can also save the cost of testing the Flash memory and reduce the complexity of the Flash memory testing process.

[0074] Alternatively, if Figure 3 As shown, the verifying the writing condition of the first test data according to the first storage data to obtain a writing verification result includes:

[0075] Determining whether the first test data is equal to the first stored data;

[0076] When the first test data is equal to the first stored data, the write verification result is that the data is written successfully;

[0077] When the first test data is not equal to the first stored data, the write verification result is data write failure, the number of write failures is increased by one, and the process returns to execute S100.

[0078] Specifically, after the write operation is completed, the first storage data (the first test data written in the previous step) is read from the Flash memory, and compared with the first test data backed up in the host computer. If the read first storage data is consistent with the first test data backed up in the host computer, it means that the written first test data is correct, and the read operation can be further performed, that is, the second storage data in the Flash memory after power-off and power-on processing is read by the data read-write software, and the read second storage data is verified according to the first test data backed up in the host computer. If the read first storage data is inconsistent with the first test data backed up in the host computer, it means that the written first test data is wrong, and the Flash memory may have a fault or data damage. At this time, the number of write failures is updated (the number of write failures is increased by one) and recorded in the host computer. Then, the write operation is performed again, that is, the new first test data is written into the Flash memory through the data read-write software.

[0079] In this optional embodiment, by comparing the first storage data read and the first test data backed up in the host computer, it can be ensured that the written data is completely consistent with the expected data, which helps to detect and correct errors in the writing process and ensure the integrity and accuracy of the data. When the write operation is successful, a subsequent Flash memory test is performed. When the write operation fails, the number of write failures is first updated (the number of write failures plus one) and recorded in the host computer to facilitate subsequent fault diagnosis and evaluation of the Flash memory. Then the write operation is performed again to ensure that even if the first write fails, the system can try to write multiple times to overcome temporary write errors and increase the probability of successful writing. The data write verification process is implemented through a simple program, does not require complex hardware configuration, reduces manual intervention, and is conducive to realizing low-cost read and write stability testing of Flash memory.

[0080] Alternatively, if Figure 3 As shown, the verification of the reading of the first test data according to the second storage data to obtain a reading verification result includes:

[0081] When the first test data is equal to the second storage data, the read verification result is that the data is read successfully, and the number of cycles is increased by one;

[0082] When the first test data is not equal to the second storage data, the read verification result is data read failure, the number of cycles is increased by one and the number of read failures is increased by one.

[0083] Specifically, if the second storage data read from the Flash memory that has undergone power-on and power-off processing is completely consistent with the first test data backed up in the host computer, it means that the read data is correct and the read operation is successful. At this time, the verification result of successful reading is obtained, the number of cycles is updated (the number of cycles is increased by one) and recorded in the host computer. If the second storage data read from the Flash memory that has undergone power-on and power-off processing is different from the first test data backed up in the host computer, it means that the first test data of the read data is wrong and the read operation fails. At this time, the verification result of read failure is obtained, the number of cycles and the number of read failures are updated (the number of cycles is increased by one, and the number of read failures is increased by one), and recorded in the host computer.

[0084] In this optional embodiment, by comparing the consistency of the second storage data read from the Flash memory that has undergone power-on and power-off processing with the first test data backed up in the host computer, it is possible to verify whether the Flash memory can correctly read the first test data, thereby ensuring the integrity and accuracy of the data. At the same time, the direct data comparison method simplifies the data verification process, eliminates the need for complex detection mechanisms, and reduces the difficulty and cost of development and implementation. According to the verification results of successful or failed reading, the number of cycles and the number of read failures are updated, and these data are recorded in the host computer, which helps to promptly discover and record potential problems of the Flash memory and reflect the stability of the Flash memory under different environments and conditions. Among them, the automatic recording function of the number of cycles and the number of read failures enables the test process to be automatically continued for a long time, reducing the cost of manual operation.

[0085] In some embodiments, when a read operation fails, the number of cycles is first updated (the number of cycles is increased by one) and recorded in the host computer, and then the number of read failures is updated (the number of read failures is increased by one) and recorded in the host computer.

[0086] In other embodiments, when a read operation fails, the number of read failures is first updated (the number of read failures is increased by one) and recorded in the host computer, and then the number of cycles is updated (the number of cycles is increased by one) and recorded in the host computer.

[0087] Optionally, during the cycles S100 to S300 , the first test data taken in each cycle is different.

[0088] Specifically, no matter whether the second storage data read from the Flash memory that has undergone power-on and power-off processing is consistent with the first test data backed up in the host computer (no matter whether the verification result after the reading operation is success or failure), when the number of cycles is less than the preset number and returns to execute S100, the first test data written is different from the first test data in the previous cycle S100 to S300. Specifically, the first test data written is a new test data. This new test data can be obtained through a certain regular change, or it can be data randomly extracted from the data set and not used in the previous cycle process.

[0089] In this optional embodiment, by using different first test data in each cycle, not only can detailed error information be provided to facilitate error diagnosis and fault location, but also the read and write stability of the Flash memory can be fully evaluated to verify its performance when processing different types of data. This method not only improves the coverage and comprehensiveness of the test, but also enhances the robustness of the system, ensuring that the Flash memory can work stably and reliably under various conditions.

[0090] Optionally, the cycle S100 to S300 is repeated multiple times, and the read and write stability of the Flash memory is evaluated according to the multiple write verification results and the read verification results obtained, including:

[0091] When the number of cycles is equal to or greater than the preset number, the number of write failures, the number of read failures and the number of cycles are output;

[0092] Determine a ratio of the number of write failures to the number of cycles as a first coefficient;

[0093] Determine the ratio of the number of read failures to the number of cycles as a second coefficient;

[0094] The read and write stability of the Flash memory is evaluated according to the first coefficient and the second coefficient.

[0095] Specifically, the above-mentioned write and read operations are repeatedly performed, the results of each write and read are recorded, and the number of read failures, the number of write failures and the number of cycles are updated until the number of cycles is equal to the preset number. When the number of cycles is equal to or greater than the preset number, the cycle of the write operation and the read operation is stopped, and the proportion of the number of write failures in the number of cycles is calculated to obtain the first coefficient, that is, the frequency of write operation failures; at the same time, the proportion of the number of read failures in the number of cycles is calculated to obtain the second coefficient, that is, the frequency of read operation failures. These two coefficients provide quantitative indicators of the reliability and stability of the Flash memory under long-term operation. The first coefficient and the second coefficient can be used to comprehensively evaluate the stability of the Flash memory, which helps to quickly identify potential problems and take corresponding measures.

[0096] Among them, the preset number refers to the total number of cycles of write and read operations that are preset during the Flash memory test process. This number is determined based on the test time requirements, resource limitations, and test objectives, and can be thousands of times or tens of thousands of times. When the preset number is set too large, it will occupy a large amount of hardware resources, such as test equipment, power supply, etc., extend the development cycle of the entire project, resulting in reduced test efficiency and increased test costs. When the preset number is set too small, all potential problems may not be discovered, especially those temporary failures or intermittent problems that only occur after long-term use, resulting in an inability to accurately reflect the true performance of the Flash memory. Reasonable setting of the preset number can reduce test costs and improve test efficiency while ensuring the effectiveness of the test.

[0097] The calculation formula of the first coefficient is:

[0098] The first coefficient = number of write failures / total number of cycles;

[0099] For example, if the total number of cycles is 1000 and the number of write failures is 10, the first coefficient is 0.01. A lower first coefficient indicates that the write operation is more reliable, while a higher first coefficient indicates that there are more write errors.

[0100] The calculation formula of the second coefficient is:

[0101] Second coefficient = number of read failures / total number of cycles;

[0102] For example, if the total number of cycles is 1000 and the number of read failures is 20, the second coefficient is 0.02. A lower second coefficient indicates that the read operation is more reliable, while a higher second coefficient indicates that there are more read errors.

[0103] In some embodiments, the first coefficient may be determined first and then the second coefficient. In other embodiments, the second coefficient may be determined first and then the first coefficient.

[0104] In this optional embodiment, by performing multiple cycles of read and write operations through existing data read and write software, a large amount of test data can be collected without adding additional hardware, reducing manual intervention and reducing testing costs. When the number of cycles is equal to or greater than the preset number of times, the number of write failures, the number of read failures and the total number of cycles are output. The first coefficient and the second coefficient are determined by simple mathematical operations without the need for complex algorithms and additional tools. Among them, the first coefficient is used to quickly evaluate the write performance of the Flash memory, and the second coefficient is used to quickly evaluate the read performance of the Flash memory. Taking these two coefficients into consideration, the stability of the Flash memory can be comprehensively evaluated. This method not only improves test efficiency, but also simplifies the data analysis process and reduces the cost of overall testing.

[0105] Alternatively, if Figure 3 As shown, the evaluating the read and write stability of the Flash memory according to the first coefficient and the second coefficient includes:

[0106] When the first coefficient is greater than a first preset threshold, determining that a write stability problem occurs in the Flash memory;

[0107] When the second coefficient is greater than a second preset threshold, it is determined that a read stability problem occurs in the Flash memory.

[0108] Specifically, the setting of the first preset threshold and the second preset threshold is completed through a simple configuration file or parameter setting, wherein the first preset threshold limits the failure rate of the write operation (the first coefficient), and the second preset threshold limits the failure rate of the read operation (the second coefficient). These two thresholds can be determined according to actual application requirements, industry standards and historical data. For example, the first preset threshold can be set to 0.01 (i.e., the write failure rate does not exceed 1%), and the second preset threshold can be set to 0.005 (i.e., the read failure rate does not exceed 0.5%). When the first coefficient exceeds the first preset threshold, it is determined that the Flash memory has a write stability problem. When the second coefficient exceeds the second preset threshold, it is determined that the Flash memory has a read stability problem. When the first coefficient exceeds the first preset threshold and the first coefficient exceeds the first preset threshold, it is determined that the Flash memory has both a write stability problem and a read stability problem. At this time, clear error prompts and operation suggestions will be provided to the operator through the user interface or log system of the electronic device to ensure that the operator can take corresponding measures in time.

[0109] In this optional embodiment, by comparing the first coefficient with the first preset threshold value, and the second coefficient with the second preset threshold value, the performance of the Flash memory in the read and write operations can be quickly evaluated. This method is simple and easy to implement, does not require complex algorithms or additional software tools, and not only provides intuitive results, facilitates the judgment of the stability problem of the Flash memory, but also improves the test efficiency and reduces the cost.

[0110] Alternatively, if Figure 3 As shown, the Flash memory testing method also includes:

[0111] When the first test data is not equal to the first stored data or the first test data is not equal to the second stored data, triggering an exception handling mechanism, and returning to execute S100, wherein the exception handling mechanism includes at least one of data backup, memory replacement, and system restart;

[0112] The data backup includes backing up the first test data to other storage media;

[0113] The memory replacement includes replacing the original Flash memory with the spare Flash memory;

[0114] The system restart includes restarting the electronic device to restore the Flash memory to a stable state.

[0115] Specifically, when the first storage data read from the Flash memory is inconsistent with the first test data backed up in the host computer, or when the second storage data read from the Flash memory that has undergone power-off and power-on processing is inconsistent with the first test data backed up in the host computer, it indicates that the Flash memory may have a fault or data corruption. At this time, the exception handling mechanism is triggered to deal with this problem. The exception handling mechanism includes data backup, that is, backing up the current first storage data or second storage data to other storage media, such as external hard disks, network storage and other reliable storage devices to retain the current data state for subsequent analysis and fault diagnosis; memory replacement, that is, physically removing the original Flash memory and installing a pre-prepared spare Flash memory to ensure that the Flash test system quickly recovers to a stable state; system restart, that is, turning the Flash test system off and on again, which can be completed by software commands or manually pressing the restart button to reinitialize the system, clear any temporary software problems (such as driver errors or system configuration problems), and restore the Flash memory to a stable state.

[0116] In this optional embodiment, data backup retains the original data, which is convenient for fault analysis and diagnosis, uses existing storage media, and reduces backup costs. Memory replacement quickly restores system operation through pre-prepared backup memory, reduces downtime, and reduces overall operating costs. System restart eliminates temporary problems and ensures the stable operation of the new memory, which is achieved through automated tools or simple operations, reducing manual operation costs. After triggering these exception handling mechanisms, the Flash test system returns to normal and continues the unfinished test process from the beginning, which is conducive to ensuring the continuity and integrity of the test, reducing misjudgments caused by errors in intermediate steps, and improving the accuracy of test results. Different triggering exception handling mechanisms can effectively deal with read errors of various Flash memories, while ensuring system stability and data security, and realizing low-cost Flash testing.

[0117] Data backup retains the original data, which facilitates fault analysis and diagnosis, and uses existing storage media to reduce backup costs. Memory replacement quickly restores system operation through pre-prepared backup memory, reducing downtime and thus reducing overall operating costs. System restart eliminates temporary problems and ensures stable operation of Flash memory. It can be achieved through automated tools or simple operations, reducing manual operation costs. Different exception handling mechanisms can effectively deal with various Flash memory read errors, while ensuring system stability and data security, and realizing low-cost Flash testing. After these exception handling mechanisms are triggered, the Flash test system can return to normal, and continuing the unfinished test process from the beginning helps to ensure the continuity and integrity of the test, reduce misjudgments caused by errors in intermediate steps, and improve the accuracy of test results.

[0118] like Figure 4 As shown, a Flash memory testing device 400 provided in an embodiment of the present invention includes:

[0119] The acquisition module 410 is used to write the first test data into the Flash memory through the data reading and writing software of the host computer;

[0120] A write verification module 420 is used to read the first storage data in the Flash memory through the data reading and writing software, verify the writing status of the first test data according to the first storage data, and obtain a write verification result. When the write verification result is that the data is written successfully, control the relay to be disconnected so that the power supply stops supplying power to the Flash memory;

[0121] A read verification module 430 is used to control the relay to close after a first preset time so that the power supply continues to supply power to the Flash memory, read the second storage data in the Flash memory through the data reading and writing software, and verify the reading of the first test data according to the second storage data to obtain a read verification result;

[0122] The evaluation module 440 is used to cycle the acquisition module 410 to the read verification module 430 for multiple times, and evaluate the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

[0123] Optionally, the write verification module 420 is specifically used to: determine whether the first test data is equal to the first stored data; when the first test data is equal to the first stored data, the write verification result is that the data is written successfully; when the first test data is not equal to the first stored data, the write verification result is that the data is written failed, the number of write failures is increased by one, and the acquisition module 410 is returned to execute.

[0124] Optionally, the read verification module 430 is specifically used for: when the first test data is equal to the second storage data, the read verification result is that the data read is successful, and the number of cycles is increased by one; when the first test data is not equal to the second storage data, the read verification result is that the data read fails, and the number of cycles is increased by one and the number of read failures is increased by one.

[0125] Optionally, in the process of looping from the acquisition module 410 to the reading verification module 430 , the first test data taken in each loop process is different.

[0126] Optionally, the evaluation module 440 is specifically used to: when the number of cycles is equal to or greater than a preset number, output the number of write failures, the number of read failures and the number of cycles; determine the ratio of the number of write failures to the number of cycles as a first coefficient; determine the ratio of the number of read failures to the number of cycles as a second coefficient; and evaluate the read and write stability of the Flash memory based on the first coefficient and the second coefficient.

[0127] Optionally, the read and write stability of the Flash memory is evaluated according to the first coefficient and the second coefficient, and the evaluation module 440 is also specifically used to: when the first coefficient is greater than a first preset threshold, determine that the Flash memory has a write stability problem; when the second coefficient is greater than a second preset threshold, determine that the Flash memory has a read stability problem.

[0128] Optionally, the Flash memory testing device 400 also includes an exception module, which is used to: when the first test data is not equal to the first storage data or the first test data is not equal to the second storage data, trigger an exception handling mechanism and return to execute the acquisition module 410, wherein the exception handling mechanism includes at least one of data backup, memory replacement and system restart; the data backup includes backing up the first test data to other storage media; the memory replacement includes replacing the original Flash memory with a spare Flash memory; the system restart includes restarting the electronic device to restore the Flash memory to a stable state.

[0129] like Figure 5 As shown, an electronic device 500 provided by an embodiment of the present invention includes a memory 520 and a processor 510; the memory 520 is used to store a computer program; the processor 510 is used to implement the Flash memory testing method as described above when executing the computer program.

[0130] In other words, an electronic device 500 includes a memory 520 and a processor 510 coupled to the memory 520; the memory 520 is configured to store a computer program; and the processor 510 is configured to perform the following operations when executing the computer program:

[0131] S100: Writing the first test data into the Flash memory through the data reading and writing software of the host computer;

[0132] S200: reading the first storage data in the Flash memory by the data reading and writing software, verifying the writing status of the first test data according to the first storage data, and obtaining a writing verification result; when the writing verification result is that the data is written successfully, controlling the relay to be disconnected so that the power supply stops supplying power to the Flash memory;

[0133] S300: After a first preset time, the relay is controlled to be closed so that the power supply continues to supply power to the Flash memory, the second storage data in the Flash memory is read by the data reading and writing software, and the reading of the first test data is verified according to the second storage data to obtain a reading verification result;

[0134] S400: looping S100 to S300 for multiple times, and evaluating the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

[0135] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the Flash memory test method as described above is implemented.

[0136] In other words, a non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor performs the following operations:

[0137] S100: Writing the first test data into the Flash memory through the data reading and writing software of the host computer;

[0138] S200: reading the first storage data in the Flash memory by the data reading and writing software, verifying the writing status of the first test data according to the first storage data, and obtaining a writing verification result; when the writing verification result is that the data is written successfully, controlling the relay to be disconnected so that the power supply stops supplying power to the Flash memory;

[0139] S300: After a first preset time, the relay is controlled to be closed so that the power supply continues to supply power to the Flash memory, the second storage data in the Flash memory is read by the data reading and writing software, and the reading of the first test data is verified according to the second storage data to obtain a reading verification result;

[0140] S400: looping S100 to S300 for multiple times, and evaluating the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

[0141] An electronic device 500 that can be used as a server or client of the present invention will now be described, which is an example of a hardware device that can be applied to various aspects of the present invention. The electronic device 500 is intended to represent various forms of digital electronic computer equipment, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 500 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present invention described and / or required herein.

[0142] The electronic device 500 includes a computing unit, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) or a computer program loaded from a storage unit into a random access memory (RAM). In the RAM, various programs and data required for the operation of the device can also be stored. The computing unit, ROM, and RAM are connected to each other via a bus. An input / output (I / O) interface is also connected to the bus.

[0143] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. In the present application, the unit described as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or it may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment of the present invention. In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0144] Although the present invention is disclosed as above, the protection scope of the present invention is not limited thereto. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications will fall within the protection scope of the present invention.

Claims

1. A Flash memory testing method, characterized in that: Based on a test system, the test system includes a host computer, a single-chip microcomputer, a relay and a power supply, the host computer is communicatively connected to the single-chip microcomputer, the single-chip microcomputer is connected to the relay, and the relay is used to control the power supply of the power supply to the Flash memory. The Flash memory test method includes: S100: Writing the first test data into the Flash memory through the data reading and writing software of the host computer; S200: reading the first storage data in the Flash memory by the data reading and writing software, verifying the writing status of the first test data according to the first storage data, and obtaining a writing verification result; when the writing verification result is that the data is written successfully, controlling the relay to be disconnected so that the power supply stops supplying power to the Flash memory; S300: After a first preset time, the relay is controlled to be closed so that the power supply continues to supply power to the Flash memory, the second storage data in the Flash memory is read by the data reading and writing software, and the reading of the first test data is verified according to the second storage data to obtain a reading verification result; S400: looping S100 to S300 for multiple times, and evaluating the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

2. The Flash memory testing method according to claim 1, characterized in that: The verifying the writing status of the first test data according to the first storage data to obtain a writing verification result includes: Determining whether the first test data is equal to the first stored data; When the first test data is equal to the first stored data, the write verification result is that the data is written successfully; When the first test data is not equal to the first stored data, the write verification result is data write failure, the number of write failures is increased by one, and the process returns to execute S100.

3. The Flash memory testing method according to claim 1, characterized in that: The verifying the reading of the first test data according to the second storage data to obtain a reading verification result includes: When the first test data is equal to the second storage data, the read verification result is that the data is read successfully, and the number of cycles is increased by one; When the first test data is not equal to the second storage data, the read verification result is data read failure, the number of cycles is increased by one and the number of read failures is increased by one.

4. The Flash memory testing method according to claim 1, characterized in that: During the cycles S100 to S300 , the first test data taken in each cycle is different.

5. The Flash memory testing method according to claim 1, characterized in that: The cycle S100 to S300 is repeated multiple times, and the read and write stability of the Flash memory is evaluated according to the multiple write verification results and the read verification results obtained, including: When the number of cycles is equal to or greater than the preset number, the number of write failures, the number of read failures and the number of cycles are output; Determine a ratio of the number of write failures to the number of cycles as a first coefficient; Determine the ratio of the number of read failures to the number of cycles as a second coefficient; The read and write stability of the Flash memory is evaluated according to the first coefficient and the second coefficient.

6. The Flash memory testing method according to claim 5, characterized in that: The step of evaluating the read and write stability of the Flash memory according to the first coefficient and the second coefficient includes: When the first coefficient is greater than a first preset threshold, determining that a write stability problem occurs in the Flash memory; When the second coefficient is greater than a second preset threshold, it is determined that a read stability problem occurs in the Flash memory.

7. The Flash memory testing method according to claim 2 or 3, characterized in that: Also includes: When the first test data is not equal to the first stored data or the first test data is not equal to the second stored data, triggering an exception handling mechanism, and returning to execute S100, wherein the exception handling mechanism includes at least one of data backup, memory replacement, and system restart; The data backup includes backing up the first test data to other storage media; The memory replacement includes replacing the original Flash memory with the spare Flash memory; The system restart includes restarting the electronic device to restore the Flash memory to a stable state.

8. A Flash memory testing device, characterized in that: Based on a test system, the test system includes a host computer, a single-chip microcomputer, a relay and a power supply, the host computer is communicatively connected with the single-chip microcomputer, the single-chip microcomputer is connected with the relay, the relay is used to control the power supply of the power supply to the Flash memory, and the Flash memory test device includes: An acquisition module, used for writing the first test data into a Flash memory through the data reading and writing software of the host computer; A write verification module, used for reading the first storage data in the Flash memory through the data reading and writing software, verifying the writing status of the first test data according to the first storage data, and obtaining a write verification result; when the write verification result is that the data is written successfully, controlling the relay to be disconnected so that the power supply stops supplying power to the Flash memory; a reading verification module, used for controlling the relay to close after a first preset time, so that the power supply continues to supply power to the Flash memory, reading the second storage data in the Flash memory through the data reading and writing software, and verifying the reading of the first test data according to the second storage data to obtain a reading verification result; An evaluation module is used to cycle from the acquisition module to the read verification module for multiple times, and evaluate the read and write stability of the Flash memory according to the multiple write verification results and the read verification results obtained.

9. An electronic device, characterized in that: including memory and processor; The memory is used to store computer programs; The processor is used to implement the Flash memory testing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the Flash memory testing method according to any one of claims 1 to 7 is implemented.

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