A prediction method for phase-locked abnormality processing of mains zero-crossing of single-phase energy storage inverter

Abstract

The invention discloses a method for predicting phase-locked abnormal processing of a single-phase energy storage inverter when the mains power passes through zero point. The method is performed according to the following steps: judging whether a phase-locked interruption starts, if not, returning to re-judgment whether the phase-locked interruption starts; if yes, judging whether Δθ is less than, if yes, reducing, if not, judging whether Δθ is greater than and less than, if yes, keeping unchanged, if not, judging whether Δθ is greater than, if yes, increasing, if not, returning to re-judgment whether the phase-locked interruption starts; Δθ is the phase of the inverter voltage leading the mains power, which is the amount by which the inverter voltage is smaller than the mains power frequency, c is the adjustment step for each time, and n is the ratio to c.

Description

Technical Field

[0001] The present invention relates to the field of electric power technology, and in particular to a method for predicting a mains zero-crossing phase-locked abnormality of a single-phase energy storage inverter. Background Art

[0002] In both the grid-connected mode of the single-phase energy storage inverter and the grid-connected bypass mode, the grid-connected power needs to be phase-locked. The traditional method is to use the grid-connected zero-point phase-locking method. For example, in the grid-connected bypass mode, by comparing the grid-connected zero-point triggering moment with the grid-connected inverter voltage output zero-point moment, the phase of the reference sine table of the inverter output voltage and the updating frequency of the tracking step are adjusted to achieve the purpose of the inverter output voltage and the grid-connected power having the same frequency and phase.

[0003] Energy storage inverter control chips generally use DSP, single-chip microcomputer and other chips. When phase-locked, a 16-bit unsigned integer variable is generally set as a counter to calculate the AC frequency, which is set as CAPLine here; at the same time, a 16-bit unsigned integer variable is also set as a counter to calculate the inverter frequency, which is set as CAPINV here. When the AC zero-crossing point (generally set to the zero-crossing point from the negative half axis to the positive half axis) completes the triggering of the CAP pin of the DSP and other chips, the DSP will call the AC zero-crossing interrupt program. The CAPLine variable obtained by the current count is multiplied by the counting cycle value Ts of CAPLine to get the cycle of the AC in the previous cycle. The reciprocal is the AC frequency. At the same time, after CAPLine is cleared, it will start counting again until the next AC zero-crossing interrupt arrives, and the phase and frequency of the AC will be updated again. Similarly, when the inverter zero-crossing point (the setting must be consistent with the mains zero-crossing point) completes the triggering of the CAP pin of the DSP and other chips, the DSP will call the mains zero-crossing point interrupt program. The CAPINV variable obtained by the current count is multiplied by the counting cycle value Ts of CAPINV to get the period of the inverter output voltage in the previous cycle. The reciprocal is the inverter output voltage frequency. At the same time, after CAPINV is cleared, it will restart counting until the next inverter zero-crossing point interrupt arrives, and the phase and frequency of the inverter output will be updated again. In this way, the phase difference of the phase lock is equal to the difference between the mains zero-crossing point moment and the inverter voltage zero-crossing point moment. If the setting conditions are all ideal, there will be no problem. However, in the actual implementation process, different interrupt priorities will cause the inverter zero-crossing point interrupt trigger calculation to be untimely, resulting in inaccurate calculated phase difference, resulting in slow dynamic tracking response of the phase lock when the mains frequency changes. The specific reasons are as follows:

[0004] Since it is impossible for any two interrupts to be calculated at the same time in the DSP interrupt program, different interrupt priorities will be set to prioritize important interrupts. The inverter feedback control interrupt is the most important and has the highest priority; due to the need for phase locking, the AC zero-crossing interrupt priority is also high, but lower than the inverter feedback control interrupt; the inverter zero-crossing interrupt has the lowest priority. It may happen that when the DSP is processing the inverter zero-crossing interrupt, an inverter feedback interrupt and a AC zero-crossing interrupt request occur. In this way, the inverter zero-crossing interrupt is suspended due to the lowest priority, and the inverter feedback interrupt and the AC zero-crossing interrupt are processed first, which will eventually cause the AC zero-crossing interrupt that "occurs later but has a higher priority" to be executed before the inverter zero-crossing interrupt that "occurs earlier but has a lower priority".

[0005] Problem found: The difference between the zero crossing points is close to the maximum value of the unsigned integer variable, 65535, with a non-negligible probability. The reason why the maximum number is 65535 is that the inverter interrupt is not processed in time and is not cleared, resulting in the continuous counting and the maximum value of the hexadecimal unsigned number.

[0006] Assuming that the frequency of the mains remains unchanged, the following six situations will occur in the zero-crossing phase lock:

[0007] Case 1, such as Figure 2 As shown: the difference between zero crossing points < inverter period / 2, no prediction is required, the phase difference = the difference between zero crossing points;

[0008] Case 2, such as Figure 3 As shown: the difference of zero crossing points < the inverter cycle, and the difference of zero crossing points < the mains cycle, then the predicted phase difference = mains cycle - the difference of zero crossing points;

[0009] Case 3, such as Figure 4 As shown: the difference between the zero crossing points < the inverter period, and the difference between the zero crossing points > the mains period, then the predicted phase difference = 0, the predicted mains period = the difference between the zero crossing points;

[0010] Case 4, such as Figure 5 As shown: the difference of zero crossing points > inverter cycle, and the difference of zero crossing points < mains cycle, then the predicted phase difference = mains cycle - difference of zero crossing points;

[0011] Case 5, such as Figure 6 As shown: the difference between zero crossing points>inverter cycle, and the difference between zero crossing points>mains cycle, and the difference between zero crossing points<65000, then the predicted phase difference = 0, and the measured mains cycle = the difference between zero crossing points;

[0012] Case 6, such as Figure 7 As shown: This is the abnormal situation where the inverter zero-crossing interrupt is suspended, and the phase difference = 65535-zero-crossing difference. Summary of the invention

[0013] The purpose of the present invention is to provide a method for predicting the abnormality of phase-locking when the mains power crosses zero in a single-phase energy storage inverter. To this end, the present invention adopts the following technical solutions:

[0014] A method for predicting the abnormality of mains zero-crossing phase locking of a single-phase energy storage inverter is carried out according to the following steps:

[0015] Determine whether the phase-locked interruption has started. If not, return to re-determine whether the phase-locked interruption has started; if so, determine whether Δθ is less than If yes, reduce Δf, if no, determine whether Δθ is greater than and less than If yes, keep Δf unchanged, if no, determine whether Δθ is greater than If yes, increase Δf, if no, return to re-judge whether the phase-locked interruption has started; Δθ is the phase of the inverter voltage leading the mains, Δf is the amount by which the inverter voltage is smaller than the mains frequency, c is the adjustment step each time, and n is the ratio of Δf to c. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 : Schematic diagram of inverter interrupt pair suspension.

[0017] Figure 2 : The phase between the inverter and the AC power when the difference between the zero crossing points is less than the inverter period / 2.

[0018] Figure 3 :The difference between the zero crossing points < the phase between the inverter and the AC power during the inverter cycle.

[0019] Figure 4 : The phase between the inverter and the AC power when the difference of zero crossing points is less than the inverter period and the difference of zero crossing points is greater than the AC period.

[0020] Figure 5 : The phase between the inverter and the AC power when the difference between the zero crossing points > the inverter period and the difference between the zero crossing points < the AC power period.

[0021] Figure 6 : The phase of inverter and AC power when the difference of zero crossing points > inverter period, and the difference of zero crossing points > AC power period, and the difference of zero crossing points < 65000.

[0022] Figure 7 : The phase of the inverter and the AC power when the inverter zero-crossing interrupt is suspended.

[0023] Figure 8 : Phase locking situation 6 Phase locking operation process under abnormal circumstances. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0025] Solution for case 6:

[0026] There are only three adjustment strategies: 1. Narrowing the frequency difference; 2. Remaining unchanged; 3. Widening the frequency difference.

[0027] Assume that the current inverter phase leads by Δθ, the frequency is Δf less than the mains, and the adjustment step is c 1 each time (the 1 is the minimum number of points increased by the counting frequency 1 / Ts, and is also the minimum counting unit 1), and Δf / c=n is abbreviated. The phase difference that can be reduced by using different adjustment strategies is as follows:

[0028] (1) Reducing the frequency difference: If the frequency difference is reduced from the next step until it is zero, the phase difference reduced in the kth step (k is the current moment) is

[0029] Δf-c*n=c*(nk)

[0030] The total reduction in phase difference is points;

[0031] (2) Remain unchanged: If the frequency difference is kept unchanged in the next step, and then the frequency difference is zero according to (1), the phase difference can be reduced to

[0032] points;

[0033] (3) Enlarging the frequency difference: If the frequency difference is enlarged in the next step, and then the frequency difference is zero according to (1), the phase difference can be reduced to

[0034]

[0035] points.

[0036] According to the relationship between the current phase difference and the phase difference that can be reduced by adopting different strategies, the frequency difference operation of case 6 can be obtained as follows: Figure 8 shown.

Claims

1. A method for predicting the abnormality of phase-locked zero-crossing of mains power supply of a single-phase energy storage inverter, characterized in that: Follow these steps: Determine whether the phase-locked interruption has started. If not, return to re-determine whether the phase-locked interruption has started; if so, determine whether Δθ is less than If yes, reduce Δf, if no, determine whether Δθ is greater than and less than If yes, keep Δf unchanged, if no, determine whether Δθ is greater than If yes, increase Δf, if no, return to re-judge whether the phase-locked interruption has started; Δθ is the phase of the inverter voltage leading the mains, Δf is the amount by which the inverter voltage is smaller than the mains frequency, c is the adjustment step each time, and n is the ratio of Δf to c.

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