A customizable RISC-V architecture processor design method for embedded scenarios

Abstract

The present invention proposes a customizable RISC-V architecture processor design method for embedded scenarios. This design scheme is aimed at increasingly complex embedded scenarios, is suitable for limited resources and has the ability to start complex operating systems. This scheme classifies the customized schemes based on processor pipelines into two categories, proposes different processor function unit design schemes for different categories, and provides flexible and powerful customized function unit interfaces. Experiments have shown that the processor control logic designed based on this scheme is simple, but the functions are complex enough to start the Linux operating system distribution, has a high degree of configurability and extensibility, and can be used for the design and verification of customized prototype systems in embedded scenarios.

Description

Technical Field

[0001] The present invention relates to the field of computer architecture, and in particular to a customizable RISC-V architecture processor design method for embedded scenarios. Background Art

[0002] With the rapid increase in the complexity and number of IoT devices and the advent of the post-Moore's Law era, the market demand for powerful and domain-specific processors has increased. On the one hand, the processor must not only use fewer resources, but also support complex operating systems used by IoT devices, such as embedded Linux; on the other hand, in order to support customized functional units in different scenarios, the processor needs to be easy to expand. Traditional embedded processors that are difficult to start the operating system and fixed processor IP cores that are difficult to customize cannot meet new requirements. Therefore, the present invention proposes a customizable processor design method for embedded scenarios that takes into account both resources and the ability to start the operating system.

[0003] RISC-V is an open source instruction set that optimizes instruction sets for modern processor microarchitectures and operating systems. At present, some institutions have open-sourced several RISC-V embedded processors, such as Sodar, Rocketchip, and Nutshell. However, processors such as Sodar are insufficient in functionality; processors represented by Rocketchip, although using agile development methods, have poor code readability, the processor is bound to the bus, the customization threshold is high, and the generated hardware circuits are complex; processors represented by Nutshell do not have functional unit expansion interfaces, so their scalability is poor. Summary of the invention

[0004] The purpose of the present invention is to provide a customizable RISC-V architecture processor design method for embedded scenarios in order to meet new requirements for processor design in embedded scenarios.

[0005] In order to realize the requirements of booting operating system distribution and customization, this design method is implemented through the following technical solutions:

[0006] The present invention discloses a customizable RISC-V architecture processor design method for embedded scenarios, comprising the following steps:

[0007] 1) Use agile development methods to design embedded processors that support the RV64GC instruction set: Based on the RISC-V instruction set manual, implement and verify the processor pipeline that supports the RV64I instruction set and the Machine privileged state, implement the standard interrupt controller Clint and PLIC, and gradually add and verify new instruction sets and privileged state support on this basis, and finally implement a complex processor that supports integer, multiplication and division, atomic, floating point, compressed instructions, and Machine, Supervisor, and User privileged states;

[0008] 2) Design and implement cache consistency and memory consistency: Design and implement cache units, use a combination of software and hardware to ensure the consistency between data cache and instruction cache, data cache and TLB, and implement a memory consistency model that is no weaker than RVWMO specified in the RISC-V manual;

[0009] 3) Design a flexible and powerful customized functional unit interface: Provide a flexible and powerful interface for the customized functional units integrated inside the processor, and appropriately adjust the design of the processor pipeline according to the functions of the interface.

[0010] As a further improvement, in step 1) of the present invention, in each round of agile development, starting from the formulation of design specifications, the current version of the processor first goes through the steps of circuit design, definition of customized functional unit interface, code implementation, correctness verification, etc., and then enters the next round to become the next version of the processor with more comprehensive functions.

[0011] As a further improvement, in steps 1) and 2) of the present invention, during the agile development process, the configurable characteristics of the processor are taken into consideration, and the cache size and replacement strategy, branch prediction strategy, the minimum privileged state supported by the processor, compressed instructions and custom extension features are all parameterized.

[0012] As a further improvement, in step 3) of the present invention, the customized functional unit interface includes a simple customized extension that can be completed in a single cycle and only writes the calculation result back to the destination register, and a complex extension that requires multiple cycles or memory access operations.

[0013] As a further improvement, the present invention places the corresponding functional unit in the pipeline execution stage for the simple customized expansion of the single-cycle operation that only writes the operation result back to the destination register.

[0014] As a further improvement, the present invention places the functional unit in the memory access segment or the write-back segment for the complex extension requiring multiple cycles or memory access operations.

[0015] As a further improvement, the present invention provides the following functions for the interface of the customized functional unit for different customized functions: for reading and writing back registers, 2 read ports and 1 write port are provided; for reading and writing back CSRs, 1 read port and 1 write port are provided; for memory access operations, 1 read port and 1 write port are provided; and an exception signal interface that may be generated by the customized functional unit is provided.

[0016] As a further improvement, the method of the present invention uses a synchronous decoupling interface to encapsulate the interactive information between the customized functional unit and other functional units, and between the customized functional unit and the processor pipeline. The decoupling interface encapsulates and transmits more customized information according to customization needs.

[0017] The beneficial effects of the present invention are as follows:

[0018] The present invention proposes a customizable RISC-V architecture processor design method for embedded scenarios. This design method is aimed at increasingly complex embedded scenarios, is suitable for limited resources and has the ability to start complex operating systems. This solution classifies the customized solutions based on the processor pipeline into two categories, proposes different processor function unit design solutions for different categories, and provides a flexible and powerful customized function unit interface. Experiments have shown that the processor control logic designed based on this solution is simple, but the functions are complex enough to start the Linux operating system distribution, with high configurability and extensibility, and can be used for the design and verification of customized prototype systems in embedded scenarios, realizing the agile development of embedded processors and improving development efficiency. The embedded processor developed using this method can be customized and expanded in the field at a low cost in specific application scenarios, and customized functions can be quickly developed and verified. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a time-event diagram of a customizable RISC-V architecture processor design method for embedded scenarios;

[0020] Figure 2 The customized interface design diagram of this method is shown by taking a customized extension unit related to memory safety as an example;

[0021] Figure 3 This is an embedded SoC design architecture diagram using the present design method, wherein the dotted box is a processor designed based on the present method. DETAILED DESCRIPTION

[0022] The specific technical scheme of the present invention is further described below in conjunction with the accompanying drawings:

[0023] The present invention discloses a customizable RISC-V architecture processor design method for embedded scenarios. Figure 1 It is a time-event diagram of a customizable RISC-V architecture processor design method for embedded scenarios, including the following steps:

[0024] (1) Use agile development methods to design embedded processors that support the RV64GC instruction set. Specifically, in this design method, starting from formulating design specifications based on the RISC-V instruction set manual and application scenarios, the processor goes through circuit design, defining customized functional unit interfaces and adjusting circuit logic accordingly, code implementation, using FPGA to initially verify the correctness of the hardware code, RTL-level fuzz testing, using ASIC area and timing optimization, and finally small-scale tape-out verification. This design method first uses a processor that supports the minimum function, such as Figure 1 As shown, processor No. 1 supports RV64I, Machine mode, Clint and PLIC; it goes through the steps from design specification to FPGA verification. After that, every time a new module is added to the previous version of the processor, it will go through the steps from design specification to FPGA. If the processor function is simple, it does not need to go through RTL fuzz testing, ASIC and tape-out, which are time-consuming and financially intensive steps. Ultimately, by using the present invention to design and develop processors, it is possible to obtain processor RTL codes that are easy to add customized extensions, and it is also possible to obtain embedded processors with simple logic, complex functions, and the ability to start Linux distributions;

[0025] (2) Design and implement cache consistency and memory consistency. Ensure the consistency of data cache and instruction cache, and data cache and TLB. The following is an example of specific implementation. In order to achieve the above cache consistency, the following specific methods can be adopted: design a two-layer cache, a private L1 instruction and data cache, and a shared L2 cache; design a private instruction TLB and data TLB located in the IMMU and DMMU respectively. The L1 data cache adopts a write-through write strategy to write data to the L2 shared cache. When the processor executes instructions involving cache consistency (such as fence.i and sfence.vma specified in the RISC-V manual), the L1 private instruction cache or TLB will be cleared, and the pipeline will also be cleared. When filling again, the L1 instruction cache or TLB obtains data consistent with the L1 data cache from the L2 cache, realizing a memory consistency model that is not weaker than the RVWMO specified in the RISC-V manual. The following design can be adopted in specific implementation: follow the SC memory consistency model, that is, the order of reading and writing memory reflected by the processor to the system bus is consistent with the order of reading and writing memory by memory access instructions during program dynamic runtime.

[0026] Figure 2The customized interface design diagram of this method is demonstrated by taking a customized expansion unit related to memory security as an example; a customizable processor design method for embedded scenarios based on the RISC-V instruction set, which also includes designing a flexible and powerful customized functional unit interface. For simple customized functions that can be completed in a single cycle and do not require memory access, the functional unit is located in the execution segment of the processor. According to the RISC-V instruction set manual, this type of interface of this design method includes the following signal groups:

[0027] (a) valid-ready, where valid means the task signal sent by the processor to the functional unit, and ready means the functional unit can receive new tasks. In a simple interface, ready also means the work completion signal returned by the functional unit to the processor;

[0028] (b) rs1-rs2-rd, rs is the value of the source register defined by RISC-V, which is passed to the functional unit by the pipeline, and rd is the value of the destination register, which is used to write into the register file;

[0029] (c) insn, a custom instruction of a customized processor, which is passed by the processor to the functional unit for further decoding;

[0030] (d) xcpt, a signal indicating whether the customized functional unit throws an exception and the number of the exception thrown, is transmitted by the functional unit to the processor.

[0031] For complex extensions that require multiple cycles or memory access operations, Figure 2 Taking the processor shown as an example, the functional unit is located in the memory access segment. According to the design method, the remaining factors of the processor that cause PC redirection (including exceptions and interrupts) can be detected in the pipeline segment before the location of the customized functional unit. Therefore, the customized interface avoids sending a signal to terminate the operation to the functional unit, thereby reducing the implementation complexity of the customized functional unit. Figure 2In the example, rs1-rs2-rd, xcpt, insn, and ready-valid signals that interact with the jump segment have the same meaning as the simple customized functional unit interface described above. In addition, considering that some extended instructions require registers in the CSR to participate in the operation, or can only be executed correctly when the processor is in a specific state recorded by the CSR (such as privilege level, page table base address, etc.), the customized functional unit interface of the present design method includes a CSR interface. Specifically, the interface can transmit the values ​​of all CSRs implemented by the processor, and the customized functional unit can select a certain CSR to participate in the operation or permission check according to the incoming instruction insn, and decide whether to write a certain calculation result back to a specific CSR through csrw. The present design method takes into account the possible memory access operations of the extended instructions, including atomic memory operations of read, write back, and read-operate-write back. In particular, in order to support the atomic memory operations and memory consistency requirements of the customized functional unit, the present invention provides a corresponding customized interface data to realize the interaction between the customized functional unit and the memory access unit. This interface requires special design of the processor, such as Figure 2 In the design, unlike the traditional implementation method of L1 data cache controlling atomic operations, the AMO and LL-SC units of the memory access segment fully control atomic memory operations. In order to support the pipeline execution of complex functions, the complex customized interface of this design method also includes a ready-valid decoupling interface that interacts with the write-back segment. The valid signal sent by the functional unit to the write-back segment indicates that the unit has a new output result, and the ready signal sent by the processor write-back segment to the functional unit indicates that the processor can receive the new output result of the functional unit.

[0032] Figure 3This is an architectural diagram of an embedded SoC built using a processor developed based on this design method; the following lists the parameters of the processor in the test program and hardware manufacturing process. The configuration parameters and specific implementation effects described here are for explanation only and are not used to limit this design method. In the Coremark test, the processor has a single-core running score of 1.51 / MHz under the configuration of L1 instruction cache and data cache of 4KB, L2 shared cache of 8KB, and branch prediction containing 256 BTB items, which is higher than the domestic open source RISC-V sequential scalar processor benchmark Nutshell with larger L1 and L2 caches; using the same processor configuration, building an SoC with a 32GB SD card containing 128MB DDR2 and SPI interface, and using a 100MHz main frequency test on the FPGA, the UnixBench system performance test set running score results are shown in Table 1 below, of which 6 items are higher than the international open source RISC-V sequential processor flagship Rocket, which can only reach 80MHz in the same FPGA environment. Under the SMIC 110nm process, after replacing SMIC's PLL and SRAM IP cores, the processor without any customized functional units can reach a main frequency of 300MHz.

[0033] Table 1: UnixBench scores of the processor developed using this design method on a 100MHz FPGA

[0034]

[0035] Those skilled in the art can understand that the above is only a single example of the invention and is not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical methods recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims

1. A customizable RISC-V architecture processor design method for embedded scenarios, characterized in that: The following steps are included: 1) Use agile development methods to design embedded processors that support the RV64GC instruction set: According to the RISC-V instruction set manual, implement and verify the processor pipeline that supports the RV64I instruction set and the Machine privileged state, implement the standard interrupt controller Clint and PLIC, and gradually add and verify new instruction sets and privileged state support on this basis, and finally implement a complex processor that supports integer, multiplication and division, atomic, floating point, compressed instructions, and Machine, Supervisor, and User privileged states; 2) Design and implement cache consistency and memory consistency: Design and implement cache units, use a combination of software and hardware to ensure the consistency between data cache and instruction cache, data cache and TLB, and implement the RVWMO memory consistency model specified in the RISC-V manual; 3) Design a flexible and powerful customized functional unit interface: Provide a flexible and powerful interface for the customized functional units integrated inside the processor, and appropriately adjust the design of the processor pipeline according to the function of the interface; In step 3), the customized functional unit interface includes a simple customized extension that can be completed in a single cycle and only writes the calculation result back to the destination register, and a complex extension that requires multiple cycles or memory access operations; For the simple customized expansion that can be completed in a single cycle and only writes the operation result back to the destination register, the corresponding functional unit is placed in the pipeline execution stage; For the complex extensions that require multiple cycles or memory access operations, the functional units are placed in the memory access segment or the write-back segment; For different customized functions, the processor pipeline provides the following functions for the interface of the customized functional unit: for reading and writing back register operations, 2 read ports and 1 write port are provided; for reading and writing back CSR, 1 read port and 1 write port are provided; for memory access operations, 1 read port and 1 write port are provided.

2. The method for designing a customizable RISC-V architecture processor for embedded scenarios according to claim 1, characterized in that: In step 1), in each round of agile development, starting from the formulation of design specifications, the current version of the processor goes through circuit design, definition of customized functional unit interface, code implementation, and correctness verification steps before entering the next round to add new functions to the next version of the processor.

3. The method for designing a customizable RISC-V architecture processor for embedded scenarios according to claim 1, characterized in that: In steps 1) and 2), during the agile development process, the configurable characteristics of the processor are taken into consideration, and the cache size and replacement strategy, branch prediction strategy, the minimum privileged state supported by the processor, compressed instructions and custom extension features are all parameterized.

4. The method for designing a customizable RISC-V architecture processor for embedded scenarios according to claim 1, characterized in that: The method uses a synchronous decoupling interface to encapsulate the interactive information between the customized functional unit and other functional units, and between the customized functional unit and the processor pipeline. The decoupling interface encapsulates and transmits more customized information according to the customization needs.

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