Timing bottleneck detection method, device, terminal equipment and storage medium

Abstract

The present invention discloses a timing bottleneck detection method, device, terminal equipment and storage medium. The method includes initializing a circuit timing diagram, and traversing each node in the circuit timing diagram from front to back according to the topological sorting result of the circuit timing diagram, and calculating the arrival time of each node; traversing each node in the circuit timing diagram from back to front according to the topological sorting result of the circuit timing diagram, and calculating the required time from each node to each corresponding sub-node; calculating the total fan-out negative margin of each node according to the arrival time of each node and the required time from each node to each corresponding sub-node; calculating the total fan-out negative margin of each combinational logic unit in the circuit timing diagram according to the total fan-out negative margin of each node, and then determining the timing bottleneck according to the total fan-out negative margin of each combinational logic unit. By implementing the present invention, the detection of timing bottlenecks in circuits can be realized.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation technology, and in particular to a timing bottleneck detection method, device, terminal equipment and storage medium. Background Art

[0002] Static timing analysis is a workflow in electronic engineering that calculates and predicts the timing of digital circuits. This process does not require simulation through input stimulation. Traditionally, people often use the operating clock frequency as one of the characteristics of high-performance integrated circuits. In order to test the ability of a circuit to operate at a specified rate, it is necessary to measure the delay of the circuit at different working stages during the design process. In addition, in different design stages (such as logic synthesis, layout, routing, and some subsequent stages), it is necessary to calculate the delay of the internal path of the circuit to guide optimization. The path that a signal passes through during transmission from a timing element to another timing element is a timing path, and one or more timing paths that have a decisive influence on the final timing performance of the circuit are defined as critical paths. The timing bottleneck is the combinational logic unit or wire network that determines the size and number of the critical path delay in the entire design, and the greatest impact on the optimization target, which is often manifested as high-delay logic or high-fan-out wire network. Reducing the delay or number of timing bottlenecks can significantly improve the convergence speed of the software and the overall performance of the circuit. To reduce the delay or number of timing bottlenecks, it is first necessary to detect the timing bottlenecks in the circuit. How to detect the timing bottlenecks in the circuit is an urgent problem that needs to be solved. Summary of the invention

[0003] The embodiments of the present invention provide a timing bottleneck detection method, an apparatus, a terminal device and a storage medium, which can detect the timing bottleneck in a circuit.

[0004] An embodiment of the present invention provides a timing bottleneck detection method, comprising: initializing a circuit timing diagram, and traversing each node in the circuit timing diagram from front to back according to a topological sorting result of the circuit timing diagram, and calculating the arrival time of each node;

[0005] According to the topological sorting result of the circuit timing diagram, each node in the circuit timing diagram is traversed from back to front, and the required time from each node to the corresponding sub-nodes is calculated;

[0006] Calculate the total fan-out negative margin of each node based on the arrival time of each node and the demand time from each node to the corresponding sub-nodes;

[0007] The total negative fan-out margin of each combinational logic unit in the circuit timing diagram is calculated according to the total negative fan-out margin of each node, and then the timing bottleneck is determined according to the total negative fan-out margin of each combinational logic unit.

[0008] Further, determining the timing bottleneck according to the total fan-out negative margin of each of the combinational logic units specifically includes:

[0009] Calculate the absolute value of the total fan-out negative margin of each combinational logic unit to obtain the timing bottleneck value of each combinational logic unit;

[0010] The timing bottleneck values ​​of the combinational logic units are sorted from large to small, and the combinational logic units that are ranked before a preset order are taken as timing bottlenecks.

[0011] Furthermore, after calculating the required time from each node to the corresponding sub-nodes, it also includes:

[0012] According to the demand time from each node to the corresponding child nodes, with the demand time as the key and the total number of child nodes corresponding to the same demand time as the value, a demand time record table for each node is generated and stored.

[0013] Furthermore, after generating the demand time record table for each node, it also includes:

[0014] When it is determined that a data pair entry recorded in a demand time record table exceeds a preset threshold value N, the interval between the maximum demand time and the minimum demand time in the demand time record table is divided into N-1 equal parts;

[0015] The maximum demand time, the minimum demand time and the time corresponding to each equally divided point are all used as mapping time;

[0016] Project each demand time onto the coordinate axis formed by each mapping time, calculate the offset between each demand time projection and the two nearest mapping times, and then use the mapping time with the smaller offset as the mapping time corresponding to the demand time;

[0017] Each demand time is replaced with the corresponding mapping time to obtain a number of updated demand times, and then the demand time record table is updated according to each updated demand time.

[0018] Furthermore, the total fan-out negative margin of each node is calculated according to the arrival time of each node and the demand time from each node to the corresponding sub-nodes, specifically including:

[0019] According to the demand time record table of each node, obtain the demand time corresponding to each node and the number of sub-nodes corresponding to each demand time;

[0020] The total fan-out negative margin of each node is calculated based on the demand times corresponding to each node, the number of child nodes corresponding to each demand time, and the arrival time of each node.

[0021] Based on the above method embodiment, the present invention provides a corresponding device embodiment;

[0022] An embodiment of the present invention provides a timing bottleneck detection device, including an arrival time calculation module, a demand time calculation module, a total fan-out negative margin calculation module, and a timing bottleneck determination module;

[0023] The arrival time calculation module is used to initialize the circuit timing diagram, and traverse each node in the circuit timing diagram from front to back according to the topological sorting result of the circuit timing diagram, and calculate the arrival time of each node;

[0024] The demand time calculation module is used to traverse each node in the circuit timing diagram from back to front according to the topological sorting result of the circuit timing diagram, and calculate the demand time from each node to the corresponding sub-nodes;

[0025] The total fan-out negative margin calculation module is used to calculate the total fan-out negative margin of each node according to the arrival time of each node and the demand time from each node to the corresponding sub-nodes;

[0026] The timing bottleneck determination module is used to calculate the total fan-out negative margin of each combinational logic unit in the circuit timing diagram according to the total fan-out negative margin of each node, and then determine the timing bottleneck according to the total fan-out negative margin of each combinational logic unit.

[0027] Furthermore, it also includes a demand time record table generation module; the demand time record table generation module is used to generate a demand time record table for each node based on the demand time from each node to the corresponding sub-nodes, with the demand time as the key and the total number of sub-nodes corresponding to the same demand time as the value, and store the demand time record table.

[0028] Furthermore, it also includes a demand time record table update module;

[0029] The demand time record table updating module is used to divide the interval between the maximum demand time and the minimum demand time in the demand time record table into N-1 parts when it is determined that the data pair entry recorded in a demand time record table exceeds a preset threshold value N;

[0030] The maximum demand time, the minimum demand time and the time corresponding to each equally divided point are all used as mapping time;

[0031] Project each demand time onto the coordinate axis formed by each mapping time, calculate the offset between each demand time projection and the two nearest mapping times, and then use the mapping time with the smaller offset as the mapping time corresponding to the demand time;

[0032] Each demand time is replaced with the corresponding mapping time to obtain a number of updated demand times, and then the demand time record table is updated according to each updated demand time.

[0033] Based on the above method embodiment, the present invention provides a terminal device embodiment;

[0034] An embodiment of the present invention provides a timing bottleneck detection terminal device, comprising: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the timing bottleneck detection method described in any one of the present invention is implemented.

[0035] Based on the above method embodiment, the present invention provides a storage medium embodiment;

[0036] An embodiment of the present invention provides a storage medium, wherein the storage medium includes a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute any one of the timing bottleneck detection methods described in the present invention.

[0037] The following beneficial effects are achieved by implementing the embodiments of the present invention:

[0038] The embodiment of the present invention provides a timing bottleneck detection method, the method first initializes the circuit timing diagram, then traverses each node in the circuit timing diagram from front to back according to the topological sorting result of the circuit timing diagram, calculates the arrival time of each node, then traverses each node from back to front, calculates the required time from each node to the corresponding sub-nodes, calculates the total fan-out negative margin of each node according to the arrival time of each node and the required time from each node to the corresponding sub-nodes, finally calculates the fan-out negative margin of each combinational logic unit, and determines the timing bottleneck of the circuit according to the fan-out negative margin of each combinational logic unit. Through the timing bottleneck detection method provided by the present invention, the detection of the timing bottleneck in the circuit can be realized, laying a foundation for the subsequent improvement of the overall performance of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flowchart of a timing bottleneck detection method provided by an embodiment of the present invention.

[0040] Figure 2 It is a schematic diagram of the principle of backtracking path information provided by an embodiment of the present invention.

[0041] Figure 3 It is another principle schematic diagram of the backtracking path information provided by an embodiment of the present invention.

[0042] Figure 4It is a schematic diagram of the principle of demand time mapping provided by an embodiment of the present invention.

[0043] Figure 5 It is a structural schematic diagram of a timing bottleneck detection device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] To better illustrate the present invention, several concepts are described below:

[0046] Static timing analysis: In electronic engineering, the process of calculating and predicting the timing of digital circuits does not require simulation through input stimulation. Traditionally, people often use the operating clock frequency as one of the characteristics of high-performance integrated circuits. In order to test the ability of a circuit to operate at a specified rate, people need to measure the delay of the circuit at different working stages during the design process. In addition, at different design stages (such as logic synthesis, layout, routing, and some subsequent stages), it is necessary to calculate the delay of the internal path of the circuit to guide optimization. Static timing analysis plays an important role in the fast and accurate measurement of circuit timing.

[0047] Timing path: The path that a signal passes through when it is transmitted from a timing element to another timing element. It is usually composed of combinational logic elements and wire network intersections.

[0048] Critical path: One or more timing paths that have a decisive influence on the final timing performance of the circuit. Generally refers to the timing path with the largest combined path delay in the design. Reducing the delay of the critical path through optimization can effectively improve the overall performance of the circuit, that is, the highest operating frequency.

[0049] Timing bottleneck: The combinational logic unit or network that determines the size and number of critical path delays in the entire design and has the greatest impact on the optimization target is often manifested as high-delay logic or high fan-out network. Reducing the delay or number of timing bottlenecks can significantly improve the convergence speed of the software and the overall performance of the circuit.

[0050] Timing diagram: A directed acyclic graph that describes the structure of a circuit. In the diagram, nodes represent the input and output pins of basic unit circuits such as registers or logic gates, and edges represent the connection from input to output of a combinational logic unit circuit, or the connection specified by the circuit netlist. Each edge is marked with the delay required to pass through the unit circuit or routing resources.

[0051] Arrival delay (arrival time): The time it takes for a signal to reach a specified location in a circuit. The arrival time of a clock signal is generally used as the reference time, or time zero. In order to calculate the arrival time, the delay accumulation calculation of all combinational logic paths on the path is required.

[0052] Required delay (required): For any position, the signal can reach without causing the overall circuit to violate the timing design requirements. Usually the path end point is reversely calculated by combining the delay from this specified position to the end point.

[0053] Delay margin: The difference between the required time and the arrival time at the same location. A positive margin at any location in the circuit means that the arrival time here can be increased by the time represented by the margin, and it will not affect the overall delay of the circuit. On the contrary, a negative margin means that the transmission on the path is too slow, and the transmission rate of this path must be increased, otherwise the overall circuit composed of it will not be able to run at the expected rate.

[0054] Timing arc: An edge between any two adjacent nodes in a timing graph.

[0055] As an important engine, static timing analysis is widely used in various stages of circuit design and optimization fields. According to different needs, a variety of technical routes have emerged. The mainstream static timing analysis methods are mainly divided into two types: graph scanning method and path enumeration method.

[0056] The graph scanning method is a linear traversal scanning method. It traverses the nodes in the timing graph from low to high or from high to low in order according to the topological sorting depth of the nodes. Each node is visited once (the arrival time and demand time are calculated respectively). After completion, the timing information of any node can be obtained.

[0057] The path enumeration method is more intuitive. It starts from the starting point and propagates to the downstream node until the end point according to the direction of signal transmission, and obtains the entire propagation footprint, that is, all path information from the starting point to the end point. The basic operation object of this algorithm is the path. The total delay of the path is obtained by adding up the delays of all nodes between the starting point and the end point of each path.

[0058] The present invention is described below. Figure 1 As shown, an embodiment of the present invention provides a timing bottleneck detection method, which at least includes:

[0059] Step S101: Initialize a circuit timing diagram, and traverse each node in the circuit timing diagram from front to back according to a topological sorting result of the circuit timing diagram, and calculate the arrival time of each node.

[0060] Step S102: traverse each node in the circuit timing diagram from back to front according to the topological sorting result of the circuit timing diagram, and calculate the required time from each node to the corresponding sub-nodes.

[0061] Step S103: Calculate the total fan-out negative margin of each node according to the arrival time of each node and the required time from each node to the corresponding sub-nodes.

[0062] Step S104: calculating the total negative fan-out margin of each combinational logic unit in the circuit timing diagram according to the total negative fan-out margin of each node, and then determining the timing bottleneck according to the total negative fan-out margin of each combinational logic unit.

[0063] For step S101, preferably, after initializing the circuit timing diagram, traverse each node in the circuit timing diagram based on the topological sorting result of the circuit timing diagram based on the graph scanning method, and calculate the arrival time of each node during the traversal process;

[0064] For step S102, in the existing graph scanning method, the demand time of any node is determined by its child nodes. If the node is the end point of the timing path, its demand time is the clock cycle. If the node is an intermediate node in the timing path, its demand time is obtained by calculating the demand time of the child node minus the delay of the timing arc. When the number of child nodes is large, the minimum value of the demand time converted from each child node is taken as the demand time of the current node. The above process shows that if the existing graph scanning method is used to traverse the nodes in the circuit timing diagram from back to front, the demand time of each node only comes from a certain child node, and the demand time converted from other child nodes is ignored, that is, the path information traced back from other child nodes is completely discarded, making it impossible to calculate the total negative margin of the fan-out of the node in the subsequent steps, and it is impossible to reflect the timing of its entire fan-out area. In order to solve this problem, in a preferred embodiment, when traversing each node in the circuit timing diagram from back to front based on the graph scanning method, the storage path information is recorded at the same time to obtain the required time from each node to the corresponding sub-nodes;

[0065] Indicatively, Figure 2As shown: 201, 202, 205 are the intermediate nodes of the timing path, 203, 204, 206, 207 are the end points of the timing path, and the required time is clock cycle 10. The delay is marked on the timing arc. When the backward traversal reaches 202, the required times reversed from the child nodes 203 and 204 are recorded as req#203:5 and req#204:9 respectively. Similarly, the 205 node records the required times reversed from 206 and 207 as req#206:7 and req#207:7. When it reaches 201, the downstream path information of 202 and 205 is transmitted and summarized, and it can be intuitively obtained that there are 4 downstream paths of 201: 201-202-203, 201-202-204, 201-205-206, 201-205-207. Their demand times are recorded on node 201, and then passed to the parent node of 201. The demand times of the downstream paths of 201 are req#203: 0, req#204: 4, req#206: 4, and req#207: 4.

[0066] Although the above method can calculate the required time from each node to the corresponding child nodes, as the backward traversal progresses or the connectivity of the time series graph increases, the path information that needs to be recorded on the node increases explosively, showing the significant characteristics of the path enumeration method. It is necessary to reduce the complexity so that the backward traversal process returns to the basic properties of the graph traversal method.

[0067] Since the subsequent calculation of the total fan-out margin of each node only requires the statistical information of all paths, no specific information of the paths is required. Therefore, in a preferred embodiment, after calculating the demand time from each node to the corresponding sub-nodes, it also includes: according to the demand time from each node to the corresponding sub-nodes, using the demand time as a key and the total number of sub-nodes corresponding to the same demand time as a value, generating a demand time record table for each node, and storing the demand time record table.

[0068] Specifically, a demand time record table (key, value) is established on each node, where the demand time is the key and the total number of paths corresponding to the demand time is the value. Figure 2 The information of each node shown is compressed to obtain Figure 3 The backtracking path information shown is as follows: Figure 3As shown, at node 202, the demand times inferred from 203 and 204 are 5 and 9 respectively, so the demand time record table stores two pairs of (key, value): req#1: (5, 1) and req#2: (9, 1); at node 205, the demand times inferred from 206 and 207 are equal (both are 7), so the lookup table only stores one pair of (key, value): req#1: (7, 2), which means that the number of paths with a demand time of 7 in the fan-out area is 2. Similarly, at node 201, the lookup table stores two pairs of (key, value): req#1: (0, 1) and req#1: (4, 3), which means that the number of paths with a demand time of 4 in its fan-out area is 3, and the number of paths with a demand time of 0 is 1. Figure 2 In comparison, the number of entries that need to be stored in nodes 201 and 205 is halved. When passing the information to the parent node, the merged information also reduces the computational complexity of the parent node.

[0069] The compression of the backtracking path information can be achieved through the above embodiment, but the above compression method requires that the number of paths can be merged only when the demand time is completely equal. When the design scale increases and the timing model becomes more complex, the demand time values ​​of the nodes will be widely distributed. When there are tens of thousands of fan-out paths, simple compression will fail.

[0070] Therefore, in a preferred embodiment, after generating the demand time record table of each node, the method further includes:

[0071] When it is determined that a data pair entry recorded in a demand time record table exceeds a preset threshold value N, the interval between the maximum demand time and the minimum demand time in the demand time record table is divided into N-1 equal parts;

[0072] The maximum demand time, the minimum demand time and the time corresponding to each equally divided point are all used as mapping time;

[0073] Project each demand time onto the coordinate axis formed by each mapping time, calculate the offset between each demand time projection and the two nearest mapping times, and then use the mapping time with the smaller offset as the mapping time corresponding to the demand time;

[0074] Each demand time is replaced with the corresponding mapping time to obtain a number of updated demand times, and then the demand time record table is updated according to each updated demand time.

[0075] Specifically, in order to further control the increase of node storage entries as the traversal progresses, we proposed a method to project the demand time and approximate the segmented target value, so that the storage entries in any node are controlled within a fixed upper limit (i.e., the above-mentioned preset threshold) N. This upper limit value does not change with the node. When the demand time entry of the node is less than N, all demand times do not need to be projected and calculated, and are saved as the original value. When the demand time entries exceed N, it is necessary to project and approximate the demand time and replace the corresponding mapping time.

[0076] Indicatively, Figure 4 As shown in the figure, when N is 6, it is assumed that there are 8 demand times recorded in the original demand time record table: Rmin (minimum demand time), Rmax (maximum demand time), R1-R6 (other demand times in the demand time record table except the minimum demand time and the maximum demand time); the closed interval determined by Rmin-Rmax is divided into 5 parts (N-1), and 6 mapping times are obtained: Dmin, Dmax, D1-D4, that is, the demand time finally stored in this node can only be any one of the 6 mapping times. Projecting R1-R6 to the coordinate axis determined by Dmin-Dmain respectively, it can be intuitively seen that R1 and R2 are approximately represented as D1, R3 is approximately represented as D2, R4, R5, and R6 are approximately represented as D3, and D4 has no match as a mapping time. The principle of approximate value is: take the mapping time with the smaller offset between the original demand time projection and the two most recent mapping times. If the projection of R6 falls between D3 and D4, and the offset from D3 is small, then the mapping time corresponding to R6 is D3. According to the above method, it can be determined that the mapping time corresponding to Rmin is Dmin, the mapping time corresponding to Rmax is Dmax, the mapping time corresponding to R1 and R2 is D1, the mapping time corresponding to R3 is D2, and the mapping time corresponding to R4, R5, and R6 is D3; then each demand time is replaced with the corresponding mapping time, and then the demand time record table is updated; assuming that the data pairs stored in the original demand time record table are: (Rmin, Nmin), (R1, N1), (R2, N2), (R3 , N3), (R4, N4), (R5, N5), (R6, N6), (Rmax, Nmax), then the updated demand time record table is: (Dmin, Nmin), (D1, N1+N2), (D2, N3), (D3, N4+N5+N6), (Dmax, Nmax), the amount of stored data is reduced from 8 to 4, which greatly reduces the amount of data. From the above process, it can be seen that no matter how large the demand time entry scale of the child node input is, the number of entries after compression does not exceed the constant N, that is, within any node. On the other hand, the larger the value of N, the smaller the segmentation, the smaller the projection approximation error, and the more accurate the result.

[0077] In addition, in other preferred embodiments, the time difference between each demand time and each mapping time in the demand time record table can be calculated one by one, and the mapping time corresponding to each demand time can be determined according to the time difference; wherein the mapping time corresponding to a demand time is the mapping time with the smallest time difference therewith;

[0078] For step S103, firstly, the total fan-out negative margin of each node is described. The total fan-out negative margin of a node is the sum of the negative values ​​of the timing margins from the node to each child node;

[0079] In a preferred embodiment, if only Figure 2 The principle shown in the figure obtains the demand time from the node to each corresponding child node, but does not generate a demand time record table for each child node. In this case, when calculating the total fan-out negative margin of each node, the timing margin from the node to each child node is calculated one by one according to the demand time from the node to each corresponding child node and the arrival time of the node. Then, the total fan-out negative margin of each node can be obtained by counting the sum of the negative values ​​of the timing margin. Specifically, Figure 2 As shown, the demand times from node 202 to child nodes 203 and 204 are 5 and 9 respectively, and the arrival time of node 202 is 8 (i.e., "arr: 8" in the figure), then the timing margin from node 202 to child node 203 is -3, and the timing margin from node 202 to child node 204 is 1, then the total fan-out negative margin of node 202 is the timing margin from node 202 to child node 203 -3; the demand times from node 205 to child nodes 206 and 207 are both 7, and the arrival time of node 205 is 6 (i.e., "arr: 6" in the figure), then the timing margin from node 205 to child node 206 is 1, and the timing margin from node 205 to child node 207 is 1, there is no negative timing margin, and the total fan-out negative margin of node 205 is 0. Similarly, the arrival time of node 201 is 3 (i.e., "arr: 3" in the figure), and the required times are 0, 4, 4, and 4, respectively, and the corresponding margins are -3, 1, 1, and 1, respectively. Therefore, the total fan-out margin of 201 is -3.

[0080] In another preferred embodiment of the present invention, if a demand time record table of each child node has been generated, then when calculating the total fan-out negative margin of each node, each demand time corresponding to the node in the demand time record table and the number of child nodes corresponding to each demand time are obtained, and then each timing margin corresponding to the node is calculated and the number corresponding to each timing margin is determined according to the number of child nodes, and finally the total fan-out negative margin of each node is calculated according to each timing margin and the number corresponding to each timing margin; specifically, as Figure 3As shown, there are two data in the demand time record table of node 201: req#1: (0,1) and req#2: (4,1); then the timing margin -3, number 1; timing margin 1, number 3 can be obtained; then the final total fan-out negative margin is: -3*1=-3.

[0081] For step S104, in a preferred embodiment, determining the timing bottleneck according to the total fan-out negative margin of each of the combinational logic units specifically includes: calculating the absolute value of the total fan-out negative margin of each combinational logic unit to obtain the timing bottleneck value of each combinational logic unit; sorting the timing bottleneck values ​​of the combinational logic units from large to small, and taking the combinational logic units before the preset order as the timing bottleneck.

[0082] In the present invention, a definition of total fan-out negative margin is proposed for a general combinatorial logic unit in a timing path: starting from all output pins of the combinatorial logic unit, in all paths to the timing end point, the path delay margin is the sum of negative values ​​(i.e., the total negative margin of each combinatorial logic unit is the sum of the total fan-out negative margins of all its output nodes). After the total fan-out negative margin of each node is calculated in step S103, the sum of the total fan-out negative margins of the output nodes corresponding to the combinatorial logic unit is calculated, and finally the total fan-out negative margin of the combinatorial logic unit is obtained, and then the absolute value of the total fan-out negative margin of each combinatorial logic unit is used as the timing bottleneck value of each combinatorial logic unit, and the timing bottleneck values ​​are sorted from large to small, and the combinatorial logic units before the preset order are used as the timing bottleneck; for example, the above preset order can be 3, then the combinatorial logic units ranked in the first two positions are used as the timing bottleneck. The above preset order can be adjusted according to actual needs.

[0083] In a preferred embodiment, after the timing bottleneck values ​​of the combinational logic units are sorted from large to small, a timing bottleneck sorting table is generated. Subsequently, the user can debug each combinational logic unit in the circuit one by one according to the sorting order according to the generated timing bottleneck sorting table to improve the circuit performance.

[0084] Based on the above method embodiment, the present invention provides a corresponding device embodiment;

[0085] like Figure 5 As shown, an embodiment of the present invention provides a timing bottleneck detection device, including: an arrival time calculation module, a demand time calculation module, a total fan-out negative margin calculation module and a timing bottleneck determination module;

[0086] The arrival time calculation module is used to initialize the circuit timing diagram, and traverse each node in the circuit timing diagram from front to back according to the topological sorting result of the circuit timing diagram, and calculate the arrival time of each node;

[0087] The demand time calculation module is used to traverse each node in the circuit timing diagram from back to front according to the topological sorting result of the circuit timing diagram, and calculate the demand time from each node to the corresponding sub-nodes;

[0088] The total fan-out negative margin calculation module is used to calculate the total fan-out negative margin of each node according to the arrival time of each node and the demand time from each node to the corresponding sub-nodes;

[0089] The timing bottleneck determination module is used to calculate the total fan-out negative margin of each combinational logic unit in the circuit timing diagram according to the total fan-out negative margin of each node, and then determine the timing bottleneck according to the total fan-out negative margin of each combinational logic unit.

[0090] In a preferred embodiment, it also includes: a demand time record table generation module; the demand time record table generation module is used to generate a demand time record table for each node based on the demand time from each node to the corresponding child nodes, with the demand time as the key and the total number of child nodes corresponding to the same demand time as the value, and store the demand time record table.

[0091] In a selected embodiment, it further includes: a demand time record table updating module; the demand time record table updating module is used to divide the interval between the maximum demand time and the minimum demand time in the demand time record table into N-1 parts when it is determined that the data pair entry recorded in a demand time record table exceeds a preset threshold value N;

[0092] The maximum demand time, the minimum demand time and the time corresponding to each equally divided point are all used as mapping time;

[0093] Project each demand time onto the coordinate axis formed by each mapping time, calculate the offset between each demand time projection and the two nearest mapping times, and then use the mapping time with the smaller offset as the mapping time corresponding to the demand time;

[0094] Each demand time is replaced with the corresponding mapping time to obtain a number of updated demand times, and then the demand time record table is updated according to each updated demand time.

[0095] Based on the above method embodiment, the present invention provides a corresponding terminal device embodiment;

[0096] An embodiment of the present invention provides a timing bottleneck detection terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements any one of the timing bottleneck detection methods described above when executing the computer program.

[0097] Based on the above method embodiment, the present invention provides a storage medium embodiment;

[0098] An embodiment of the present invention provides a storage medium, wherein the storage medium includes a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute any one of the timing bottleneck detection methods described above.

[0099] It should be noted that the above-mentioned timing bottleneck detection device / terminal device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps in the above-mentioned timing bottleneck detection method embodiments are implemented, for example Figure 1 Alternatively, the processor implements the functions of each module in the above-mentioned device embodiments when executing the computer program.

[0100] Exemplarily, the computer program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program in the timing bottleneck detection device / terminal device.

[0101] The timing bottleneck detection device / terminal device can be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The timing bottleneck detection device / terminal device can include, but is not limited to, a processor and a memory. Those skilled in the art can understand that the schematic diagram is only an example of the timing bottleneck detection device / terminal device and does not constitute a limitation on the timing bottleneck detection device / terminal device. It can include more or less components than shown in the figure, or combine certain components, or different components. For example, the timing bottleneck detection device / terminal device can also include input and output devices, network access devices, buses, etc.

[0102] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the timing bottleneck detection device / terminal device, and uses various interfaces and lines to connect various parts of the entire timing bottleneck detection device / terminal device.

[0103] The memory can be used to store the computer program and / or module, and the processor realizes various functions of the timing bottleneck detection device / terminal device by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0104] Wherein, if the module integrated in the timing bottleneck detection device / terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media does not include electrical carrier signals and telecommunication signals.

[0105] It should be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the accompanying drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art may understand and implement it without paying any creative effort.

[0106] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A timing bottleneck detection method, characterized in that: include: Initialize the circuit timing diagram, and traverse each node in the circuit timing diagram from front to back according to the topological sorting result of the circuit timing diagram, and calculate the arrival time of each node; According to the topological sorting result of the circuit timing diagram, each node in the circuit timing diagram is traversed from back to front, and the required time from each node to the corresponding sub-nodes is calculated; Calculate the total fan-out negative margin of each node based on the arrival time of each node and the demand time from each node to the corresponding sub-nodes; Calculating the total negative fan-out margin of each combinational logic unit in the circuit timing diagram according to the total negative fan-out margin of each node, and then determining the timing bottleneck according to the total negative fan-out margin of each combinational logic unit; After calculating the required time from each node to the corresponding sub-nodes, it also includes: According to the demand time from each node to the corresponding child nodes, with the demand time as the key and the total number of child nodes corresponding to the same demand time as the value, a demand time record table for each node is generated, and the demand time record table is stored; After generating the demand time record table for each node, it also includes: When it is determined that the data pair entry recorded in a demand time record table exceeds a preset threshold value N, the interval between the maximum demand time and the minimum demand time in the demand time record table is divided into N-1 equal parts; The maximum demand time, the minimum demand time and the time corresponding to each equally divided point are all used as mapping time; Project each demand time onto the coordinate axis formed by each mapping time, calculate the offset between each demand time projection and the two nearest mapping times, and then use the mapping time with the smaller offset as the mapping time corresponding to the demand time; Each demand time is replaced with the corresponding mapping time to obtain a number of updated demand times, and then the demand time record table is updated according to each updated demand time.

2. The timing bottleneck detection method according to claim 1, characterized in that: Determining the timing bottleneck according to the total fan-out negative margin of each of the combinational logic units specifically includes: Calculate the absolute value of the total fan-out negative margin of each combinational logic unit to obtain the timing bottleneck value of each combinational logic unit; The timing bottleneck values ​​of the combinational logic units are sorted from large to small, and the combinational logic units that are ranked before a preset order are taken as timing bottlenecks.

3. The timing bottleneck detection method according to claim 1, characterized in that: The total fan-out negative margin of each node is calculated according to the arrival time of each node and the demand time from each node to the corresponding sub-nodes, specifically including: According to the demand time record table of each node, obtain the demand time corresponding to each node and the number of sub-nodes corresponding to each demand time; The total fan-out negative margin of each node is calculated based on the demand times corresponding to each node, the number of child nodes corresponding to each demand time, and the arrival time of each node.

4. A timing bottleneck detection device, characterized in that: include: Arrival time calculation module, demand time calculation module, total fan-out negative margin calculation module and timing bottleneck determination module; The arrival time calculation module is used to initialize the circuit timing diagram, and traverse each node in the circuit timing diagram from front to back according to the topological sorting result of the circuit timing diagram, and calculate the arrival time of each node; The demand time calculation module is used to traverse each node in the circuit timing diagram from back to front according to the topological sorting result of the circuit timing diagram, and calculate the demand time from each node to the corresponding sub-nodes; The total fan-out negative margin calculation module is used to calculate the total fan-out negative margin of each node according to the arrival time of each node and the demand time from each node to the corresponding sub-nodes; The timing bottleneck determination module is used to calculate the total fan-out negative margin of each combinational logic unit in the circuit timing diagram according to the total fan-out negative margin of each node, and then determine the timing bottleneck according to the total fan-out negative margin of each combinational logic unit; The timing bottleneck detection device further includes: a demand time record table generation module; The demand time record table generation module is used to generate a demand time record table for each node according to the demand time from each node to the corresponding sub-nodes, using the demand time as a key and the total number of sub-nodes corresponding to the same demand time as a value, and store the demand time record table; The timing bottleneck detection device also includes: a demand time record table updating module; The demand time record table updating module is used to divide the interval between the maximum demand time and the minimum demand time in the demand time record table into N-1 parts when it is determined that the data pair entry recorded in a demand time record table exceeds a preset threshold value N; The maximum demand time, the minimum demand time and the time corresponding to each equally divided point are all used as mapping time; Project each demand time onto the coordinate axis formed by each mapping time, calculate the offset between each demand time projection and the two nearest mapping times, and then use the mapping time with the smaller offset as the mapping time corresponding to the demand time; Each demand time is replaced with the corresponding mapping time to obtain a number of updated demand times, and then the demand time record table is updated according to each updated demand time.

5. A timing bottleneck detection terminal device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the timing bottleneck detection method according to any one of claims 1 to 3 when executing the computer program.

6. A storage medium, characterized in that: The storage medium includes a stored computer program, wherein when the computer program is executed, the device where the storage medium is located is controlled to execute the timing bottleneck detection method according to any one of claims 1 to 3.

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