Programming and verification methods applied to a multi-level memory cell array

Abstract

A programming and verification method for a multi-level memory cell array, the multi-level memory cell array comprising: a plurality of memory cells in a first column, connected to a word line, a source line, an erase line, and a plurality of bit lines, each of the memory cells being programmed to a target storage state during a programming cycle, the target storage state being one of X storage states, the programming and verification method comprising the following steps: (a1) determining the first column as a selected column and setting A equal to 1; (a2) in the selected column, except for the memory cells that have reached the target storage state and the defective memory cells, programming the other memory cells to a first A storage state; (a3) when A is not equal to X, incrementing A by 1 and returning to step (a2); and (a4) when A is equal to X, ending the programming cycle; wherein, in step (a2), multiple write operations and multiple verification operations are performed on the other memory cells of the selected column until the other memory cells reach the first A storage state.

Description

Technical Field

[0001] The present invention relates to a control method for an array of memory cells, and more particularly to a programming and verification method for a multi-level memory cell array. Background Art

[0002] As is well known, non-volatile memory can continuously record data even after the power supply is stopped. Therefore, non-volatile memory has been widely used in various electronic devices. Generally, non-volatile memory can be divided into one-time programmable non-volatile memory (OTP non-volatile memory for short) and multi-time programmable non-volatile memory (MTP non-volatile memory for short). Furthermore, the OTP non-volatile memory includes a plurality of one-time programmable non-volatile memory cells (OTP memory cells for short), and the MTP non-volatile memory includes a plurality of multi-time programmable non-volatile memory cells (MTP memory cells for short).

[0003] Please refer to Figure 1A and Figure 1B , which shows a known MTP memory cell composed of a floating gate transistor and a bias schematic diagram. This MTP memory cell 100 is disclosed in U.S. Patent No. US 8,941,167.

[0004] The MTP memory cell 100 includes a select transistor T, a floating gate transistor M, and a capacitor C. Among them, the select transistor T and the floating gate transistor M are P-type transistors, which are fabricated in an N-type well region NW. In addition, the capacitor C is composed of an N-type transistor, which is fabricated in a P-type well region PW.

[0005] The source terminal of the select transistor T is connected to a source line SL, the gate terminal of the select transistor T is connected to a word line WL, the source terminal of the floating gate transistor M is connected to the drain terminal of the select transistor T, and the drain terminal of the floating gate transistor M is connected to a bit line BL. Furthermore, the gate terminal of the N-type transistor is the first end of the capacitor C and is connected to the floating gate terminal of the floating gate transistor M, and the drain terminal and the source terminal of the N-type transistor are connected to each other, serving as the second end of the capacitor C and connected to an erase line EL. Among them, a programming path and a read path can be formed between the source line SL and the bit line BL of the MTP memory cell 100, and an erase path is formed between the floating gate terminal and the erase line EL.

[0006] As shown in Figure 1BAs shown, during a program cycle, a write action can be performed to cause the memory cell 100 to assume different storage states. When performing a write action, the memory cell 100 can be programmed or program inhibition can be applied to the memory cell 100. When programming the memory cell 100, the floating gate of the hot carrier injection floating gate transistor M can be controlled. When inhibiting the programming of the memory cell 100, the injection of hot carriers into the floating gate of the floating gate transistor M can be controlled. Herein, the hot carriers are electrons.

[0007] When programming the memory cell 100, a turn-on voltage of 4V is provided to the word line WL, a programming voltage Vpp of 8V is provided to the source line SL and the N-type well region NW, and a ground voltage (0V) is provided to the bit line BL, the erase line EL, and the P-type well region PW. At this time, the selection transistor T is turned on, and a programming current is generated in the programming path between the source line SL and the bit line BL, causing electrons to be injected into the floating gate from the channel region of the floating gate transistor M.

[0008] In addition, when inhibiting the programming of the memory cell 100, a turn-on voltage of 4V is provided to the word line WL, a programming voltage Vpp of 8V is provided to the source line SL and the N-type well region NW, a ground voltage (0V) is provided to the erase line EL and the P-type well region PW, and the bit line BL is floated (floating, F). At this time, no programming current is generated between the source line SL and the bit line BL, so no electrons are injected into the floating gate of the floating gate transistor M.

[0009] In addition, during a read cycle (READ), a read action can be performed to confirm the storage state of the memory cell 100. When performing a read action, a turn-on voltage of 0V is provided to the word line WL, a read voltage Vr of 3V is provided to the source line SL and the N-type well region NW, 0.4V is provided to the bit line BL, and a ground voltage (0V) is provided to the erase line EL and the P-type well region PW. At this time, the selection transistor T is turned on, and a cell current is generated in the read path between the source line SL and the bit line BL.

[0010] Furthermore, depending on whether the floating gate stores electrons, the memory cell 100 can generate cell currents of different magnitudes to determine the storage state of the memory cell 100. For example, when the memory cell 100 is in the first storage state, the floating gate does not store electrons and the cell current is very small, almost zero. When the memory cell 100 is in the second storage state, the floating gate stores electrons and the cell current is larger.

[0011] Therefore, during a read cycle (READ), a sense amplifier is connected to the bit line BL to receive the memory cell current. According to the magnitude of the memory cell current, the sense amplifier can determine whether the memory cell 100 is in the first storage state or the second storage state.

[0012] Furthermore, during an erase cycle (ERS), a ground voltage (0V) is provided to the source line SL, N-type well region NW, word line WL, bit line BL, and P-type well region PW, and an erase voltage of 14V is provided to the erase line EL. Therefore, the electrons stored on the floating gate will exit to the erase line EL via the erase path. That is to say, the electrons stored on the floating gate will pass through the capacitor C and exit to the erase line EL, leaving the memory cell 100.

[0013] The known memory cell 100 is used as a single level memory cell. That is to say, one memory cell stores 1 bit of data, and this data can be in the first storage state or the second storage state. Therefore, during a programming cycle, only by controlling whether hot carriers are injected into the floating gate or not can the memory cell 100 present two different storage states. In other words, during a programming cycle, only one write operation for programming or inhibiting the programming of the memory cell 100 is required to make the memory cell 100 present two different storage states.

[0014] In addition, during a single write operation, providing a higher programming voltage Vpp and a longer write time can ensure that a large number of hot carriers are injected into the floating gate, and make the memory cell 100 present the second storage state. Generally speaking, the known programming voltage Vpp is 8V, and the write time is about 50 μs. In addition, due to a large number of hot carriers being injected into the floating gate, during a read operation, the memory cell 100 can generate a memory cell current greater than 30 μA.

[0015] However, when the known memory cell 100 is used as a multi-level cell, one memory cell has to store at least 2 bits of data or more. Taking a multi-level cell that stores 2 bits as an example, the memory cell 100 can be in the first storage state, the second storage state, the third storage state, or the fourth storage state. Similarly, a multi-level cell that stores 3 bits will have eight (2^3) storage states, and a multi-level cell that stores 4 bits will have sixteen (2^4) storage states.

[0016] In addition, in known multi-level cells, the current difference between storage cells in different storage states is relatively large, and the difference between each storage state is about 10 μA. Taking a multi-level cell storing 3 bits as an example, the storage cell current in the eighth storage state is about 80 μA, the storage cell current in the seventh storage state is about 70 μA, the storage cell current in the sixth storage state is about 60 μA, and so on. In other words, a known multi-level cell array consumes a large amount of energy during operation.

[0017] In the field of artificial intelligence (AI), a large number of in-memory computing (IMC) applications need to be used. In IMC applications, multi-level cells are used to store weights. In order to meet the requirements of low-power operation, for multi-level cells used in IMC applications, the current difference between storage cells in different storage states should be as small as possible. Taking a multi-level cell storing 4 bits as an example, the storage cell currents from the first storage state to the sixteenth storage state are distributed between 0.1 μA and 1.6 μA. For example, the storage cell current in the sixteenth storage state is about 1.6 μA, the storage cell current in the fifteenth storage state is about 1.5 μA, the storage cell current in the fourteenth storage state is about 1.4 μA, and so on.

[0018] In IMC applications, in order to be able to control the multi-level cell to generate an accurate storage cell current, during the programming cycle, it is necessary to be able to accurately control the number of hot carriers injected into the floating gate so that the storage cell can present various different storage states. Obviously, using Figure 1B the biasing method will not achieve this effect. Summary of the Invention

[0019] The present invention relates to a programming and verification method for a multi-layer memory cell array. The multi-layer memory cell array includes: a plurality of memory cells in a first column, connected to a word line, a source line, an erase line, and a plurality of bit lines. Each memory cell is programmed to a target storage state during a programming cycle, and the target storage state is one of X storage states. The programming and verification method includes the following steps: (a1) determining the first column as a selected column and setting A equal to 1; (a2) in the selected column, except for the memory cells that have reached the target storage state and the defective memory cells, programming the other memory cells to a first A storage state; (a3) when A is not equal to X, incrementing A by 1 and returning to step (a2); and (a4) when A is equal to X, ending the programming cycle; wherein, in step (a2), multiple write operations and multiple verification operations are performed on the other memory cells in the selected column until the other memory cells reach the first A storage state.

[0020] For a better understanding of the above and other aspects of the present invention, the following preferred embodiments are specifically described below in conjunction with the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A AND Figure 1B is a schematic diagram of a known MTP memory cell composed of a floating gate transistor and a bias voltage.

[0022] Figure 2 The schematic diagram of the memory cell array of the present invention is shown.

[0023] Figure 3A AND Figure 3B is a schematic diagram of the distribution area line of each storage state of the memory cell.

[0024] Figure 4 is a schematic diagram of the bias voltage applied to the multi-layer memory cell of the present invention.

[0025] Figures 5A to 5C is a programming control method and example for applying the present invention to a multi-layer memory cell array.

[0026] Figure 6A AND Figure 6B is a programming bias voltage table and an operation flowchart of the programming stage.

[0027] Figure 7 is a schematic diagram of a complete programming bias voltage.

[0028] Figure 8A AND Figure 8B is a detailed operation flow of two verification operations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] According to an embodiment of the present invention, the present invention willFigure 1A The storage cells are used as multi-level cells, and an array of multi-level cells is formed. Since all the storage cells in the storage cell array are multi-level cells, each storage cell has at least four storage states, and storage cells with different storage states generate storage cell currents of different magnitudes.

[0030] As Figure 2 shown, it illustrates a schematic diagram of the storage cell array of the present invention. The storage cell array 200 includes m×n storage cells c11~cmn, where m and n are positive integers. Furthermore, each of the storage cells c11~cmn includes a selection transistor T 1,1 ~T m,n , a floating gate transistor M 1,1 ~M m,n and a capacitor C 1,1 ~C m,n . The structure of each of the storage cells c11~cmn is the same as that of the MTP storage cell 100 of Figure 1A , and its detailed structure will not be elaborated here. In addition, in each of the storage cells c11~cmn, the source terminals of the selection transistors T 1,1 ~T m,n are all connected to the source line SL, and the second terminals of the capacitors C 1,1 ~C m,n are all connected to the erase line EL.

[0031] In the storage cell array 200, the gate terminals of the selection transistors T 1,1 ~T 1,n in the first column of n storage cells c11~c1n are all connected to the word line WL1, and the drain terminals of the floating gate transistors M 1,1 ~M 1,n are connected to the corresponding bit lines BL1~BLn. The control terminals of the gate terminals of the selection transistors T 2,1 ~T 2,n in the second column of n storage cells c21~c2n are all connected to the word line WL2, and the drain terminals of the floating gate transistors M 2,1 ~M 2,n are connected to the corresponding bit lines BL1~BLn. Similarly, the storage cells in other columns also have similar connection relationships, which will not be elaborated here.

[0032] Basically, during the program cycle or read cycle of a non-volatile memory, only one of the m word lines WL1 to WLm in the memory cell array 200 will be activated, and the other word lines will not be activated. For example, during the program cycle, the word line WL1 is activated, making the first column the selected column. At this time, by controlling the memory cells c11 to c1n in the selected column to perform multiple write operations, the memory cells c11 to c1n can be made to exhibit various storage states.

[0033] Of course, in order to prevent the memory cells c11 to cmn from interfering with each other during the program cycle and read cycle, a shielding line (SH) can be added to the memory cell array 200. Among them, the shielding line SH is not connected to the memory cells c11 to cmn in the memory cell array 200, and its function is to prevent the coupling effect caused by different numbers of hot carriers between the memory cells. Generally, during the read cycle and program cycle, making the shielding line SH and the erase line EL receive the same voltage can prevent the coupling effect between the memory cells.

[0034] In a multi-level memory cell, according to the number of hot carriers injected into the floating gate from less to more, the memory cell can be in the first storage state to the Xth storage state, and X is greater than or equal to 4. That is to say, for the memory cell in the first storage state, the floating gate stores the fewest hot carriers; for the memory cell in the Xth storage state, the floating gate stores the most hot carriers.

[0035] Please refer to Figure 3A and Figure 3B , which shows a schematic diagram of the distribution area lines of the respective storage states of the memory cell. As Figure 3A shown, according to the number of hot carriers injected into the floating gate in the memory cell from less to more, the multi-level memory cell storing four-bit data can be in one of the first storage state (1st) to the sixteenth storage state (16th), that is, X = 16. Furthermore, memory cells in different storage states will generate different magnitudes of memory cell current during the read operation. For example, the memory cell current of the first storage state is 0.1 μA, the memory cell current of the second storage state is 0.2 μA, the memory cell current of the third storage state is 0.3 μA, and so on. The memory cell current of the sixteenth storage state is 1.6 μA.

[0036] Similarly, when the multi-level memory cell can store three-bit data, X = 8, that is, the memory cell can be in one of the first to eighth storage states. When the multi-level memory cell can store two-bit data, then X = 4, that is, the memory cell can be in one of the first to fourth storage states.

[0037] For example, as Figure 3B shown, in a multi-level memory cell storing two-bit data, the memory cell current in the first storage state is 0.2 μA, the memory cell current in the second storage state is 0.6 μA, the memory cell current in the third storage state is 1.0 μA, and the memory cell current in the fourth storage state is 1.4 μA. Of course, the memory cell current values corresponding to the above storage states are only an example. In fact, the memory cell current corresponding to each storage state can have other current values according to the characteristics of the memory cell.

[0038] In order to enable the memory cell to generate an accurate memory cell current, it is necessary to accurately control the number of hot carriers injected into the floating gate. Therefore, the present invention proposes a programming and verification method applied to a multi-level memory cell array. In the programming cycle, multiple write operations are used to gradually accumulate the number of hot carriers in the floating gate, and a verify action is used to determine whether the memory cell has reached a predetermined storage state. Furthermore, in order to prevent too many hot carriers from being injected into the floating gate during the write operation, the write time of each write operation is very short, for example, 100 ns.

[0039] Please refer to Figure 4 , which shows a bias voltage schematic diagram of the present invention applied to a multi-level memory cell. Among them, during the program cycle, a write operation can be performed on the memory cell for programming (abbreviation: PGM) or inhibiting programming (abbreviation: PGM inhibit) of the memory cell.

[0040] When programming the memory cell, an enable voltage Von1 is provided to the word line WL, a programming voltage Vpp is provided to the source line SL and the N-type well region NW, a ground voltage (0 V) is provided to the bit line BL and the P-type well region PW, and an erase voltage V EL is provided to the erase line EL and the shield line SH. At this time, the select transistor T is turned on, and a programming current is generated in the programming path between the source line SL and the bit line BL, so that electrons are injected into the floating gate from the channel region of the floating gate transistor.

[0041] In addition, when suppressing the programming of the memory cell, a turn-on voltage Von1 is provided to the word line WL, a programming voltage Vpp is provided to the source line SL and the N-type well region NW, a ground voltage (0V) is provided to the P-type well region PW, an erase voltage V EL is provided to the erase line EL and the shield line SH, and the bit line BL is floated (floating, F). At this time, no programming current is generated between the source line SL and the bit line BL, so no electrons are injected into the floating gate of the floating gate transistor.

[0042] According to an embodiment of the present invention, since the memory cell performs multiple write operations during the programming cycle, the programming voltage Vpp and the erase voltage V EL vary with the number of write operations. For example, the programming voltage Vpp varies between 6.35V and 6.95V, and the erase voltage V EL varies between 1.5V and 3.25V. In addition, the turn-on voltage Von1 can be 4.5V.

[0043] In addition, during the read cycle, a read operation can be performed to read (READ) the memory cell or inhibit the read (READ inhibit) of the memory cell. Among them, when reading the memory cell, the memory cell can be controlled to generate a memory cell current. When inhibiting the reading of the memory cell, the memory cell can be controlled not to generate a memory cell current. In other words, if it is necessary to determine the storage state of the selected memory cell, that is, during the read operation, the selected memory cell is read so that the selected memory cell generates a memory cell current. On the contrary, if the storage state of the selected memory cell is already known or it is not necessary to determine the storage state of the selected memory cell, then during the read operation, the selected memory cell is read to inhibit the selected memory cell so that the selected memory cell does not generate a memory cell current.

[0044] When reading the memory cell, a turn-on voltage Von2 is provided to the word line WL, a read voltage of 2.1V is provided to the source line SL and the N-type well region NW, a ground voltage (0V) is provided to the erase line EL, the shield line SH and the P-type well region PW, and a bias voltage of 1.2V is provided to the bit line BL. At this time, the selection transistor is turned on, and the memory cell outputs a memory cell current through the bit line BL. Basically, according to the number of electrons in the floating gate, the memory cell can generate different magnitudes of memory cell currents. And a sense amplifier (not shown) connected to the bit line BL can further determine the storage state of the memory cell according to the magnitude of the memory cell current.

[0045] When suppressing the reading of a memory cell, a turn-on voltage Von2 is provided to the word line WL, a reading voltage of 2.1 V is provided to the source line SL and the N-type well region NW, a ground voltage (0 V) is provided to the erase line EL, the shield line SH, and the P-type well region PW, and the bit line BL is floated (floating, F). At this time, the memory cell cannot generate a cell current. For example, the turn-on voltage Von2 is the ground voltage (0 V).

[0046] Furthermore, during an erase cycle (ERS), a ground voltage (0 V) is provided to the word line WL, the source line SL, the N-type well region NW, the bit line BL, the shield line SH, and the P-type well region PW, and an erase voltage of 14 V is provided to the erase line EL. At this time, the electrons stored on the floating gate will pass through the capacitor C and exit to the erase line EL.

[0047] According to an embodiment of the present invention, during a program cycle, multiple write actions and verify actions are performed on the memory cell. The time of each write action is very short, for example, 100 ns, so that a small amount of hot carriers are injected into the floating gate of the memory cell. Furthermore, during the verify action, a read action is performed on the memory cell and it is determined whether the cell current generated by the memory cell reaches a predetermined storage state. If the memory cell has not reached the predetermined storage state, the write action is continued to inject a small amount of hot carriers into the floating gate of the memory cell again.

[0048] Hereinafter, a multi-layer memory cell array composed of memory cells storing two-bit data will be taken as an example for illustration. Of course, the present invention is not limited thereto, and those skilled in the art can also apply the present invention to memory cells storing more bits.

[0049] Please refer to Figures 5A to 5C , which shows a programming control method and an example thereof for applying the present invention to a multi-layer memory cell array. According to an embodiment of the present invention, during a program cycle, n memory cells in a selected row of the memory cell array 200 are gradually programmed to a target storage state.

[0050] According to an embodiment of the present invention, each program cycle includes multiple programming stages. As Figure 5AAs shown, at the start of the programming cycle, a selected column is determined from the memory cell array 200 (step S504), and A is set to 1 (step S506), which is used to represent the stage of programming to the first storage state.

[0051] Next, in the selected column, except for the memory cells that have reached the target storage state and the bad cells, the other memory cells are programmed to the A-th storage state (step S508). In step S508, the good cells that have not reached the A-th storage state will perform multiple write operations and verification operations until the storage states of these good cells reach the A-th storage state.

[0052] After that, it is judged whether A is equal to X (step S510). When A is not equal to X, A is incremented by 1 (step S512), and the process returns to step S508 to start another programming stage. On the contrary, when A is equal to X, it means that all the memory cells in the selected column have reached the target storage state, and the programming cycle ends. Here, both X and A are positive integers.

[0053] The following uses Figure 5B and Figure 5C to illustrate the above programming cycle. As Figure 5B shown, the i-th column in the memory cell array is the selected column and includes six memory cells ci1 to ci6. Each of the memory cells ci1 to ci6 will be programmed to the target storage state during the programming cycle, which are the third storage state (3th), the first storage state (1st), the second storage state (2nd), the fourth storage state (4th), the second storage state (2nd), and the third storage state (3rd) respectively. Furthermore, it is assumed that the six memory cells ci1 to ci6 in the i-th column are all good cells.

[0054] As Figure 5C shown, when A is equal to 1, it represents the stage of programming to the first storage state. After multiple write operations and verification operations, the memory cells ci1 to ci6 will be programmed to the first storage state 1st. After this stage is completed, the memory cell ci2 has reached the target storage state.

[0055] When A is equal to 2, it represents the stage of programming to the second storage state. At this time, in the selected column, except for the memory cell ci2 that has reached the target storage state, the other memory cells ci1, ci3 to ci6 will be programmed to the second storage state 2nd after multiple write operations and verification operations. After this stage is completed, the memory cells ci3 and ci5 have reached the target storage state.

[0056] When A is equal to 3, it represents the stage of programming to the third storage state. At this time, in the selected column, except for the storage cells ci2, ci3, and ci5 that have reached the target storage state, the other storage cells ci1, ci4, and ci6 will be programmed to the third storage state 3rd after multiple write operations and verification operations. After this stage is completed, the storage cells ci1 and ci6 have reached the target storage state.

[0057] When A is equal to 4, it represents the stage of programming to the fourth storage state. At this time, in the selected column, except for the storage cells ci1-ci3 and ci5-ci6 that have reached the target storage state, the other storage cell ci4 will be programmed to the fourth storage state 4th after multiple write operations and verification operations, and the storage cell ci4 will reach the target storage state. After this stage is completed, all the storage cells ci1-ci6 in the selected column have reached the target storage state, and the program cycle of the selected column ends.

[0058] After that, a new program cycle can be started for another selected column of the memory cell array 200.

[0059] From the above description, it can be seen that for a multi-layer memory cell array storing two-bit data, during the program cycle, four (X = 4) program stages are required to confirm that all the memory cells in the selected column are programmed to the target storage state. Similarly, for a multi-layer memory cell array storing three-bit data, eight (X = 8) program stages are required during the program cycle to confirm that all the memory cells in the selected column are programmed to the target storage state. For a multi-layer memory cell array storing four-bit data, sixteen (X = 16) program stages are required during the program cycle to confirm that all the memory cells in the selected column are programmed to the target storage state.

[0060] According to an embodiment of the present invention, each program stage requires multiple write operations to program the memory cell to a predetermined storage state. Furthermore, due to the characteristic differences of each memory cell, verification operations are required during the program stage to determine whether the memory cell has reached the predetermined storage state. Among them, the predetermined storage state can be one of the first storage state to the fourth storage state. The following takes the stage of programming to the second storage state as an example to illustrate the detailed steps of the program stage.

[0061] Please refer to Figure 6A and Figure 6B , which shows the programming bias table and the operation flowchart of the program stage. As Figure 6AAs shown, it is a program bias table used in the stage of programming to the second storage state, which includes a plurality of program bias sub-tables Q 2 [1] to Q 2 [8], and can be loaded in sequence from program bias sub-table Q 2 [1] to program bias sub-table Q 2 [8].

[0062] Furthermore, each program bias sub-table Q 2 [1] to Q 2 [8] includes three fields for indicating the program voltage Vpp, erase voltage V EL required during the programming stage, and the upper limit of the number of write operations. For example, program bias sub-table Q 2 [1] indicates a program voltage Vpp of 6.45V, an erase voltage V EL of 1.5V, and an upper limit of 24 write operations.

[0063] As Figure 6B shown, at the start of a programming stage, the program bias table is first loaded (step S602). Then, steps S604 and S606 are verification operations.

[0064] In the verification operation, a read operation is first performed to inhibit reading of memory cells that have reached the A storage state, and read memory cells that have not reached the A storage state (step S604). Then, it is determined whether all the read memory cells have reached the A storage state (step S606). When all the read memory cells in the selected column have reached the A storage state, the programming stage ends.

[0065] Taking the A storage state as the second storage state as an example for illustration. In the verification operation, a read operation is first performed. At this time, except for the memory cells that have reached the target storage state, the memory cells in the selected column that have reached the second storage state will be inhibited from being read, while the memory cells in the selected column that have not reached the second storage state will be read. Then, according to the memory cell current, it is confirmed whether these read memory cells have reached the second storage state.

[0066] For example, a memory cell in the second storage state may generate a memory cell current of 0.2 μA. Therefore, during the verification operation, if the memory cell currents of some memory cells in the selected column are greater than or equal to 0.2 μA, it is confirmed that these memory cells have reached the second storage state. Conversely, if the memory cell currents of another part of the memory cells in the selected column are less than 0.2 μA, it is confirmed that the other part of the memory cells have not reached the second storage state. At this time, these memory cells that have not reached the second storage state need to perform a write operation again.

[0067] When there is still another part of the memory cells read in the selected column that have not reached the A storage state, it is determined whether the number of write operations has reached the upper limit (step S608). That is, it is determined whether the number of write operations performed has reached the number of write operations specified in the programming bias sub-table.

[0068] When the number of write operations has not reached the upper limit, at least one write operation is performed to inhibit the programming of the memory cells that have reached the A storage state and program the memory cells that have not reached the A storage state (step S612). In step S612, the memory cells in the selected column that have reached the second storage state will be inhibited from programming, and of course, the memory cells in the selected column that have reached the target storage state will also be inhibited from programming. Therefore, only the memory cells in the selected column that have not reached the second storage state are programmed. That is, according to the programming voltage Vpp and the erase voltage V indicated in the programming bias sub-table EL to perform a write operation to inject hot carriers into the memory cells that have not reached the second storage state again. Then, after at least one write operation is completed, step S604 is entered again to perform a verification operation.

[0069] In addition, when the number of write operations reaches the upper limit, it means that there will still be memory cells that cannot reach the second storage state when using the content of the old programming bias sub-table to perform the write operation. Therefore, after confirming that there is still an unloaded programming bias sub-table (step S609), the next programming bias sub-table is loaded (step S610), and step S612 is continued. At this time, according to the programming voltage Vpp and the erase voltage V indicated in the new programming bias sub-table EL to perform a write operation to inject hot carriers into the memory cells that have not reached the second storage state again. Then, after at least one write operation is completed, step S604 is entered again to perform a verification operation.

[0070] From the above description, it can be seen that during the stage of programming to the second storage state, the programming bias sub-table Q 2 [1] will be loaded first, and write operations and verification operations will be performed according to its content. If after 24 write operations, there are still memory cells in the selected column that have not reached the second storage state, then the programming bias sub-table Q 2[2] will be loaded. Similarly, if after another 24 write operations, there are still memory cells in the selected column that have not reached the second storage state, the programming bias sub-table Q 2 [3] will be loaded. And so on, until all the memory cells in the selected column except those that have reached the target storage state reach the second storage state.

[0071] Of course, as shown in step S609, when all the programming bias sub-tables Q 2 [1] to Q 2 [8] have been loaded and there are still memory cells that have not reached the second storage state, these memory cells may be bad cells. Therefore, the remaining memory cells that have not reached the A storage state (have not reached the second storage state) are set to reach the target storage state (step S613), and the stage of programming to the second storage state is terminated (abort).

[0072] From the above description, it can be seen that in the stage of programming to the second storage state, at most 8 sub-programming sub-tables Q 2 [1] to Q 2 [8] are loaded sequentially, and in the stage of programming to the second storage state, at most 192 (8 × 24) write operations will be performed. Of course, the present invention is not limited to Figure 6A the values of the programming voltage Vpp, the erasing voltage V EL and the number of write operations in it. Those skilled in the art can modify these values according to actual needs.

[0073] In addition, Figure 6B it can also be appropriately modified to the case of using only a single programming bias sub-table. For example, when there is only one programming bias sub-table, the steps S602 and step 610 of loading the programming bias sub-table are not required, and steps S608, step S609, and step S613 are deleted. That is, when all the memory cells read have not reached the A storage state, step S612 is performed.

[0074] Please refer to Figure 7 , which shows a complete programming bias schematic diagram. And Figure 6B the flowchart of Figure 7 matched with the programming bias table of

[0075] can complete the operation process of a programming cycle. Figure 7 As shown in 1 [1] to Q 1 [8] of the programming bias table for programming to the first storage state includes multiple programming bias sub-tables Q[8]. The programming bias table used in the stage of programming to the second storage state includes a plurality of programming bias sub-tables Q 2 [1] to Q 2 [8]. The programming bias table used in the stage of programming to the third storage state includes a plurality of programming bias sub-tables Q 3 [1] to Q 3 [8]. The programming bias table used in the stage of programming to the fourth storage state includes a plurality of programming bias sub-tables Q 4 [1] to Q 4 [8]. In other words, according to Figure 7 the programming bias table and Figure 6B the operation flow, as well as the cell currents of the memory cells in the four storage states, the four programming stages of the programming cycle can be performed, and all the memory cells in the selected column can be programmed to the target storage state.

[0076] Similarly, for a multi-level memory cell array storing three-bit data, there are eight programming stages in the programming cycle, and a programming bias table for programming to eight storage states is required. For a multi-level memory cell array storing four-bit data, there are sixteen programming stages in the programming cycle, and a programming bias table for programming to sixteen storage states is required.

[0077] Please refer to Figure 8A , which shows the detailed operation flow of the verification operation. First, it is confirmed that the M memory cells have not reached the A-th storage state (step S802). That is, except for the cells that have reached the target storage state, it is confirmed that the number of memory cells in the selected column that have not been programmed to the A-th storage state is M.

[0078] Next, set B equal to 1 and the count value Count = 0 (step S804), where both B and the count value Count are integers.

[0079] Furthermore, it is determined whether the cell current of the B-th memory cell is greater than or equal to a predetermined cell current (step S806). Here, the predetermined cell current is the cell current of the A-th storage state. Therefore, in step S806, the B-th memory cell is read to generate a cell current for the B-th memory cell, and it is determined whether the cell current of the B-th memory cell is greater than or equal to the cell current of the A-th storage state.

[0080] When the cell current of the B-th memory cell is not greater than the cell current of the A-th storage state, it means that the B-th memory cell has not reached the A-th storage state. Then, step S810 is performed.

[0081] Conversely, when the memory cell current of the B-th memory cell is greater than the memory cell current of the A-th storage state, it represents that the B-th memory cell has reached the A-th storage state, and the count value Count is incremented by 1 (step S808). After that, step S810 is performed. In other words, this B-th memory cell will be inhibited from being read and inhibited from being programmed in the subsequent processes of the programming phase.

[0082] Step S810 determines whether B is equal to M. If B is not equal to M, B is incremented by 1 (step 812), and then it returns to step S806. Furthermore, if B is equal to M, it is then determined whether the count value Count is equal to M (step S814).

[0083] Basically, the above step S810 determines whether the M memory cells have been read and determined. If not, it continues to determine other memory cells. Furthermore, step S814 is the same as step S606, which is used to determine that all the M memory cells read have reached the A-th storage state.

[0084] Please refer to Figure 8B which shows the detailed operation process of another verification operation. Compared with Figure 8A its difference lies in step S820, and the rest of the steps are the same. In step S820, among the N memory cells that have not reached the A-th storage state, M memory cells are confirmed to have the target storage state as the A-th storage state, where M and N are integers. That is to say, Figure 8B in the verification operation of Figure 8A only the memory cells in the selected column that have not reached the A-th storage state and have the target storage state as the A-th storage state are judged. Compared with

[0085] the verification operation of

[0086] fewer memory cells can be verified, and the verification time can be saved. 2 [1] to Q 2 [8] as an example, after loading the programming bias sub-table Q 2 [1], when performing step S612, twelve write operations are performed and then one verification operation is performed. After loading the programming bias sub-table Q 2 [2], when performing step S612, four write operations are performed and then one verification operation is performed. After loading the programming bias sub-table Q 2 [3] or Q 2[4], after that, when performing step S612, a secondary write operation is executed followed by a verification operation. After loading the programming bias sub-table Q 2 [5], Q 2 [6], Q 2 [7] or Q 2 [8], when performing step S612, a single write operation is executed followed by a verification operation.

[0087] From the above description, the present invention provides a programming and verification method applied to a multi-level memory cell array. The programming cycle of the present invention includes multiple programming stages, and a write operation and a verification operation are continuously performed in each programming stage. Therefore, after the programming cycle ends, it can be confirmed that all memory cells on the selected column reach the target storage state.

[0088] In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.

[0089] [Symbol Description]

[0090] 100: Memory cell

[0091] 200: Memory cell array

[0092] S504~S512, S602~S612, S802~S820: Process steps

Claims

1. A programming and verification method for a multi-level memory cell array, the multi-level memory cell array comprises: A plurality of memory cells in a first column, connected to a first word line, a source line, an erase line, and a plurality of bit lines. A shield line is located between the plurality of memory cells in the first column, and the shield line is not connected to the plurality of memory cells in the first column. Each of the memory cells is programmed to a target storage state during a programming cycle, and the target storage state is one of X storage states. The programming and verification method includes the following steps: (a1) Activate the first word line to determine that the first column is a selected column, and set A equal to 1 to represent the stage of programming to a first storage state; (a2) In the selected column, except for the memory cells that have reached the target storage state and the bad memory cells, program the other memory cells to a first A storage state; (a3) When A is not equal to X, increment A to represent the stage of programming to the first A storage state, and return to step (a2); and (a4) When A is equal to X, end the programming cycle; wherein, A and X are integers; wherein, in step (a2), perform multiple write operations and multiple verification operations on the other memory cells in the selected column until the other memory cells reach the first A storage state; wherein, during a read cycle and the programming cycle, the shield line and the erase line receive the same voltage to prevent a coupling effect between the plurality of memory cells in the first column.

2. The programming and verification method according to claim 1, wherein step (a2) further includes the following steps: (b1) Perform a read operation on the other memory cells, suppressing the reading of the memory cells that have reached the first A storage state, and reading the memory cells that have not reached the first A storage state; (b2) When all the read memory cells have reached the first A storage state, return to step (a3); and (b3) When there are still memory cells among all the read memory cells that have not reached the first A storage state, program the memory cells that have not reached the first A storage state.

3. The programming and verification method according to claim 1, wherein step (a2) further includes the following steps: (c1) Load a programming bias sub-table; (c2) Perform a read operation on the other memory cells, suppressing the reading of the memory cells that have reached the first A storage state, and reading the memory cells that have not reached the first A storage state; (c3) When all the read memory cells have reached the first A storage state, return to step (a3); (c4) When there are still memory cells among all the read memory cells that have not reached the first A storage state, determine whether the number of write operations has reached an upper limit; (c5) When the number of write operations has not reached the upper limit, return to step (c8); (c6) When the number of write operations has reached the upper limit and it is confirmed that there is still an unloaded programming bias sub-table, load the next programming bias sub-table and return to step (c8); (c7) When the number of write operations reaches the upper limit and it is confirmed that there is no unloaded programming bias sub-table, set the memory cells that have not reached the A-th storage state to reach the target storage state, and return to step (a3); (c8) Perform at least one of the write operations to inhibit programming of the memory cells that have reached the A-th storage state, and program the memory cells that have not reached the A-th storage state, and return to step (c2).

4. The programming and verification method according to claim 3, wherein the programming bias sub-table and the next programming bias sub-table indicate a programming voltage, an erase voltage, and an upper limit of the number of write operations during the at least one write operation.

5. The programming and verification method according to claim 3, wherein step (c2) further comprises the following steps: (d1) In the other memory cells, confirm that M memory cells have not reached the A-th storage state; (d2) Set B equal to 1, and set a count value equal to 0, where M, B, and the count value are integers; (d3) When the storage cell current of a B-th storage cell among the M memory cells is greater than or equal to a predetermined storage cell current, confirm that the B-th storage cell has reached the A-th storage state, and increment the count value by 1; (d4) When B is not equal to M, increment B and return to step (d3); (d5) When the count value is equal to M, return to step (a3); and (d6) When the count value is not equal to M, return to step (c4).

6. The programming and verification method according to claim 3, wherein step (c2) further comprises the following steps: (d1) In the other memory cells, confirm that N memory cells have not reached the A-th storage state, and among them, the target storage state of M memory cells is the A-th storage state; (d2) Set B equal to 1, and set a count value equal to 0, where M, N, B, and the count value are integers; (d3) When the storage cell current of a B-th storage cell among the M memory cells is greater than or equal to a predetermined storage cell current, confirm that the B-th storage cell has reached the A-th storage state, and increment the count value by 1; (d4) When B is not equal to M, increment B and return to step (d3); (d5) When the count value is equal to M, return to step (a3); and (d6) When the count value is not equal to M, return to step (c4).

7. The programming and verification method according to claim 1, wherein the memory cell array, including m×n memory cells, is connected to m word lines, the source line, the erase line, and n bit lines, and each of the memory cells can be one of X storage states, and X is greater than or equal to 4.

8. A programming and verification method for a multi-level memory cell array, the multi-level memory cell array comprises: a first column of a plurality of memory cells, connected to a first word line, a source line, an erase line, and a plurality of bit lines, each of the memory cells being programmed to a target storage state during a programming cycle, the target storage state being one of X storage states, the programming and verification method comprising the following steps: (a1) Determine that the first column is a selected column and set A equal to 1; (a2) In the selected column, program other memory cells, except for the memory cells that have reached the target storage state and the defective memory cells, to a first A storage state; (a3) When A is not equal to X, increment A by 1 and return to step (a2); and (a4) When A is equal to X, end the programming cycle; wherein A and X are integers; wherein step (a2) further includes the following steps: (c1) Load a programming bias sub-table; (c2) Perform a read operation on the other memory cells, suppressing the reading of the memory cells that have reached the first A storage state and reading the memory cells that have not reached the first A storage state; (c3) When all the memory cells being read have reached the first A storage state, return to step (a3); (c4) When there are still memory cells among all the memory cells being read that have not reached the first A storage state, determine whether the number of write operations has reached an upper limit; (c5) When the number of write operations has not reached the upper limit, return to step (c8); (c6) When the number of write operations has reached the upper limit and it is confirmed that there is still an unloaded programming bias sub-table, load the next programming bias sub-table and return to step (c8); (c7) When the number of write operations has reached the upper limit and it is confirmed that there is no unloaded programming bias sub-table, set the memory cells that have not reached the first A storage state to reach the target storage state and return to step (a3); (c8) Perform at least one write operation, suppressing the programming of the memory cells that have reached the first A storage state and programming the memory cells that have not reached the first A storage state, and return to step (c2).

9. The programming and verification method according to claim 8, wherein the programming bias sub-table and the next programming bias sub-table indicate a programming voltage, an erase voltage, and an upper limit of the number of write operations when indicating the at least one write operation.

10. The programming and verification method according to claim 8, wherein step (c2) further includes the following steps: (d1) Among the other memory cells, confirm that M memory cells have not reached the first A storage state; (d2) Set B equal to 1 and set a count value equal to 0, where M, B, and the count value are integers; (d3) When the storage cell current of a B-th storage cell among the M memory cells is greater than or equal to a predetermined storage cell current, confirm that the B-th storage cell has reached the first A storage state and increment the count value by 1; (d4) When B is not equal to M, increment B by 1 and return to step (d3); (d5) When the count value is equal to M, return to step (a3); and (d6) When the count value is not equal to M, return to step (c4).

11. The programming and verification method according to claim 8, wherein step (c2) further includes the following steps: (d1) Among the other memory cells, confirm that N memory cells have not reached the first A storage state, and the target storage state of M of them is the first A storage state; (d2) Set B equal to 1 and set a count value equal to 0, where M, N, B, and the count value are integers; (d3) When the cell current of one of the B-th cells among the M memory cells is greater than or equal to a predetermined cell current, it is confirmed that the B-th cell reaches the A-th storage state, and the count value is incremented by 1; (d4) When B is not equal to M, increment B by 1 and return to step (d3); (d5) When the count value is equal to M, return to step (a3); and (d6) When the count value is not equal to M, return to step (c4).

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