Driver circuit for driving a voltage-controlled electro-optical modulator and system thereof

Abstract

The invention relates to a driver circuit for driving a voltage-controlled electro-optical modulator by providing an output voltage to the electro-optical modulator in dependence on an input voltage. The driver circuit comprises a supply input for receiving a direct supply voltage having a positive supply voltage level and an input for receiving the input voltage, wherein the input voltage varies between a low input level and a high input level. The driver circuit further comprises a level shifter circuit comprising two capacitors and being electrically connected to the input, and a voltage distribution circuit electrically connected between the level shifter circuit and an output of the driver circuit for providing the output voltage. The level shifter circuit is configured to generate, based on the input voltage and using a first of the two capacitors, a first voltage varying between the positive supply voltage level and a positive first level greater than the positive supply voltage level.

Description

TECHNICAL FIELD

[0001] The present invention relates to a driver circuit for driving a voltage-controlled electro-optical modulator and a system comprising this driver circuit and a voltage-controlled electro-optical modulator. BACKGROUND

[0002] A voltage-controlled electro-optical modulator is an optical intensity modulator. An example of a voltage-controlled electro-optical modulator is a ring modulator (RM), in particular a silicon RM. Ring modulators (RMs) are used in optical communications to modulate a continuous laser and encode binary information to be transmitted optically in a non-return-to-zero format (NRZ, also known as PAM2). SUMMARY

[0003] Embodiments of the present invention are also based on the following considerations made by the inventors:

[0004] Without going into details of the RM physics, a RM is an optical resonator realized with a PN junction. That is, a RM is an example of an electro-optical modulator that behaves electrically like a diode. The resonant wavelength of the optical resonator (or RM), i.e. the "transparency" for a specific wavelength of light, depends on the voltage applied to the PN junction. For a RM operating in reverse bias, the anode-cathode voltage (VAK), i.e. the voltage applied to the PN junction, should be lower than the direct forward bias threshold (about 0.6 V for a silicon RM). The "direct forward bias threshold" can also be referred to as "positive forward voltage level for forward bias". Due to the reverse bias in the RM and the lack of photon-to-electron conversion, no current flows between the anode and the cathode of the PN junction for VAK<0.6 V. To modulate light, the RM operates in reverse bias. The RM and the circuitry used to control the VAK of the RM according to the data to be transmitted form a transmitter. The circuitry can also be referred to as a driver circuit for driving the RM, which is an example of a voltage-controlled electro-optical modulator. The data to be transmitted optically is input to the driver circuit as an electrical digital signal in the form of an input voltage.

[0005] By simplification, a RM (and in general any voltage-controlled electro-optical modulator) can be considered as a black box that works as follows:

[0006] When a logical high (logical one) "1" of the bit stream of the digital input signal (data signal) is to be transmitted optically, the RM is configured to let as much light as possible pass through. In this case, the optical output power corresponds to the optical output power PI. The insertion loss (IL) is the optical attenuation in this case.

[0007] When the logic low (logic zero) "0" of the bit stream of the digital input signal is to be optically transmitted, the RM is configured to block as much light as possible. In this case, the optical output power corresponds to the optical output power P0. As a result, the optical output power P0 is less than the optical output power P1 (P0 < P1). The extinction ratio (ER) is the ratio between the light transmitted in the case of optical transmission of logic high "1" and optical transmission of logic low "0" (ER = P1 / P0).

[0008] Alternatively, the logic high can be optically transmitted using the optical output power P0, while the logic low can be optically transmitted using the optical output power P1.

[0009] For a given laser power at the input of the RM, the maximum optical modulation amplitude (OMA = P1-P0) given by the difference between the optical power of the logic high "1" and the logic low "0" is achieved by minimizing IL and maximizing ER. The OMA is a key parameter of the optical transmitter, as it measures the amplitude of the transmitter signal (optical signal) that carries the binary information. The transmitter penalty TP is equal to the input laser power divided by twice the optical output OMA. The TP of a theoretically perfect transmitter, which can be completely transparent and completely opaque (IL = 1 or 0 dB, ER = infinite or infinite dB), is 3 dB, and its OMA is equal to its input laser power. Any real implementation will have a higher penalty TP. In general: The terms "greater than" and "higher than" can be used as synonyms. The terms "less than" and "lower than" can be used as synonyms.

[0010] As the RM resonance (and thus the RM transparency to the suitable wavelength of laser light) is a monotonic function of the voltage applied to the RM, a larger difference in the applied voltage between the voltage applied for optical transmission of the optical output power P0 corresponding to the logic low "0" and the voltage applied for optical transmission of the optical output power P1 corresponding to the logic high "1" results in a higher optical difference between the optical output powers P1 and P0 and thus in a higher OMA. This is exemplarily shown in Figure 6 for three different values of VAK, VAK1, VAK2, and VAK3. In order for the RM to work under reverse bias, VAK can only be negative, or if positive, be limited below the threshold of forward bias (e.g. 0.6 volts for a silicon RM) to avoid forward conduction.

[0011] For a VAK voltage swing of ~ 1 volt, state-of-the-art silicon RMs achieve IL ~ 3 dB and ER ~ 3 dB. This corresponds to a TP of ~ 9 dB. Increasing the applied voltage swing of VAK, i.e. increasing the difference between the voltage applied for optical transmission of the optical output power P0 and the voltage applied for optical transmission of the optical output power P1, results in an increased ER, thus a lower TP for the same laser power and a higher OMA. This is shown in Figure 6 .

[0012] On the left side of Figure 6 , when a voltage value VAK1 is applied, laser light at the laser wavelength is modulated such that an optical output power P0 is transmitted for optical transmission, e.g. a logic low "0". When a voltage value VAK2 (VAK2 < VAK1) smaller than the voltage value VAK1 is applied, laser light at the laser wavelength is modulated such that an optical output power P1 is transmitted for optical transmission, e.g. a logic high "1". On the right side of Figure 6 , when a voltage value VAK1 is applied, laser light at the laser wavelength is modulated such that an optical output power P0 is transmitted for optical transmission, e.g. a logic low "0". When a voltage value VAK3 (VAK3 < VAK2) smaller than the voltage value VAK2 is applied, laser light at the laser wavelength is modulated such that an optical output power P1 is transmitted for optical transmission, e.g. a logic high "1". The terms "voltage level" and "voltage value" can be used as synonyms.

[0013] As can be determined on the basis of the two graphs shown in Figure 6 , when the VAK voltage swing between the voltage value for transmission P0 (both graphs VAK1) and the voltage value for transmission P1 (left graph: VAK2, right graph: VAK3) increases, the gap between the two optical output powers P0 and P1 increases. That is, the gap between the two optical output powers P0 and P1 caused by the VAK voltage swing between the two values / levels VAK1 and VAK3 shown on the right side is larger than the gap between the two optical output powers P0 and P1 caused by the VAK voltage swing between the two values VAK1 and VAK2. The increase of the VAK voltage swing thus results in a larger ER and thus for the same laser power in a smaller TP and a larger OMA.

[0014] The VAK voltage swing across the RM is typically limited by the power supply of the driver circuit used to drive the RM, which mainly depends on the chosen technology. Typically this voltage swing corresponds to twice the power supply voltage VDD of the driver circuit (2 · VDD). For advanced CMOS nodes, the power supply voltage VDD is typically below 1 volt (e.g. 0.8 volt), which leads to a maximum theoretical VAK voltage swing of e.g. 2 · VDD = 1.6 V (from -VDD to +VDD) when the two terminals are switched in opposite directions. However, given that VAK should be below the forward bias threshold (e.g. about 0.6 volt for silicon), the maximum swing that can be achieved is only VDD + 0.6 volt (e.g. VDD + 0.6 volt = 1.4 volt).

[0015] In view of the above-mentioned drawbacks, it is an object of embodiments of the present invention to increase the voltage swing across the RM beyond the limit imposed by the supply voltage VDD and thus increase the ER without the need to provide additional power supplies, additional control voltages and additional clocks of additional supply voltages other than the supply voltage VDD. It is an object to provide a driver circuit for driving a voltage-controlled electro-optical modulator, such as a RM, by providing an output voltage to the modulator as a function of an input voltage, wherein the driver circuit is configured to increase the voltage swing of the output voltage compared to the voltage swing of the input voltage. In particular, it is an object to provide such a driver circuit configured to increase the voltage swing of the output voltage beyond the limit imposed by the supply voltage VDD without the need to provide additional power supplies, additional control voltages and additional clocks of additional supply voltages other than the supply voltage VDD.

[0016] A first aspect of the present invention provides a driver circuit for driving a voltage-controlled electro-optical modulator by providing an output voltage to the electro-optical modulator as a function of an input voltage. The driver circuit comprises a supply input for receiving a direct supply voltage having a positive supply voltage level and an input for receiving the input voltage, wherein the input voltage varies between a low input level and a high input level. The driver circuit further comprises a level shifter circuit comprising two capacitors and being electrically connected to the input, and a voltage distribution circuit electrically connected between the level shifter circuit and an output of the driver circuit for providing the output voltage. The level shifter circuit is configured to generate, based on the input voltage and using a first of the two capacitors, a first voltage varying between the positive supply voltage level and a positive first level greater than the positive supply voltage level. In addition, the level shifter circuit is configured to generate, based on the input voltage and using a second of the two capacitors, a second voltage varying between a ground and a negative second level. The voltage distribution circuit is configured to distribute the first voltage and the second voltage to the output such that the output voltage can vary between a positive third level equal to or smaller than the positive supply voltage level and a negative fourth level, wherein an absolute value of the negative fourth level is greater than an absolute value of the positive first level.

[0017] The driver circuit according to the first aspect achieves the above-mentioned object of increasing the voltage swing of the output voltage beyond the limit imposed by the positive supply voltage level of the direct current supply voltage. That is, the output voltage of the driver circuit can vary between a positive third level and a negative fourth level which are equal to or less than the positive supply voltage level. The absolute value of the negative fourth level is greater than the absolute value of the positive first level and thus greater than the absolute value of the positive supply voltage level. The driver circuit is advantageous in that it achieves the increased voltage swing of the output voltage without an additional supply voltage to provide an additional supply voltage other than the direct current supply voltage which can be received at the supply input of the driver circuit, without an additional control voltage other than the input voltage which can be received at the input of the driver circuit, and without an additional clock.

[0018] In particular, the absolute value of the negative fourth level can be equal to the sum of the absolute values of the positive first level and the negative second level.

[0019] The driver circuit is configured to provide the output voltage without an additional supply voltage, in particular without an additional supply voltage comprising a positive level which is greater than the positive supply voltage level which can be received at the supply input. That is, the driver circuit is powered only by the direct current supply voltage to convert the input voltage into the output voltage.

[0020] The voltage-controlled electro-optical modulator which can be driven by the driver circuit according to the first aspect of the present invention can behave electrically like a capacitor or a diode. In case the modulator behaves electrically like a diode, the output voltage corresponds to the anode-cathode voltage (VAK). Furthermore, in case the modulator behaves electrically like a diode, the electro-optical modulator is configured to be electrically operated in reverse bias for modulating a laser, advantageously a continuous laser. The electro-optical modulator can be an optical ring modulator (optical RM) which behaves electrically like a diode. In case the electro-optical modulator behaves electrically like a capacitor, there is no restriction on the polarity and amplitude of the output voltage for driving the modulator compared to the case where the electro-optical modulator behaves electrically like a diode. That is, in case the electro-optical modulator behaves electrically like a diode, the driver circuit can advantageously be configured to limit the positive third level of the output voltage to be below a positive forward voltage level for forward biasing the electro-optical modulator. This allows the electro-optical modulator (when driven by the driver circuit) to be operated in reverse bias and thus configured to modulate light, such as a laser.

[0021] In particular, the two capacitors of the level shifter circuit are bootstrap capacitors.

[0022] The input voltage can be a switching voltage or a switching signal that toggles between a low input level and a high input level. In the case that the input voltage is a switching voltage, the output voltage is also a switching voltage or a switching signal that toggles between a positive third level and a negative fourth level. Further, the input voltage can be a digital signal, optionally a binary digital signal. In particular, the input voltage can be an electrical data signal. In this case, the output voltage is also an electrical data signal that can be used to drive an electro-optical modulator. The output voltage carries the same information as the input voltage. The output voltage has a voltage swing that is larger than the voltage swing of the input voltage. The electro-optical modulator can transform the output voltage of the driver circuit into an optical signal by modulating light, in particular laser light, where the optical signal carries the same information as the output voltage and thus as the input voltage. That is, the electro-optical modulator is configured to transform an electrical data signal (output voltage) into an optical data signal (laser light modulated according to the output voltage).

[0023] The low input level of the input voltage can correspond to a logic low or a logic zero ("0") and the high input level of the input voltage can correspond to a logic high or a logic one ("1"), or vice versa. The low input level can be greater than or equal to ground. The high input level can be less than or equal to a positive supply voltage level. The low input level can advantageously be less than half of the positive supply voltage level and the high input level can advantageously be greater than half of the positive supply voltage level. That is, the input voltage can advantageously be centered around half of the positive supply voltage level.

[0024] According to an embodiment, the low input level is equal to ground and the high input level is equal to the positive supply voltage level. According to another embodiment, the high input level is less than the positive supply voltage level. Further, the low input level can optionally be greater than ground.

[0025] The driver circuit can be configured to generate the output voltage such that the output voltage changes its level when the input voltage changes its level.

[0026] The driver circuit can optionally be configured to generate the output voltage such that the output voltage is equal to the positive third level when the input voltage is equal to the low input level and the output voltage is equal to the negative fourth level when the input voltage is equal to the high input level. The level converter circuit can be configured to generate the first voltage such that the first voltage is equal to the positive supply voltage level when the input voltage is equal to the low input level and the first voltage is equal to the positive first level when the input voltage is equal to the high input level. The level converter circuit can be configured to generate the second voltage such that the second voltage is equal to ground when the input voltage is equal to the low input level and the second voltage is equal to the negative second level when the input voltage is equal to the high input level.

[0027] Alternatively, the driver circuit can be configured to generate an output voltage such that the output voltage equals a positive third level when the input voltage equals the high input level and the output voltage equals a negative fourth level when the input voltage equals the low input level. The level shifter circuit can be configured to generate a first voltage such that the first voltage equals the positive supply voltage level when the input voltage equals the high input level and the first voltage equals the positive first level when the input voltage equals the low input level. The level shifter circuit can be configured to generate a second voltage such that the second voltage equals ground when the input voltage equals the high input level and the second voltage equals the negative second level when the input voltage equals the low input level.

[0028] The level shifter can be based on CMOS technology. Additionally or alternatively, the voltage distribution circuit can be based on CMOS technology.

[0029] In case the positive supply voltage level is less than a positive forward voltage level for forward biasing an electro-optical modulator, the modulator behaves electrically like a diode, the positive third level can equal the positive supply voltage level. In case the modulator behaves electrically like a capacitor, the positive third level can equal the positive supply voltage level.

[0030] Alternatively, in case the positive supply voltage level is equal to or greater than a positive forward voltage level for forward biasing an electro-optical modulator, the modulator behaves electrically like a diode, the positive third level can be less than the positive supply voltage level.

[0031] The term "voltage level" can be used as a synonym for the term "level". The terms "voltage level" and "voltage value" can be used as synonyms. Thus, the terms "level" and "value" can be used as synonyms.

[0032] The terms "change", "alternate" and "vary" can be used as synonyms.

[0033] The terms "connect" and "electrically connect" can be used as synonyms.

[0034] In an implementation form of the first aspect, the positive first level equals or is less than twice the positive supply voltage level, the absolute value of the negative second level can equal or be less than the positive supply voltage level, and / or the absolute value of the negative fourth level equals or is less than three times the positive supply voltage level.

[0035] In case the positive first level equals twice the positive supply voltage level and the absolute value of the negative second level equals the positive supply voltage level, the absolute value of the negative fourth level is three times the positive supply voltage level.

[0036] In an implementation form of the first aspect, the level shifter circuit comprises a level up shifter circuit and a level down shifter circuit connected to each other at two nodes. The level up shifter circuit comprises the first capacitor of the level shifter circuit and is configured to provide the first voltage to the voltage distribution circuit. The level down shifter circuit comprises the second capacitor of the level shifter circuit and is configured to provide the second voltage to the voltage distribution circuit.

[0037] That is, the level up shifter circuit is configured to generate the first voltage and the level down shifter circuit is configured to generate the second voltage.

[0038] The level up shifter circuit can be based on CMOS technology. Additionally or alternatively, the level down shifter circuit can be based on CMOS technology.

[0039] In an implementation form of the first aspect, the driver circuit is configured to provide a control voltage to a first one of the two nodes of the level shifter circuit and an inverted control voltage to a second one of the two nodes of the level shifter circuit on the basis of the input voltage. The control voltage varies between ground and a positive supply voltage level. The first capacitor can be connected on one side to a supply input and on the other side to the first node via a first n-channel metal-oxide-semiconductor field-effect transistor (first NMOS transistor) of the level up shifter circuit, wherein a gate terminal of the first NMOS transistor can be controlled by the second node. The second capacitor can be connected on one side to ground and on the other side to the second node via a first p-channel metal-oxide-semiconductor field-effect transistor (first PMOS transistor) of the level down shifter circuit, wherein a gate terminal of the first PMOS transistor can be controlled by the first node.

[0040] The term “NMOS transistor” is used herein as a synonym for the term “n-channel metal-oxide-semiconductor field-effect transistor” and the term “PMOS transistor” is used herein as a synonym for the term “p-channel metal-oxide-semiconductor field-effect transistor”.

[0041] The driver circuit can comprise one or more inverters electrically connected between the input and the level shifter circuit, wherein the one or more inverters are configured to provide the control voltage and / or the inverted control voltage to the level shifter circuit on the basis of the input voltage.

[0042] In case the low input level of the input level corresponds to ground and the high input level of the input voltage corresponds to the positive supply voltage level, the control voltage can be equal to the input voltage and the inverted control voltage can be equal to the inverted input voltage. Alternatively, in case the low input level of the input level corresponds to ground and the high input level of the input voltage corresponds to the positive supply voltage level, the control voltage can be equal to the inverted input voltage and the inverted control voltage can be equal to the input voltage.

[0043] In case the low input level is greater than ground and / or the high input level is less than the positive supply voltage level, the driver circuit can comprise a plurality of inverters, wherein the inverters are configured to transform the input voltage into a control voltage or an inverted control voltage. That is, the plurality of inverters is configured to provide the control voltage to the first node of the level shifter on the basis of the input voltage and to provide the inverted control voltage to the second node of the level shifter circuit.

[0044] The driver circuit can be configured to provide the control voltage such that in case the input voltage is equal to the low input level the control voltage is equal to ground and in case the input voltage is equal to the high input level the control voltage is equal to the positive supply voltage level. Alternatively, the driver circuit can be configured to provide the control voltage such that in case the input voltage is equal to the low input level the control voltage is equal to the positive supply voltage level and in case the input voltage is equal to the high input level the control voltage is equal to ground.

[0045] In an implementation form of the first aspect, the level up shifter circuit comprises a third capacitor connected between the second node and a gate terminal of the first NMOS transistor. A third node between the third capacitor and the gate terminal of the first NMOS transistor is connected to the supply input via a second NMOS transistor of the level up shifter circuit and a gate terminal of the second NMOS transistor is connected to a fourth node between the first NMOS transistor and the first capacitor. Additionally or alternatively, the level down shifter circuit can comprise a fourth capacitor connected between the first node and a gate terminal of the first PMOS transistor. A fifth node between the fourth capacitor and the gate terminal of the first PMOS transistor is connected to ground via a second PMOS transistor of the level down shifter circuit and a gate terminal of the second PMOS transistor is connected to a sixth node between the first PMOS transistor and the second capacitor.

[0046] That is, one side of the third capacitor is connected to the second node and the other side of the third capacitor is connected to the gate terminal of the first NMOS transistor and to the supply input via the second NMOS transistor. Thus, the gate terminal of the first NMOS transistor can be connected to the second node via the third capacitor.

[0047] Thus, one side of the fourth capacitor is connected to the first node and the other side of the fourth capacitor is connected to the gate terminal of the first PMOS transistor and to ground via the second PMOS transistor. Thus, the gate terminal of the first PMOS transistor can be connected to the first node via the fourth capacitor.

[0048] In an implementation form of the first aspect, the voltage distribution circuit is connected to a fourth node of the level shifter circuit between the first NMOS transistor and the first capacitor, wherein at the fourth node the level up shifter circuit is configured to provide the first voltage to the voltage distribution circuit. Further, the voltage distribution circuit is connected to a sixth node of the level shifter circuit between the first PMOS transistor and the second capacitor, wherein at the sixth node the level down shifter circuit is configured to provide the second voltage to the voltage distribution circuit.

[0049] In an implementation form of the first aspect, the output comprises a first output terminal for providing a third voltage to the electro-optical modulator and a second output terminal for providing a fourth voltage to the electro-optical modulator. The voltage distribution circuit can comprise a first voltage distribution circuit and a second voltage distribution circuit. The first voltage distribution circuit is configured to distribute the first voltage such that at the first output terminal the third voltage can vary between ground and a positive first level. The second voltage distribution circuit is configured to distribute the second voltage such that at the second output terminal the fourth voltage can vary between a negative second level and a positive third level.

[0050] In case the electro-optical modulator electrically behaves like a diode, the third voltage can correspond to a cathode voltage and the fourth voltage can correspond to an anode voltage. The output voltage corresponds to a difference between the third voltage and the fourth voltage, wherein the third voltage is subtracted from the fourth voltage. Thus, in case the electro-optical modulator electrically behaves like a diode, the output voltage can correspond to an anode-cathode voltage (VAK) and thus to a difference between the cathode voltage and the anode voltage, wherein the cathode voltage is subtracted from the anode voltage.

[0051] The first voltage distribution circuit can be based on CMOS technology. Additionally or alternatively, the second voltage distribution circuit can be based on CMOS technology.

[0052] In an implementation form of the first aspect, the first voltage distribution circuit comprises a third PMOS transistor and a third NMOS transistor. The third PMOS transistor is configured to provide the first voltage to the first output terminal in case the level of the first voltage corresponds to the positive first level. The third NMOS transistor is configured to provide a conductive path between the first output terminal and ground in case the level of the first voltage corresponds to the positive supply voltage level.

[0053] In other words, the third PMOS transistor is configured to provide the first voltage to the first output terminal in case the first voltage equals the positive first level. The third NMOS transistor is configured to provide a conductive path between the first output terminal and ground in case the first voltage equals the positive supply voltage level.

[0054] That is, the third NMOS transistor is configured to pull down the first output terminal to ground in case the first voltage equals the positive supply voltage level.

[0055] In an implementation form of the first aspect, the first output terminal is connected to a drain terminal of a third PMOS transistor and to a drain terminal of a third NMOS transistor. A gate terminal of the third PMOS transistor can be connected to the supply input. The level shifter circuit can be configured to control the gate terminal of the third NMOS transistor depending on the input voltage. In particular, the level shifter circuit can be configured to control the gate terminal of the third NMOS transistor by an inverted control voltage.

[0056] The level shifter circuit, in particular the level up shifter circuit, can be configured to provide the first voltage to a source terminal of a third PMOS transistor of the first voltage distribution circuit. The third PMOS transistor of the first voltage distribution circuit can be connected between a fourth node of the level shifter circuit and the first output terminal. A gate terminal of the third NMOS transistor can be connected to a second node of the level shifter circuit. Thereby, the gate terminal of the third NMOS transistor can be controlled by the second node of the level shifter circuit. A source terminal of the third NMOS transistor can be connected to ground.

[0057] In an implementation form of the first aspect, the second voltage distribution circuit comprises a fourth NMOS transistor and a fourth PMOS transistor. The fourth NMOS transistor is configured to provide the second voltage to the second output terminal in case a level of the second voltage corresponds to a negative second level. The fourth PMOS transistor is configured to provide a conductive path between the second output terminal and the supply input in case the level of the second voltage corresponds to ground.

[0058] In other words, the fourth NMOS transistor is configured to provide the second voltage to the second output terminal in case the second voltage equals the negative second level. The fourth PMOS transistor is configured to provide a conductive path between the second output terminal and the supply input in case the second voltage equals ground.

[0059] In an implementation form of the first aspect, the gate terminal of the fourth NMOS transistor is connected to ground. The level shifter circuit can be configured to control the gate terminal of the fourth PMOS transistor in dependence of the input voltage. In particular, the level shifter circuit can be configured to control the gate terminal of the fourth PMOS transistor by the control voltage. According to an embodiment, the second output terminal is connected to the drain terminal of the fourth NMOS transistor and to the drain terminal of the fourth PMOS transistor. According to another embodiment, the second output terminal is connected to the drain terminal of the fourth NMOS transistor, to the source terminal of a fifth PMOS transistor of the second voltage distribution circuit, and to the drain terminal of the fourth PMOS transistor via a fifth NMOS transistor of the second voltage distribution circuit, wherein the drain terminal and the gate terminal of the fifth PMOS transistor are connected to ground.

[0060] The gate terminal of the fourth PMOS transistor can be connected to a first node of the level shifter circuit. Thereby, the gate terminal of the third NMOS transistor can be controlled by the first node of the level shifter circuit.

[0061] The level shifter circuit can be configured to control the gate terminal of the fifth NMOS transistor by the inverted control voltage. The gate terminal of the fifth NMOS transistor can be connected to a second node of the level shifter circuit. The level shifter circuit can be configured to control the gate terminal of the fifth NMOS transistor in line with the control of the gate terminal of the third NMOS transistor of the first voltage distribution circuit.

[0062] The level shifter circuit, in particular the level down shifter circuit, can be configured to provide the second voltage to the source terminal of the fourth NMOS transistor. A low speed NMOS transistor can be connected between a sixth node of the level shifter circuit and the second output terminal.

[0063] In an implementation form of the first aspect, the fifth NMOS transistor and the fifth PMOS transistor are configured to limit the fourth voltage at the second output terminal to a positive third level below a positive forward voltage level for forward biasing the electro-optical modulator in case the electro-optical modulator behaves electrically like a diode.

[0064] In an implementation form of the first aspect, the first voltage distribution circuit comprises a sixth NMOS transistor, wherein the drain terminal of the third NMOS transistor is connected to the first output terminal via the sixth NMOS transistor, and the gate terminal of the sixth NMOS transistor is connected to the power input. Additionally or alternatively, the second voltage distribution circuit can comprise a sixth PMOS transistor, wherein the drain terminal of the fourth PMOS transistor is connected to the second output terminal via the sixth PMOS transistor, optionally via the sixth PMOS transistor and the fifth NMOS transistor, and the gate terminal of the sixth PMOS transistor is connected to ground.

[0065] When the sixth NMOS transistor is connected in series to the third NMOS transistor, the stress on the third NMOS transistor is reduced because the voltage between the power input and the second output terminal is divided across the series connection of the two NMOS transistors. When the sixth PMOS transistor is connected in series to the fourth PMOS transistor, the stress on the fourth PMOS transistor is reduced because the voltage between the power input and the second output terminal is divided across the series connection of the two PMOS transistors.

[0066] The drain terminal of the sixth NMOS transistor can be connected to the drain terminal of the third PMOS transistor and the first output terminal, the drain terminal of the third NMOS transistor can be connected to the source terminal of the sixth NMOS transistor and the source terminal of the third NMOS transistor can be connected to ground. That is, the first output terminal can be connected to ground via the cascode connection of the third NMOS transistor and the sixth NMOS transistor.

[0067] The source terminal of the sixth PMOS transistor can be connected to the drain terminal of the fourth PMOS transistor. The drain terminal of the sixth PMOS transistor can be connected to the drain terminal of the fourth NMOS transistor and the second output terminal. Alternatively, the drain terminal of the sixth PMOS transistor can be connected to the drain terminal of a fifth NMOS transistor, wherein the source terminal of the fifth NMOS transistor is connected to the drain terminal of the fourth NMOS transistor and the second output terminal.

[0068] That is, the second output terminal can be connected to the power input via the cascode connection of the fourth PMOS transistor and the sixth PMOS transistor. Alternatively, the second output terminal can be connected to the power input via the fifth NMOS transistor and the cascode connection of the fourth PMOS transistor and the sixth PMOS transistor.

[0069] In an implementation form of the first aspect, the body terminal of the third PMOS transistor of the first voltage distribution circuit is connected to the source terminal of the third PMOS transistor. Additionally or alternatively, the body terminal of the fourth NMOS transistor of the second voltage distribution circuit can be connected to the source terminal of the fourth NMOS transistor.

[0070] The third PMOS transistor of the first voltage distribution circuit can comprise an n-doped well (n-well) and the source terminal can be connected to the n-well. The fourth NMOS transistor of the second voltage distribution circuit can comprise a p-doped well (p-well) and the source terminal can be connected to the p-well. The p-doped well of the fourth NMOS transistor can be an isolated p-doped well (isolated p-well).

[0071] In case the connection at the body terminal of the transistor is not mentioned, it can be assumed that in case of an NMOS transistor the p-doped well (p-well) of the NMOS transistor is connected to ground and in case of a PMOS transistor the n-doped well (n-well) is connected to the power input. That is, in case the connection at the body terminal is not mentioned, the body terminal of the NMOS transistor can be connected to ground and the body terminal of the PMOS transistor can be connected to the power input.

[0072] Beneficially, the positive supply voltage level of the direct current supply voltage can be larger than the maximum of the absolute value of the threshold voltage of the NMOS transistor and the absolute value of the threshold voltage of the PMOS transistor. In other words, when the direct current supply voltage is received at the power input by the driver circuit, the direct current supply voltage is such that the driver circuit, in particular the transistors of the driver circuit, can function properly.

[0073] To realize the driver circuit according to the first aspect of the present disclosure, some or all of the implementation forms and optional features of the first aspect as described above can be combined with each other.

[0074] A second aspect of the present disclosure provides a system. The system can comprise a driver circuit according to the first aspect or any of its implementation forms and a voltage-controlled electro-optical modulator. The electro-optical modulator is electrically connected to the output of the driver circuit. The driver circuit is configured to drive the electro-optical modulator by providing an output voltage to the electro-optical modulator in dependence on an input voltage.

[0075] The above description of the driver circuit according to the first aspect and any of its implementation forms is valid for the system of the second aspect, in particular for the driver circuit in the system. The above description with respect to the electro-optical modulator is valid for the voltage-controlled electro-optical modulator of the system of the second aspect.

[0076] In particular, the electro-optical modulator is electrically connected to two output terminals of the output of the driver circuit.

[0077] The electro-optical modulator can electrically behave like a diode or a capacitor.

[0078] The voltage-controlled electro-optical modulator can be an electro-optical modulator with a silicon p-n, III-V p-n or hybrid p-n depletion diode, such as an optical ring modulator (operating under reverse bias). In this case, the electro-optical modulator electrically behaves like a diode. Alternatively, the voltage-controlled electro-optical modulator can be a metal-oxide-semiconductor capacitor based electro-optical modulator (MOSCAP electro-optical modulator) or a semiconductor-insulator-semiconductor capacitor based electro-optical modulator (SISCAP electro-optical modulator). In this case, the electro-optical modulator electrically behaves like a capacitor.

[0079] The system can correspond to an optical transmitter for transmitting an optical signal based on an electrical data signal (digital signal) that can be input as an input voltage to an input terminal of the driver circuit.

[0080] The voltage-controlled electro-optical modulator can be configured to transform the output voltage of the driver circuit into an optical signal by modulating light, in particular laser light, wherein the optical signal carries the same information as the output voltage and thus as the input voltage. That is, the electro-optical modulator can be configured to transform an electrical data signal (output voltage of the driver circuit) into an optical data signal (laser light modulated according to the output voltage).

[0081] The system can further comprise a laser for providing laser light that can be modulated by the voltage-controlled electro-optical modulator to transmit the optical signal.

[0082] The system can comprise a single power supply, wherein the single power supply is configured to provide a direct current supply voltage to the power supply input terminal of the driver circuit.

[0083] The system of the second aspect achieves the same advantages as the driver circuit of the first aspect and can be extended by the respective implementations for the driver circuit of the first aspect as described above.

[0084] To implement the system according to the second aspect of the present disclosure, some or all of the implementation forms and optional features of the second aspect as described above can be combined with each other. BRIEF DESCRIPTION OF DRAWINGS

[0085] The aspects and implementations described above are explained in greater detail with reference to the drawings, in which:

[0086] Figure 1 A driver circuit according to an embodiment of the present application is shown.

[0087] Figure 2 A driver circuit according to an embodiment of the present application is shown.

[0088] Figure 3 A driver circuit according to an embodiment of the present application is shown. Figure 1 and 2 Examples of voltage curves of voltages at different terminals and nodes of the driver circuit of

[0089] Figure 4A and 4B A driver circuit according to an embodiment of the present application is shown.

[0090] Figure 5A and 5B A system according to an embodiment of the present application is shown.

[0091] Figure 6An exemplary representation is shown of the response of a ring modulator (RM) to three different anode-cathode voltage (VAK) values, VAK1, VAK2, and VAK3, applied to the RM.

[0092] In the accompanying drawings, corresponding elements are labeled with the same reference numerals. Detailed Implementation

[0093] Figure 1 A driver circuit according to an embodiment of the present invention is shown.

[0094] The above description of the driver circuitry for the first aspect or any implementation thereof is for Figure 1 The driver circuit 1 is correspondingly effective. Therefore, in the following... Figure 1 In the description of the driver circuit 1, the elements (i.e., transistors, capacitors, and nodes), voltages, and voltage levels of the driver circuit 1 use the same numbering as used in the description of the driver circuit of the first aspect or any implementation thereof above. The terms "source terminal," "drain terminal," and "gate terminal" are abbreviated as the terms "source," "drain," and "gate," respectively.

[0095] like Figure 1 As shown, driver circuit 1 includes a power input terminal SP for receiving DC power supply voltage VDD and an input terminal IN for receiving input voltage Vin. The power input terminal SP is implemented using a power input terminal, and the input terminal IN is implemented using an input terminal, as shown below. Figure 1 As shown. Driver circuit 1 includes an output terminal, which is implemented by a first output terminal OUT1 and a second output terminal OUT2, as follows. Figure 1 As shown. Driver circuit 1 is configured to provide an output voltage Vout at its output terminal based on the input voltage Vin.

[0096] Voltage-controlled electro-optic modulators (such as ring modulators (RM)) can be connected to output terminals OUT1 and OUT2 (not in... Figure 1 (As shown in the figure). The driver circuit 1 is configured to drive the electro-optic modulator by providing an output voltage Vout to the electro-optic modulator according to the input voltage Vin.

[0097] From the perspective of the driver circuit 1, the voltage-controlled electro-optical modulator (when connected to the output terminals of the driver circuit 1) corresponds to a capacitance and does not generate any relevant photo current during operation. That is, the current flowing via the electro-optical modulator across the output terminals OUT1 and OUT2 (when the modulator is connected to these output terminals) is negligible. This is the case in situations where the voltage-controlled electro-optical modulator behaves electrically like a diode, which is the case if the modulator is operated under reverse bias (i.e., if the positive level of the output voltage Vout is less than the positive forward voltage level for forward biasing the modulator).

[0098] Furthermore, the driver circuit 1 comprises a level shifter circuit 2 and a voltage distribution circuit 3. The level shifter circuit 2 comprises a level up shifter circuit 2a and a level down shifter circuit 2b connected to each other at a first node nl and a second node n2 of the driver circuit 1, in particular of the level shifter circuit 2. The voltage distribution circuit 3 comprises a first voltage distribution circuit 3a and a second voltage distribution circuit 3b.

[0099] The driver circuit 1 comprises a first NMOS transistor nT1, a first PMOS transistor pT1, an optional second NMOS transistor nT2, an optional second PMOS transistor pT2, a third NMOS transistor nT3, a third PMOS transistor pT3, a fourth NMOS transistor nT4, a fourth PMOS transistor pT4, an optional fifth NMOS transistor nT5, an optional fifth PMOS transistor pT5, an optional sixth NMOS transistor nT6, an optional PMOS transistor pT6, a first capacitor Cl, a second capacitor C2, an optional third capacitor C3, an optional fourth capacitor C4, and an optional inverter INV1.

[0100] The transistors of the driver circuit 1 are implemented by CMOS technology, as shown in Figure 1 Alternatively, the transistors of the driver circuit 1 can be implemented by FinFET transistors (e.g., 12 nm FinFET transistors). The implementation by FinFET transistors is merely an example and does not limit the present disclosure.

[0101] When the electro-optic modulator is connected to the output of driver circuit 1 and driven / operated by driver circuit 1, the capacitances of the first and second capacitors C1 and C2 can advantageously be larger than the capacitance corresponding to the voltage-controlled electro-optic modulator from the viewpoint of driver circuit 1 (C1, C2 >> capacitance of the electro-optic modulator). For example, the capacitance of the first capacitor C1 can optionally be equal to 3.5 pF, and the capacitance corresponding to the electro-optic modulator can optionally be equal to 50 fF. The capacitances of the first and second capacitors C1 and C2 can be advantageously implemented such that the voltage-controlled electro-optic modulator does not draw charge from the relevant portion of the capacitor when connected as a load to the output of driver circuit 1, whether as transient current or direct current. That is, the transient current or direct current is considered negligible.

[0102] An optional third capacitor C3 is configured to restore the charge lost on the first capacitor C1. An optional fourth capacitor C4 is configured to restore the charge on the second capacitor C2.

[0103] like Figure 1 As shown, a first NMOS transistor nT1, an optional second NMOS transistor nT2, a first capacitor C1, and an optional third capacitor C3 form a level-up converter circuit 2a. A first PMOS transistor pT1, an optional second PMOS transistor pT2, a second capacitor C2, and an optional fourth capacitor C4 form a level-down converter circuit 2b.

[0104] The drains of the first NMOS transistor nT1 and the optional second NMOS transistor nT2 are connected to the power input terminal SP. The source of the first NMOS transistor nT1 is connected to one side of the first capacitor C1, with the other side of the first capacitor C1 connected to the first node n1. The source of the optional second NMOS transistor nT2 is connected to one side of the optional third capacitor C3, with the other side of the optional third capacitor C3 connected to the second node n2. The gate of the first NMOS transistor nT1, the source of the optional second NMOS transistor nT2, and the optional third capacitor C3 are each connected to the third node n3 of the level shifter circuit 2. The gate of the optional second NMOS transistor nT2, the source of the first NMOS transistor nT1, and the first capacitor C1 are each connected to the fourth node n4 of the level shifter circuit 2. In cases where the optional second NMOS transistor nT2 and the optional third capacitor C3 are not part of the driver circuit 1 (not in...), ... Figure 1 As shown in the diagram, the gate of the first NMOS transistor nT1 can still be controlled by the second node n2, specifically by the voltage Vc' supplied to the second node n2. For example, the gate of the first NMOS transistor nT1 can be connected to the second node n2.

[0105] The drains of the first PMOS transistor pT1 and the optional second PMOS transistor pT2 are connected to ground GND. The source of the first PMOS transistor pT1 is connected to one side of the second capacitor C2, the other side of which is connected to the second node n2. The source of the optional second PMOS transistor pT2 is connected to one side of the optional fourth capacitor C4, the other side of which is connected to the first node n1. The gate of the first PMOS transistor pT1, the source of the optional second PMOS transistor pT2, and the optional fourth capacitor C4 are each connected to the fifth node n5 of the level shifter circuit 2. The gate of the optional second PMOS transistor pT2, the source of the first PMOS transistor pT1, and the second capacitor C2 are each connected to the sixth node n6 of the level shifter circuit 2. In the case where the optional second PMOS transistor pT2 and the optional fourth capacitor C4 are not part of the driver circuit 1 (not in...), ... Figure 1 As shown in the diagram, the gate of the first PMOS transistor pT1 can still be controlled by the first node n1, specifically by the voltage Vc supplied to the first node n1. For example, the gate of the first PMOS transistor pT1 can be connected to the first node n1.

[0106] In addition, such as Figure 1 As shown, the third NMOS transistor nT3, the third PMOS transistor pT3, and the optional sixth NMOS transistor nT6 form the first voltage distribution circuit 3a. The fourth NMOS transistor nT4, the fourth PMOS transistor pT4, the optional fifth NMOS transistor nT5, the optional fifth PMOS transistor pT5, and the optional sixth PMOS transistor pT6 form the second voltage distribution circuit 3b.

[0107] The three transistors of the first voltage distribution circuit 3a are connected in series between the fourth node n4 of the level shifter circuit 2 and ground GND. The source of the third PMOS transistor pT3 is connected to the level shifter circuit 2a, specifically to the fourth node n4 of the level shifter circuit 2. The drain of the third PMOS transistor pT3 is connected to the drain of an optional sixth NMOS transistor nT6, the source of the optional sixth NMOS transistor nT6 is connected to the drain of the third NMOS transistor nT3, and the source of the third NMOS transistor nT3 is connected to ground GND. The gates of the third PMOS transistor pT3 and the optional sixth NMOS transistor nT6 are connected to the power input terminal SP, and the gate of the third NMOS transistor nT3 is connected to the second node n2 of the level shifter circuit 2. The first output terminal OUT1 is connected to the drain of the third PMOS transistor pT3. In the case where the optional sixth NMOS transistor nT6 is not part of the driver circuit 1 (not in...), ... Figure 1The drain of the third PMOS transistor pT3 is connected to the drain of the third NMOS transistor nT3, as shown in

[0108] The transistors in the second voltage distribution circuit 3b, except for the optional fifth PMOS transistor pT5, are connected in series between the supply input SP and a sixth node n6 of the level shifter circuit 2. The source of the fourth PMOS transistor pT4 is connected to the supply input SP and the drain of the fourth PMOS transistor pT4 is connected to the source of an optional sixth PMOS transistor pT6. The drain of the optional sixth PMOS transistor pT6 is connected to the drain of an optional fifth NMOS transistor nT5. The source of the optional fifth NMOS transistor nT5 is connected to the drain of a fourth NMOS transistor nT4 and to the source of the optional fifth PMOS transistor pT5. The source of the fourth NMOS transistor nT4 is connected to the sixth node n6 of the level shifter circuit 2. The drain of the optional fifth PMOS transistor pT5 is connected to ground GND. The gate of the fourth PMOS transistor pT4 is connected to the first node nl of the level shifter circuit 2. The gate of the optional fifth NMOS transistor nT5 is connected to the second node n2 of the level shifter circuit 2. The gates of the fourth NMOS transistor nT4, the optional fifth PMOS transistor pT5 and the optional sixth PMOS transistor pT6 are connected to ground GND. The second output terminal OUT2 is connected to the drain of the fourth NMOS transistor nT4. In case the optional sixth PMOS transistor pT6 is not part of the driver circuit 1 (not shown in Figure 1 The drain of the fourth PMOS transistor pT4 is connected to the drain of the optional fifth NMOS transistor nT5, as shown in Figure 2 The drain of the fourth PMOS transistor pT4 is connected to the drain of the optional fifth NMOS transistor nT5, as shown in Figure 2 The drain of the fourth PMOS transistor pT4 is connected to the drain of the optional fifth NMOS transistor nT5, as shown in

[0109] The driver circuit 1 is configured to provide, based on an input voltage Vin which can be received at the input terminal IN, a control voltage Vc for controlling the gates of the first PMOS transistor pTl and the fourth PMOS transistor pT4 to the first node nl of the level shifter circuit 2. The driver circuit 1 is further configured to provide a control voltage Vc’ for controlling the gates of the first NMOS transistor nTl, the third NMOS transistor nT3 and the optional fifth NMOS transistor nT5 to the second node n2 of the level shifter circuit 2.

[0110] As Figure 1As shown, the driver circuit 1 comprises an optional inverter INV1 connected between the input IN and the second node n2 of the level shifter circuit 2 for providing an inverted control voltage Vc'. The inverted control voltage can also be generated differently in any way known to the skilled person.

[0111] As shown, the control voltage Vc is equal to the input voltage Vin and the inverted control voltage Vc' is thereby equal to the inverted input voltage Vin. This is merely by way of example and does not limit the present disclosure. Figure 1

[0112] That is, alternatively, the control voltage Vc can be equal to the inverted input voltage Vin and the inverted control voltage Vc' can be equal to the input voltage Vin (not shown in Figure 1 Figure 1 As shown, the control voltage Vc is equal to the input voltage Vin and the inverted control voltage Vc' is thereby equal to the inverted input voltage Vin. This is merely by way of example and does not limit the present disclosure.

[0113] Figure 1 An embodiment of the driver circuit is shown in case the input voltage Vin varies between a low input level and a high input level (not shown in Figure 1

[0114] In case the high input level is less than the positive supply voltage level Vdd, additional circuitry can be provided in the driver circuit 1. This is described in the following with reference to Figure 4A 4B

[0115] The input voltage Vin can be a switching voltage that is switched between a low input level and a high input level. The input voltage Vin can be a data signal.

[0116] The input voltage Vin can be a digital data signal, in particular it can be a binary digital signal. For example, the input voltage can be a signal of 20 Giga bits per second (Gbps). This is merely by way of example and does not limit the present disclosure to a specific data rate of the input voltage.

[0117] According to an embodiment, such as Figure 1 ​​​​​The driver circuit 1 is configured to provide the control voltage Vc based on an input voltage Vin that can be received at the input terminal IN such that the control voltage Vc equals ground when the input voltage Vin equals a low input level and the control voltage Vc equals a positive supply voltage level Vdd when the input voltage Vin equals a high input level. Alternatively, the driver circuit 1 can be configured to provide the control voltage Vc based on the input voltage Vin such that the control voltage Vc equals ground when the input voltage Vin equals a high input level and the control voltage Vc equals the positive supply voltage level Vdd when the input voltage Vin equals a low input level (not shown in Figure 1 the middle).

[0118] The voltage at the fourth node n4 (i.e. between the fourth node n4 and ground GND) is referred to as the first voltage V1. The voltage at the sixth node n6 (i.e. between the sixth node n4 and ground GND) is referred to as the second voltage V2. The voltage at the first output terminal OUT1 (i.e. between the first output terminal OUT1 and ground GND) is referred to as the third voltage V3 and the voltage at the second output terminal OUT2 (i.e. between the second output terminal OUT2 and ground GND) is referred to as the fourth voltage V4. The voltage between the first output terminal OUT1 and the second output terminal OUT2 is the output voltage Vout. As Figure 1 indicated, the output voltage Vout corresponds to the difference between the third voltage V3 and the fourth voltage V4, wherein the third voltage 3 is subtracted from the fourth voltage V4.

[0119] Figure 1 The functionality of the driver circuit 1 of Figure 3 is exemplarily described in the following, Figure 3 exemplarily showing voltage curves of the input voltage Vin, the control voltage Vc, the first voltage V1, the second voltage V2, the third voltage V3, the fourth voltage V4 and the output voltage Vout over time.

[0120] Figure 2 A driver circuit according to an embodiment of the present application is shown. Figure 2 The driver circuit 1 of Figure 1 corresponds to the driver circuit 1 of Figure 1 and without the optional fifth NMOS transistor nT5 and the optional PMOS transistor pT5. Thus, the above description of the driver circuit 1 of Figure 2 is accordingly valid and mainly describes in the following Figure 1 the differences between the circuits of 2 and

[0121] Figure 2 The driver circuit 1 of Figure 2the optional fifth NMOS transistor nT5 and the optional PMOS transistor pT5 shown in the driver circuit 1. As a result, as shown in Figure 3 the fourth NMOS transistor nT4, the fourth PMOS transistor pT4 and the optional sixth PMOS transistor pT6 form the second voltage distribution circuit 3b.

[0122] The three transistors of the second voltage distribution circuit 3b are connected in series between the supply input SP of the level shifter circuit 2 and the sixth node n6. The source of the fourth PMOS transistor pT4 is connected to the supply input SP and the drain of the fourth PMOS transistor pT4 is connected to the source of the optional sixth PMOS transistor pT6. The drain of the optional sixth PMOS transistor pT6 is connected to the drain of the fourth NMOS transistor nT4. The source of the fourth NMOS transistor nT4 is connected to the sixth node n6 of the level shifter circuit 2. The gate of the fourth PMOS transistor pT4 is connected to the first node n1 of the level shifter circuit 2. The gates of the fourth NMOS transistor nT4 and the optional sixth PMOS transistor pT6 are connected to ground GND. The second output terminal OUT2 is connected to the drain of the fourth NMOS transistor nT4. In case the optional sixth PMOS transistor pT6 is not part of the driver circuit 1 (not shown in Figure 1 ), the drain of the fourth PMOS transistor pT4 is connected to the drain of the fourth NMOS transistor nT4.

[0123] Figure 1 Examples of voltage curves of voltages at different terminals and nodes of the driver circuit 1 are shown in Figure 3 and 2 . In the following, reference is made to elements of the driver circuit 1. The above description of the driver circuit of the first aspect or any implementation form thereof is accordingly valid for describing the function of the driver circuit 1 using the voltage curves shown in Figure 1 and 2 . Thus, in the following description, the same numbering or labeling as used in the above description of the driver circuit of the first aspect or any implementation form thereof and the same numbering or labeling as used in the above description of the driver circuit 1 is used for the voltages and voltage levels shown in Figure 3 and Figure 1 . The above description of the driver circuit 1 is accordingly valid for describing the function of the driver circuit 1 using the voltage curves shown in 2 and Figure 3 . Thus, in the following description, the same numbering or labeling as used in the above description of the driver circuit of the first aspect or any implementation form thereof and the same numbering or labeling as used in the above description of the driver circuit 1 is used for the voltages and voltage levels shown in Figure 3 and 2 . The above description of the driver circuit 1 is accordingly valid for describing the function of the driver circuit 1 using the voltage curves shown in

[0124] As Figure 1As shown, the input voltage Vin varies, in particular switches, between a low input level "low" and a high input level "high". The control voltage Vc varies, in particular switches, between a ground GND and a positive supply voltage level Vdd of a supply voltage VDD that can be received at a supply input SP. The positive supply voltage level Vdd can be equal to 0.8 volts (Vdd = 0.8 volts). The ground GND can be equal to 0 volts (GND = 0 volts). These values of the positive supply voltage level Vdd and the ground GND are merely examples and do not limit the present disclosure.

[0125] For the following description of the function of the driver circuit based on the voltage curves of Figure 1 Figure 1 and 2 it is assumed that the positive supply voltage level Vdd of the direct current supply voltage VDD is greater than the maximum of the absolute value of the threshold voltage of the NMOS transistor and the absolute value of the threshold voltage of the PMOS transistor of the driver circuit. That is, it is assumed that the driver circuit is powered via a supply input with this supply voltage VDD that allows the transistors of the driver circuit to function properly as described below. However, in case the positive supply voltage level Vdd is lower, the driver circuit can still operate at a reduced speed due to subthreshold conduction.

[0126] The first voltage V1 varies between the positive supply voltage level Vdd and a positive first level L1 (L1 > Vdd) that is greater than the positive supply voltage level Vdd. The second voltage V2 varies between a negative second level L2 and the ground GND. The third voltage V3 varies between the ground GND and the positive first level L1. The fourth voltage V4 varies between the negative second level L2 and a positive third level L3 (L3 < Vdd) that is equal to or smaller than the positive supply voltage level Vdd. The output voltage Vout varies between a negative fourth level L4 and the positive third level L3, wherein the absolute value of the negative fourth level L4 is greater than the positive first level L1 (|L4| > L1). In particular, the absolute value of the negative fourth level L4 is equal to the sum of the positive first level L1 and the absolute value of the negative second level L2 (|L4| = L1 + |L2|).

[0127] According to embodiments of Figure 1 and 2 the positive first level L1 is equal to twice the positive supply voltage level Vdd (L1 = 2 · Vdd), and the absolute value of the negative second level L2 is equal to the positive supply voltage level Vdd (|L2| = Vdd or L2 = -Vdd). Thereby, the absolute value of the negative fourth level L4 is equal to three times the positive supply voltage level Vdd (|L4| = 3 · Vdd or L4 = 3 · (-Vdd)).

[0128] ​Alternatively, the positive first level L1 can be less than twice the positive supply voltage level Vdd (L1 < 2 · Vdd) and / or the absolute value of the negative second level L2 can be less than the positive supply voltage level Vdd (|L2| < Vdd). In this case, the absolute value of the negative fourth level L4 is less than three times the positive supply voltage level Vdd (|L4| < 3 · Vdd).

[0129] The level up-converter circuit 2a, in particular the first capacitor C1, of the driver circuit 1 is configured to convert the control voltage Vc (and thereby the input voltage Vin) at the fourth node n4 of the level converter circuit 2 into the first voltage V1. That is, the level up-converter circuit 2a is configured to convert the voltage range between ground GND and the positive supply voltage level Vdd at the fourth node n4 of the level converter circuit 2 into the voltage range between the positive supply voltage level Vdd and the positive first level L1 (L1 = 2 · Vdd). The level down-converter circuit 2b, in particular the second capacitor C2, is configured to convert the control voltage Vc (and thereby the input voltage Vin) at the sixth node n6 of the level converter circuit 2 into the second voltage V2. That is, the level down-converter circuit 2b is configured to convert the voltage range between ground GND and the positive supply voltage level Vdd at the sixth node n6 of the level converter circuit 2 into the voltage range between ground GND and the negative second level L2 (|L2| = Vdd or L2 = -Vdd). This results in the differential voltage (V1 - V2) between the fourth node n4 and the sixth node n6 of the level converter circuit 2 replicating the input voltage Vin or the control voltage Vc, but with the voltage range between the positive supply voltage level Vdd and the sum of the positive first level L1 and the absolute value of the negative second level L2 being equal to three times the positive supply voltage level Vdd (L1 + |L2| = 3 · VDD).

[0130] The third PMOS transistor pT3 is configured to apply the positive first level L1 of the first voltage V1 to the first output terminal OUT1 and the fourth NMOS transistor nT4 is configured to apply the negative second level L2 of the second voltage V2 to the second output terminal OUT2. Because the first voltage V1 at the fourth node n4 is higher than the positive supply voltage level Vdd of the supply voltage VDD (in case V1 = L1), the body terminal of the third PMOS transistor pT3 handling the fourth node n4 is not connected to the supply input terminal SP and thereby not to the supply voltage VDD, as shown in Figure 1 and 2 Because the second voltage V2 at the sixth node n6 is lower than ground GND (in case V2 = L2), the body terminal of the fourth NMOS transistor nT4 handling the sixth node n6 is not connected to ground GND, as shown in Figure 3 and 2Otherwise, this would result in a forward bias of the source body diode. To avoid this, source body connections are implemented for the third PMOS transistor pT3 and the fourth NMOS transistor nT4 as shown in Figure 2 and 2 The n-doped well (n-well) of the third PMOS transistor pT3 is connected to the source of the third PMOS transistor pT3. The p-doped well (p-well) of the fourth NMOS transistor nT4 is connected to the source of the fourth NMOS transistor nT4. Due to CMOS technology, the p-well of the fourth NMOS transistor nT4 can advantageously be an isolated p-well.

[0131] An optional cascode transistor, i.e. an optional sixth NMOS transistor nT6, can be provided in series connection to the third NMOS transistor nT3, such that a third voltage V3 equal to the positive first level L1 (L1 = 2 · Vdd) is shunted over the two drain source voltages of these two transistors. This prevents an excessive stress on a single transistor. This occurs when the third voltage V3 at the first output voltage OUT1 is equal to the positive first level L1 and is discharged to ground GND by switching the third NMOS transistor nT3 and the optional sixth NMOS transistor nT6 into a conductive state. Accordingly, an optional cascode transistor, i.e. an optional sixth PMOS transistor pT6, can be provided in series connection to the fourth PMOS transistor pT4, such that a voltage greater than the positive supply voltage level Vdd is shunted over the two drain source voltages of these two transistors. Said voltage corresponds to the sum of the positive supply voltage level Vdd and the absolute value of the negative second level L2 (Vdd + |L2|), which is equal to twice the positive supply voltage level Vdd (Vdd + |L2| = 2 · Vdd). This prevents an excessive stress on a single transistor. This occurs when the fourth voltage V4 at the second output voltage OUT2 is equal to the negative second level L2 and is charged to the positive third level L3 by switching the fourth PMOS transistor pT4, the optional fifth NMOS transistor nT5 and the optional sixth PMOS transistor pT6 into a conductive state.

[0132] Thereby, the optional sixth NMOS transistor nT6 and the optional sixth PMOS transistor pT6 can be used to handle voltages greater than the supply voltage VDD of the positive supply voltage level Vdd generated within the driver circuit 1.

[0133] As shown in Figure 3 the third voltage V3 at the first output terminal OUT1 varies, in particular is switched, between the positive first level L1 and ground GND. The fourth voltage at the second output terminal OUT2 varies, in particular is switched, between the negative second level L2 and the positive third level L3.

[0134] In case the voltage-controlled electro-optical modulator driven by the driver circuit 1 behaves electrically like a diode and is thereby operated under reverse bias for modulating light and in case the positive supply voltage level Vdd is equal to or larger than the positive forward voltage level for forward biasing the electro-optical modulator, the positive third level L3 is advantageously smaller than the positive supply voltage level Vdd (L3 < Vdd). This is achieved by the optional fifth NMOS transistor nT5 and the optional fifth PMOS transistor pT5. In particular, the optional fifth NMOS transistor nT5 is configured to limit the positive third level L3 below the positive forward voltage level. The optional fifth PMOS transistor pT5 is configured to bias the anode branch of the voltage-controlled electro-optical modulator behaving electrically like a diode (in case the modulator is connected to the output terminals OUT1 and OUT2) when the fourth NMOS transistor nT4 is in a non-conductive state. Thus, the optional fifth PMOS transistor pT5 is configured to clip the maximum voltage at the second output terminal OUT2. In other words, the optional fifth NMOS transistor nT5 and the optional fifth PMOS transistor pT5 are configured to limit the positive third level L3 of the fourth voltage V4 at the second output terminal OUT2 below the positive forward voltage level for forward biasing the electro-optical modulator in case the electro-optical modulator behaves electrically like a diode.

[0135] In case the positive supply voltage level Vdd is smaller than the positive forward voltage level for forward biasing the electro-optical modulator or in case the electro-optical modulator does not behave electrically like a diode but like a capacitor, the positive third level L3 can be equal to the positive supply voltage level Vdd (L3 = Vdd). In this case, the optional fifth NMOS transistor nT5 and the optional fifth PMOS transistor pT5 can be omitted from the driver circuit 1 as in the case of the driver circuit of Figure 3 .

[0136] The term "on state" can be used as a synonym for the term "conductive state" and the term "off state" can be used as a synonym for the term "non-conductive state".

[0137] As Figure 3As shown, until time tl, between times t2 and t3 and after time t4, the input voltage Vin corresponds to a low input level (Vin = low) and the control voltage Vc corresponds to ground GND (Vc = GND). Therefore, the voltage at the first node nl of the level shifter circuit 2 to which the control voltage Vc is applied is equal to ground GND and the voltage at the second node n2 of the level shifter circuit 2 to which the inverted control voltage Vc' is applied is equal to the positive supply voltage level Vdd. As a result, the first NMOS transistor nTl and the first PMOS transistor pTl of the level shifter circuit 2 are switched to a conductive state and the second NMOS transistor nT2 and the second PMOS transistor pT2 of the level shifter circuit 2 are switched to a non-conductive state. Therefore, the first voltage VI at the fourth node n4 corresponds to the positive supply voltage level Vdd (VI = Vdd) and the second voltage V2 at the sixth node n6 corresponds to ground GND (V2 = GND). For the first voltage distribution circuit 3a, the third PMOS transistor pT3 is switched to a non-conductive state and the third NMOS transistor nT3 and the optional sixth NMOS transistor nT6 are switched to a conductive state. Therefore, the third voltage V3 at the first output terminal OUT1 is equal to ground GND (V3 = GND). For the second voltage distribution circuit 3b, the fourth PMOS transistor pT4, the optional fifth NMOS transistor nT5, the optional fifth PMOS transistor pT5 and the optional sixth PMOS transistor pT6 are switched to a conductive state and the fourth NMOS transistor nT4 is switched to a non-conductive state. Therefore, the fourth voltage V4 at the second output terminal OUT2 is equal to a positive third level L3 (L3 < Vdd) smaller than the positive supply voltage level Vdd (V4 = L3). In case the optional fifth NMOS transistor nT5 and the optional fifth PMOS transistor pT5 are not part of the driver circuit 1, the positive voltage level L3 is equal to the positive supply voltage level Vdd (L3 = Vdd). The output voltage Vout being the difference (V4 - V3) between the third voltage V3 and the fourth voltage V4 is equal to the positive third level L3 as shown. Figure 3

[0138] As Figure 1 ​As shown, during the time period between times ti and t2 and the time period between times t3 and t4, the output voltage Vin corresponds to the high input level (Vin = high) and the control voltage Vc corresponds to the positive supply voltage level Vdd (Vc = Vdd). As a result, the voltage at the first node nl of the level shifter circuit 2 to which the control voltage Vc is applied is equal to the positive supply voltage level Vdd and the voltage at the second node n2 of the level shifter circuit 2 to which the inverted control voltage Vc’ is applied is equal to ground GND. As a consequence, the first NMOS transistor nTl and the first PMOS transistor pTl of the level shifter circuit 2 are switched to a non-conductive state and the second NMOS transistor nT2 and the second PMOS transistor pT2 of the level shifter circuit 2 are switched to a conductive state. As a result, the first voltage VI at the fourth node n4 corresponds to the positive first level LI (VI = LI = 2 · Vdd) and the second voltage V2 at the sixth node corresponds to the negative second level L2 (V2 = L2 = -Vdd, |L2| = Vdd). For the first voltage distribution circuit 3a, the third PMOS transistor pT3 is switched to a conductive state and the third NMOS transistor nT3 and the optional sixth NMOS transistor nT6 are switched to a non-conductive state. As a result, the third voltage V3 at the first output terminal OUT1 is equal to the positive first level (V3 = LI). For the second voltage distribution circuit 3b, the fourth PMOS transistor pT4, the optional fifth NMOS transistor nT5, the optional fifth PMOS transistor pT5 and the optional sixth PMOS transistor pT6 are switched to a non-conductive state and the fourth NMOS transistor nT4 is switched to a conductive state. As a result, the fourth voltage V4 at the second output terminal OUT2 is equal to the negative second level L2 (V4 = L2). The output voltage Vout being the difference between the third voltage V3 and the fourth voltage V4 (the third voltage V3 is subtracted from the fourth voltage V4) is equal to the negative fourth level L4 as shown. The absolute value of the negative fourth level L4 is equal to the sum of the absolute values of the positive first level LI and the negative second level L2 (|L4| = LI + |L2| or L4 = L2 - LI). Thus, in the case of the embodiment of Figure 3 Figure 3 and 2 the absolute value of the negative fourth level L4 is equal to three times the positive supply voltage level Vdd (|V4| = 3 · Vdd).

[0139] ​In view of the above, the driver circuit 1, in particular the level shifter circuit 2 and the voltage distribution circuit 3, is configured to convert an input voltage Vin, which can be switched between ground GND and a positive supply voltage level Vdd, into an output voltage Vout, which is switched between a negative fourth level L4 and a positive third level L3. Thereby, the driver circuit 1 is configured to increase a voltage swing of the input voltage Vin, which is at maximum the positive supply voltage level Vdd, to a larger voltage swing of the output voltage Vout, which can be four times (4 · Vdd) the positive supply voltage level Vdd. This is the case when the first level LI is equal to twice the positive supply voltage level Vdd (LI = 2 · VDD), the absolute value of the negative second level L2 is equal to Vdd of the positive supply voltage level (|L2| = VDD) and the positive third level L3 is equal to the positive supply voltage level Vdd (L3 = VDD).

[0140] As shown in Figure 1 , the levels of the output voltage Vout are inverted with respect to the levels of the input voltage. That is, the low level of the two levels of the input voltage Vin (low input level "low") is transformed into the high level of the two levels of the output voltage Vout (positive third level L3). The high level of the two levels of the input voltage Vin (high input level "high") is transformed into the low level of the two levels of the output voltage Vout (negative fourth level L4).

[0141] As an alternative to the voltage curves shown in Figure 3 , the driver circuit can also be configured to generate a control voltage Vc (not shown in Figure 3 and 2 ) which is inverted with respect to the input voltage Vin. That is, in case the input voltage Vin is equal to the low input level (Vin = low), the control voltage Vc can be equal to the positive supply voltage level Vdd (Vc = Vdd) and in case the input voltage Vin is equal to the high input level (Vin = high), the control voltage Vc can be equal to ground GND (Vc = GND). As a result, the voltage curves of the control voltage Vc, the first voltage VI, the second voltage V2, the third voltage V3, the fourth voltage V4 and the output voltage Vout will be inverted with respect to the voltage curves shown in Figure 4A and Figure 4AThe curve corresponding to the voltage curve of the input voltage Vin shown is inverted. That is, in the case where the first voltage VI equals the positive first level LI (VI = LI), when the input voltage Vin equals the low input level (Vin = low) and thereby the control voltage Vc equals the positive supply voltage level Vdd (Vc = Vdd), the second voltage V2 equals the negative second level L2 (V2 = L2), the third voltage V3 equals the positive first level LI (V3 = LI), the fourth voltage V4 equals the negative second level L2 (V4 = L2) and the output voltage Vout equals the negative fourth level L4 (Vout = L4). Thus, in this case, when the input voltage Vin equals the high input level (Vin = high) and thereby the control voltage Vc equals ground GND (Vc = GND), the first voltage VI equals the positive supply voltage level (VI = Vdd), the second voltage V2 equals ground GND (V2 = GND), the third voltage V3 equals ground GND (V3 = GND), the fourth voltage V4 equals the positive third level L3 (V4 = L3) and the output voltage Vout equals the positive third level L3 (Vout = L3).

[0142] Figure 1 and 4B Each shows a driver circuit according to an embodiment of the application.

[0143] Figure 1 The driver circuit 1 of Figure 4A The driver circuit 1 of Figure 3 The above description of the driver circuit 1 of Figure 4A The above description of the driver circuit 1 of Figure 1 The above description of the driver circuit 1 of Figure 4A The above description of the driver circuit 1 of Figure 4A and 4A The above description of the driver circuit 1 of

[0144] As shown in Figure 4A The driver circuit 1 comprises, in addition to the inverter INV1, an additional inverter connected between the input IN and the level shifter circuit 2. That is, the driver circuit 1 comprises a plurality of inverters connected between the input IN and the level shifter circuit 2. In particular, two inverters are connected between the input IN and the first node nl of the level shifter circuit 2 for providing the control voltage Vc to the first node nl. Three inverters are connected between the input IN and the second node n2 of the level shifter circuit 2 for providing the inverted control voltage Vc' to the second node n2. Figure 4AThe number of inverters shown, i.e. four inverters, is merely exemplary and can be greater than four, as long as the control voltage Vc is provided to the first node nl and the inverted control voltage Vc' is provided to the second node n2.

[0145] The plurality of inverters is configured to provide the control voltage Vc to the first node nl and the inverted control voltage Vc' to the second node n2 of the level shifter circuit 2 based on the input voltage Vin. In particular, the inverters connected between the input IN and the first node nl are configured to transform a low input level of the input voltage Vin into ground GND and a high input level of the input voltage Vin into the positive supply voltage level Vdd for generating the control voltage Vc at the first node nl. To achieve this, an even number of inverters is connected between the input IN and the first node nl as shown in Figure 4A The inverters connected between the input IN and the second node n2 are configured to transform a low input level of the input voltage Vin into the positive supply voltage level Vdd and a high input level into ground GND for generating the inverted control voltage Vc' at the second node n2. To achieve this, an odd number of inverters is connected between the input IN and the first node nl as shown in Figure 4A .

[0146] Alternatively, the inverters connected between the input IN and the first node nl can be configured to transform a high input level of the input voltage Vin into ground GND and a low input level of the input voltage Vin into the positive supply voltage level Vdd for generating the control voltage Vc at the first node nl (not shown in Figure 4A ). To achieve this, an odd number of inverters can be connected between the input IN and the first node nl (not shown in Figure 4A ). The inverters connected between the input IN and the second node n2 can be configured to transform a high input level of the input voltage Vin into the positive supply voltage level Vdd and a low input level into ground GND for generating the inverted control voltage Vc' at the second node n2 (not shown in Figure 4A ). To achieve this, an even number of inverters can be connected between the input IN and the second node n2 (not shown in Figure 4B ).

[0147] Figure 4AEmbodiments are shown in which a high input level of the input voltage Vin is less than the positive supply voltage level Vdd. In this case, the flying capacitor can be used to generate a control voltage Vc varying between ground GND and the positive supply voltage level Vdd based on the input voltage Vin. In other words, the input voltage Vin can be buffered by the inverter chain to achieve a voltage swing (with a sudden transition) of the control voltage Vc between ground GND and the positive supply voltage level Vdd.

[0148] Figure 4A The driver circuit 1 of Figure 4B corresponds to the driver circuit 1 of Figure 4B and 4B The difference between the circuit of Figure 2 is that the driver circuit 1 of Figure 4A does not comprise the optional fifth NMOS transistor nT5 and the optional PMOS transistor pT5. For this difference, Figure 2 the driver circuit 1 of Figure 4B corresponds to the driver circuit 1 of Figure 5A . Thus, the above description of the driver circuit 1 of Figure 5A and the above description of the driver circuit 1 of are correspondingly valid for the driver circuit 1 of

[0149] . Figure 1 5B Each of the figures shows a system according to an embodiment of the application.

[0150] Figure 1 A system 6 is shown which comprises the driver circuit 1 according to the first aspect or any of its implementation forms and the voltage-controlled electro-optical modulator 5. The above description of the driver circuit 1 of the first aspect and any of its implementation forms is valid for the system 6, in particular for the driver circuit 1 of the system 6. The above description of the system of the second aspect or any of its implementation forms is correspondingly valid for the system 6.

[0151] The driver circuit 1 can be any of the driver circuits according to Figure 5A , 2 , 3, 4A and 4B. Thereby, the above description with reference to Figure 5A , 2 , 3, 4A and 4B is correspondingly valid for the system 6, in particular for the driver circuit 1 of the system 6.

[0152] As Figure 5AAs shown, the electro-optical modulator 5 is connected to the output of the driver circuit 1, in particular to the output terminals OUT1 and OUT2. The driver circuit 1 is configured to drive the electro-optical modulator 5 by providing an output voltage Vout at the output in dependence on an input voltage Vin that can be input to an input IN of the driver circuit 1. As a result, the electro-optical modulator 5 is configured to modulate light, such as laser light, in dependence on the input voltage. The input voltage Vin can be a digital data signal, advantageously it can be a binary digital signal. Thus, the driver circuit 1 is configured to drive the voltage-controlled electro-optical modulator 5 so that the electro-optical modulator 5 transforms an electrical data signal Vin into an optical signal by modulating light, such as laser light.

[0153] The system 6 can also be referred to as a transmitter that is configured to optically transmit information that is input to the transmitter, in particular to the input IN of the driver circuit 1, as an electrical digital data signal Vin.

[0154] Advantageously, the system 6 can comprise a light source (not shown in Figure 5B ) configured to provide light to the electro-optical modulator 5 for the electro-optical modulator 5 to modulate, such as a laser.

[0155] As indicated in ​ , the voltage-controlled electro-optical modulator 5 can correspond to a voltage-controlled electro-optical modulator that behaves electrically like a diode, such as a ring modulator (RM). An example of such a modulator is an electro-optical modulator with a silicon p-n, III-V p-n or hybrid p-n depletion diode. In this case, the output voltage Vout corresponds to an anode-cathode voltage (VAK) and thus the third voltage V3 at the first output terminal OUT1 corresponds to a cathode voltage and the fourth voltage V4 at the second output terminal OUT2 corresponds to an anode voltage. As already described in the above, the voltage-controlled electro-optical modulator that behaves electrically like a diode is operated in reverse bias for modulating light, such as laser light. Thus, in this case, the driver circuit 1 is configured to provide the output voltage Vout so that a positive level of the output voltage Vout, i.e. the positive third level, is limited to below a positive forward voltage level for forward biasing the electro-optical modulator 5.

[0156] Alternatively, the voltage-controlled electro-optical modulator 5 can behave electrically like a capacitor. This case is indicated in ​ . An example of such a modulator is an electro-optical modulator based on a metal-oxide-semiconductor capacitor (MOSCAP electro-optical modulator) or an electro-optical modulator based on a semiconductor-insulator-semiconductor capacitor (SISCAP electro-optical modulator).

Claims

1. A driver circuit (1) for driving a voltage-controlled electro-optical modulator (5) by providing an output voltage (Vout) to the electro-optical modulator (5) in dependence on an input voltage (Vin), wherein the driver circuit (1) comprises: a supply input (SP) for receiving a direct supply voltage (VDD) having a positive supply voltage level (Vdd), an input (IN) for receiving the input voltage (Vin), wherein the input voltage (Vin) varies between a low input level and a high input level, a level shifter circuit (2) comprising two capacitors and being electrically connected to the input (IN), and a voltage distribution circuit (3) electrically connected between the level shifter circuit (2) and an output of the driver circuit (1) for providing the output voltage (Vout); the level shifter circuit (2) is configured to: generate, based on the input voltage (Vin) and using a first capacitor (CI) of the two capacitors, a first voltage (VI) varying between the positive supply voltage level (Vdd) and a positive first level (LI) being greater than the positive supply voltage level (Vdd), and generate, based on the input voltage (Vin) and using a second capacitor (C2) of the two capacitors, a second voltage (V2) varying between ground (GND) and a negative second level (L2); and the voltage distribution circuit (3) is configured to distribute the first voltage (VI) and the second voltage (V2) to the output such that the output voltage (Vout) can vary between a positive third level (L3) being equal to or less than the positive supply voltage level (Vdd) and a negative fourth level (L4), wherein an absolute value of the negative fourth level (L4) is greater than an absolute value of the positive first level (LI), the driver circuit (1) is configured to be powered only by the direct supply voltage (VDD) for converting an input voltage (Vin) into an output voltage (Vout) without requiring additional power supplies of additional supply voltages other than the direct supply voltage (VDD).

2. The driver circuit (1) of claim 1, wherein the positive first level (LI) is equal to or less than twice the positive supply voltage level (Vdd); an absolute value of the negative second level (L2) is equal to or less than the positive supply voltage level (Vdd); and / or an absolute value of the negative fourth level (L4) is equal to or less than three times the positive supply voltage level (Vdd).

3. The driver circuit (1) of claim 1, wherein the level shifter circuit (2) comprises a level up shifter circuit (2a) and a level down shifter circuit (2b) electrically connected to each other at two nodes; the level up shifter circuit (2a) comprises the first capacitor (CI) of the level shifter circuit (2) and is configured to provide the first voltage (VI) to the voltage distribution circuit (3); and the level down shifter circuit (2b) comprises the second capacitor (C2) of the level shifter circuit (2) and is configured to provide the second voltage (V2) to the voltage distribution circuit (3). ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The level down-converter circuit (2b) comprises the second capacitor (C2) of the level converter circuit (2) and is configured to provide the second voltage (V2) to the voltage distribution circuit (3).

4. The driver circuit (1) of claim 3, wherein the driver circuit (1) is configured to provide a control voltage (Vc) to a first one (nl) of the two nodes of the level converter circuit (2) and an inverted control voltage (Vc’) to a second one (n2) of the two nodes of the level converter circuit (2) on the basis of the input voltage (Vin), wherein the control voltage (Vc) varies between ground (GND) and the positive supply voltage level (Vdd); the first capacitor (Cl) is connected on one side to the supply input (SP) and on the other side to the first node (nl) via a first n-channel metal-oxide-semiconductor field-effect transistor (nTl), i.e. first NMOS transistor, of the level up-converter circuit (2a), wherein a gate terminal of the first NMOS transistor (nTl) is controllable by the second node (n2); the second capacitor (C2) is connected on one side to ground (GND) and on the other side to the second node (n2) via a first p-channel metal-oxide-semiconductor field-effect transistor (pTl), i.e. first PMOS transistor, of the level down-converter circuit (2b), wherein a gate terminal of the first PMOS transistor (pTl) is controllable by the first node (nl).

5. The driver circuit (1) of claim 4, wherein the level up-converter circuit (2a) comprises a third capacitor (C3) connected between the second node (n2) and the gate terminal of the first NMOS transistor (nTl), wherein a third node (n3) between the third capacitor (C3) and the gate terminal of the first NMOS transistor (nTl) is connected to the supply input (SP) via a second NMOS transistor (nT2) of the level up-converter circuit (2a), and a gate terminal of the second NMOS transistor (nT2) is connected to a fourth node (n4) between the first NMOS transistor (nTl) and the first capacitor (Cl); and / or the level down-converter circuit (2b) comprises a fourth capacitor (C4) connected between the first node (nl) and the gate terminal of the first PMOS transistor (pTl), wherein a fifth node (n5) between the fourth capacitor (C4) and the gate terminal of the first PMOS transistor (pTl) is connected to ground (GND) via a second PMOS transistor (pT2) of the level down-converter circuit (2b), and a gate terminal of the second PMOS transistor (pT2) is connected to a sixth node (n6) between the first PMOS transistor (pTl) and the second capacitor (C2).

6. The driver circuit (1) of claim 5, wherein the voltage distribution circuit (3) is connected to: the fourth node (n4) of the level shifter circuit (2) between the first NMOS transistor (nTl) and the first capacitor (Cl), wherein the level up shifter circuit (2a) at the fourth node (n4) is configured to provide the first voltage (VI) to the voltage distribution circuit (3), and the sixth node (n6) of the level shifter circuit between the first PMOS transistor (pTl) and the second capacitor (C2), wherein the level down shifter circuit (2b) at the sixth node (n6) is configured to provide the second voltage (V2) to the voltage distribution circuit (3).

7. The driver circuit (1) of claim 4, wherein the output comprises a first output terminal (OUT1) for providing a third voltage (V3) to the electro-optical modulator (5) and a second output terminal (OUT2) for providing a fourth voltage (V4) to the electro-optical modulator (5); the voltage distribution circuit (3) comprises a first voltage distribution circuit (3a) and a second voltage distribution circuit (3b); the first voltage distribution circuit (3a) is configured to distribute the first voltage (VI) such that the third voltage (V3) at the first output terminal (OUT1) can vary between ground (GND) and the positive first level (LI); and the second voltage distribution circuit (3b) is configured to distribute the second voltage (V2) such that the fourth voltage (V4) at the second output terminal (OUT2) can vary between the negative second level (L2) and the positive third level (L3).

8. The driver circuit (1) of claim 7, wherein the first voltage distribution circuit (3a) comprises a third PMOS transistor (pT3) and a third NMOS transistor (nT3); the third PMOS transistor (pT3) is configured to provide the first voltage (VI) to the first output terminal (OUT1) in case the level of the first voltage (VI) corresponds to the positive first level (LI); and the third NMOS transistor (nT3) is configured to provide a conductive path between the first output terminal (OUT1) and ground (GND) in case the level of the first voltage (VI) corresponds to the positive supply voltage level (Vdd).

9. The driver circuit (1) of claim 8, wherein the first output terminal (OUT1) is connected to a drain terminal of the third PMOS transistor (pT3) and to a drain terminal of the third NMOS transistor (nT3); a gate terminal of the third PMOS transistor (pT3) is connected to the supply input (SP); and a gate terminal of the third NMOS transistor (nT3) is connected to ground (GND). The level shifter circuit (2) is configured to control the gate terminal of the third NMOS transistor (nT3) in dependence of the input voltage (Vin), in particular the inverted control voltage (Vc’).

10. The driver circuit (1) of claim 7, wherein The second voltage distribution circuit (3b) comprises a fourth NMOS transistor (nT4) and a fourth PMOS transistor (pT4); The fourth NMOS transistor (nT4) is configured to provide the second voltage (V2) to the second output terminal (OUT2) in case the level of the second voltage (V2) corresponds to the negative second level (L2); and The fourth PMOS transistor (pT4) is configured to provide a conductive path between the second output terminal (OUT2) and the supply input (SP) in case the level of the second voltage (V2) corresponds to ground (GND).

11. The driver circuit (1) of claim 10, wherein the gate terminal of the fourth NMOS transistor (nT4) is connected to ground (GND); and The level shifter circuit (2) is configured to control the gate terminal of the fourth PMOS transistor (pT4) in dependence of the input voltage (Vin), in particular the control voltage (Vc), and wherein The second output terminal (OUT2) is connected to the drain terminal of the fourth NMOS transistor (nt4) and the drain terminal of the fourth PMOS transistor (pT4), or The second output terminal (OUT2) is connected to the drain terminal of the fourth NMOS transistor (nT4), to the source terminal of a fifth PMOS transistor (pT5) of the second voltage distribution circuit (3b), and to the drain terminal of the fourth PMOS transistor (pT4) via a fifth NMOS transistor (nT5) of the second voltage distribution circuit (3b), wherein the drain terminal and the gate terminal of the fifth PMOS transistor (pT5) are connected to ground (GND).

12. The driver circuit (1) of claim 11, wherein The fifth NMOS transistor (nT5) and the fifth PMOS transistor (pT5) are configured to limit the positive third level of the fourth voltage (V4) at the second output terminal (OUT2) below a positive forward voltage level for forward biasing the electro-optical modulator (5) in case the electro-optical modulator (5) behaves electrically like a diode.

13. The driver circuit (1) of claim 11, wherein The first voltage distribution circuit (3a) comprises a third NMOS transistor (nT3) and a sixth NMOS transistor (nT6), the third NMOS transistor (nT3) being configured to provide a conductive path between the first output terminal (OUT1) and ground (GND) in case the level of the first voltage (V1) corresponds to the positive supply voltage level (Vdd), a drain terminal of the third NMOS transistor (nT3) is connected to the first output terminal (OUT1) via the sixth NMOS transistor (nT6), and a gate terminal of the sixth NMOS transistor (nT6) is connected to the supply input (SP); and / or wherein the second voltage distribution circuit (3b) comprises a sixth PMOS transistor (pT6), a drain terminal of the fourth PMOS transistor (pT4) is connected to the second output terminal (OUT2) via the sixth PMOS transistor (pT6), optionally via the sixth PMOS transistor (pT6) and the fifth NMOS transistor (nT5), and a gate terminal of the sixth PMOS transistor (pT6) is connected to ground (GND).

14. The driver circuit (1) of claim 10, wherein the first voltage distribution circuit (3a) comprises a third PMOS transistor (pT3) configured to provide the first voltage (V1) to the first output terminal (OUT1) in case a level of the first voltage (V1) corresponds to the positive first level (L1), a body terminal of the third PMOS transistor (pT3) being connected to a source terminal of the third PMOS transistor (pT3); and / or a body terminal of the fourth NMOS transistor (nT4) of the second voltage distribution circuit (3b) is connected to a source terminal of the fourth NMOS transistor (nT4).

15. A system (6) comprising: a driver circuit (1) according to any one of the preceding claims; and a voltage-controlled electro-optical modulator (5), and the electro-optical modulator (5) is electrically connected to the output of the driver circuit (1), and the driver circuit (1) is configured to drive the electro-optical modulator (5) by providing the output voltage (Vout) to the electro-optical modulator (5) in dependence on the input voltage (Vin).

16. The system (6) of claim 15, wherein the driver circuit (1) is configured to provide the output voltage (Vout) to the electro-optical modulator (5) in dependence on the input voltage (Vin) by providing a first voltage (V1) to the first output terminal (OUT1) in dependence on the input voltage (Vin) and by providing a second voltage (V2) to the second output terminal (OUT2) in dependence on the input voltage (Vin).

17. The system (6) of claim 15 or 16, wherein the driver circuit (1) is configured to provide the output voltage (Vout) to the electro-optical modulator (5) in dependence on the input voltage (Vin) by providing a first voltage (V1) to the first output terminal (OUT1) in dependence on the input voltage (Vin) and by providing a second voltage (V2) to the second output terminal (OUT2) in dependence on the input voltage (Vin) and by providing a third voltage (V3) to the third output terminal (OUT3) in dependence on the input voltage (Vin).

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