Memory system and power supply circuit

Abstract

An embodiment provides a memory system and a power supply circuit capable of preventing malfunction of a PLP function. According to the embodiment, the memory system includes a first terminal, a nonvolatile memory, a capacitor having a second terminal, and a power supply circuit. The power supply circuit generates at least one second voltage using a first voltage applied to the first terminal, supplies at least one second voltage to the nonvolatile memory, generates a third voltage using the first voltage, and applies the third voltage to the second terminal, thereby charging electrical energy into the capacitor. The power supply circuit is configured such that, when the voltage corresponding to the first terminal falls below a first threshold voltage, a fourth voltage based on the energy of the capacitor is supplied to the first terminal without stopping the charging of the capacitor, and when the voltage corresponding to the second terminal falls below a second threshold voltage, the charging of the capacitor is stopped, and a fifth voltage based on the energy of the capacitor is supplied to the first terminal.

Description

[0001] [Related Applications]

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-157520 (filing date: September 18, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a memory system and a power supply circuit. Background Art

[0004] Memory systems including nonvolatile memories have become widely used. As an example of such memory systems, a solid-state drive (SSD) including flash memory is known.

[0005] Some SSDs have a power loss protection (PLP) feature that prevents data from being lost in the event of an unexpected power outage. PLP uses the energy (hereafter referred to as "energy") in a capacitor, which serves as a backup power source, to write data to the flash memory when the power supply voltage drops due to a power outage, preventing data from being lost mid-write.

[0006] Sometimes, peak currents are generated in the SSD. This peak current can cause the power supply voltage to drop, triggering the PLP function. In this case, the power supply itself is normal, and the PLP function is not normally active. Activating the PLP function under these circumstances is called a malfunction of the PLP function. If the PLP function malfunctions, unnecessary processing may occur within the SSD. Summary of the Invention

[0007] The present invention provides a memory system and a power supply circuit capable of preventing malfunction of a PLP function.

[0008] According to an embodiment, a memory system includes a first terminal, a nonvolatile memory, a capacitor having a second terminal, and a power supply circuit. The power supply circuit generates at least one second voltage using a first voltage applied to the first terminal, supplies the at least one second voltage to the nonvolatile memory, generates a third voltage using the first voltage, and applies the third voltage to the second terminal, thereby charging electrical energy into the capacitor. The power supply circuit is configured such that, when the voltage corresponding to the first terminal falls below a first threshold voltage, a fourth voltage based on the energy of the capacitor is supplied to the first terminal without stopping charging of the capacitor, and when the voltage corresponding to the second terminal falls below a second threshold voltage, charging of the capacitor is stopped, and a fifth voltage based on the energy of the capacitor is supplied to the first terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment.

[0010] Figure 2 This is a circuit diagram showing an example of the configuration of a power supply circuit according to the embodiment.

[0011] Figure 3 This is a flowchart showing an example of the operation of the power supply circuit according to the embodiment.

[0012] Figure 4 (a) to (e) are timing charts showing an example of the operation of the power supply circuit according to the embodiment. DETAILED DESCRIPTION

[0013] The following description will be made with reference to the accompanying drawings. The following description will illustrate an apparatus or method for embodying the technical concept of the embodiment. The technical concept of the embodiment is not limited to the structure, shape, configuration, material, etc. of the constituent elements described below. Changes that can be easily conceived by the industry are of course included in the scope of disclosure. In order to make the description clearer, there are also cases where the size, thickness, plane dimensions or shape of each element are changed relative to the actual implementation form and schematically represented in the drawings. There are also cases where multiple drawings contain elements with different dimensional relationships or ratios. There are also cases where the same reference numerals are added to corresponding elements in multiple drawings and repeated descriptions are omitted. There are cases where multiple names are added to several elements, but the examples of these names are only for illustration and do not deny the addition of other names to these elements. In addition, for elements that do not have multiple names, the addition of other names is not denied. In addition, in the following description, "connected" refers not only to direct connection, but also to the case of connection via other elements.

[0014] Hereinafter, this embodiment will be described in detail with reference to the drawings.

[0015] (System Configuration)

[0016] Figure 1This is a block diagram showing an example of the configuration of an information processing system including a memory system of an embodiment. A memory system is a semiconductor storage device configured to write data to a non-volatile memory and read data from the non-volatile memory. An example of a memory system is an SSD. Examples of non-volatile memories are NAND (Not AND) type flash memory, NOR (NOT OR) type flash memory, MRAM (Magneto-resistive Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistive Random Access Memory) and FeRAM (Ferroelectric Random Access Memory). In the present application, an example of a non-volatile memory is a NAND type flash memory (hereinafter referred to as a flash memory).

[0017] Information processing system 10 includes a host device (hereinafter referred to as a host) 12 and an SSD 14. Host 12 is an information processing device that accesses SSD 14. Host 12 can be a server (storage server). Host 12 can also be a personal computer. SSD 14 can be an SSD suitable for commercial use, such as those installed in a server in a data center, or it can be an SSD suitable for personal use, such as those installed in a personal computer.

[0018] The SSD 14 may be used as a main memory of the host 12. The SSD 14 may also be built into the host 12. The SSD 14 may also be provided outside the host 12 and connected to the host 12 via a cable or a network.

[0019] The SSD 14 includes a flash memory 16 , a controller 18 , a DRAM (Dynamic Random Access Memory) 20 , a power supply circuit 22 , and the like.

[0020] The controller 18 functions as a memory controller configured to control the flash memory 16. The controller 18 can be configured by a circuit such as a SoC (system on a chip).

[0021] The controller 18 writes data to or reads data from the flash memory 16 based on commands from the host 12. Furthermore, the controller 18 generates a control signal for controlling the value of the voltage generated by the power supply circuit 22 based on the commands from the host 12 and various information from the power supply circuit 22. The controller 18 transmits the generated control signal to the power supply circuit 22. Thus, the controller 18 controls the generation of multiple voltages applied to various devices of the SSD 14 (e.g., the flash memory 16, the controller 18, and the DRAM 20).

[0022] DRAM 20 is an example of volatile memory. For example, DRAM 20 is DDR3L (Double Data Rate 3 Low Voltage) compliant DRAM (Dynamic Random Access Memory). Alternatively, SRAM (Static Random Access Memory) can be used instead of DRAM 20 as volatile memory. DRAM 20 can also be provided within controller 18. A write buffer, a read buffer, a cache area for a lookup table (LUT), and a storage area for system management information can also be provided within DRAM 20.

[0023] The write buffer is a buffer used to temporarily store data supplied from the host 12 and to be written to the flash memory 16 until the writing is complete. In other words, the write buffer stores data that is being written. Since the DRAM 20 is a volatile memory, this data that is being written is lost when the power to the SSD 14 is turned off.

[0024] The read buffer is a buffer area for temporarily storing data read from the flash memory 16 .

[0025] The LUT cache area is an area for caching the LUT. The LUT is a correspondence table between logical addresses specified by the host 12 and physical addresses of the flash memory 16. The LUT is also called an address translation table or a logical address / physical address translation table.

[0026] The system management information is various information and various tables used in the operation of the SSD 14 .

[0027] The flash memory 16 may also include multiple flash memory chips (also called flash memory dies). The flash memory 16 may also include a memory cell array including multiple memory cells arranged in a matrix. The flash memory 16 may have a two-dimensional structure or a three-dimensional structure.

[0028] The memory cell array included in the flash memory 16 includes multiple blocks. Each block includes multiple pages. A block functions as the minimum unit for data erasing. Each page includes multiple memory cells connected to the same word line. A page functions as the unit for data writing and data reading. The write buffer or the read buffer has storage capacity for one page of data. When writing data, the data of one page of write units read from the write buffer is written to the flash memory 16. When reading data, the data of one page of read units read from the flash memory 16 is written to the read buffer. Alternatively, a word line can be used as the unit for data writing or data reading instead of a page. In this case, the data of one word line is the data of the write unit or the data of the read unit.

[0029] The power supply circuit 22 utilizes the power supply of an external device (e.g., host 12) connected to the SSD 14. A first voltage output from the power supply of the host 12 is applied to the power supply circuit 22 via a connector not shown. The power supply circuit 22 (more specifically, the LDO (Low-Dropout) regulator 56 and the DC (Direct Current) / DC converter 58 in the power supply circuit 22) uses the first voltage to generate a plurality of second voltages required by each device of the SSD 14, and applies the plurality of second voltages to each device of the SSD 14. In order to realize the PLP function, the power supply circuit 22 has a capacitor (also called a PLP capacitor) as a backup power supply. For details, please refer to Figure 2 Provide explanation.

[0030] The controller 18 includes a CPU (Central Processing Unit) 32 , a host interface (host I / F) 34 , a NAND interface (NAND I / F) 36 , a DRAM interface (DRAM I / F) 38 , and the like.

[0031] The CPU 32, the host I / F 34, the NAND I / F 36, and the DRAM I / F 38 are connected to the bus line 42. The CPU 32 executes the firmware stored in the flash memory 16 to realize various functions.

[0032] The host 12 is electrically connected to the host I / F 34 , the flash memory 16 is electrically connected to the NAND I / F 36 , and the DRAM 20 is electrically connected to the DRAM I / F 38 .

[0033] The host I / F 34 is based on standards such as SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), ATA (AT Attachment (Advanced Technology Attachment)), SATA (Serial ATA), PCIe (PCI Express (Peripheral Component Interconnect Express)) (registered trademark), Ethernet (registered trademark), Fibre Channel, NVMe (NVM Express (Non-Volatile Memory Express)) (registered trademark), USB (Universal Serial Bus) (registered trademark), and UART (Universal Asynchronous Receiver / Transmitter) (registered trademark).

[0034] The NAND I / F 36 complies with standards such as Toggle DDR (Double Data Rate) and ONFI (OpenNAND Flash Interface). The NAND I / F 36 controls the flash memory 16. The NAND I / F 36 can also be connected to multiple flash memory chips within the flash memory 16 via multiple channels.

[0035] (Configuration Example of Power Supply Circuit 22)

[0036] Figure 2 This is a circuit diagram showing an example of the configuration of the power supply circuit 22. The power supply circuit 22 may also be composed of a single or multiple integrated circuits (ICs). An integrated circuit is also called a PMIC (power management IC). For ease of explanation, the numerical values ​​of the voltages are recorded, but these numerical values ​​are examples and can be changed arbitrarily. In addition, the number of the second voltages generated is also an example and can be changed arbitrarily. The first voltage output by the host 12 is, for example, DC5 V (or DC3.3 V). In the following description, the expression DC is omitted. The host 12 is not limited to outputting a single first voltage, but may also output multiple first voltages.

[0037] If the first voltage (5V) output from the host 12 is applied to the input terminal 51 of the power supply circuit 22, then the current corresponding to the input voltage is supplied to the LDO (Low Dropout) regulator 56 and the DC / DC converter 58 through the fuse 52, the load switch 54 and the MOSFET (metal-oxide-semiconductor field-effect transistor) (called MOS transistor) 82 in series.

[0038] Fuse 52 is a metal fuse. Fuse 52 melts when an overcurrent exceeding a predetermined current flows through it. When fuse 52 melts, input current does not flow to load switch 54 unless fuse 52 is replaced. Fuse 52 is not limited to a metal fuse; an electronic fuse that opens upon detecting an overcurrent may also be used.

[0039] The load switch 54 is a switch that switches between an on state and an off state by the control logic 60. In the initial state, the control logic 60 turns the load switch 54 to the on state. In the on state, the load switch 54 outputs a voltage obtained by subtracting the differential voltage from the input voltage. For ease of explanation, the differential voltage is set to 0V here, and in the on state, the output voltage of the load switch 54 is 5V. When the voltage of the second monitoring terminal 74 becomes lower than the second threshold voltage (the explanation will be described below), the control logic 60 turns the load switch 54 to the off state. In the off state, the output voltage of the load switch 54 is 0V. The output terminal 72 of the load switch 54 is a terminal for monitoring the first voltage supplied from the host 12. Hereinafter, the output terminal 72 is also referred to as the first monitoring terminal 72. The first monitoring terminal 72 is connected to the control logic 60.

[0040] The control logic 60 is powered via a terminal (not shown) different from the input terminal 51. Therefore, the control logic 60 operates even when the first voltage is not applied to the input terminal 51. The host 12 may also supply voltage to the control logic 60 via a terminal (not shown) different from the input terminal 51.

[0041] The gate terminal of the MOS transistor 82 is connected to the control logic 60. Figure 2 In FIG. 8 , the MOS transistor 82 is shown as an n-channel transistor, but a p-channel transistor may also be used.

[0042] The control logic 60 changes the on state (conductive state) / off state (non-conductive state) of the MOS transistor 82 according to changes in the voltage of the first monitoring terminal 72 or the second monitoring terminal 74 , which are output terminals of the load switch 54 .

[0043] The control logic 60 compares the voltage of the first monitoring terminal 72 with the startup threshold voltage. The startup threshold voltage is set to the voltage (5V) applied to the input terminal 51 by the host 12.

[0044] If the voltage at the first monitoring terminal 72 does not reach the startup threshold voltage, the control logic 60 turns off the MOS transistor 82 (non-conductive state). In this case, no voltage is applied to the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58. Therefore, the LDO regulator 56 and the DC / DC converter 58 do not generate the plurality of second voltages, and the SSD 14 does not operate.

[0045] When the voltage at the first monitoring terminal 72 reaches the activation threshold voltage, the control logic 60 turns on the MOS transistor 82 (conductive state). In this case, 5V is applied to the input terminals 73 of the LDO regulator 56 and the DC / DC converter 58. Consequently, the LDO regulator 56 and the DC / DC converter 58 generate multiple second voltages. The SSD 14 operates using these multiple second voltages.

[0046] The LDO regulator 56 is a circuit that outputs a voltage for devices requiring low current, such as the SSD 14. The DC / DC converter 58 is a circuit that outputs a voltage for devices requiring high current, such as the SSD 14. The LDO regulator 56 and the DC / DC converter 58 can be implemented as separate ICs or as a single IC.

[0047] The LDO regulator 56 steps down the voltage (5V) at the input terminal 73 to generate a plurality of second voltages, for example, two second voltages of 3.3V and 2.5V. Furthermore, when the host 12 supplies a 3.3V voltage to the input terminal 51 instead of 5V, the 3.3V input voltage may be directly output from the LDO regulator 56 as a 3.3V second voltage. The 3.3V and 2.5V voltages are supplied to the controller 18.

[0048] The DC / DC converter 58 steps down the voltage (5V) at the input terminal 73 to generate a plurality of voltages, for example, four second voltages of 2.8V, 1.8V, 1.35V, and 1V. For example, the voltages of 2.8V and 1.8V are supplied to the flash memory 16, the voltage of 1.35V is supplied to the DRAM 20, and the voltage of 1V is supplied to the controller 18.

[0049] The LDO regulator 56 and the DC / DC converter 58 may each generate a single second voltage. The power supply circuit 22 does not need to include both the LDO regulator 56 and the DC / DC converter 58, but may include only one. In this case, the power supply circuit 22 may also generate a single second voltage.

[0050] The LDO regulator 56 and the DC / DC converter 58 each include one or more switching elements. The on / off states of the switching elements of the LDO regulator 56 and the DC / DC converter 58 are controlled by the control logic 60. Based on the voltage at the input terminal 73, the control logic 60 adjusts the ratio of the on-state period to the off-state period (duty cycle) of each switching element of the LDO regulator 56 and the DC / DC converter 58, thereby changing the voltage step-down rate. This allows the LDO regulator 56 and the DC / DC converter 58 to consistently generate multiple second voltages of the specified voltage value, even if the voltage output from the host 12 fluctuates slightly.

[0051] When the host 12 receives a power-off instruction from the user, it sends a power-off notification to the SSD 14 before actually shutting off the power. In response to this notification, the controller 18 writes the data currently being written, stored in the DRAM 20, to the flash memory 16. When the writing is complete, the controller 18 sends a write completion report to the host 12. The host 12 waits for this completion report before shutting off the power. Therefore, the data currently being written is not lost.

[0052] However, if the host 12 is unexpectedly powered off due to a power outage, the host 12 cannot send a power outage notification to the SSD 14. In this case, the controller 18 cannot receive the notification and therefore cannot complete writing the data in progress to the flash memory 16.

[0053] To cope with this unexpected power outage, the power supply circuit 22 includes a PLP capacitor 80 as a backup power source. To detect a power outage, the power supply circuit 22 compares the voltage of the second monitoring terminal 74 (described below) with a second threshold voltage. When the power supply circuit 22 detects a power outage by detecting that the voltage of the second monitoring terminal 74 falls below the second threshold voltage, it uses the energy of the PLP capacitor 80 to supply voltage to each device in the SSD 14. This executes the PLP function, which writes data in progress to the flash memory 16.

[0054] The capacitance of the PLP capacitor 80 is set slightly higher than the target capacitance required to charge the electrical energy required to achieve the PLP function. This is because if the capacitance of the PLP capacitor 80 is pre-set with a margin, the PLP function can continue to be achieved even if the capacitance of the capacitor decreases slightly due to aging, thereby suppressing the failure rate of the SSD 14. For example, in order to ensure that the PLP function can be achieved even if the capacitance decreases, as long as the decrease is within 30% of the initial capacitance, the initial capacitance of the PLP capacitor 80 can be pre-set to approximately 1.43 times the target capacitance. As examples of the PLP capacitor 80, an electric double layer capacitor, a conductive polymer aluminum electrolytic capacitor, or a conductive polymer tantalum solid electrolytic capacitor can be used.

[0055] Input terminal 73 of LDO regulator 56 and DC / DC converter 58 is connected in series to reference voltage (ground voltage) terminal 88 via coil 84 and MOS transistor 92. Input terminal 73 is also connected in series to reference voltage (ground voltage) terminal 89 via coil 84, diode 86, and PLP capacitor 80. The anode terminal of diode 86 is connected to coil 84. The cathode terminal of diode 86 is connected to anode terminal 74 of PLP capacitor 80. The cathode terminal of PLP capacitor 80 is connected to reference voltage terminal 89.

[0056] The gate terminal of MOS transistor 92 is connected to control logic 60. The on / off state of MOS transistor 92 is controlled by control logic 60. As MOS transistor 92 repeatedly switches between the on and off states, coil 84 and diode 86 boost the voltage (5V) at input terminal 73 to a third voltage, for example, 28V. In other words, MOS transistor 92, coil 84, and diode 86 constitute a boost DC / DC converter. Alternatively, the boost DC / DC converter can be integrally formed with DC / DC converter 58. The output voltage of the boost DC / DC converter is variable. Here, the maximum output voltage is set to 28V.

[0057] Thus, the PLP capacitor 80 is charged with electric energy corresponding to the boosted voltage (28 V) of the boost DC / DC converter while the 5 V voltage is applied from the host computer 12 to the power supply circuit 22 .

[0058] The higher the charging voltage applied to the PLP capacitor 80, the more likely it is to short-circuit. Therefore, an upper limit is set on the charging voltage that can be applied to the PLP capacitor 80. Here, the maximum allowable voltage that can be applied to the PLP capacitor 80 is 28V.

[0059] The anode terminal 74 of the PLP capacitor 80 (or the cathode terminal of the diode 86) is also connected to the control logic 60. The anode terminal 74 of the PLP capacitor 80 can monitor the charging voltage of the PLP capacitor 80. The anode terminal 74 is also referred to as the second monitoring terminal 74.

[0060] Second monitoring terminal 74 is connected to the input terminal of step-down DC / DC converter 90. Step-down DC / DC converter 90 steps down the input voltage at a variable step-down rate corresponding to the input voltage, for example, to output a constant 5.3 V output. The output terminal of step-down DC / DC converter 90 is connected in series to input terminal 73 of LDO regulator 56 and DC / DC converter 58 via coil 94 and diode 96.

[0061] The anode terminal of the diode 96 is connected to the coil 94. The cathode terminal of the diode 96 is connected to the input terminal 73. The connection point between the coil 94 and the diode 96 (or the anode terminal of the diode 96) is connected to a reference voltage (ground voltage) terminal 99 via a capacitor 98.

[0062] The threshold voltage of diode 96 is, for example, 0.4 V. Therefore, when the voltage at input terminal 73 of LDO regulator 56 and DC / DC converter 58 (or the cathode terminal of diode 96 ) is 5 V, the anode terminal of diode 96 is 5.3 V, and thus diode 96 is in an off state.

[0063] The control logic 60 transmits information indicating various states of the power supply circuit 22 to the controller 18 according to a specified communication standard. The communication standard between the control logic 60 and the controller 18 may also be a serial communication standard, for example. An example of a serial communication standard is the I2C (Inter-Integrated Circuit) method. An I2C interface (I2C I / F) 64 is connected to the control logic 60. The I2C I / F 64 communicates with the controller 18 based on control signals from the control logic 60. Based on the control signals from the controller 18, the control logic 60 supplies control signals to the load switch 54, the LDO regulator 56, and the DC / DC converter 58.

[0064] (Operation Example of Power Supply Circuit 22)

[0065] Figure 3 This is a flowchart showing an example of the operation of the power supply circuit 22 . Figure 4 2 is a timing chart showing an example of the operation of the power supply circuit 22. Figure 3 、 Figure 4 , an example of the operation related to the peak current countermeasure based on the power supply circuit 22 and the PLP function when the power is cut off is described.

[0066] When voltage is supplied to the control logic 60 via a terminal (not shown), the control logic 60 begins operating. When the control logic 60 begins operating, it monitors the voltages of the first monitoring terminal 72, the second monitoring terminal 74, and the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58, and turns on the load switch 54.

[0067] Assume that when the operation starts, no 5V voltage is applied from the host 12 to the input terminal 51 of the power supply circuit 22. Figure 4 As shown in (a) and (d), the voltage of the first monitoring terminal 72 and the voltage of the second monitoring terminal 74 are both 0 V. Although not shown, the voltage of the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58 is also 0 V.

[0068] In addition, when the action starts, the control logic 60 is as follows Figure 4 As shown in (b) and (c) of FIG. , MOS transistor 82 and MOS transistor 92 are turned off. Although not shown, control logic 60 also stops the switching operation of LDO regulator 56 and DC / DC converter 58.

[0069] As a result, the LDO regulator 56 and the DC / DC converter 58 do not generate the plurality of second voltages, and the SSD 14 enters an operation-stopped state.

[0070] Since the voltage of the second monitoring terminal 74 is 0 V, the output voltage of the step-down DC / DC converter 90 is 0 V. The potential difference (0 V) between the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58 and the output terminal of the step-down DC / DC converter 90 is less than the threshold voltage (0.4 V) of the diode 96. Figure 4 As shown in (e), the diode 96 is in the off state.

[0071] The control logic 60 determines whether the voltage of the first monitoring terminal 72 is equal to or higher than the start threshold voltage ( Figure 3 The startup threshold voltage is set to the first voltage applied to the input terminal 51 by the host 12, for example, 5 V. If the determination result of step S102 is negative, the determination process of step S102 is repeated.

[0072] A first voltage of 5V is applied from the host 12 to the input terminal 51, and the voltage of the input terminal 51 is applied to the first monitoring terminal 72 via the fuse 52 and the load switch 54. Figure 4 As shown in (a), when the voltage of the first monitoring terminal 72 becomes 5V, Figure 3 The determination result of step S102 becomes yes.

[0073] If the determination result of step S102 is yes, the control logic 60 will proceed as follows: Figure 4 As shown in (b), the MOS transistor 82 is turned on, and the first voltage (5V) from the host 12 applied to the first monitoring terminal 72 is supplied to the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58 ( Figure 3 The control logic 60 further adjusts the ratio of the on-period to the off-period of the switching elements of the LDO regulator 56 and the DC / DC converter 58 according to the desired voltage and the voltage of the input terminal 73, thereby generating a plurality of specified second voltages ( Figure 3 As a result, the LDO regulator 56 and the DC / DC converter 58 supply the plurality of second voltages to the flash memory 16 , the controller 18 , and the DRAM 20 .

[0074] Control logic 60 such as Figure 4 As shown in (c), the state of the MOS transistor 92 is periodically changed to the on state and the off state, the first voltage (5V) from the host 12 applied to the first monitoring terminal 72 is boosted to the third voltage, and the electric energy (5V) is charged to the PLP capacitor 80 at the third voltage. Figure 3 The third voltage varies according to the ratio of the on-period to the off-period of the MOS transistor 92. Therefore, the control logic 60 adjusts the ratio of the on-period to the off-period of the MOS transistor 92 so that the third voltage becomes 28V.

[0075] Note that the processing of step S104 and the processing of step S106 may be performed in reverse order, or both processing may be performed simultaneously in the same step.

[0076] During step S104, the LDO regulator 56 and DC / DC converter 58 step down the 5V from the host 12 to generate the second voltage required for the operation of each device in the SSD 14, and then supply the second voltage to each device. During this time, the step-up DC / DC converter, which includes the coil 84, the diode 86, and the MOS transistor 92, steps up the 5V from the host 12 to the third voltage, charging the PLP capacitor 80 with energy. The amount of energy charged is (1 / 2)CV2. C is the capacitance of the PLP capacitor 80, and V is the third voltage (28V).

[0077] When SSD 14 performs certain operations, such as writing to flash memory 16, the current consumption of SSD 14 may increase momentarily. This current consumption is called peak current. The current capacity of the host 12 power supply is designed with a margin to handle the peak current of SSD 14, which serves as a power supply load. However, it cannot handle peak currents exceeding the expected level. If peak currents occur, the host 12 may shut down.

[0078] For example, assume that five SSDs 14 are connected to a host 12. The power consumption of each SSD 14 is 12W. The host 12 supplies 12V, 1A of power to each SSD 14. The power that the host 12 can supply is 100W. Since 100W is greater than 60W (=12W×5), as long as each SSD 14 consumes 12W of power, the host 12 can stably supply the rated voltage of 12V to each SSD 14. However, assume that a peak current of 2A is generated in each SSD 14. If the output voltage of the host 12 remains at the rated 12V, the total power consumption of the five SSDs 14, 120W (=2A×12V×5), exceeds the power that the host 12 can supply, 100W. Therefore, if the peak current is generated, the host 12 reduces the power supplied to each SSD 14 to, for example, 20W. As a result, the 24W of power required by each SSD 14 becomes insufficient. The PLP capacitor 80 of the embodiment uses the charging energy to supplement the power shortage of each SSD 14 (4 W=24 W−20 W).

[0079] In addition, in a data center, multiple SSDs 14 may be connected to a single server. There is a high probability that multiple SSDs 14 processing similar workloads will generate peak currents at the same time.

[0080] As described above, even if there is no abnormality in the power supply of the host computer 12 itself, the voltage supplied from the host computer 12 may drop due to the peak current.

[0081] When the voltage at the first monitoring terminal 72 falls below a certain threshold voltage (e.g., 4.8V), the conventional power supply circuit 22 turns off MOS transistors 82 and 92, stopping charging of the PLP capacitor 80. This discharges the energy in the PLP capacitor 80, and a voltage corresponding to this discharged energy is supplied to the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58. While the voltage based on the discharged energy is being supplied, the LDO regulator 56 and the DC / DC converter 58 generate the voltage (second voltage) required to drive the SSD 14. This PLP function allows the SSD 14 to write data in progress to the flash memory 16. However, in this case, the PLP function may malfunction. Increasing the difference between the voltage supplied from the host 12 and the threshold voltage can prevent malfunction of the PLP function, but sometimes it is difficult to design this difference to be large. For example, in some SSDs 14, the difference between the voltage supplied from the host 12 and the second voltage supplied to each device in the SSD 14 is small. In this case, the threshold voltage must be designed to be close to the voltage supplied from the host 12 .

[0082] According to the embodiment, when a peak current is generated, the discharge energy of the PLP capacitor 80 is used to compensate for the drop in voltage supplied from the host 12. Specifically, the output voltage (5.3V) of the step-down DC / DC converter 90 is supplied as a compensation voltage to the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58.

[0083] Through the processing of step S104, the power circuit 22 generates the second voltage during the period, as shown in FIG. Figure 4 As shown in (a), the voltage of the first monitoring terminal 72 is 5V, so the cathode terminal of the diode 96 is also 5V. Figure 4 As shown in (d), the voltage at the second monitoring terminal 74 is 28 V, and the output voltage of the step-down DC / DC converter 90, that is, the voltage at the anode terminal of the diode 96, is 5.3 V. The voltage between the anode and cathode of the diode 96 is 0.3 V, which is lower than the threshold voltage (0.4 V) of the diode 96, and the diode 96 is in the off state. Therefore, no current flows from the output of the step-down DC / DC converter 90 to the diode 96, and the energy of the PLP capacitor 80 is not consumed.

[0084] When the peak current of SSD 14 is generated, the voltage applied from host 12 to input terminal 51 is reduced. Figure 4 As shown in (a), the voltage of the first monitoring terminal 72 decreases. If the voltage of the first monitoring terminal 72 decreases below the first threshold voltage (e.g., 4.9V), the voltage of the cathode terminal of the diode 96 also decreases below 4.9V. The output voltage of the step-down DC / DC converter 90, i.e., the voltage of the anode terminal of the diode 96, is 5.3V. Therefore, the voltage between the anode and cathode of the diode 96 becomes 0.4V or more. Figure 4 As shown in (e), the diode 96 is turned on. Therefore, the current using the energy of the PLP capacitor 80 flows from the output of the step-down DC / DC converter 90 through the diode 96 to the input terminal 73 of the LDO regulator 56 and the DC / DC converter 58. Therefore, the compensation voltage corresponding to the discharge energy of the PLP capacitor 80 is applied to the input terminal 73. Figure 4 As shown in (a), the voltage of the first power supply monitoring terminal 72 is restored to 5 V. As a result, malfunction of the PLP function due to the generation of a peak current can be prevented.

[0085] When the voltage at first monitoring terminal 72 returns to 5V, the voltage between the anode and cathode of diode 96 drops to 0.3V, which is below the threshold voltage of diode 96. Consequently, diode 96 is turned off. Current utilizing the energy of PLP capacitor 80 does not flow through diode 96, and the energy of PLP capacitor 80 is not consumed.

[0086] Next, the PLP function will be described. As described above, conventional power supply circuits compare the voltage at first monitoring terminal 72 with a certain threshold voltage to activate the PLP function. However, according to the embodiment, if the voltage at first monitoring terminal 72 drops, a voltage corresponding to the discharge energy of PLP capacitor 80 is supplied to input terminal 73 of LDO regulator 56 and DC / DC converter 58. As a result, the voltage at first monitoring terminal 72 returns to its original voltage and does not fall below the threshold voltage. Therefore, the voltage at first monitoring terminal 72 cannot be used to determine the start of the PLP function.

[0087] Furthermore, when the power to the host computer 12 is turned off, the voltage at the first monitoring terminal 72 drops, and the output voltage of the step-down DC / DC converter 90 is supplied as the compensation voltage to the input terminal 73. Consequently, the discharged energy of the PLP capacitor 80 is completely consumed by the compensation voltage, and the energy used for the PLP function is lost.

[0088] In the embodiment, the charging voltage of the PLP capacitor 80 applied to the anode terminal of the PLP capacitor 80, that is, the charging voltage of the PLP capacitor 80 monitored by the second monitoring terminal 74, is used as the activation start condition of the PLP function. While the power supply circuit 22 supplies the second voltage to the flash memory 16, the controller 18, and the DRAM 20, the control logic 60 determines whether the voltage of the second monitoring terminal 74 is below the second threshold voltage ( Figure 3 The second threshold voltage is set to 25V, for example.

[0089] When the voltage of the second monitoring terminal 74 is not lower than the second threshold voltage, the determination process of step S108 is repeatedly executed.

[0090] In the event that the power supply to the host 12 is unexpectedly cut off due to a power outage or the like, power is not supplied from the host 12. Figure 4 As shown in (a), the voltage of the first monitoring terminal 72 decreases. When the voltage of the first monitoring terminal 72 decreases below the first threshold voltage, as shown in Figure 4 As shown in (e), the diode 96 is turned on. Therefore, the PLP capacitor 80 starts to discharge, and a voltage corresponding to the discharge energy is applied to the input terminal 73. Figure 4 As shown in (a), the voltage of the first monitoring terminal 72 returns to 5V.

[0091] If further discharge is made from the PLP capacitor 80, then Figure 4As shown in (d), the voltage of the second monitoring terminal 74 decreases. When the voltage of the second monitoring terminal 74 decreases below the second threshold voltage (25V), the control logic 60 turns off the MOS transistor 82. As a result, the voltage corresponding to the discharge energy of the PLP capacitor 80 is no longer supplied to the first monitoring terminal 72. Figure 4 As shown in (a), the voltage of the first monitoring terminal 72 drops to 0 V. When the voltage of the second monitoring terminal 74 drops below the second threshold voltage, the control logic 60 turns off the MOS transistor 92. This stops charging the PLP capacitor 80.

[0092] Since the voltage of the first monitoring terminal 72 is 0 V, the diode 96 remains in the on state, and the voltage corresponding to the discharge energy of the PLP capacitor 80 continues to be supplied to the LDO regulator 56 and the DC / DC converter 58 .

[0093] If the PLP capacitor 80 is further discharged and the voltage of the second monitoring terminal 74 drops to 0V, then Figure 4 As shown in (e), the diode 96 is in an OFF state.

[0094] On the other hand, when the voltage of the second monitoring terminal 74 drops below a second threshold voltage (eg, 25 V), the control logic 60 transmits a notification indicating power off to the controller 18 via the I2C I / F 64 .

[0095] When the controller 18 receives this notification, if data in progress is stored in the DRAM 20, it writes the data in progress to the flash memory 16. During this writing period, the power supply circuit 22 uses the discharge energy of the PLP capacitor 80 to supply the second voltage to the flash memory 16, the controller 18, and the DRAM 20.

[0096] Thus, even if the power supply of the host computer 12 is unexpectedly turned off, the controller 18 can write the data in the middle of being written stored in the DRAM 20 to the flash memory 16 .

[0097] As described above, according to the embodiment, when a peak current is generated in SSD 14, a current utilizing the energy of PLP capacitor 80 is passed to LDO regulator 56 and DC / DC converter 58, thereby preventing malfunction of the PLP function. Furthermore, since the start of the PLP function is determined by monitoring the charge voltage of PLP capacitor 80, the PLP function can be properly activated.

[0098] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, PLP capacitor 80 and MOS transistor 82 may be provided independently of power supply circuit 22, rather than within power supply circuit 22. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0099] [Explanation of Symbols]

[0100] 12 Host

[0101] 14 SSD

[0102] 16 Flash memory

[0103] 18 Controller

[0104] 22 Power supply circuit

[0105] 60 Control Logic

[0106] 56 LDO voltage regulators

[0107] 58, 90 Step-down DC / DC converter

[0108] 80 PLP capacitors

[0109] 82, 92 MOS transistors

[0110] 96 diodes.

Claims

1. A memory system, characterized in that have: Terminal 1; Non-volatile memory; a capacitor having a second terminal; and The power supply circuit includes a third terminal and is configured as follows: applying a first voltage to the first terminal based on the voltage applied to the third terminal, generating at least one second voltage using the first voltage, and supplying the at least one second voltage to the nonvolatile memory; When the voltage at the third terminal becomes equal to or greater than a first threshold voltage, a third voltage is generated using the first voltage, and the third voltage is applied to the second terminal, thereby starting to charge the energy of the capacitor. When the voltage at the third terminal is lower than a second threshold voltage that is lower than the first threshold voltage and the voltage at the second terminal is higher than a third threshold voltage, charging of the capacitor is continued and a fourth voltage based on energy of the capacitor is supplied to the first terminal. When the voltage of the third terminal is lower than the second threshold voltage and the voltage of the second terminal becomes lower than the third threshold voltage, charging of the capacitor is stopped and a fifth voltage based on energy of the capacitor is supplied to the first terminal; The third voltage is higher than the first voltage, and The third threshold voltage is higher than the first threshold voltage.

2. The memory system according to claim 1, wherein: The second terminal is a terminal on the anode side of the capacitor.

3. The memory system according to claim 1, wherein: The power supply circuit comprises: a first converter for stepping down the voltage of the second terminal; as well as a diode electrically connected to the output terminal of the first converter and the first terminal; and The diode includes an anode electrically connected to the output terminal and a cathode electrically connected to the first terminal.

4. The memory system according to claim 3, wherein: The power supply circuit allows current to flow from the anode to the cathode when a difference between a voltage at the first terminal and a voltage at an output terminal of the first inverter becomes equal to or greater than a fourth threshold value.

5. The memory system according to claim 3, wherein: The power supply circuit includes a second converter that boosts the first voltage to the third voltage, and the second terminal is connected to an output terminal of the second converter.

6. The memory system according to claim 5, wherein: When the voltage of the third terminal is lower than or equal to the second threshold voltage, and the voltage of the second terminal becomes lower than or equal to the third threshold voltage, The power supply circuit stops the voltage boosting operation of the second converter.

7. The memory system according to claim 1, wherein Also features: volatile memory; and a controller that controls writing of data to the nonvolatile memory; and Composition: The controller writes data to be written to the non-volatile memory into the volatile memory. The power supply circuit sends a notification signal to the controller when the voltage at the third terminal is lower than the second threshold voltage and the voltage at the second terminal becomes lower than the third threshold voltage, and the controller responds to the notification signal by writing the data written to the volatile memory to the non-volatile memory.

8. The memory system according to claim 1, wherein Also includes: a MOS transistor electrically connected to the third terminal and the first terminal; And the power supply circuit is composed of: By turning on the MOS transistor, the first voltage is applied to the first terminal. When the voltage of the third terminal is equal to or higher than the first threshold voltage, the MOS transistor is turned on, and When the voltage of the third terminal is lower than the second threshold voltage and the voltage of the second terminal becomes lower than the third threshold voltage, the MOS transistor is turned off to stop applying the first voltage to the first terminal, thereby stopping charging of the capacitor.

9. A power supply circuit, characterized in that A power supply circuit for a memory system, the memory system comprising A first terminal, a nonvolatile memory, and a capacitor having a second terminal, wherein the power supply circuit is configured as follows: applying a first voltage to the first terminal, generating at least one second voltage using the first voltage, and supplying the at least one second voltage to the nonvolatile memory; When the voltage at the third terminal becomes equal to or greater than a first threshold voltage, a third voltage is generated using the first voltage, and the third voltage is applied to the second terminal, thereby starting to charge the energy of the capacitor. When the voltage at the third terminal is lower than a second threshold voltage that is lower than the first threshold voltage and the voltage at the second terminal is higher than a third threshold voltage, charging of the capacitor is continued and a fourth voltage based on energy of the capacitor is supplied to the first terminal. When the voltage of the third terminal is lower than the second threshold voltage and the voltage of the second terminal becomes lower than the third threshold voltage, charging of the capacitor is stopped and a fifth voltage based on energy of the capacitor is supplied to the first terminal. The third voltage is higher than the first voltage, and The third threshold voltage is higher than the first threshold voltage.

10. The power supply circuit according to claim 9, characterized in that Also includes: a first converter for stepping down the voltage of the second terminal; as well as a diode electrically connected to the output terminal of the first converter and the first terminal; and The diode includes an anode electrically connected to the output terminal and a cathode electrically connected to the first terminal.

11. The power supply circuit according to claim 10, wherein: comprising a second converter for boosting the first voltage to the third voltage, The second terminal is connected to the output terminal of the second converter, and When the voltage of the third terminal is lower than or equal to the second threshold voltage and the voltage of the second terminal becomes lower than or equal to the third threshold voltage, the boosting operation of the second converter is stopped.

12. The power supply circuit according to claim 9, characterized in that Include: a first converter for stepping down the voltage of the second terminal; as well as a diode electrically connected to the output terminal of the first converter and the first terminal; and The diode includes an anode electrically connected to the output terminal and a cathode electrically connected to the first terminal.

13. The power supply circuit according to claim 12, wherein: When the difference between the voltage at the first terminal and the voltage at the output terminal of the first inverter becomes equal to or greater than a fourth threshold value, current is caused to flow from the anode to the cathode.

14. The power supply circuit according to claim 9, characterized in that include: a MOS transistor electrically connected to the third terminal and the first terminal; and By turning on the MOS transistor, the first voltage is applied to the first terminal. When the voltage of the third terminal is equal to or higher than the first threshold voltage, the MOS transistor is turned on. When the voltage of the third terminal is lower than the second threshold voltage and the voltage of the second terminal becomes lower than the third threshold voltage, the MOS transistor is turned off to stop applying the first voltage to the first terminal, thereby stopping charging of the capacitor.

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