Chip memory fault repair device and chip

Abstract

The present application provides a memory fault repair device and chip for a chip, which are used to solve the problem that the hardware circuit fuse fault causes the chip fault repair failure. When performing fault detection and repair on the chip memory, the present application uses a processor to read the first repair information in the flash. If it is determined to perform fault detection on the chip based on the first repair information, a detection instruction is sent to the register, and the detection module obtains the detection instruction in the register, performs fault detection on the memory, and generates a detection result. The repair module generates repair data based on the detection result and sends it to the register. Then, the processor updates the first repair information based on the repair data of each memory to obtain the second repair information, and writes the repair data of each memory into the flash for backup. Finally, if it is determined to repair the chip, a repair instruction is sent to the register, and the repair module receives the repair instruction and repairs the memory.

Description

Technical Field

[0001] The present application relates to the field of chip detection technology, and in particular to a chip memory fault repair device and a chip. Background Art

[0002] At present, when a chip performs memory diagnosis and repair, it generally uses a one-time programmable fuse storage repair. For the chip, it is necessary to add a fuse macro and a control circuit, which increases the chip area and cost. At the same time, conventional chip storage repair requires the addition of hardware circuits to control functions such as reading and writing repair data and starting reset after repair. Once a hardware circuit fails, the chip repair cannot be completed, and hardware failures lead to greater risks. In addition, the existing solution uses fuse storage repair data, which can only read and write data once, increasing the risk of chip repair failure. Summary of the invention

[0003] The purpose of the present application is to provide a chip memory fault repair device and chip, so as to solve the problem of chip fault repair failure caused by hardware circuit fuse failure.

[0004] In a first aspect, the present application provides a chip fault repair device, the device comprising:

[0005] A processor, a non-volatile memory flash, a register, and a chip, wherein the chip includes a plurality of memories, each memory corresponds to a detection module, and each detection module includes a test module and a repair module, wherein:

[0006] The processor is configured to read the first repair information in the flash; if it is determined to perform fault detection on the chip based on the first repair information, then send a detection instruction to the register;

[0007] The test module of the memory is used for obtaining the detection instruction in the register, performing fault detection on the memory, and sending the detection result to the repair module of the memory;

[0008] A repair module of the memory, configured to generate repair data based on the detection result and send the repair data to the register;

[0009] The processor is further configured to update the first repair information based on the repair data of each memory to obtain second repair information, and write the repair data of each memory into the flash for backup, and send a repair instruction to the register if it is determined to repair the chip based on the second repair information;

[0010] The repair module is further configured to perform a repair operation on the memory based on the repair data of the memory if the repair instruction is received from the register.

[0011] In some embodiments, the processor is specifically configured to determine whether to perform fault detection on the chip based on the following method:

[0012] If the first repair information indicates that the chip has not been fault-detected, it is determined to perform fault-detection on the chip.

[0013] If the first repair information indicates that the chip has been subjected to fault detection and the test has passed and does not need to be repaired, determining that the chip does not need to be subjected to fault detection;

[0014] If the repair information indicates that the chip has been subjected to fault detection and the chip is faulty but can be repaired, determining that the chip does not need to be subjected to fault detection;

[0015] If the repair information indicates that the chip has been subjected to a fault test and the chip that failed the test is a bad chip, it is determined that the chip does not need to be subjected to a fault test;

[0016] If the repair information indicates other situations except the above four types, it is determined that the chip needs to perform fault detection.

[0017] In some embodiments, the performing of fault detection on the memory, the testing module is specifically used for:

[0018] Sending a test stimulus to the memory and obtaining response information of the test stimulus;

[0019] Based on the comparison result between the response information and the preset value, a detection result of the memory is generated.

[0020] In some embodiments, the memory includes a plurality of slices, each slice includes a plurality of rows and columns, the detection result includes a fault code, and the fault code includes: first data, second data and third data, wherein:

[0021] The first data is used to indicate the row / column where the bit with the fault is located;

[0022] The second data is used to indicate the slice identifier of the bit where the fault is located. If the first data indicates that multiple rows / columns are faulty, the second data is used to indicate the slice where the lowest column / row of the rows / columns where the fault is located;

[0023] The third data is used to indicate the total number of slices in the slice area where the row / column with the fault is located.

[0024] And / or, the detection result further includes a first detection signal, a second detection signal and a third detection signal, wherein,

[0025] The first detection signal is used to indicate whether the memory has been tested;

[0026] The second detection signal is used to indicate whether the memory has passed the test;

[0027] The third detection signal is used to indicate whether the memory is repairable.

[0028] In some embodiments, the repair module includes a first unit, a second unit and a third unit, wherein:

[0029] The first unit is used to receive the first detection signal and store the fault code;

[0030] The second unit is used to analyze the fault code to generate the repair data, and generate an analysis completion signal after generating the repair data;

[0031] The third unit is used to obtain the analysis completion signal. If at the rising edge of the analysis completion signal, the repair data is sent to the register and a sending completion signal is generated to the register, wherein the sending completion signal is used to indicate to the register that the sending of the repair data is completed.

[0032] In some embodiments, the analyzing the fault code to generate the repair data is performed, and the second unit is specifically used to:

[0033] If the memory includes a redundant unit, the repair data is generated based on the following method:

[0034] If the first data indicates that there is no faulty row / column, generating repair data indicating that there is no fault and no need for repair according to the data format of the repair data;

[0035] If the first data indicates that at most n rows / columns are faulty, and the third data indicates that the faulty rows / columns can be repaired using redundant units, then generating repair data indicating that there is a fault and that it can be repaired according to a data format of the repair data; wherein n is the number of redundant units of the memory;

[0036] If the first data indicates that at most n rows / columns are faulty, and the third data indicates that the faulty rows / columns cannot be repaired using redundant units, then generating repair data indicating that there is a fault and cannot be repaired according to the data format of the repair data;

[0037] If the first data indicates that at least m rows / columns are faulty, repair data indicating that there is a fault and cannot be repaired is generated according to the data format of the repair data, wherein m is greater than the n.

[0038] In some embodiments, the device further includes a peripheral bus APB module, and the APB module is used to transfer data between the flash and the register in response to the scheduling of the processor.

[0039] In some embodiments, the device further includes a serial peripheral interface SPI module, and the processor is specifically configured to perform read and write operations on the flash through the SPI module.

[0040] In some embodiments, the processor is further configured to:

[0041] If the repair information of the register and the repair module is lost, the process returns to the step of reading the first repair information in the flash.

[0042] In some embodiments, the processor is further configured to detect whether multiple areas in the flash are faulty based on the following method:

[0043] For any one target area among the multiple areas, write random data into the target area;

[0044] Reading the random data, and comparing the read value with the random data;

[0045] If the read value is consistent with the random data, writing a no-fault flag in the target area;

[0046] If the read value is inconsistent with the random data, writing a fault flag in the target area;

[0047] The no-fault flag is used to instruct the processor to write the second repair information and the repair data of each memory in the target area;

[0048] The fault flag is used to instruct the processor to prohibit reading and writing data in the target area.

[0049] In a second aspect, the present application provides a chip, comprising any of the devices provided in the first aspect of the present application.

[0050] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0051] Based on the above-mentioned chip fault repair device and chip, the present application uses board-level flash to repair the chip, and completes the chip memory fault repair with a small amount of additional hardware circuits, such as clocks, thereby avoiding the increase of chip area and cost, and adopts software to read and write repair data without increasing the read and write data and reset circuits, thereby reducing the risks brought by hardware circuit failures. Among them, the flash used in the present application supports multiple burning of the same location. Even if the flash target location fails, the software can flexibly store the repair data to other locations, and use external flash to replace the on-chip fuse to solve the problem of chip fault repair failure caused by the inability to replace the fuse once it fails, thereby better providing the fault tolerance of the entire device, providing users with a simpler and more convenient method, and improving the user experience.

[0052] It should be understood that the above general description and the following detailed description are only exemplary and explanatory and cannot limit the present application. Based on the common sense in the art, the above preferred conditions can be combined arbitrarily to obtain the preferred embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A schematic diagram of the structure of a chip fault repair device provided in an embodiment of the present application;

[0055] Figure 2 A schematic diagram of a flow chart of a processor determining whether to perform fault detection on a chip memory provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of a flow chart of a test module provided in an embodiment of the present application performing fault detection on a memory;

[0057] Figure 4 A schematic diagram of the format of a redundant unit interface provided in an embodiment of the present application;

[0058] Figure 5 A schematic diagram of a process for repairing a faulty memory provided in an embodiment of the present application;

[0059] Figure 6 A schematic diagram of a process for performing fault detection on a flash module provided in an embodiment of the present application;

[0060] Figure 7A schematic diagram of the overall workflow of the chip fault repair device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Among them, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0062] Furthermore, in the description of the embodiments of the present application, unless otherwise specified, “ / ” means or. For example, A / B can mean A or B. The “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0063] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as suggesting or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more.

[0064] A chip fault repair device and a chip provided by the present application will be introduced below in conjunction with embodiments.

[0065] The embodiments of the present application are mainly used to solve the problem of failure of chip fault repair caused by hardware circuit fuse failure. The inventive concept of the present application can be summarized as follows: when performing fault detection and repair on the chip memory, the present application uses a processor to read the first repair information in the flash. If it is determined to perform fault detection on the chip based on the first repair information, a detection instruction is sent to the register. The detection module obtains the detection instruction in the register, performs fault detection on the corresponding memory, and sends the detection result to the repair module of the memory. The repair module generates repair data based on the detection result and sends it to the register. Then, the processor updates the first repair information based on the repair data of each memory to obtain the second repair information, and writes the repair data of each memory into the flash for backup. Finally, if it is determined to repair the chip based on the second repair information, a repair instruction is sent to the register. The repair module receives the repair instruction and completes the repair operation on the memory. In summary, the embodiments of the present application use board-level flash to repair the chip. In the case of adding a small amount of additional hardware circuits, such as clocks, the small amount of added hardware devices is Figure 1 It is not reflected in the chip memory, and the fault detection and fault repair of the chip memory are completed, avoiding the increase of chip area and cost. The software method is used to read and write the repair data, without increasing the read and write data and reset circuit, reducing the risk of hardware circuit failure. In addition, the flash used in this application supports multiple burning of the same location. Even if the flash target location fails, the software can flexibly store the repair data to other locations, and use external flash to replace the on-chip fuse to solve the problem that the fuse cannot be replaced once it fails, and better provide the fault tolerance of the entire device. Provide users with a chip fault repair device to improve user experience.

[0066] The memory fault repair device of the chip provided in this application can be used in the chip testing scenario before the terminal device leaves the factory. For example, before the chip built into the smart TV leaves the factory, the fault repair device provided in this application can complete the chip fault detection and repair.

[0067] After introducing the main inventive ideas of the embodiments of the present application, the following briefly introduces the application scenarios to which the technical solutions of the embodiments of the present application can be applied. It should be noted that the application scenarios introduced below are only used to illustrate the embodiments of the present application and are not limited. In specific implementation, the technical solutions provided by the embodiments of the present application can be flexibly applied according to actual needs.

[0068] Based on the above description, the present application provides a chip fault repair device, such as Figure 1As shown, the device includes: a processor 101, a memory 108, a non-volatile memory 103 flash 103, a register 105, and a chip. The chip includes multiple memories 108, each memory 108 corresponds to a detection module, and each detection module includes a test module 106 and a repair module 107, wherein:

[0069] Processor 101, corresponding to Figure 1 The CPU in the memory 108 is used to read the first repair information in the non-volatile memory flash; if it is determined to perform a fault detection on the chip based on the first repair information, a detection instruction is sent to the register 105.

[0070] In some embodiments, the processor 101 determines whether to perform fault detection on the chip memory 108 based on the following method: Figure 2 Can be implemented as:

[0071] In step 201, if the first repair information indicates that the chip memory 108 has not been fault-detected, it is determined to perform fault detection on the chip. For example, if the first repair information repair_data0 is FFxxxxxx, it means that fault detection has not been performed, and the first flag bit boot_mode=0 is generated. Based on the first flag bit, it is determined to perform fault detection on the chip, and the processor 101 sends a detection instruction to the register 105 to trigger the construction of each memory 108.

[0072] In step 202, if the first repair information indicates that the chip memory 108 has been subjected to fault detection and the test has passed and no repair is required, it is determined that the chip does not need to be subjected to fault detection. For example, if the first repair information repair_data0 is 80xxxxxx, then the second flag bit boot_mode=1 is generated, indicating that the chip memory 108 has been subjected to fault detection and the test has passed and no repair is required, and based on the second flag bit, it is determined that the chip does not need to be subjected to fault detection.

[0073] In step 203, if the first repair information indicates that the chip has been fault-detected and the chip is faulty but can be repaired, it is determined that the chip does not need to be fault-detected. For example, the first repair information repair_dataO is C0xxxxxx, and the third flag bit boot_mode=2 is generated, indicating that the chip has been fault-detected and the chip is faulty but can be repaired, and based on the third flag bit, it is determined that the chip does not need to be fault-detected.

[0074] In step 204, if the first repair information indicates that the chip has been tested for a fault and the chip that failed the test is a bad chip, it is determined that the chip does not need to be tested for a fault. For example, the first repair information repair_dataO is A0xxxxxx, and the fourth flag boot_mode=3 is generated, indicating that the chip has been tested for a fault and the chip that failed the test is a bad chip. Based on the fourth flag, it is determined that the chip does not need to be tested for a fault.

[0075] In step 205 , if the first repair information indicates other situations except the above four types, a first flag is generated, that is, all are processed according to the first type, and it is determined to perform fault detection on the chip memory 108 .

[0076] The working mechanisms of the memories 108 and their corresponding detection modes are the same. For ease of understanding, the following describes how to test a memory 108 from the perspective of a memory 108 .

[0077] The test module 106 of the memory 108 corresponds to Figure 1 The BIST module in the memory 108 is used to obtain the detection instruction sent by the processor 101 in the register 105TOP_REG, perform fault detection on the memory 108, and send the detection result to the repair module 107 of the memory 108, that is, Figure 1 The RepariDataGen module in .

[0078] In some embodiments, the test module 106 performs fault detection on the memory 108, and configures the module to enter the BIST MODE (test mode) through the processor 101. In this mode, the corresponding test stimulus is issued to the chip memory 108, and the chip memory 108 is waited for to respond and output the result, and then the result is compared with the expected value. If the result is consistent with the expected value, it means that the chip memory 108 has no fault, otherwise it means that the chip memory 108 has a fault. Figure 3 Can be implemented as:

[0079] In step 301 , the processor 101 configures the BIST module to be enabled.

[0080] In step 302, the BIST module performs different types of fault detection in sequence.

[0081] In step 303, a stimulus is transmitted to the memory 108mem and then the response of the memory 108mem is read and compared with the expected value.

[0082] In step 304, a fault detection result is generated.

[0083] The memory 108 includes a plurality of slices, each of which includes a plurality of rows and columns, as shown in the following Table 1:

[0084] Table 1

[0085] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

[0086] Assuming that Table 3 is a 6x4 array, and every two rows are divided into one area, the array of each area is 2x4, including 2 rows and 4 columns.

[0087] The detection result includes a fault code, and the fault code includes: first data, second data and third data, wherein:

[0088] The first data is used to indicate the row / column where the bit with the fault is located;

[0089] The second data is used to indicate the slice identifier of the bit where the fault is located. If the first data indicates that multiple rows / columns are faulty, the second data is used to indicate the slice where the lowest column / row of the rows / columns where the fault is located;

[0090] The third data is used to indicate the total number of slices in the slice area where the row / column with the fault is located. For example, the following Table 2 shows the first data, the second data and the third data:

[0091] Table 2

[0092] dataO data1 data2

[0093] In which, taking the 8192x64 memory 108 as an example, the memory 108 includes a column redundancy unit. The first data data0 has a bit width of 64 bits, which corresponds to the 64 bits of the output Q one by one. The value of 1 indicates that the corresponding bit of the output Q is faulty, such as 10001 indicates that the 0th and 4th bits of the output Q are faulty. The second data data1 indicates which column the faulty Q is located in, and the column is the slice where the bit with the fault is located, such as the 8192 rows of the 8192x64 memory 108 are divided into four columns. If multiple bits of the output Q are faulty, for the memory 108 including the row redundancy unit, only the slice where the lowest row of the row with the faulty output Q is located is recorded, or for the memory 108 including the column redundancy unit, only the slice where the lowest column of the column with the faulty output Q is located is recorded. The third data data2 indicates whether the fault corresponds to multiple columns with faults.

[0094] It should be noted that the above is the case where the memory 108 includes one redundant unit. If the memory 108 has two redundant units, data0 needs to be split into data0_H and data0_L. data0_H corresponds to the upper 32 bits of the 8192x64 memory 108, that is, bits 32 to 63, and data0_L corresponds to the lower 32 bits of the 8192x64 memory 108, that is, bits 0 to 31. The corresponding data1 and data2 should also be split based on the same principle. As shown in Table 3 below:

[0095] Table 3

[0096] data0_H data0_L data1_H data1_L data2_H data2_L

[0097] Here, taking the 8192x64 memory 108 as an example, it is assumed that the memory 108 includes 2 column redundancy units. The first data data0_H has a bit width of 32 bits, and the data0_L has a bit width of 32 bits, which correspond to the 64 bits of the output Q one by one. The value of 1 indicates that the corresponding bit of the output Q is faulty. For example, the data0_H value is 10001, which indicates that the 32nd and 36th bits of the output Q are faulty, and the data0_L value is 10001, which indicates that the 0th and 4th bits of the output Q are faulty. Based on the same working mechanism, the second data data1_H and data1_L indicate which column the faulty Q is located in. The column is the area where the faulty bit is located. For example, the 8192 rows of the 8192x64 memory 108 are divided into four columns. If multiple bits of output Q fail, for the memory 108 including row redundancy units, only the slice where the lowest column of the row with the failure of output Q is located is recorded, and the third data data2_H and data2_L indicate whether the corresponding multiple columns have failures.

[0098] In addition to generating the above-mentioned first data, second data and third data, the test module 106 also has other signals as status outputs, so the detection result also includes the first detection signal, the second detection signal and the third detection signal, wherein:

[0099] The first detection signal bist_done is used to indicate whether the memory 108 has been tested;

[0100] The second detection signal bist_pass is used to indicate whether the memory 108 has passed the test. If there is no fault, the signal value is 1, otherwise the value is 0;

[0101] The third detection signal bist_repairable is used to indicate whether the memory 108 is repairable.

[0102] In summary, the detection result of the memory 108 may include: a first detection signal bist_done, a second detection signal bist_pass, a third detection signal bist_repairable and a fault code.

[0103] After completing the fault detection of the memory 108, the repair module 107 of the memory 108 generates repair data based on the detection result and sends it to the register 105, that is, Figure 1 The RepairDataGen module in generates repair data based on the detection results generated by the BIST module and sends it to the register 105.

[0104] In some embodiments, Figure 1 As shown, the repair module 107 includes a first unit, a second unit and a third unit, wherein:

[0105] The first unit FaultCapture is used to receive the first detection signal and store the fault code. Specifically, the main task of FaultCapture is to receive the bist_done signal of the BIST module and latch the fault code to ensure that the BIST module has completed the fault detection at this time, which is the final fault code.

[0106] In some embodiments, the second unit RepairCalculate is used to analyze the fault code to generate repair data, and generate an analysis completion signal after generating the repair data, as follows:

[0107] If the memory 108 includes redundant cells, the repair data is generated based on the following method:

[0108] If the first data indicates that there is no row / column with a fault, generating repair data for indicating that there is no fault and no need for repair according to the data format of the repair data;

[0109] If the first data indicates that at most n rows / columns are faulty, and the third data indicates that the faulty rows / columns can be repaired using redundant units, then repair data indicating that there is a fault and that it can be repaired is generated according to the data format of the repair data; wherein n is the number of redundant units of the memory 108;

[0110] If the first data indicates that at most n rows / columns are faulty, and the third data indicates that the faulty rows / columns cannot be repaired using redundant units, then generating repair data indicating that there is a fault and cannot be repaired according to the data format of the repair data;

[0111] If the first data indicates that at least m rows / columns are faulty, repair data indicating that the fault is unrepairable is generated according to the data format of the repair data, where m is greater than n.

[0112] Taking the memory 108 including one redundant unit as an example, for the column redundant unit, the row redundant unit generates repair data based on the following method:

[0113] If the first data indicates that there is no faulty bit, generating repair data for indicating that there is no fault and no need for repair according to the data format of the repair data;

[0114] If the first data indicates that one column of bits is faulty, and the third data indicates that the faulty bits are in one slice, repair data indicating that there is a fault and that it is repairable is generated according to the data format of the repair data; wherein if the redundancy unit is row redundancy, one slice is a number of columns, and if the redundancy unit is column redundancy, one slice is a number of rows;

[0115] If the first data indicates that one column of bits is faulty, and the third data indicates that the faulty bits are in multiple slices, then generating repair data indicating that the fault is unrepairable according to the data format of the repair data;

[0116] If the first data indicates that multiple columns of bits are faulty, repair data indicating that the fault is present and cannot be repaired is generated according to the data format of the repair data.

[0117] For row redundancy units, repair data is generated based on the same working principle:

[0118] If the first data indicates that there is no faulty bit, generating repair data for indicating that there is no fault and no need for repair according to the data format of the repair data;

[0119] If the first data indicates that a row of bits is faulty, and the third data indicates that the faulty bits are in a slice, then repair data indicating that there is a fault and that it is repairable is generated according to the data format of the repair data; wherein, if the redundancy unit is row redundancy, one slice is a number of columns;

[0120] If the first data indicates that one row of bits is faulty, and the third data indicates that the faulty bits are in multiple slices, then generating repair data indicating that there is a fault and cannot be repaired according to the data format of the repair data;

[0121] If the first data indicates that multiple rows of bits are faulty, repair data indicating that the fault is unrepairable is generated according to the data format of the repair data.

[0122] Analyze the fault code to generate repair data. This step is mainly divided into two steps:

[0123] The first step is to determine whether it is repairable. The judgment basis is that only one row or one column of the bits corresponding to each redundant unit is faulty, and there is only one column in the slice where the faulty bit is located. The corresponding first data data0, or data0_H and data0_L, has only one bit that is 1, and data2 is 0, or data2_H and data2_L are 0.

[0124] For example, for a memory 108 including a redundant unit, both row redundant units and column redundant units are applicable. If dataO is all 0, the mem has no fault and does not need to be repaired; if dataO has only one bit that is 1, and data2=0, it means that the memory 108 has one bit fault and is located in one column, which can be repaired; if dataO has only one bit that is 1, and data2=1, it means that the mem has one bit fault, but is located in multiple columns, which cannot be repaired; if dataO has multiple bits that are 1, it means that multiple bits of the memory 108 have faults and cannot be repaired.

[0125] For the memory 108 including 2 column redundant units, taking the 8192x64 memory 108 as an example, assuming that the memory 108 includes 2 column redundant units, data0 needs to be split into data0_H and data0_L, data0_H corresponds to the upper 32 bits of the 8192x64 memory 108, that is, 32 to 63 bits, dataO_L corresponds to the lower 32 bits of the 8192x64 memory 108, that is, 0 to 31 bits, and the corresponding datal and data2 should also be split based on the same principle. If data0_H and dataO_L are all 0, the mem has no fault and does not need to be repaired. If data0_H has only 1 bit as 1, and data2_H=0, it means that there is a 1-bit fault in the upper 32 bits of the memory 108, and it is located in 1 slice column, which can be repaired. In addition, data0_L has only 1 bit as 1, and data2_L=0, it means that there is a 1-bit fault in the lower 32 bits of the memory 108, and it is located in 1 slice column, which can be repaired; if data0_H has only 1 bit as 1, and data2_H=1, it means that there is a 1-bit fault in the upper 32 bits of the memory 108, but it is located in multiple columns, which cannot be repaired; if data0_L has only 1 bit as 1, and data2_L=1, it means that there is a 1-bit fault in the lower 32 bits of the memory 108, but it is located in multiple columns, which cannot be repaired. If multiple bits of data0_H and data0_L are 1, it means that multiple bits of both the upper 32 bits and the lower 32 bits of the memory 108 are faulty and cannot be repaired. Only when the faulty bits of both the upper 32 bits and the lower 32 bits of the memory 108 can be repaired, can the entire memory 108 be repaired.

[0126] Then, based on the judgment result, a bist_repairable signal is generated, the value of which is 1 if the device is repairable, and 0 otherwise.

[0127] The second step is to generate repair data repair_data. This unit converts data0 and data1 into repair data repairdata. After generating the repair data, this unit generates an analysis completion signal update and sends the signal to the third unit UpdateRepairData.

[0128] The redundant unit interface of the redundant memory 108 is generally in a fixed format. For example, the ARM memory uses a 64-bit repair for output Q. For the format, please refer to Figure 4 For a memory containing two column redundancy units, the specific meanings are as follows:

[0129] Columnsegment(Right) indicates that the redundant unit is located at the far right;

[0130] ShiftIORange: Q[31:0] indicates that the right redundancy can repair bits 0 to 31 of Q;

[0131] FuseSet{FuseMap...} indicates the correspondence between FuseMap[4:0] and Q[31:0] on the right. For the specific correspondence, see Figure 4 ;

[0132] PinMap{ReapirEnable: CRE1 indicates that the enable signal of the right redundant unit is CRE1;

[0133] FuseMap[0]: FCA1[0] indicates that FCA1[0] corresponds to the right FuseMap[0];

[0134] FuseMap[1]: FCA1[0] indicates that FCA1[1] corresponds to the right FuseMap[1];

[0135] FuseMap[2]: FCA1[0] indicates that FCA1[2] corresponds to the right FuseMap[2];

[0136] FuseMap[3]: FCA1[0] indicates that FCA1[3] corresponds to the right FuseMap[3];

[0137] FuseMap[4]: FCA1[0] indicates that FCA1[4] corresponds to the right FuseMap[4];

[0138] Columnsegment(Left) indicates that the redundant unit is located at the far left;

[0139] ShiftIORange: Q[63:32] indicates that the left redundancy can repair bits 63 to 32 of Q;

[0140] FuseSet{FuseMap...} indicates the correspondence between the left FuseMap and Q[63:32]. For details, see Figure 4 ;

[0141] PinMap{ReapirEnable: CRE2 indicates the enable signal CRE2 of the left redundant unit;

[0142] FuseMap[0]: FCA1[0] indicates that FCA1[0] corresponds to the left FuseMap[0];

[0143] FuseMap[1]: FCA1[0] indicates that FCA1[1] corresponds to the left FuseMap[1];

[0144] FuseMap[2]: FCA1[0] indicates that FCA1[2] corresponds to the left FuseMap[2];

[0145] FuseMap[3]: FCA1[0] indicates that FCA1[3] corresponds to the left FuseMap[3];

[0146] FuseMap[4]: FCA1[0] indicates that FCA1[4] corresponds to the left FuseMap[4].

[0147] The interface signals are CRE1 / FCA1[4:0] and CRE2 / FCA2[4:0]. CRE1 controls whether to use the first redundant unit. When the CRE1 value is 1, it means that the redundant unit replaces the faulty unit. When the value is 0, it means that the redundant unit is not used. FCA1[4:0] indicates that the first redundant unit can repair the bits of Q. Figure 4 As shown in , if FCA1[4:0]=0, it means that the 32nd bit of Q is faulty and the 32nd bit of Q can be repaired by the redundant unit. The same is true for CRE2 and FCA2. In this example, CRE1 can repair bits 0-31 of Q, and CRE2 can repair bits 32-63 of Q, that is, all bits of Q of the memory 108 can be repaired.

[0148] In some embodiments, the third unit UpdateRepairData converts data0 and data1 into repair data repairdata to generate repair data, and the format of the repair data is as shown in Table 4 below:

[0149] Table 4

[0150] CRE2 FCA2[4] FCA2[3] FCA2[2] FCA2[1] FCA2[0] CRE1 FCA1[4] FCA1[3] FCA1[2] FCA1[1] FCA1[0]

[0151] In the table, CRE1 and CRE2 both include two states, that is, the value is 1 or 0, 1 indicates that the repair is enabled and 0 indicates that the repair is not enabled. At the same time, FCA1[4:0] and FCA2[4:0] correspond to outputs 0-31 and 32-63 respectively, and the values ​​are 1 or 0. The 5 positions occupied by FCA1[4:0] and FCA2[4:0] in Table 4 are 5-bit binary values, which represent the fault bits corresponding to the repairable output Q. The 12 interface signals CRE1, FCA1[4:0], CRE2 and FCA2[4:0] in Table 4 correspond to 12-bit binary, and the 12-bit binary is the repair data of the corresponding memory 108.

[0152] The third unit UpdataRepairData is used to obtain the analysis completion signal. If the rising edge of the analysis completion signal is obtained, the repair data is sent to the register 105, and a sending completion signal repair_done is generated to the register 105, wherein the sending completion signal is used to indicate to the register 105 that the sending of the repair data is completed.

[0153] At this point, the RepairDataGen module completes the judgment of whether it is repairable, the generation of repair data, and the transmission and latching of repair data. RepairDataGen mainly generates the transmission completion signal repair_done, the repairable signal repair_pass and the repair data repairdata, and then sends these two signals and the repair data to the register 105.

[0154] The above describes a process for generating detection and repair data of the memory 108 .

[0155] In some embodiments, after the present application completes fault detection of the memory 108 and generates repair data, the processor 101 is also used to update the first repair information based on the repair data of each memory 108 to obtain the second repair information. For example, the original value of the first repair information repair_data0 is FFxxxxxx. After the CPU sends an instruction to the test module 106 to complete fault detection and generate repair data, the repair data is summarized and read from the register 105. If it is determined based on the repair data that the memory 108 does not have a fault, the first repair information repair_data0 is updated to obtain the second repair information of 80xxxxxx, and the repair data of each memory 108 is written to the flash for backup. If it is determined based on the second repair information that the memory 108 is to be repaired. The steps for repairing the faulty memory 108 are as follows: Figure 5 Can be implemented as:

[0156] In step 501 , the processor 101 sends a repair instruction to the register 105 .

[0157] In step 502, if the repair module 107 receives a repair instruction from the register 105, it performs a repair operation on the memory 108 based on the repair data of the memory 108. The repair data is configured to the repair interface of the memory 108 by repair_data_gen, for example, CRE1 / FCA1 / CRE2 / FCA2.

[0158] The memory 108 is repaired by adding redundant cells and replacing the faulty cells with normal cells in the redundant cells, including row redundant cells and column redundant cells.

[0159] Row redundancy unit: For example, if the mem is 8192x64, two redundancy units will be added at the top and bottom, which is actually 8194 64-bit data, corresponding to [8193:0]. Under normal circumstances, the middle 8192 64-bit are used, that is, [8192:1]x[63:0]. If the Nth bit of address A1 fails, the data read and write of this bit is abnormal. After repair, the address A1 will be skipped and the storage unit will be divided into two parts, left and right. Assuming that address A1 is on the right, the address range of mem after repair is {[8193:A1+1], [A1-1:1]}x[63:0]. If address A1 is on the left, the address range of mem after repair is {[8192:A1+1], [A1-1:0]}x[63:0].

[0160] Column redundancy unit: 8192x64 storage mem, mainly for output Q repair, actually 8192x66, normal use [8191∶0]x[64:1], after repair use [8191:0]x{[65:A1+1],[A1-1:1]} or [8191:0]x{[64:A1+1],[A1-1:0]}. Both redundancy methods actually exist in projects. Column redundancy units are more widely used, and this application is directed to the memory 108 with column redundancy units.

[0161] It should be added that the device provided in the embodiment of the present application also includes a peripheral bus APB module 102, which is used to respond to the scheduling of the processor 101 to transmit data between the flash and the register 105, and mainly cooperates with the CPU to complete the transfer of repair data, mainly including transferring from TOP_REG to the CPU, and transferring the repair data from the CPU to TOP_REG.

[0162] The device also includes a serial peripheral interface 103 SPI module, and the processor 101 performs read and write operations on the flash through the SPI module. The SPI module is a chip's own function, and uses the existing SPI read and write program to reduce the repeated development of chip software.

[0163] In some embodiments, if the entire device is powered off, the repair information of register 105 and repair module 107 will be lost, but the repair data is still saved in the flash, then the processor 101 can read the data in the flash and return to execute the step of reading the first repair information in the flash.

[0164] In some embodiments, the flash module is a storage unit and is a board-level device. Usually, 2-3 repair areas are allocated, the first repair area is the default, and the second and third are alternative areas. The processor 101 is also used to detect whether multiple areas in the flash are faulty based on the following method: Figure 6Can be implemented as:

[0165] In step 601, random data is written into any target area among multiple areas in the flash.

[0166] In step 602, random data is read and the read value is compared with the random data.

[0167] In step 603, if the read value is consistent with the random data, a no-fault flag is written in the target area, and the no-fault flag is used to instruct the processor 101 to write the second repair information and the repair data of each memory 108 in the target area. For example, if the read value is consistent with the random data, return to step 601, repeat the test 20 times, and if the 20 tests pass, the first byte of the area is written with the no-fault flag number FF.

[0168] In step 604, if the read value is inconsistent with the random data, a fault flag is written in the target area, and the fault flag is used to instruct the processor 101 to prohibit writing the second repair information and the repair data of each memory 108 in the target area. For example, if the read value is inconsistent with the random data, it indicates that the area is faulty, and the first byte of the area is written with the fault flag 00, and the next candidate area is replaced for testing, and steps 601-603 are repeated.

[0169] In some embodiments, the overall workflow of the chip fault repair device provided by the present application is as follows: Figure 7 Can be implemented as:

[0170] In step 701, the chip is reset, that is, the chip is powered on and starts working.

[0171] In step 702, the CPU reads data information in the flash.

[0172] In step 703, it is determined whether the value of the highest 8 bits of the first repair data in the exclusive data information is FF, that is, it is determined whether the first repair information repair_data0 is FFxxxxxx, and whether the chip performs fault detection.

[0173] In step 704, if the value of the highest 8 bits of the first repair data is FF, the CPU issues an instruction to configure the repair interface of the memory 108 to be in an invalid state to avoid the influence of the data information in the flash on the repair interface, and configures the clock and rst of the memory 108 to be in a working state.

[0174] In step 705, the CPU configures the test module 106BIST to issue a fault detection start signal for the memory 108 and to issue a read and write command.

[0175] In step 706, the test module 106 performs fault detection on the corresponding memory 108 to obtain a fault result. Since a chip usually has N memories 108, each memory 108 is given a corresponding number N, and then N bist_done, bist_pass, and bist_repairable are generated.

[0176] In step 707, the repair module 107 corresponding to the memory 108 analyzes the fault result of the memory 108, generates repair data, and sends it to the register 105. Because N fault results bist_done, bist_pass, bist_repairable are generated in step 706, N repair_done / preairable / repair_data are generated. For the convenience of explanation, they are hereinafter referred to as repair_done_n, repairable_n, and repairdata_n.

[0177] In step 708, the CPU collects and reads the repair data from the register 105. If it is determined based on the repair data that the memory 108 is not faulty, the first repair information repair_data0 is updated to obtain the second repair information 80xxxxxx, and the values ​​of repair_data1-repair_data254 are read and written as 0.

[0178] In step 709, the CPU writes the repair data into the flash for backup.

[0179] In step 710, if the CPU determines that the memory 108 has a fault based on the repair data and that the memory 108 is repairable, the first repair information repair_data0 is written and updated to obtain the second repair information C0xxxxxx, and the values ​​of repair_data1-repair_data254 are read from TOP_REG.

[0180] In step 711 , the CPU writes the repair data into the flash for backup and repairs the fault memory 108 at the same time.

[0181] In step 712, if the CPU determines that the memory 108 has a fault based on the repair data, and determines that the memory 108 is not repairable, the first repair information repair_data0 is updated, and the second repair information is obtained as A0xxxxxx, and the memory 108 is determined to be a bad chip. The above steps truly realize the use of board-level flash to repair the chip, and complete the fault repair of the chip memory 108 without adding additional hardware circuits, avoiding the increase of chip area and cost, and using software to read and write repair data, without adding read and write data and reset circuits, reducing the risks caused by hardware circuit failures. Among them, the flash used in this application supports multiple burning of the same location. Even if the flash target location fails, the software can flexibly store the repair data to other locations, which better provides the fault tolerance of the entire device. Provide users with a chip fault repair device and chip to improve user experience.

[0182] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0183] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

[0184] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0185] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0186] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0187] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0188] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A memory fault repair device for a chip, characterized in that: The device comprises: A processor, a non-volatile memory flash, a register, and a chip, wherein the chip includes a plurality of memories, each memory corresponds to a detection module, and each detection module includes a test module and a repair module, wherein: The processor is configured to read the first repair information in the flash; if it is determined to perform fault detection on the chip based on the first repair information, then send a detection instruction to the register; The test module of the memory is used for obtaining the detection instruction in the register, performing fault detection on the memory, and sending the detection result to the repair module of the memory; A repair module of the memory, configured to generate repair data based on the detection result and send the repair data to the register; The processor is further configured to update the first repair information based on the repair data of each memory to obtain second repair information, and write the repair data of each memory into the flash for backup, and send a repair instruction to the register if it is determined to repair the chip based on the second repair information; The repair module is further configured to perform a repair operation on the memory based on the repair data of the memory if the repair instruction is received from the register; The processor determines to perform fault detection on the chip in any of the following situations: The first repair information indicates that the chip has not performed fault detection; The first repair information indicates other situations except that the chip has undergone fault detection and passed the test and does not need to be repaired, the chip has undergone fault detection and the chip is faulty but can be repaired, and the chip has undergone fault testing and the chip that failed the test is a bad chip.

2. The device according to claim 1, characterized in that The processor is further configured to: If the first repair information indicates that the chip has been subjected to fault detection and the test has passed and does not need to be repaired, determining that the chip does not need to be subjected to fault detection; If the first repair information indicates that the chip has been subjected to fault detection and the chip is faulty but can be repaired, determining that the chip does not need to be subjected to fault detection; If the first repair information indicates that the chip has been subjected to a fault test and the chip that failed the test is a bad chip, it is determined that the chip does not need to be subjected to a fault detection.

3. The device according to claim 1, characterized in that Executing the fault detection on the memory, the test module is specifically used for: Sending a test stimulus to the memory and obtaining response information of the test stimulus; Based on the comparison result between the response information and the preset value, a detection result of the memory is generated.

4. The device according to claim 1 or 3, characterized in that: The memory includes a plurality of slices, each of which includes a plurality of rows and columns. The detection result includes a fault code, and the fault code includes: first data, second data, and third data, wherein: The first data is used to indicate the row / column where the bit with the fault is located; The second data is used to indicate the slice identifier of the bit where the fault is located. If the first data indicates that multiple rows / columns are faulty, the second data is used to indicate the slice where the lowest column / row of the rows / columns where the fault is located; The third data is used to indicate the total number of slices in the slice area where the row / column with the fault is located; And / or, the detection result also includes a first detection signal, a second detection signal and a third detection signal, wherein: The first detection signal is used to indicate whether the memory has been tested; The second detection signal is used to indicate whether the memory has passed the test; The third detection signal is used to indicate whether the memory is repairable.

5. The device according to claim 4, characterized in that The repair module includes a first unit, a second unit and a third unit, wherein: The first unit is used to receive the first detection signal and store the fault code; The second unit is used to analyze the fault code to generate the repair data, and generate an analysis completion signal after generating the repair data; The third unit is used to obtain the analysis completion signal. If at the rising edge of the analysis completion signal, the repair data is sent to the register and a sending completion signal is generated to the register, wherein the sending completion signal is used to indicate to the register that the sending of the repair data is completed.

6. The device according to claim 5, characterized in that Executing the analysis of the fault code to generate the repair data, the second unit is specifically used for: If the memory includes a redundant unit, the repair data is generated based on the following method: If the first data indicates that there is no faulty row / column, generating repair data indicating that there is no fault and no need for repair according to the data format of the repair data; If the first data indicates that at most n rows / columns are faulty, and the third data indicates that the faulty rows / columns can be repaired using redundant units, then generating repair data indicating that there is a fault and that it can be repaired according to a data format of the repair data; wherein n is the number of redundant units of the memory; If the first data indicates that at most n rows / columns are faulty, and the third data indicates that the faulty rows / columns cannot be repaired using redundant units, then generating repair data indicating that there is a fault and cannot be repaired according to the data format of the repair data; If the first data indicates that at least m rows / columns are faulty, repair data indicating that there is a fault and cannot be repaired is generated according to the data format of the repair data, wherein m is greater than the n.

7. The device according to claim 1, characterized in that The device further comprises a peripheral bus APB module, and the APB module is used for transmitting data between the flash and the register in response to the scheduling of the processor.

8. The device according to claim 1, characterized in that The processor is further configured to: If the repair information of the register and the repair module is lost, the process returns to the step of reading the first repair information in the flash.

9. The device according to claim 1, characterized in that The processor is also used to detect whether multiple areas in the flash are faulty based on the following method: For any target area among the multiple areas, write random data into the target area; Reading the random data, and comparing the read value with the random data; If the read value is consistent with the random data, a no-fault flag is written in the target area; If the read value is inconsistent with the random data, writing a fault flag in the target area; The no-fault flag is used to instruct the processor to write the second repair information and the repair data of each memory in the target area; The fault flag is used to instruct the processor to prohibit reading and writing data in the target area.

10. A chip, characterized in that: The invention comprises the device described in any one of claims 1 to 9.

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