Pseudo-gate planarization method

Abstract

The present invention provides a dummy gate planarization method, comprising the steps of: etching to form an initial dummy gate structure comprising a dummy gate layer, a first mask layer, and a second mask layer, wherein the materials of the first mask layer and the second mask layer are different; modifying the second mask layer to obtain a modified mask layer, wherein the etching rates of the modified mask layer and the first mask layer in a subsequent chemical mechanical planarization process are substantially the same; forming a barrier layer and a filling layer; and removing a portion of the filling layer, a portion of the barrier layer, the modified mask layer, the first mask layer, and a portion of the dummy gate layer using a chemical mechanical planarization process to obtain a plurality of dummy gate structures of the same height. This method overcomes the load effect caused by the height difference of different initial dummy gate structures, achieves a higher-precision planarization effect, and obtains a highly consistent dummy gate structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a pseudo-gate planarization method. Background Art

[0002] With the continuous reduction of large-scale integrated circuit geometry, especially after entering the FinField-Effect Transistor (FinFET) process, the local non-uniformity of chemical mechanical polishing (CMP) has become an increasingly serious and urgent problem. In the FinFET process, if the local flattening of the dummy gate structure does not meet the requirements, the silicon nitride on the surface of some dummy gate structures cannot be completely cleaned during the polishing process, and various work function metals cannot be filled in the subsequent process, resulting in yield loss. If the local height flattening of the dummy gate structure is not good, it will also cause the height of devices in different positions to be inconsistent, thus affecting device performance.

[0003] The local height difference between dummy gate structures of different structures needs to be less than 10 angstroms, which is difficult to achieve with conventional CMP methods due to their inherent characteristics. A common solution in the industry is to use etchback (EB) in conjunction with CMP to achieve consistent dummy gate heights for different structures. However, this combination has significant drawbacks. EB can cause different dummy gate structures to have a loading effect, making differences between different products difficult to eliminate and making process control difficult.

[0004] Therefore, it is necessary to provide a novel dummy gate planarization method to solve the above problems existing in the prior art. Summary of the Invention

[0005] The object of the present invention is to provide a pseudo gate planarization method, which can overcome the load effect caused by the height difference of different initial pseudo gate structures in the front, obtain a higher precision planarization effect, and obtain a highly consistent pseudo gate structure.

[0006] To achieve the above-mentioned object, the dummy gate planarization method of the present invention comprises the steps of:

[0007] S1: etching to form a plurality of initial dummy gate structures, wherein the initial dummy gate structures include a dummy gate layer, a first mask layer, and a second mask layer sequentially disposed on a surface of a substrate, and the materials of the first mask layer and the second mask layer are different;

[0008] S2: modifying the second mask layer to obtain a modified mask layer;

[0009] S3: after forming a barrier layer covering the upper surface of the substrate and the surface of the initial dummy gate structure, forming a filling layer on the upper surface of the barrier layer, and making the filling layer cover the barrier layer;

[0010] S4: using a chemical mechanical planarization process to remove part of the filling layer, part of the barrier layer, the modified mask layer, the first mask layer and part of the dummy gate layer to obtain a plurality of dummy gate structures with the same height.

[0011] The beneficial effect of the pseudo gate planarization method of the present invention is that: through step S1: etching to form a number of initial pseudo gate structures, the initial pseudo gate structure includes a pseudo gate layer, a first mask layer and a second mask layer sequentially arranged on the surface of the substrate, and the material of the first mask layer and the material of the second mask layer are different, which is conducive to making the size of the target pseudo gate structure more accurate. Through step S2: modifying the second mask layer to obtain a modified mask layer, so that the etching speed of the modified mask layer and the first mask layer in the subsequent chemical mechanical planarization process of step S4 is basically the same, which is conducive to obtaining a number of pseudo gate structures with the same height. Through step S3: after forming a barrier layer covering the upper surface of the substrate and the surface of the initial pseudo gate structure, a filling layer is formed on the upper surface of the barrier layer, and the filling layer is covered by the barrier layer, so that the barrier layer protects the first mask layer, the modified mask layer, the pseudo gate layer, and other structures arranged in the substrate, avoiding damage caused by them during the chemical mechanical planarization process. Through step S4: a chemical mechanical planarization process is used to remove part of the filling layer, part of the blocking layer, the modified mask layer, the first mask layer and part of the dummy gate layer to obtain several dummy gate structures with the same height, so as to overcome the load effect caused by the height difference of the initial dummy gate structures with different predecessors, and finally obtain a highly consistent dummy gate structure.

[0012] Optionally, in step S4, the step of removing part of the filling layer, part of the barrier layer, the modified mask layer, the first mask layer, and part of the dummy gate layer by a chemical mechanical planarization process to obtain a plurality of dummy gate structures of the same height includes:

[0013] S41: performing a first chemical mechanical planarization process to remove a portion of the filling layer until the barrier layer located on the upper surface of the highest initial dummy gate structure is exposed, and making the removal rate of the filling layer greater than the removal rate of the barrier layer;

[0014] S42: Perform a second chemical mechanical planarization process to remove part of the filling layer, part of the blocking layer, the modified mask layer, the first mask layer and part of the dummy gate layer, and make the removal rate of the filling layer lower than the removal rate of the blocking layer to obtain several dummy gate structures with the same height.

[0015] Optionally, the step of modifying the second mask layer in step S2 to obtain a modified mask layer includes:

[0016] S21: forming an organic thin film on the upper surface of the substrate and the surface of the initial dummy gate structure, and making the organic thin film cover the second mask layer;

[0017] S22: performing an etching back process on the organic thin film until the entire second mask layer is exposed;

[0018] S23: modifying the second mask layer to obtain a modified mask layer;

[0019] S24: removing the remaining portion of the organic thin film.

[0020] Optionally, a ratio of a removal rate of the modified mask layer formed in step S2 to a removal rate of the first mask layer is 0.9:1 to 1:1.

[0021] Optionally, the step of performing the first chemical mechanical planarization process in step S41 includes controlling the ratio of the removal rate of the filling layer to the removal rate of the barrier layer to be 20:1 to 100:1.

[0022] Optionally, the step of performing a second chemical mechanical planarization process in step S42 includes: controlling the ratio of the removal rate of the blocking layer to the removal rate of the filling layer to be 2:1 to 3:1, controlling the ratio of the removal rate of the blocking layer to the removal rate of the dummy gate layer to be 10:1 to 20:1, and controlling the ratio of the removal rate of the blocking layer to the removal rate of the modified mask layer to be 0.9:1 to 1:1.

[0023] Optionally, after the organic thin film is etched back in step S22 , the upper surface of the remaining portion of the organic thin film is not lower than the upper surface of the dummy gate layer.

[0024] Optionally, in step S23 , the second mask layer is modified by ion implantation or chemical treatment.

[0025] Optionally, in step S23 , the second mask layer is modified by vertical ion implantation, and the ions used in the vertical ion implantation include N ions.

[0026] Further optionally, the material of the first mask layer includes silicon nitride, and the material of the second mask layer includes silicon oxide.

[0027] Optionally, in step S1, the step of etching to form a plurality of initial dummy gate structures, wherein the initial dummy gate structures include a dummy gate layer, a first mask layer, and a second mask layer sequentially disposed on the surface of the substrate, and wherein the material of the first mask layer and the material of the second mask layer are different, includes:

[0028] S11: depositing the dummy gate layer, the first mask layer, and the second mask layer in sequence on the upper surface of the substrate, and making the materials of the first mask layer and the second mask layer different;

[0029] S12: etching the second mask layer, the first mask layer, and the dummy gate layer in sequence by photolithography and etching to form a plurality of initial dummy gate structures.

[0030] Optionally, the distance between the upper surface of the filling layer formed in step S3 and the upper surface of the barrier layer located on the upper surface of the highest initial dummy gate structure is not less than twice the thickness of the highest initial dummy gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a flow chart of a dummy gate planarization method according to an embodiment of the present invention;

[0032] Figure 2 Schematic diagram of a structure obtained after forming a dummy gate layer, a first mask layer, a second mask layer and a photoresist on a substrate according to an embodiment of the present invention;

[0033] Figure 3 For Figure 2 Schematic diagram of the structure obtained after the structure shown is etched to form an initial dummy gate structure;

[0034] Figure 4 For Figure 3 Schematic diagram of the structure obtained after an organic thin film is formed on the structure shown;

[0035] Figure 5 For Figure 4 Schematic diagram of the structure obtained after the organic thin film in the structure shown is etched back;

[0036] Figure 6 For Figure 5 A schematic diagram of the structure obtained after the second mask layer in the structure shown is modified;

[0037] Figure 7 For Figure 6 Schematic diagram of the structure obtained after removing the remaining organic film in the structure shown;

[0038] Figure 8 For Figure 7 Schematic diagram of the structure obtained after forming a barrier layer and a filling layer on the structure shown;

[0039] Figure 9 For Figure 8 Schematic diagram of the structure obtained after the first step of chemical mechanical planarization process is performed on the structure shown;

[0040] Figure 10 For Figure 9 Schematic diagram of the structure obtained after the structure shown undergoes the second step chemical mechanical planarization process. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0042] In order to overcome the problems existing in the prior art, an embodiment of the present invention provides a pseudo gate flattening method, which can overcome the load effect caused by the height difference of different initial pseudo gate structures in the front end, and obtain a higher precision flattening effect. Moreover, through two chemical mechanical flattening processes, the concave defects caused by the chemical mechanical flattening process can be effectively eliminated, and finally a highly consistent pseudo gate structure is obtained.

[0043] In some embodiments of the present invention, the dummy gate planarization method includes the steps of:

[0044] S1: etching to form a plurality of initial dummy gate structures, wherein the initial dummy gate structures include a dummy gate layer, a first mask layer, and a second mask layer sequentially disposed on a surface of a substrate, and the materials of the first mask layer and the second mask layer are different;

[0045] S2: modifying the second mask layer to obtain a modified mask layer;

[0046] S3: after forming a barrier layer covering the upper surface of the substrate and the surface of the initial dummy gate structure, forming a filling layer on the upper surface of the barrier layer, and making the filling layer cover the barrier layer;

[0047] S4: using a chemical mechanical planarization process to remove part of the filling layer, part of the barrier layer, the modified mask layer, the first mask layer and part of the dummy gate layer to obtain a plurality of dummy gate structures with the same height.

[0048] Specifically, step S1 is performed: etching is performed to form a plurality of initial dummy gate structures, wherein the initial dummy gate structures include a dummy gate layer, a first mask layer, and a second mask layer sequentially disposed on the surface of the substrate, and the material of the first mask layer is different from the material of the second mask layer, i.e., the etching rates of the first mask layer and the second mask layer are different. Compared with disposing only one mask layer on the surface of the dummy gate layer, disposing two mask layers on the surface of the dummy gate layer is more conducive to making the size of the target dummy gate structure more accurate. Step S2 is performed: modifying the second mask layer to obtain a modified mask layer, so that the etching rates of the modified mask layer and the first mask layer in the subsequent chemical mechanical planarization process in step S4 are substantially the same, which is conducive to obtaining a plurality of dummy gate structures with the same height. Through step S3: after forming a barrier layer covering the upper surface of the substrate and the surface of the initial pseudo gate structure, a filling layer is formed on the upper surface of the barrier layer, and the filling layer covers the barrier layer, even if the upper surface of the filling layer is higher than the barrier layer located on the upper surface of the highest initial pseudo gate structure, the barrier layer protects the first mask layer, the modified mask layer, the pseudo gate layer, and other structures provided in the substrate, thereby avoiding damage caused by the chemical mechanical planarization process. Through step S4: using a chemical mechanical planarization process to remove part of the filling layer, part of the barrier layer, the modified mask layer, the first mask layer and part of the pseudo gate layer to obtain several pseudo gate structures with the same height, so that the load effect caused by the height difference of the initial pseudo gate structures with different predecessors can be overcome, and finally a highly consistent pseudo gate structure is obtained.

[0049] In some possible embodiments of the present invention, the material of the dummy gate layer is polysilicon.

[0050] Figure 2 Schematic diagram of a structure obtained after forming a dummy gate layer, a first mask layer, a second mask layer and a photoresist on a substrate according to an embodiment of the present invention; Figure 3 For Figure 2 The structure shown is a schematic diagram of the structure obtained after the initial dummy gate structure is formed by etching the structure.

[0051] In some embodiments of the present invention, the step of etching to form a plurality of initial dummy gate structures in step S1, wherein the initial dummy gate structures include a dummy gate layer, a first mask layer, and a second mask layer sequentially disposed on the surface of the substrate, and the material of the first mask layer and the material of the second mask layer are different, includes: Figure 2 and Figure 3 :

[0052] S11: depositing a dummy gate layer 120, a first mask layer 130, and a second mask layer 140 in sequence on the upper surface of the substrate 110, and making the materials of the first mask layer 130 and the second mask layer 140 different;

[0053] S12 : etching the second mask layer 140 , the first mask layer 130 and the dummy gate layer 120 in sequence by photolithography and etching to form a plurality of the initial dummy gate structures 210 .

[0054] Specifically, refer to Figure 2 and Figure 3 , each of the initial dummy gate structures 210 obtained after executing step S1 includes a dummy gate layer 120, a first mask layer 130, and a second mask layer 140. During the etching process of the initial dummy gate structure 210, if the target dummy gates prepared have different structures, the etching speeds of the mask layers in the initial dummy gate structure 210 will be different, which will lead to a loading effect, resulting in different thicknesses of the second mask layer 140 in the initial dummy gate structure 210, that is, different heights of the initial dummy gate structures 210 formed in the end. The different structures of the target dummy gates refer to different cross-sectional widths or different cross-sectional areas of the target dummy gates.

[0055] In some specific embodiments of the present invention, reference Figure 2 and Figure 3 In step S1 , the removal rate of the first mask layer 130 is controlled to be greater than the removal rate of the second mask layer 140 , so as to make the size of the target dummy gate structure more accurate.

[0056] In some specific embodiments of the present invention, reference Figure 2 and Figure 3 The step S12 further includes the step of spin-coating a photoresist 101 on the upper surface of the second mask layer 140 to form a pattern for defining the shape of the initial dummy gate structure 210 .

[0057] In some possible embodiments of the present invention, reference Figure 3 After the step S1 is executed, the isolation layer 111 covered by the dummy gate layer 120 is exposed. The isolation layer 111 is disposed on the upper surface of the substrate 110 .

[0058] In some possible embodiments of the present invention, reference Figure 3 Between step S1 and step S2 , a step is further included: forming a source 112 and a drain 113 in the substrate 110 , and electrically connecting the source 112 and the drain 113 to the dummy gate layer 120 .

[0059] In some specific embodiments of the present invention, the material of the first mask layer is silicon nitride, and the material of the second mask layer is silicon oxide. Modification of the silicon oxide is relatively easy, and it is easier to achieve substantially the same etching rate for the modified mask layer and the first mask layer in the subsequent chemical mechanical planarization process in step S4.

[0060] Figure 4 For Figure 3 Schematic diagram of the structure obtained after an organic thin film is formed on the structure shown; Figure 5 For Figure 4 Schematic diagram of the structure obtained after the organic thin film in the structure shown is etched back; Figure 6 For Figure 5 A schematic diagram of the structure obtained after the second mask layer in the structure shown is modified; Figure 7 For Figure 6 Schematic diagram of the structure obtained after removing the remaining organic film in the structure shown.

[0061] In some embodiments of the present invention, the step of modifying the second mask layer in step S2 to obtain a modified mask layer includes: Figures 4 to 7 :

[0062] S21: forming an organic film 150 on the upper surface of the substrate 110 and the surface of the initial dummy gate structure 210, and making the organic film 150 cover the second mask layer 140, and the obtained structure is as follows: Figure 4 As shown;

[0063] S22: The organic film 150 is etched back until the entire second mask layer 140 is exposed. The resulting structure is as follows: Figure 5 As shown;

[0064] S23: Modify the second mask layer 140 to obtain a modified mask layer 141. The obtained structure is as follows: Figure 6 As shown;

[0065] S24: Remove the remaining portion of the organic film 150, and the resulting structure is as follows Figure 7 shown.

[0066] Specifically, refer to Figures 4 to 7 Each of the initial dummy gate structures 210 obtained after executing step S2 includes the dummy gate layer 120 , the first mask layer 130 and the modified mask layer 141 .

[0067] The step S2 not only ensures that the etching speeds of the modified mask layer and the first mask layer in the chemical mechanical planarization process of the subsequent step S4 are basically the same, which is conducive to obtaining several pseudo-gate structures with the same height, but also during the modification process of the second mask layer, the organic film can protect the structure it covers and wraps, thereby preventing damage and affecting the performance of the device.

[0068] In some possible embodiments of the present invention, a ratio of a removal rate of the modified mask layer formed in step S2 to a removal rate of the first mask layer is 0.9:1 to 1:1.

[0069] In some specific embodiments of the present invention, reference Figure 4 In step S21, an organic film 150 is formed on the upper surface of the substrate 110 and the surface of the initial dummy gate structure 210 by spin coating, and the organic film 150 covers the upper surface of the substrate 110 and encapsulates the initial dummy gate structure 210.

[0070] In some possible embodiments of the present invention, the distance between the upper surface of the organic film formed in step S21 and the upper surface of the second mask layer in the highest initial dummy gate structure is 500-1000 Å. This allows the organic film to completely fill the trenches generated during the formation of the initial dummy gate structure, thereby ensuring the flatness of the surface of the initial dummy gate structure.

[0071] Specifically, refer to Figure 4 The initial dummy gate structure 210 includes a first initial dummy gate structure 211, a second initial dummy gate structure 212, and a third initial dummy gate structure 213. The first initial dummy gate structure 211 is the highest of the initial dummy gate structures 210. A distance L1 between the upper surface of the organic film and the upper surface of the second mask layer 140 in the first initial dummy gate structure 211 is 500-1000 Å.

[0072] In some embodiments of the present invention, after the organic thin film is etched back in step S22, the upper surface of the remaining portion of the organic thin film is not lower than the upper surface of the dummy gate layer. This protects the dummy gate layer, substrate, and other underlying structures covered by the remaining portion of the organic thin film, thereby preventing lateral damage to these structures during the modification process, which could affect device performance.

[0073] In some specific embodiments of the present invention, reference Figure 5 After the organic film 150 is etched back in step S22 , the upper surface of the remaining portion of the organic film 150 is flush with the upper surface of the first mask layer 130 .

[0074] In some other specific embodiments of the present invention, after the organic thin film is etched back in step S22 , the upper surface of the remaining portion of the organic thin film is flush with the upper surface of the dummy gate layer.

[0075] In some further specific embodiments of the present invention, after the organic thin film is etched back in step S22 , the upper surface of the remaining portion of the organic thin film is disposed between the upper surface of the dummy gate layer and the upper surface of the first mask layer.

[0076] In some embodiments of the present invention, in step S23 , the second mask layer is modified by ion implantation or chemical treatment.

[0077] In some possible embodiments of the present invention, step S23 modifies the second mask layer using vertical ion implantation, where the ions used include nitrogen ions. This allows for precise control and avoids side damage to the dummy gate layer, substrate, and other underlying structures covered by the organic thin film during the modification process, thereby impacting device performance.

[0078] In some specific embodiments of the present invention, the material of the first mask layer includes silicon nitride, and the material of the second mask layer includes silicon oxide; the second mask layer is modified by vertical ion implantation and using N ions to obtain a modified mask layer composed of silicon oxynitride material, thereby achieving basically the same etching speed of the modified mask layer and the first mask layer in the chemical mechanical planarization process of the subsequent step S4.

[0079] In some embodiments of the present invention, the organic thin film is made of spin-on carbon (SOC), an organic material grown by spin coating. The film made of this material has good fluidity and can completely fill the grooves formed during the initial formation of the dummy gate structure.

[0080] Figure 8 For Figure 7 Schematic diagram of the structure obtained after forming a barrier layer and a filling layer on the structure shown.

[0081] In some specific embodiments of the present invention, reference Figure 8 In step S3, the barrier layer 160 is deposited to cover the upper surface of the substrate 110 and the surface of the initial dummy gate structure 210. The barrier layer 160 protects the first mask layer 130, the modified mask layer 141, the dummy gate layer 120, and other structures disposed within the substrate 110, thereby preventing damage during the chemical mechanical planarization process that could affect device performance.

[0082] In some embodiments of the present invention, reference Figure 8 In step S3 , the filling layer 170 is deposited on the upper surface of the barrier layer 160 , so that the upper surface of the filling layer 170 is higher than the barrier layer 160 located on the upper surface of the highest initial dummy gate structure 210 .

[0083] In some possible embodiments of the present invention, the distance between the upper surface of the filling layer 170 formed in step S3 and the upper surface of the barrier layer 160 located on the upper surface of the highest initial dummy gate structure 210 is not less than twice the thickness of the highest initial dummy gate structure 210. This is beneficial for obtaining a highly uniform dummy gate structure after the chemical mechanical planarization process.

[0084] In some embodiments of the present invention, the step of using a chemical mechanical planarization process in step S4 to remove a portion of the filling layer, a portion of the barrier layer, the modified mask layer, the first mask layer, and a portion of the dummy gate layer to obtain a plurality of dummy gate structures of the same height includes:

[0085] S41: performing a first chemical mechanical planarization process to remove a portion of the filling layer until the barrier layer located on the upper surface of the highest initial dummy gate structure is exposed, and making the removal rate of the filling layer greater than the removal rate of the barrier layer;

[0086] S42: Performing a second chemical mechanical planarization process to remove part of the filling layer, part of the barrier layer, the modified mask layer, the first mask layer, and part of the dummy gate layer, and making the removal rate of the filling layer lower than the removal rate of the barrier layer, so as to obtain a plurality of dummy gate structures with the same height. This can overcome the load effect caused by the height difference of the initial dummy gate structures with different front ends, and obtain a higher precision planarization effect. In addition, through the two chemical mechanical planarization processes, the concave defects caused by the chemical mechanical planarization process can be effectively eliminated, that is, through the second chemical mechanical planarization process, the concave defects caused by the first chemical mechanical planarization process can be effectively eliminated, and finally a highly consistent dummy gate structure is obtained.

[0087] Figure 9 For Figure 8 Schematic diagram of the structure obtained after the first step of chemical mechanical planarization process is performed on the structure shown; Figure 10 For Figure 9 Schematic diagram of the structure obtained after the structure shown undergoes the second step chemical mechanical planarization process.

[0088] In some specific embodiments of the present invention, reference Figure 9 and Figure 10In step S41, a first chemical mechanical planarization process is performed until the barrier layer 160 located on the upper surface of the highest initial dummy gate structure 210 is exposed, that is, the barrier layer 160 located on the upper surface of the first initial dummy gate structure 211 is exposed. Since the removal rate of the filling layer 170 is greater than the removal rate of the barrier layer 160, at this time, the filling layer 170 located on the upper surface of the second initial dummy gate structure 212 and the third initial dummy gate structure 213 at a lower height will be removed more than the filling layer 170 located on the upper surface of the first initial dummy gate structure 211 at a higher height, so that a butterfly-shaped recess 171 is formed in the upper surface area of ​​the second initial dummy gate structure 212 and the third initial dummy gate structure 213, and the obtained structure is as shown. Figure 9 In the second chemical mechanical planarization process in step S42, since the removal rate of the filling layer 170 is lower than the removal rate of the barrier layer 160, the butterfly-shaped recess 171 caused by the first chemical mechanical planarization process can be effectively repaired, and finally a highly consistent pseudo gate structure 230 is obtained. The obtained structure is as shown in FIG. Figure 10 As shown. The dummy gate structure 230 includes a first dummy gate structure 231, a second dummy gate structure 232, and a third dummy gate structure 233. After the second chemical mechanical planarization process in step S42, the upper surfaces of the dummy gate layers (not shown in the figure) of the dummy gate structures 230 are flush, that is, the first dummy gate structure 231, the second dummy gate structure 232, and the third dummy gate structure 233 are at the same height.

[0089] In some embodiments of the present invention, the step of performing a first chemical mechanical planarization process in step S41 includes controlling the ratio of the removal rate of the filling layer to the removal rate of the barrier layer to be 20:1 to 100:1. This removes a portion of the filling layer to expose the barrier layer located on the upper surface of the highest initial dummy gate structure. Specifically, the polishing liquid in the first chemical mechanical planarization process is a cerium oxide-based or silicon oxide-based polishing liquid with an acidic pH.

[0090] In some embodiments of the present invention, the step of performing a second chemical mechanical planarization process in step S42 includes: controlling the ratio of the removal rate of the barrier layer to the removal rate of the filling layer to be 2:1 to 3:1, controlling the ratio of the removal rate of the barrier layer to the removal rate of the dummy gate layer to be 10:1 to 20:1, and controlling the ratio of the removal rate of the barrier layer to the removal rate of the modified mask layer to be 0.9:1 to 1:1. Furthermore, the removal rate of the barrier layer is controlled to be the same as the removal rate of the first mask layer. Specifically, the pH value of the polishing liquid in the second chemical mechanical planarization process is acidic. Since the removal rate of the barrier layer is faster than the removal rate of the filling layer, the butterfly defects in the area on the upper surface of the initial dummy gate structure at a lower height caused by the first chemical mechanical planarization process can be effectively repaired, and finally a highly consistent dummy gate layer is obtained.

[0091] In some specific embodiments of the present invention, the material of the blocking layer and the material of the first mask layer are the same, both being silicon nitride, the material of the filling layer is silicon oxide, and the material of the modified mask layer is silicon oxynitride.

[0092] In some embodiments of the present invention, the thickness of the portion of the dummy gate layer removed in step S4 is less than 100 Å.

[0093] In some embodiments of the present invention, step S4 may further include the following steps: removing the dummy gate structure to form a dummy gate trench, and then depositing a gate filling material in the dummy gate trench to obtain a gate.

[0094] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A pseudo-gate planarization method, characterized in that: Including steps: S1: etching to form a plurality of initial dummy gate structures, wherein the initial dummy gate structures include a dummy gate layer, a first mask layer, and a second mask layer sequentially disposed on a surface of a substrate, and the materials of the first mask layer and the second mask layer are different; S2: modifying the second mask layer to obtain a modified mask layer, including S21: forming an organic thin film on the upper surface of the substrate and the surface of the initial dummy gate structure, and making the organic thin film cover the second mask layer; S22: performing a back etching process on the organic thin film until the entire second mask layer is exposed; S23: modifying the second mask layer to obtain a modified mask layer; S24: removing the remaining portion of the organic thin film; S3: after forming a barrier layer covering the upper surface of the substrate and the surface of the initial dummy gate structure, forming a filling layer on the upper surface of the barrier layer, and making the filling layer cover the barrier layer; S4: Using a chemical mechanical planarization process to remove part of the filling layer, part of the blocking layer, the modified mask layer, the first mask layer and part of the dummy gate layer to obtain several dummy gate structures with the same height, including: S41: performing a first chemical mechanical planarization process to remove part of the filling layer until the blocking layer located on the upper surface of the highest initial dummy gate structure is exposed, and making the removal rate of the filling layer greater than the removal rate of the blocking layer; S42: performing a second chemical mechanical planarization process to remove part of the filling layer, part of the blocking layer, the modified mask layer, the first mask layer and part of the dummy gate layer, and making the removal rate of the filling layer less than the removal rate of the blocking layer to obtain several dummy gate structures with the same height.

2. The dummy gate planarization method according to claim 1, wherein: The ratio of the removal rate of the modified mask layer formed in step S2 to the removal rate of the first mask layer is 0.9:1 to 1:

1.

3. The dummy gate planarization method according to claim 1, wherein: The step of performing the first chemical mechanical planarization process in step S41 includes controlling the ratio of the removal rate of the filling layer to the removal rate of the barrier layer to be 20:1-100:

1.

4. The dummy gate planarization method according to claim 1, wherein: The steps of performing a second chemical mechanical planarization process in step S42 include: controlling the ratio of the removal rate of the barrier layer to the removal rate of the filling layer to be 2:1~3:1, controlling the ratio of the removal rate of the barrier layer to the removal rate of the dummy gate layer to be 10:1~20:1, and controlling the ratio of the removal rate of the barrier layer to the removal rate of the modified mask layer to be 0.9:1~1:

1.

5. The dummy gate planarization method according to claim 1, wherein: After the organic thin film is etched back in step S22 , the upper surface of the remaining portion of the organic thin film is not lower than the upper surface of the dummy gate layer.

6. The dummy gate planarization method according to claim 1, wherein: In the step S23 , the second mask layer is modified by ion implantation or chemical treatment.

7. The dummy gate planarization method according to claim 1, wherein: In step S23 , the second mask layer is modified by vertical ion implantation. The ions used in the vertical ion implantation include N ions. The material of the first mask layer includes silicon nitride, and the material of the second mask layer includes silicon oxide.

8. The dummy gate planarization method according to claim 1, wherein: The distance between the upper surface of the filling layer formed in step S3 and the upper surface of the barrier layer located on the upper surface of the highest initial dummy gate structure is not less than twice the thickness of the highest initial dummy gate structure.

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