Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present invention relates to the field of semiconductor technology, and proposes a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing a semiconductor structure comprises: providing a substrate, on which an isolation trench is formed; forming a silicon-rich isolation layer in the isolation trench, the silicon-rich isolation layer covering the inner surface of the isolation trench; forming an isolation oxide layer in the isolation trench; wherein the isolation oxide layer fills the isolation trench. The formation of the silicon-rich isolation layer can ensure the size of the active area and increase the depth of the isolation trench, thereby enhancing the isolation effect and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the existing shallow trench isolation (STI) technology, the shallow trench leads to poor isolation effect, while the small size of the active area limits the device connection. It is difficult for the process in the related art to achieve a deeper trench while increasing the size of the active area accordingly. Therefore, the trench structure in the existing technology is difficult to meet the performance requirements of the semiconductor structure. Summary of the invention

[0003] The invention provides a manufacturing method of a semiconductor structure and a semiconductor structure to improve the performance of the semiconductor structure.

[0004] According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, comprising:

[0005] Providing a substrate, on which an isolation trench is formed;

[0006] forming a silicon-rich isolation layer in the isolation trench, wherein the silicon-rich isolation layer covers the inner surface of the isolation trench;

[0007] forming an isolation oxide layer in the isolation trench;

[0008] The isolation oxide layer fully fills the isolation trench.

[0009] In one embodiment of the present invention, forming an isolation oxide layer in an isolation trench includes:

[0010] forming a first isolation oxide layer in the isolation trench, wherein at least a portion of the first isolation oxide layer is formed by oxidizing the silicon-rich isolation layer;

[0011] A second isolation oxide layer is formed in the isolation trench, the second isolation oxide layer covers the first isolation oxide layer, and the first isolation oxide layer and the second isolation oxide layer serve as isolation oxide layers.

[0012] In one embodiment of the present invention, after the first isolation oxide layer is formed in the isolation trench, the silicon-rich isolation layer is completely oxidized into the first oxide layer.

[0013] In one embodiment of the present invention, forming a first isolation oxide layer includes:

[0014] forming a second oxide layer in the isolation trench, the second oxide layer covering the silicon-rich isolation layer, and after the second oxide layer is formed, a portion of the silicon-rich isolation layer is oxidized into the first oxide layer;

[0015] oxidizing the silicon-rich isolation layer by an in-situ water vapor generation process, wherein at least a portion of the silicon-rich isolation layer is oxidized into a first oxide layer after the in-situ water vapor generation process is completed;

[0016] forming a third oxide layer in the isolation trench, wherein the third oxide layer covers the second oxide layer;

[0017] After the third oxide layer is formed, the silicon-rich isolation layer is completely oxidized into the first oxide layer, and the first oxide layer, the second oxide layer and the third oxide layer serve as the first isolation oxide layer.

[0018] In one embodiment of the present invention, the isolation channel includes a first isolation channel and a second isolation channel, and the width of the first isolation channel is greater than the width of the second isolation channel;

[0019] The first oxide layer, the second oxide layer, the third oxide layer and the second isolation oxide layer are used as the first isolation channel oxide layer to fill the first isolation channel, and the first oxide layer, the second oxide layer and the third oxide layer are used as the second isolation channel oxide layer to fill the second isolation channel.

[0020] In one embodiment of the present invention, the second oxide layer and the third oxide layer are both formed by an atomic deposition process.

[0021] In one embodiment of the present invention, the second isolation oxide layer is formed by a spin-on dielectric layer process.

[0022] In one embodiment of the present invention, the silicon-rich isolation layer is a polysilicon layer.

[0023] In one embodiment of the present invention, the silicon-rich isolation layer covering the sidewall of the isolation trench has the same thickness from the bottom of the isolation trench to the top of the isolation trench.

[0024] In one embodiment of the present invention, the silicon-rich isolation layer covering the sidewall of the isolation trench gradually increases in thickness from the bottom of the isolation trench to the top of the isolation trench.

[0025] In one embodiment of the present invention, the silicon-rich isolation layer is formed by a low step coverage furnace process.

[0026] According to a second aspect of the present invention, there is provided a semiconductor structure, comprising:

[0027] A substrate, on which an isolation channel and a plurality of active regions are formed, wherein the isolation channel is located between the plurality of active regions;

[0028] An isolation oxide layer, the isolation oxide layer is located in the isolation trench, the isolation oxide layer includes a first isolation oxide layer and a second isolation oxide layer, and the first isolation oxide layer covers the inner surface of the isolation trench;

[0029] Wherein, at least a portion of the first isolation oxide layer is formed by oxidation of a silicon-rich isolation layer covering the inner surface of the isolation trench.

[0030] In one embodiment of the present invention, the isolation channel includes a first isolation channel and a second isolation channel, and the width of the first isolation channel is greater than the width of the second isolation channel;

[0031] The first isolation trench is filled with a first isolation oxide layer and a second isolation oxide layer, and the second isolation trench is filled with the first isolation oxide layer.

[0032] The manufacturing method of the semiconductor structure of the present invention forms a silicon-rich isolation layer in the isolation trench first, and then forms an isolation oxide layer. The silicon-rich isolation layer can prevent oxidation of the substrate during the formation of the isolation oxide layer, that is, the isolation oxide layer finally formed will not occupy the area where the active area is located, thereby ensuring the size of the active area. In addition, due to the isolation effect of the silicon-rich isolation layer, the depth of the isolation trench can be increased under process-permitted conditions, thereby enhancing the isolation effect and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various objects, features and advantages of the present invention will become more apparent by considering the following detailed description of preferred embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present invention and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0034] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0035] Figure 2 is a top view of a semiconductor structure according to an exemplary embodiment;

[0036] Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure at AA in the middle;

[0037] Figure 4 is a structural schematic diagram of forming an isolation channel in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0038] Figure 5 is a structural schematic diagram of forming a silicon-rich isolation layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0039] Figure 6 is a structural schematic diagram of forming a second oxide layer according to a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0040] Figure 7is a schematic structural diagram of a method for manufacturing a semiconductor structure through an in-situ water vapor generation process according to an exemplary embodiment;

[0041] Figure 8 is a structural schematic diagram of forming a third oxide layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0042] Fig. 9 is a structural schematic diagram of forming a second isolation oxide layer by a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0043] Fig.10 is a structural schematic diagram of forming a silicon-rich isolation layer in a method for manufacturing a semiconductor structure according to another exemplary embodiment;

[0044] Fig.11 is a structural schematic diagram of forming a second oxide layer in a method for manufacturing a semiconductor structure according to another exemplary embodiment;

[0045] Fig.12 is a schematic structural diagram of a method for manufacturing a semiconductor structure through an in-situ water vapor generation process according to another exemplary embodiment;

[0046] Fig.13 is a structural schematic diagram of forming a third oxide layer in a method for manufacturing a semiconductor structure according to another exemplary embodiment;

[0047] Fig.14 is a structural schematic diagram of forming a second isolation oxide layer in a method for manufacturing a semiconductor structure according to another exemplary embodiment.

[0048] The following are the descriptions of the reference numerals:

[0049] 10. substrate; 11. isolation channel; 111. first isolation channel; 112. second isolation channel; 12. active area; 20. silicon-rich isolation layer; 30. isolation oxide layer; 31. first isolation oxide layer; 32. second isolation oxide layer; 33. first oxide layer; 34. second oxide layer; 35. third oxide layer. DETAILED DESCRIPTION

[0050] Typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments without departing from the scope of the present invention, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present invention.

[0051] In the following description of different exemplary embodiments of the present invention, reference is made to the accompanying drawings, which form a part of the present invention and in which different exemplary structures, systems and steps that can implement various aspects of the present invention are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present invention. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present invention, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present invention.

[0052] An embodiment of the present invention provides a method for manufacturing a semiconductor structure. Figure 1 , a method for manufacturing a semiconductor structure comprises:

[0053] S101, providing a substrate 10, on which an isolation trench 11 is formed;

[0054] S103, forming a silicon-rich isolation layer 20 in the isolation trench 11, wherein the silicon-rich isolation layer 20 covers the inner surface of the isolation trench 11;

[0055] S105, forming an isolation oxide layer 30 in the isolation trench 11;

[0056] The isolation oxide layer 30 completely fills the isolation trench 11 .

[0057] In a method for manufacturing a semiconductor structure according to an embodiment of the present invention, a silicon-rich isolation layer 20 is first formed in an isolation trench 11, and then an isolation oxide layer 30 is formed. The silicon-rich isolation layer 20 can prevent oxidation of the substrate 10 during the process of forming the isolation oxide layer 30, that is, the isolation oxide layer 30 finally formed will not occupy the area where the active area 12 is located, thereby ensuring the size of the active area 12. Due to the isolation effect of the silicon-rich isolation layer 20, the depth of the isolation trench 11 can be increased under process conditions, thereby enhancing the isolation effect and improving the performance of the semiconductor structure.

[0058] It should be noted that, due to the limitation of the etching process, the size of the isolation trench 11 on the substrate 10 has a limit value, that is, the minimum size is limited. If the size of the isolation trench 11 is etched to the minimum size, at this time, if the isolation oxide layer 30 is formed according to the formation process of the related technology, the substrate 10 will be oxidized during the formation of the isolation oxide layer 30, thereby occupying the area where the active area 12 is located. Therefore, it is difficult to achieve the deepening of the isolation trench 11 and the enlargement of the size of the active area 12 by adjusting the etching depth-to-width ratio in the related technology.

[0059] The manufacturing method of the semiconductor structure of the present invention can utilize the isolation channel 11 of minimum size, firstly form a silicon-rich isolation layer 20 covering the inner surface of the isolation channel 11, and then form an isolation oxide layer 30. Even if oxidation occurs during the process of forming the isolation oxide layer 30, it is oxidation of the silicon-rich isolation layer 20, and oxidation of the substrate 10 will not occur.

[0060] It should be noted that the silicon-rich isolation layer 20 will be oxidized during the formation of the isolation oxide layer 30, that is, the isolation oxide layer 30 includes a thin film formed after the silicon-rich isolation layer 20 is oxidized. In this embodiment, after the isolation oxide layer 30 is formed in the isolation trench 11, the silicon-rich isolation layer 20 is completely oxidized to become a part of the isolation oxide layer 30.

[0061] The formation process of the isolation oxide layer 30 may include an atomic layer deposition (ALD) process, an in-situ steam generation (ISSG) process, a spin on dielectric (SOD) process, etc.

[0062] In one embodiment, the substrate 10 may be formed of a silicon-containing material. The substrate 10 may be formed of any suitable material, for example, at least one of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.

[0063] It should be noted that after etching the isolation trench 11 on the substrate 10, a silicon-rich isolation layer 20 can be formed in the isolation trench 11 by using a chemical vapor deposition (CVD) process. In one embodiment, forming an isolation oxide layer 30 in the isolation trench 11 includes: forming a first isolation oxide layer 31 in the isolation trench 11, wherein at least a portion of the first isolation oxide layer 31 is formed by oxidation of the silicon-rich isolation layer 20; forming a second isolation oxide layer 32 in the isolation trench 11, wherein the second isolation oxide layer 32 covers the first isolation oxide layer 31, and the first isolation oxide layer 31 and the second isolation oxide layer 32 serve as the isolation oxide layer 30.

[0064] Specifically, in the process of forming the first isolation oxide layer 31, an atomic layer deposition process, an in-situ water vapor generation process and other processes are used to oxidize the silicon-rich isolation layer 20, thereby forming the first isolation oxide layer 31, that is, on the basis of preventing oxidation of the substrate 10, the silicon-rich isolation layer 20 can be finally used as a part of the isolation oxide layer 30, thereby ensuring that the isolation oxide layer 30 has sufficient isolation capability. After the first isolation oxide layer 31 is formed, the second isolation oxide layer 32 is covered on the first isolation oxide layer 31, and the second isolation oxide layer 32 fills the remaining space of the isolation trench 11.

[0065] In one embodiment, after the first isolation oxide layer 31 is formed in the isolation trench 11, the silicon-rich isolation layer 20 is completely oxidized into the first oxide layer 33, that is, the first isolation oxide layer 31 includes a thin film formed after at least a portion of the silicon-rich isolation layer 20 is oxidized, and the first oxide layer 33 formed by the completely oxidized silicon-rich isolation layer 20 can ensure that the isolation oxide layer 30 has sufficient isolation capability.

[0066] Specifically, in the process of forming the first isolation oxide layer 31, the silicon-rich isolation layer 20 is completely oxidized. For example, in the process of forming the first isolation oxide layer 31 using an atomic layer deposition process or an in-situ water vapor generation process, the silicon-rich isolation layer 20 is gradually oxidized, and finally the first isolation oxide layer 31 is completely formed.

[0067] In one embodiment, forming the first isolation oxide layer 31 includes: forming a second oxide layer 34 in the isolation trench 11, the second oxide layer 34 covers the silicon-rich isolation layer 20, and after the second oxide layer 34 is formed, part of the silicon-rich isolation layer 20 is oxidized into the first oxide layer 33; oxidizing the silicon-rich isolation layer 20 through an in-situ water vapor generation process, after the in-situ water vapor generation process is completed, at least part of the silicon-rich isolation layer 20 is oxidized into the first oxide layer 33; forming a third oxide layer 35 in the isolation trench 11, the third oxide layer 35 covers the second oxide layer 34; wherein, after the third oxide layer 35 is formed, the silicon-rich isolation layer 20 is completely oxidized into the first oxide layer 33. The first oxide layer 33, the second oxide layer 34, and the third oxide layer 35 serve as the first isolation oxide layer 31.

[0068] Specifically, the formation process of the first isolation oxide layer 31 mainly includes three steps, namely, firstly, forming a second oxide layer 34 on the inner surface of the silicon-rich isolation layer 20, and this process may also oxidize a portion of the silicon-rich isolation layer 20, and treating the silicon-rich isolation layer 20 through an in-situ water vapor generation process. At this time, the silicon-rich isolation layer 20 is at least partially oxidized into a first oxide layer 33. Finally, a third oxide layer 35 is formed on the surface of the second oxide layer 34. The first oxide layer 33, the second oxide layer 34 and the third oxide layer 35 constitute the first isolation oxide layer 31.

[0069] In one embodiment, the second oxide layer 34 and the third oxide layer 35 are both formed by an atomic deposition process, that is, the second oxide layer 34 is formed on the surface of the silicon-rich isolation layer 20 by an atomic deposition process, and after the silicon-rich isolation layer 20 is oxidized by an in-situ water vapor generation process to form the first oxide layer 33, the third oxide layer 35 is formed on the surface of the second oxide layer 34 by an atomic deposition process.

[0070] In one embodiment, the second isolation oxide layer 32 is formed by a spin-on dielectric layer process, that is, after the first isolation oxide layer 31 is formed, the second isolation oxide layer 32 is formed in the isolation trench 11 by a spin-on dielectric layer process. At this time, the empty area of ​​the isolation trench 11 is completely filled, and the second isolation oxide layer 32 covers the first isolation oxide layer 31 located on the upper surface of the substrate 10.

[0071] It should be noted that the second oxide layer 34 is formed on the inner surface of the silicon-rich isolation layer 20 and the upper surface of the substrate 10 by an atomic deposition process. Figure 6 and Fig.11 The uniformity of the film formed by the atomic layer process is particularly good, that is, the uniformity of the second oxide layer 34 can be guaranteed to meet the requirements. The silicon-rich isolation layer 20 is oxidized by the in-situ water vapor generation process to form the first oxide layer 33 inside the second oxide layer 34. For details, see Figure 7 and Fig.12 The in-situ water vapor generation process is to perform annealing by H2 / O2, which can ensure that most of the silicon-rich isolation layer 20 is oxidized, and can increase the density of the second oxide layer 34 to ensure the effect of the isolation oxide layer. The third oxide layer 35 is formed on the inner surface of the second oxide layer 34 and the second oxide layer 34 located on the upper surface of the substrate 10 by an atomic deposition process. For details, see Figure 8 and Fig.13 Finally, the second isolation oxide layer 32 is formed on the inner surface of the third oxide layer 35 and the third oxide layer 35 located on the upper surface of the substrate 10 by spin-coating a dielectric layer process. Fig. 9 and Fig.14 The spin-on dielectric layer process can ensure that the isolation trench 11 is fully filled, and an annealing process is added later to ensure the formation of silicon oxide.

[0072] In one embodiment, Figure 2 and Figure 3As shown, a plurality of active areas 12 are formed on the substrate 10, and an isolation channel 11 is located between the plurality of active areas 12. The isolation channel 11 includes a first isolation channel 111 and a second isolation channel 112. The width of the first isolation channel 111 is greater than the width of the second isolation channel 112, and the depth of the first isolation channel 111 is greater than the depth of the second isolation channel 112, that is, the filling amount in the first isolation channel 111 is greater than the filling amount in the second isolation channel 112.

[0073] In one embodiment, the first oxide layer 33, the second oxide layer 34, the third oxide layer 35 and the second isolation oxide layer 32 are used as the first isolation channel oxide layer to fill the first isolation channel 111. Since the width of the first isolation channel 111 is relatively large, some areas will not be filled after the first oxide layer 33, the second oxide layer 34 and the third oxide layer 35 are formed, so it is necessary to form the second isolation oxide layer 32 by a spin-on dielectric layer process for filling.

[0074] In one embodiment, the first oxide layer 33, the second oxide layer 34 and the third oxide layer 35 are used as the second isolation channel oxide layer to fill the second isolation channel 112. Since the width of the second isolation channel 112 is relatively small, the second isolation channel 112 can be completely filled after the first oxide layer 33, the second oxide layer 34 and the third oxide layer 35 are formed. Of course, it is not excluded that after the first isolation oxide layer 31 is formed, there is still an unfilled area in the second isolation channel 112, and this area is filled by the second isolation oxide layer 32.

[0075] In one embodiment, the isolation oxide layer 30 is a silicon dioxide layer.

[0076] In one embodiment, the silicon-rich isolation layer 20 is a polysilicon layer, which is oxidized to form a silicon dioxide layer through a subsequent process.

[0077] In one embodiment, the silicon-rich isolation layer 20 is formed by a furnace process.

[0078] In one embodiment, forming the silicon-rich isolation layer 20 includes: introducing C6H17NSi into a furnace tube to form a seed crystal on the surface of the isolation channel 11 ; introducing Si2H4 into the furnace tube to form the silicon-rich isolation layer 20 on the inner surface of the isolation channel 11 .

[0079] Specifically, C6H17NSi is introduced into the furnace tube, the reaction time is controlled to be 8min-12min, and the temperature is controlled to be 400℃-440℃, so that the seed crystal is quickly grown on the surface of the substrate 10. In this embodiment, the reaction time is controlled to be 10min, and the temperature is controlled to be 420℃. Then Si2H4 is introduced, the reaction time is controlled to be 8min-12min, and the temperature is controlled to be 400℃-440℃, so as to form the silicon-rich isolation layer 20. In this embodiment, the reaction time is controlled to be 10min, and the temperature is controlled to be 420℃.

[0080] In one embodiment, the silicon-rich isolation layer 20 covering the sidewalls of the isolation trench 11 has the same thickness from the bottom of the isolation trench 11 to the top of the isolation trench 11 , that is, a silicon-rich isolation layer 20 with uniform thickness is formed on the surface of the substrate 10 .

[0081] It should be noted that the thickness of the silicon-rich isolation layer 20 located at the bottom of the isolation trench 11 may also be equal to the thickness of the silicon-rich isolation layer 20 covering the sidewalls of the isolation trench 11 .

[0082] Specifically, the manufacturing method of the semiconductor structure in this embodiment includes:

[0083] like Figure 4 As shown, an isolation channel 11 is etched on the substrate 10, and the isolation channel 11 includes a first isolation channel 111 and a second isolation channel 112. The depth and width of the first isolation channel 111 are greater than the depth and width of the second isolation channel 112, wherein the depth of the first isolation channel 111 can be 260nm-300nm, and the depth of the second isolation channel 112 can be 225nm-265nm.

[0084] exist Figure 4 On the basis of, a silicon-rich isolation layer 20 is formed in the isolation trench 11 by using a chemical vapor deposition process, such as Figure 5 As shown, the thickness of the silicon-rich isolation layer 20 is consistent, and the thickness of the silicon-rich isolation layer 20 can be 2.3nm-3.1nm.

[0085] exist Figure 5 On the basis of, an atomic layer deposition process is used to form a second oxide layer 34 on the inner surface of the silicon-rich isolation layer 20 and the upper surface of the substrate 10, such as Figure 6 As shown, part of the silicon-rich isolation layer 20 is oxidized during this process (considering that less part of the silicon-rich isolation layer 20 is oxidized during this process, Figure 6 The oxidized portion of the silicon-rich isolation layer 20 is not shown).

[0086] exist Figure 6 Based on the above, the silicon-rich isolation layer 20 is oxidized by an in-situ water vapor generation process to form a first oxide layer 33, such as Figure 7 As shown, at least a portion of the silicon-rich isolation layer 20 is oxidized to form a first oxide layer 33 ( Figure 7 In the embodiment, the silicon-rich isolation layer 20 is completely oxidized by an in-situ water vapor generation process).

[0087] exist Figure 7 On the basis of, the third oxide layer 35 is formed by an atomic layer deposition process, such as Figure 8 As shown, if there is an unoxidized silicon-rich isolation layer 20 after the in-situ water vapor generation process, it is all oxidized during this process, and the first oxide layer 33 , the second oxide layer 34 and the third oxide layer 35 serve as the first isolation oxide layer 31 .

[0088] exist Figure 8 On the basis of, a second isolation oxide layer 32 is formed by a spin coating process, forming Fig. 9 As shown, the first isolation oxide layer 31 and the second isolation oxide layer 32 are used as the isolation oxide layer 30 to fill the isolation trench 11, that is, finally forming the following Figure 2 and Figure 3 The semiconductor structure shown. (The isolation oxide layers 30 are all made of the same material, such as silicon oxide).

[0089] It should be noted that after forming the first isolation oxide layer 31 , the second isolation trench 112 has been completely filled. The second isolation oxide layer 32 is used to fill the first isolation trench 111 and cover the portion of the first isolation oxide layer 31 located on the upper surface of the substrate 10 .

[0090] In one embodiment, the silicon-rich isolation layer 20 covering the sidewall of the isolation trench 11 gradually increases in thickness from the bottom of the isolation trench 11 to the top of the isolation trench 11 , that is, a silicon-rich isolation layer 20 with a gradient thickness is formed on the surface of the substrate 10 .

[0091] In one embodiment, the silicon-rich isolation layer 20 is formed by a low step coverage furnace process, so that a silicon-rich isolation layer 20 with a gradient thickness can be formed on the surface of the substrate 10 .

[0092] It should be noted that the silicon-rich isolation layer 20 located at the upper part of the isolation channel 11 has the largest thickness, while the silicon-rich isolation layer 20 located at the lower part of the isolation channel 11 has the smallest thickness. Due to the limitations of the manufacturing process, the silicon-rich isolation layer 20 at the upper part of the isolation channel 11 is oxidized faster in the subsequent process. Therefore, this structure can ensure that the silicon-rich isolation layer 20 is oxidized synchronously without the problem of oxidizing the substrate 10.

[0093] Specifically, the manufacturing method of the semiconductor structure in this embodiment includes:

[0094] An isolation trench 11 is etched on the substrate 10. The specific structure and size of the isolation trench 11 can be referred to Figure 4 The structure shown will not be described in detail here.

[0095] exist Figure 4 On the basis of, a silicon-rich isolation layer 20 is formed in the isolation trench 11 by using a chemical vapor deposition process, such as Fig.10 As shown, the thickness of the silicon-rich isolation layer 20 is a gradient structure, and the thickness of the silicon-rich isolation layer 20 can be 2.3nm-3.1nm. In this embodiment, the thickness of the silicon-rich isolation layer 20 located at the upper portion of the isolation channel 11 can be 2.8nm-3.1nm, the thickness of the silicon-rich isolation layer 20 located in the middle portion of the isolation channel 11 can be 2.6nm-2.9nm, and the thickness of the silicon-rich isolation layer 20 located at the bottom of the isolation channel 11 can be 2.3nm-2.7nm.

[0096] exist Fig.10 On the basis of, an atomic layer deposition process is used to form a second oxide layer 34 on the inner surface of the silicon-rich isolation layer 20 and the upper surface of the substrate 10, such as Fig.11 As shown, part of the silicon-rich isolation layer 20 is oxidized during this process (considering that less part of the silicon-rich isolation layer 20 is oxidized during this process, Fig.11 The oxidized portion of the silicon-rich isolation layer 20 is not shown).

[0097] exist Fig.11 On the basis of, the silicon-rich isolation layer 20 is oxidized by an in-situ water vapor generation process to form a first oxide layer 33, such as Fig.12 As shown, at least a portion of the silicon-rich isolation layer 20 is oxidized to form a first oxide layer 33 ( Fig.12 In the embodiment, the silicon-rich isolation layer 20 is completely oxidized by an in-situ water vapor generation process).

[0098] exist Fig.12 On the basis of, the third oxide layer 35 is formed by an atomic layer deposition process, such as Fig.13 As shown, if there is an unoxidized silicon-rich isolation layer 20 after the first oxide layer 33 is formed, it is all oxidized during this process, and the first oxide layer 33 , the second oxide layer 34 and the third oxide layer 35 serve as the first isolation oxide layer 31 .

[0099] exist Fig.13 On the basis of, a second isolation oxide layer 32 is formed by a spin coating process, forming Fig.14 As shown, the first isolation oxide layer 31 and the second isolation oxide layer 32 are used as the isolation oxide layer 30 to fill the isolation trench 11, that is, finally forming the following Figure 2 and Figure 3 The semiconductor structure shown. (The isolation oxide layers 30 are all made of the same material, such as silicon oxide).

[0100] It should be noted that after forming the first isolation oxide layer 31 , the second isolation trench 112 has been completely filled. The second isolation oxide layer 32 is used to fill the first isolation trench 111 and cover the portion of the first isolation oxide layer 31 located on the upper surface of the substrate 10 .

[0101] In some embodiments, when the silicon-rich isolation layer 20 is oxidized by an in-situ water vapor generation process, part of the silicon-rich isolation layer 20 may not be oxidized. When the third oxide layer 35 is subsequently formed by an atomic layer deposition process, the unoxidized silicon-rich isolation layer 20 is completely oxidized into the first oxide layer 33.

[0102] It should be noted that Fig. 9 and Fig.14 In the semiconductor structure, the first isolation oxide layer 31 and the second isolation oxide layer 32 filled in the isolation trench 11 are made of the same material, that is, the first isolation oxide layer 31 and the second isolation oxide layer 32 constitute the isolation oxide layer 30, that is, the isolation oxide layer 30 can be silicon oxide, specifically as Figure 2 and Figure 3 shown. Figures 4 to 14 The focus is on explaining the manufacturing process of the semiconductor structure and does not represent the final form of the semiconductor structure.

[0103] The manufacturing method of the semiconductor structure of the present invention fills polysilicon in the isolation trench before filling silicon dioxide to prevent subsequent in-situ water vapor from generating and oxidizing the silicon in the active area, thereby increasing the length and width of the active area while effectively increasing the depth of the isolation trench. The obtained semiconductor structure improves the isolation effect to a certain extent and increases the area of ​​the active area.

[0104] An embodiment of the present invention further provides a semiconductor structure, please refer to Figure 2 , Figure 3 , Fig. 9 as well as Fig.14 , including: a substrate 10, on which an isolation channel 11 and multiple active areas 12 are formed, and the isolation channel 11 is located between the multiple active areas 12; an isolation oxide layer 30, the isolation oxide layer 30 is located in the isolation channel 11, and the isolation oxide layer 30 includes a first isolation oxide layer 31 and a second isolation oxide layer 32, and the first isolation oxide layer 31 covers the inner surface of the isolation channel 11; wherein, at least a portion of the first isolation oxide layer 31 is formed by oxidizing the silicon-rich isolation layer 20 covering the inner surface of the isolation channel 11.

[0105] The isolation oxide layer 30 of the semiconductor structure of one embodiment of the present invention is formed by a first isolation oxide layer 31 and a second isolation oxide layer 32, and at least a portion of the first isolation oxide layer 31 is formed by oxidation of the silicon-rich isolation layer 20 covering the inner surface of the isolation trench 11, that is, the isolation oxide layer 30 in the isolation trench 11 of the semiconductor structure will not occupy the area where the active area 12 is located, thereby ensuring the size of the active area 12. And due to the isolation effect of the silicon-rich isolation layer 20, the depth of the isolation trench 11 can be increased under process conditions, thereby enhancing the isolation effect and improving the performance of the semiconductor structure.

[0106] In one embodiment, the silicon-rich isolation layer 20 may be polysilicon, and the isolation oxide layer 30 may be silicon dioxide.

[0107] In one embodiment, Figure 4 As shown, the isolation channel 11 includes a first isolation channel 111 and a second isolation channel 112, and the width of the first isolation channel 111 is greater than the width of the second isolation channel 112; wherein the first isolation channel 111 is filled with a first isolation oxide layer 31 and a second isolation oxide layer 32, and the second isolation channel 112 is filled with the first isolation oxide layer 31. For details, see Figure 8 and Fig. 9 as well as Fig.13 and Fig.14 .

[0108] In one embodiment, the semiconductor structure is formed by the above-mentioned method for manufacturing the semiconductor structure.

[0109] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and example embodiments are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the preceding claims.

[0110] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, on which an isolation trench is formed; forming a silicon-rich isolation layer in the isolation trench, wherein the silicon-rich isolation layer covers an inner surface of the isolation trench; forming an isolation oxide layer in the isolation trench; Wherein, the isolation oxide layer fully fills the isolation trench; Wherein, forming an isolation oxide layer in the isolation trench comprises: forming a first isolation oxide layer in the isolation trench, wherein at least a portion of the first isolation oxide layer is formed by oxidizing the silicon-rich isolation layer; forming a second isolation oxide layer in the isolation trench, wherein the second isolation oxide layer covers the first isolation oxide layer, and the first isolation oxide layer and the second isolation oxide layer serve as the isolation oxide layer; Wherein, after the first isolation oxide layer is formed in the isolation trench, the silicon-rich isolation layer is completely oxidized into the first oxide layer; Wherein, forming the first isolation oxide layer comprises: forming a second oxide layer in the isolation trench, the second oxide layer covering the silicon-rich isolation layer, and after the second oxide layer is formed, a portion of the silicon-rich isolation layer is oxidized into the first oxide layer; oxidizing the silicon-rich isolation layer through an in-situ water vapor generation process, wherein after the in-situ water vapor generation process is completed, at least a portion of the silicon-rich isolation layer is oxidized into the first oxide layer; forming a third oxide layer in the isolation trench, wherein the third oxide layer covers the second oxide layer; After the third oxide layer is formed, the silicon-rich isolation layer is completely oxidized into the first oxide layer, and the first oxide layer, the second oxide layer and the third oxide layer serve as the first isolation oxide layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The isolation channel comprises a first isolation channel and a second isolation channel, and the width of the first isolation channel is greater than the width of the second isolation channel; The first oxide layer, the second oxide layer, the third oxide layer and the second isolation oxide layer are used as a first isolation channel oxide layer to fill the first isolation channel, and the first oxide layer, the second oxide layer and the third oxide layer are used as a second isolation channel oxide layer to fill the second isolation channel.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The second oxide layer and the third oxide layer are both formed by an atomic deposition process.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The second isolation oxide layer is formed by a spin-on dielectric layer process.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The silicon-rich isolation layer is a polysilicon layer.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The silicon-rich isolation layer covering the sidewall of the isolation trench has the same thickness from the bottom of the isolation trench to the top of the isolation trench.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The silicon-rich isolation layer covering the sidewall of the isolation trench gradually increases in thickness from the bottom of the isolation trench to the top of the isolation trench.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The silicon-rich isolation layer is formed by a low step coverage furnace process.

9. A semiconductor structure formed by the manufacturing method according to claim 1, characterized in that: include: A substrate, on which an isolation channel and a plurality of active regions are formed, wherein the isolation channel is located between the plurality of active regions; An isolation oxide layer, the isolation oxide layer is located in the isolation trench, the isolation oxide layer comprises a first isolation oxide layer and a second isolation oxide layer, the first isolation oxide layer covers the inner surface of the isolation trench; At least part of the first isolation oxide layer is formed by oxidizing a silicon-rich isolation layer covering the inner surface of the isolation trench.

10. The semiconductor structure according to claim 9, characterized in that: The isolation channel comprises a first isolation channel and a second isolation channel, and the width of the first isolation channel is greater than the width of the second isolation channel; The first isolation trench is filled with the first isolation oxide layer and the second isolation oxide layer, and the second isolation trench is filled with the first isolation oxide layer.

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