Method for manufacturing a structure

Abstract

The present invention provides a method for manufacturing a structure that can be easily joined to a joining object. The method comprises: a conductive layer forming step of locally forming a conductive layer having conductivity on a surface of an insulating support having at least one surface; a valve metal layer forming step of forming a valve metal layer that covers at least a portion of the conductive layer; an anodic oxide film forming step of performing an anodic oxidation treatment using the conductive layer as an electrode to form the valve metal layer in a region above the conductive layer into an anodic oxide film; a micropore forming step of forming a plurality of micropores extending in the thickness direction of the anodic oxide film; and a filling step of filling the micropores with a conductive substance, wherein a valve metal layer removal step of removing the valve metal layer after the anodic oxide film forming step is included between the anodic oxide film forming step and the filling step.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a structure for bonding to an object, and in particular to a method for manufacturing a structure in which a valve metal layer is anodized using a conductive layer to form an anodized film and micropores extending in the thickness direction of the anodized film are filled with a conductive substance. Background Art

[0002] Currently, various methods are used for electrically connecting electronic components such as semiconductor elements to each other and for electrically connecting electronic components to circuit boards.

[0003] The miniaturization of electronic components such as semiconductor elements is obvious. In the previous methods such as wire bonding, direct connection to the wiring substrate, flip chip bonding, and thermocompression bonding, the stability of the electrical connection of electronic components cannot be fully guaranteed. Therefore, in the electrical connection of electronic components, for example, bottom fillers with adhesion to Cu / Sn bumps are used. However, depending on the electronic component or circuit substrate to be connected, the reliability of the electrical connection will be reduced due to the mismatch of CTE (coefficient of thermal expansion) and the induction of local stress.

[0004] Furthermore, semiconductor devices require connection densities exceeding tens of millions per die. To meet this demand, bumps must be reduced in size to approximately 1-2 μm in diameter. However, conventional Cu / Sn electroplating methods have difficulty achieving bumps smaller than 5 μm.

[0005] Therefore, in order to meet the reliability of the above-mentioned electrical connection and the required connection density, a bonding method called hybrid bonding has been developed, in which the bonding surfaces of a wafer or semiconductor element constituting the semiconductor element to be connected are mirror-polished by CMP (chemical mechanical polishing) and then bonded (for example, refer to non-patent document 1).

[0006] Previous technical literature

[0007] Non-patent literature

[0008] Non-patent literature 1: R.Taibi, et al., "Full characterization of Cu / Cu directbonding for 3D integration", Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th, 2010, p.219-225 Summary of the Invention

[0009] Technical issues to be solved by the invention

[0010] In the hybrid bonding method described in Non-Patent Document 1, the bonding surface of a wafer or semiconductor element must be mirror-polished using CMP (chemical mechanical polishing). CMP exposes the copper (Cu) used for electrical connection or the silicon (Si) used as an insulator. However, to prevent uneven surfaces such as dishing from forming on the bonding surface, the flatness of the bonding surface must be precisely controlled. This complicates the bonding process.

[0011] Furthermore, hybrid bonding requires strict environmental control to ensure electrical connectivity at the joint and to prevent contamination from particles entering between the bonding surfaces during bonding, leading to a more complex bonding process. Furthermore, neglecting environmental control during bonding can lead to contamination of the bonding surfaces, increasing the number of areas where electrical connectivity is not ensured after bonding, significantly reducing yield and making it difficult to achieve a bond that meets specifications. Therefore, hybrid bonding is difficult to simplify the bonding process.

[0012] The present invention has been made in view of the above-mentioned problems based on the conventional technology, and an object of the present invention is to provide a method for manufacturing a structure that can be easily joined to a joining object.

[0013] Means for solving technical problems

[0014] In order to achieve the above-mentioned purpose, the present invention provides a method for manufacturing a structure, which comprises: a conductive layer forming process, locally forming a conductive layer with conductivity on the surface of an insulating support body having at least one surface; a valve metal layer forming process, forming a valve metal layer covering at least a portion of the conductive layer; an anodized film forming process, performing an anodizing treatment using the conductive layer as an electrode to form the valve metal layer in the area on the conductive layer in the valve metal layer into an anodized film; a micropore forming process, forming a plurality of micropores extending in the thickness direction in the anodized film; and a filling process, filling the micropores with a conductive substance, and a valve metal layer removing process for removing the valve metal layer after the anodized film forming process is provided between the anodized film forming process and the filling process.

[0015] It is preferable to perform the valve metal layer removal step between the anodic oxide film forming step and the micropore forming step or between the micropore forming step and the filling step.

[0016] The micropore forming step preferably includes a step of penetrating the anodized film in the thickness direction to expose the conductive layer.

[0017] In the valve metal layer forming step, the valve metal layer is preferably formed at a temperature of the insulating support of 60° C. or lower.

[0018] It is preferable to include a protruding step of causing a plurality of conductive paths composed of the filled conductive material to protrude from the anodized film.

[0019] It is preferable that the heights of the protruding portions of the plurality of conductive paths protruding from the anodized film be the same.

[0020] It is preferred that the conductive layer and the conductive substance include the same material.

[0021] A preferred valve metal is aluminum.

[0022] Preferably, the surface of the insulating support has a device region, and in the conductive layer forming step, the conductive layer is formed on the device region on the surface of the insulating support.

[0023] Effects of the Invention

[0024] According to the present invention, a structure that can be easily joined to a joining object can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0026] Figure 2 This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0027] Figure 3 This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0028] Figure 4 This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0029] Figure 5 This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0030] Figure 6This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0031] Figure 7 This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0032] Figure 8 This is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structured body according to an embodiment of the present invention.

[0033] Figure 9 This is a schematic cross-sectional view showing one step of a second example of the method for manufacturing a structured body according to the embodiment of the present invention.

[0034] Figure 10 This is a schematic cross-sectional view showing one step of a second example of the method for manufacturing a structured body according to the embodiment of the present invention.

[0035] Figure 11 This is a schematic cross-sectional view showing one step of a third example of the method for manufacturing a structure according to an embodiment of the present invention.

[0036] Figure 12 This is a schematic cross-sectional view showing one step of a third example of the method for manufacturing a structure according to an embodiment of the present invention.

[0037] Figure 13 This is a schematic plan view showing an example of a structure according to an embodiment of the present invention.

[0038] Figure 14 This is a schematic cross-sectional view showing an example of a structure according to an embodiment of the present invention.

[0039] Figure 15 This is a schematic cross-sectional view showing an example of the structure of a structured body according to an embodiment of the present invention.

[0040] Figure 16 This is a schematic cross-sectional view showing one step of an example of a method for joining a structure using an embodiment of the present invention.

[0041] Figure 17 This is a schematic cross-sectional view showing one step of an example of a method for joining a structure using an embodiment of the present invention.

[0042] Figure 18 This is a schematic diagram showing a first example of a stacked device using the structure according to the embodiment of the present invention.

[0043] Figure 19 This is a schematic diagram showing a second example of a stacked device using the structure according to the embodiment of the present invention.

[0044] Figure 20 This is a schematic diagram showing a third example of a stacked device using the structure according to the embodiment of the present invention.

[0045] Figure 21 This is a schematic diagram showing a fourth example of a stacked device using the structure according to the embodiment of the present invention.

[0046] Figure 22 This is a schematic diagram showing one step of a first example of a method for manufacturing a stacked device using a structure according to an embodiment of the present invention.

[0047] Figure 23 This is a schematic diagram showing one step of a first example of a method for manufacturing a stacked device using a structure according to an embodiment of the present invention.

[0048] Figure 24 This is a schematic diagram showing one step of a first example of a method for manufacturing a stacked device using a structure according to an embodiment of the present invention.

[0049] Figure 25 This is a schematic diagram showing one step of a second example of a method for manufacturing a stacked device using the structure according to the embodiment of the present invention.

[0050] Figure 26 This is a schematic diagram showing one step of a third example of a method for manufacturing a stacked device using the structure according to the embodiment of the present invention.

[0051] Figure 27 This is a schematic diagram showing one step of a third example of a method for manufacturing a stacked device using the structure according to the embodiment of the present invention.

[0052] Figure 28 This is a graph showing a first example of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention.

[0053] Figure 29 This is a graph showing a second example of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention.

[0054] Figure 30 This is a graph showing a third example of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention.

[0055] Figure 31 This is a graph showing a fourth example of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention.

[0056] Figure 32 This is a graph showing a fifth example of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention.

[0057] Figure 33 This is a graph showing a sixth example of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention.

[0058] Figure 34 This is a graph showing a seventh example of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention.

[0059] Figure 35 It is a schematic cross-sectional view showing a first example of a semiconductor package.

[0060] Figure 36 It is a schematic cross-sectional view for explaining the coaxial structure.

[0061] Figure 37 It is a schematic top view for explaining the coaxial structure.

[0062] Figure 38 It is a schematic cross-sectional view showing a second example of a semiconductor package.

[0063] Figure 39 This is a schematic diagram showing a first example of an electronic device using the structure according to the embodiment of the present invention.

[0064] Figure 40 This is a schematic diagram showing a second example of an electronic device using the structure according to the embodiment of the present invention.

[0065] Figure 41 This is a schematic diagram showing a third example of an electronic device using the structure according to the embodiment of the present invention.

[0066] Figure 42 This is a schematic diagram showing a fourth example of an electronic device using the structure according to the embodiment of the present invention. DETAILED DESCRIPTION

[0067] Hereinafter, a method for producing a structure of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

[0068] In addition, the drawings described below are illustrative drawings for explaining the present invention, and the present invention is not limited to the drawings shown below.

[0069] In addition, the following "to" indicating a numerical range includes the values described on both sides. For example, "ε is a value α to a value β" means that the range of ε is a range including the values α and β, and in mathematical notation, it is α≤ε≤β.

[0070] Unless otherwise specified, angles such as “orthogonal” include the error range generally allowed in the relevant technical field. Furthermore, regarding environments such as temperature, humidity, or air pressure, unless otherwise specified, the error range generally allowed in the relevant technical field is also included.

[0071] Here, a structure is a structure having electrodes or element regions. Examples of structures having electrodes include semiconductor elements that perform specific functions on their own, but also include structures in which multiple structures are aggregated to perform specific functions. Furthermore, structures that only transmit electrical signals, such as wiring components, are also included as structures having electrodes, as are printed wiring boards.

[0072] The component area is an area where various components that function as electronic components form circuits. Examples of the component area include areas where memory circuits such as flash memory are formed, logic circuits such as microprocessors and FPGAs (field-programmable gate arrays), and areas where communication modules such as wireless tags and wiring are formed. In addition, MEMS (Micro Electro Mechanical Systems) may also be formed in the component area. Examples of MEMS include sensors, actuators, and antennas. Examples of sensors include various sensors such as acceleration, sound, and light.

[0073] As described above, the component region is formed with components constituting a circuit, etc., and an electrode (not shown) is provided for electrically connecting the semiconductor chip to the outside. The component region has an electrode region in which an electrode is formed. In addition, the electrode in the component region is, for example, a Cu column. The electrode region basically refers to a region containing all the electrodes formed. However, if the electrodes are discretely arranged, the region in which each electrode is provided is also referred to as an electrode region.

[0074] The form of the structure may be a separate piece form like a semiconductor chip, a semiconductor wafer, or a wiring layer form.

[0075] [First Example of Method for Manufacturing a Structure]

[0076] Figures 1 to 8 This is a schematic cross-sectional view showing a first example of a method for manufacturing a structure according to an embodiment of the present invention in order of steps. Figures 1 to 8 In the first example of the method for manufacturing a structure shown in the figure, a structure having a device region 10 c on the surface 10 a of the insulating support 10 is described as an example.

[0077] like Figure 1 As shown, first, a conductive layer forming step is performed to partially form a conductive layer 12 having conductivity on a surface 10 a of an insulating support 10 having at least one surface.

[0078] For example, the surface 10a of the insulating support 10 has a device region 10c. In the conductive layer forming step, the conductive layer 12 is formed on the device region 10c of the surface 10a of the insulating support 10. The conductive layer 12 is formed only on the device region 10c, and the conductive layer 12 is partially formed on the surface 10a of the insulating support 10.

[0079] In order to form the conductive layer 12, first, a resist layer 11 is formed on the surface 10a of the insulating support 10, and the resist layer 11 on the element region 10c is removed by patterning using a photolithography method, for example. Then, a seed layer (not shown) is formed on the resist layer 11, for example, and the conductive layer 12 is formed by electroplating. When the conductive layer 12 is formed, the surfaces of the resist layer 11 and the conductive layer 12 are flattened by a flattening treatment. In addition, the conductive layer 12 is formed by electroplating, but the method for forming the conductive layer 12 is not particularly limited. However, in a film forming method with a high temperature, the temperature of the element region 10c becomes high, causing malfunctions, etc., so it is preferable to use a film forming method with a low temperature.

[0080] Then, if Figure 2 As shown, a valve metal layer forming process is implemented to form a valve metal layer 13 covering at least a portion of the conductive layer 12. In the valve metal layer forming process, the valve metal layer 13 is formed on the surface 12a of the conductive layer 12 and the surface of the resist layer 11, for example, by a vapor deposition method. The valve metal is not particularly limited, and aluminum can be used, for example. In addition, in the valve metal layer forming process, it is preferred to form the valve metal layer at a temperature of the insulating support body 10 below 60°C. In the case where the temperature is high when forming the valve metal layer 13, the temperature of the element region 10c will also become high, resulting in malfunctions, etc., and therefore, it is preferred to set the temperature below 60°C. Furthermore, it is also preferred that the temperature be low when forming the conductive layer 12, and in this case, the temperature is also preferably below 60°C.

[0081] Next, an anodic oxidation treatment is performed using the conductive layer 12 as an electrode, such as Figure 3 As shown, an anodic oxide film forming step is performed to form the valve metal layer 13 in the region on the conductive layer 12 into an anodic oxide film 14. In the anodic oxide film forming step, an anodic oxidation treatment is performed in, for example, an oxalic acid aqueous solution, with the conductive layer 12 serving as a cathode electrode and the valve metal layer 13 serving as an anode electrode. As a result, the valve metal layer 13 on the conductive layer 12 is anodized to form the anodic oxide film 14. For example, if an extraction electrode is provided for the conductive layer 12, a direct current is applied to the conductive layer 12 using the extraction electrode.

[0082] Furthermore, if the valve metal layer 13 is made of aluminum, the anodized film 14 is made of aluminum oxide.

[0083] Next, a micropore forming process is performed to form a plurality of micropores extending in the thickness direction Dt in the anodized film 14. The anodized film 14 has a plurality of micropores at the time of formation. However, among the plurality of micropores, there are also micropores that do not penetrate in the thickness direction Dt. In addition, there is a barrier layer (not shown) at the bottom of the micropores. Therefore, the micropore forming process preferably includes the following steps: Figure 3 The anodized film 14 shown in FIG. 1 is formed by expanding the micropores and removing the barrier layer, thereby Figure 4 As shown, a plurality of through holes 15 are formed in the anodized film 14 penetrating in the thickness direction Dt to expose the conductive layer 12 .

[0084] The pores are expanded by pore widening. The pore widening process involves immersing the anodic oxide film in an acidic or alkaline aqueous solution to dissolve the anodic oxide film and expand the pore diameter. For the pore widening process, aqueous solutions of inorganic acids such as sulfuric acid, phosphoric acid, nitric acid, and hydrochloric acid, or mixtures thereof, or aqueous solutions of sodium hydroxide, potassium hydroxide, and lithium hydroxide can be used.

[0085] In removing the barrier layer, for example, the barrier layer of the anodized film 14 is removed by using an alkaline aqueous solution containing ions of a metal M1 having a higher hydrogen overvoltage than the valve metal layer, and at the same time, a metal layer (not shown) composed of a metal (metal M1) as a conductive material is formed at the bottom of the micropores.

[0086] Furthermore, the barrier layer at the bottom of the micropores can also be removed during the pore expansion process. By using an aqueous sodium hydroxide solution during the pore expansion process, the micropores can be expanded and the barrier layer can be removed.

[0087] Next, after forming a plurality of through-holes 15 in the anodized film 14 , a valve metal layer removal step is performed to remove the valve metal layer 13 after the anodized film forming step.

[0088] In the anodizing treatment, as described above, the conductive layer 12 is used as an electrode, and the valve metal layer 13 is not completely anodized. Therefore, the valve metal layer 13 is not completely anodized. After the anodizing treatment, there are still areas in the state of the valve metal layer 13. In the valve metal layer removal step, a treatment solution that does not dissolve the anodized film 14 but dissolves the valve metal layer 13 is used to remove the valve metal layer 13 that has not been anodized. Figure 5 As shown, the valve metal layer 13 on both sides of the anodic oxide film 14 is removed to expose the surface 11a of the resist layer 11. When the valve metal layer 13 is made of aluminum and the anodic oxide film 14 is aluminum oxide, a copper chloride aqueous solution is used as the treatment liquid.

[0089] Then, if Figure 6As shown, a filling step is performed to fill a plurality of micropores, i.e., a plurality of through-holes 15, which penetrate the anodized film 14 along the thickness direction Dt. In the filling step, the method for filling the plurality of micropores with the conductive substance is not particularly limited. For example, electrolytic plating can be used to fill the plurality of micropores of the anodized film with a conductive material. As a result, the conductive substance is filled in the through-holes 15, forming a plurality of conductive paths 16. The conductive paths 16 are composed of the filled conductive substance and have conductivity.

[0090] In addition, the valve metal layer removal step is not particularly limited as long as it is between the anodized film forming step and the filling step, and can be implemented between the anodized film forming step and the micropore forming step or between the micropore forming step and the filling step.

[0091] Next, a protrusion step is performed to cause a plurality of conductive paths 16 formed of a filled conductive material to protrude from the anodized film 14. By the protrusion step, a plurality of conductive paths 16 are formed. In the protrusion step, as shown in FIG. Figure 7 As shown, a portion of the surface 14a of the anodized film 14 is removed and a plurality of conductive paths 16 are made to protrude from the anodized film 14. Thus, the conductive paths 16 are formed in the anodized film 14. The conductive paths 16 have protruding portions 16a that protrude from the surface 14a of the anodized film 14.

[0092] Next, the resist layer 11 is removed to obtain Figure 8 The structure 18 shown. In the structure 18, a plurality of conductive paths 16 are separated from each other and extend along the thickness direction Dt of the electrically insulating anodized film 14. With this structure, the structure 18 has conductivity in the thickness direction Dt and has anisotropic conductivity. In addition, the anodized film 14 containing the conductive paths 16 in the structure 18 is electrically referred to as a conductive component 19, and the conductive component 19 also has anisotropic conductivity. In the structure 18, the conductive component 19 is formed on the conductive layer 12, and the conductive component 19 selectively having anisotropic conductivity is formed to ensure conductivity during bonding.

[0093] In the structure 18, a bonded body can be obtained by aligning the position with the bonding object and bonding. By providing the conductive path 16, even if the bonding surface has unevenness, the conductive path 16 will follow the unevenness of the bonding surface, so there is no need to perform the mirroring based on CMP required in the above-mentioned mixed bonding. In addition, the environment during bonding does not need to be strictly managed and can be selected from an inert atmosphere such as the atmosphere, a nitrogen atmosphere, and a reduced pressure atmosphere including a vacuum atmosphere. Moreover, a conventional wafer bonding device can be used. In this way, the structure obtained by the above-mentioned manufacturing method can be easily bonded to the bonding object.

[0094] The method for manufacturing structure 18 may further include a resin layer forming step for forming a resin layer on protruding portion 16a of surface 14a of anodized film 14 of conductive path 16. The resin layer in the resin layer forming step serves both as a bond to the object being bonded and as a protective layer for conductive path 16. Furthermore, if protruding portion 16a is not provided in conductive path 16, the protruding step is not necessarily required. If protruding portion 16a is not provided, the resin layer forming step may be omitted.

[0095] [Second Example of Method for Manufacturing Structure]

[0096] Figure 9 and Figure 10 This is a schematic cross-sectional view showing a second example of a method for manufacturing a structure according to an embodiment of the present invention in the order of steps. Figure 9 and Figure 10 In, with Figures 1 to 8 In the manufacturing method of the structure shown, the same components are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0097] As described above, the timing of performing the valve metal layer removal step is not particularly limited as long as it is between the anodized film forming step and the filling step. The valve metal layer removal step may be performed between the anodized film forming step and the micropore forming step.

[0098] The second example of the method for manufacturing a structure differs from the first example of the method for manufacturing a structure in that Figure 3 The anodic oxide film forming process shown in FIG. Figure 9 As shown in the figure, the valve metal layer 13 is removed as the valve metal layer is not anodized; Figure 9 In the state of the valve metal layer 13 shown, the anodic oxide film 14 is subjected to a micropore forming step, and the other steps are the same as those of the first example of the method for manufacturing a structure.

[0099] In the second example of the method for manufacturing the structure, after removing the valve metal layer 13, as shown in FIG. Figure 10 As shown in FIG. 1 , a micropore forming step is performed to form a plurality of through holes 15 in the anodized film 14. After the plurality of through holes 15 are formed in the anodized film 14, the above-mentioned filling step is performed, and a protruding step is performed as needed. In the second example of the method for manufacturing a structure, the same as the first example of the method for manufacturing a structure can also be obtained. Figure 8 The structure 18 is shown.

[0100] [Third Example of Method for Producing a Structure]

[0101] Figure 11 and Figure 12This is a schematic cross-sectional view showing a third example of a method for manufacturing a structure according to an embodiment of the present invention in the order of steps. Figure 11 and Figure 12 In, with Figures 1 to 8 In the manufacturing method of the structure shown, the same components are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0102] Furthermore, the valve metal layer removal step may be performed after the filling step.

[0103] The third example of the method for manufacturing a structure differs from the first example of the method for manufacturing a structure in that Figure 4 After the micropore forming process shown, the valve metal layer removal process is not performed. Figure 11 As shown in FIG. 1 , in the presence of the valve metal layer 13, the plurality of micropores, ie, the plurality of through holes 15 of the anodized film 14 are filled with a conductive material. Figure 12 As shown in FIG. 1 , the valve metal layer 13 is removed, and other steps are the same as those of the first example of the method for manufacturing a structure.

[0104] In the third example of the method for manufacturing a structure, Figure 11 As shown, after the conductive material is filled into the plurality of through holes 15 of the anodic oxide film 14 in the presence of the valve metal layer 13, a treatment solution that does not dissolve the conductive material and the anodic oxide film 14 but dissolves the valve metal layer 13 is used. Figure 12 As shown, the valve metal layer 13 is removed to expose the surface 11a of the resist layer 11.

[0105] Then, if Figure 7 As shown in FIG. 1 , a protruding portion 16a is formed so that the conductive path 16 protrudes from the surface 14a of the anodic oxide film 14. Next, the resist layer 11 is removed, and in the third example of the method for manufacturing a structure, the structure is obtained in the same manner as in the first example of the method for manufacturing a structure. Figure 8 The structure 18 is shown.

[0106] Hereinafter, each step of the method for producing the structure will be further described.

[0107] [Conductive layer forming step]

[0108] The conductive layer is provided in a device region or a wiring region of the insulating support body, and supplies current or voltage to or outputs current or voltage to the device region or the wiring region.

[0109] As will be described later, locally providing the conductive layer means that the element region or wiring region is not present in the entire region of the insulating support but is provided unevenly. Therefore, the conductive layer provided in the element region or wiring region is also uneven and provided locally.

[0110] The conductive layer is not particularly limited as long as it is conductive, but it is preferably composed of the same material as the conductive substance being filled, for example, copper. That is, the conductive layer and the conductive path are preferably composed of the same material. By making the conductive layer and the conductive substance from the same material, the bond between the conductive layer and the conductive substance is improved, which can suppress increases in resistance and, by extension, the occurrence of electromigration. This can prevent disconnection at the junction between the conductive path and the conductive layer, improving the reliability of the conductive path.

[0111] <Insulation support>

[0112] The insulating support has at least one surface, specifically, at least one plane. The component region or wiring region is disposed on the plane of the insulating support. However, the component region or wiring region is not disposed over the entire surface of the insulating support, but is disposed unevenly.

[0113] More specifically, an insulating support body forms a device region, a wiring region, and the like on the surface of various wafers such as a silicon wafer, and the surface of the insulating support body is the surface of the wafer.

[0114] The insulating support is not particularly limited to a wafer form, and may be a chip form in which a wafer having a device region and a wiring region formed on its surface is singulated for each device region or wiring region.

[0115] [Valve Metal Layer Formation Process]

[0116] An anodic oxide film is preferred because through-holes having a desired average opening diameter can be formed as through-holes and a conductive path can be easily formed.

[0117] The method for forming the valve metal layer is not particularly limited, and the valve metal layer can be formed, for example, by sputtering, vapor deposition, or electroplating. Furthermore, a combination of these methods can also be used to form the valve metal layer. However, as mentioned above, when forming the valve metal layer, it is preferable to set the temperature of the insulating support to 60°C or below. In this case, for example, the insulating support is placed on a cooling plate, and the temperature of the insulating support is maintained at 60°C or below while the valve metal layer is formed.

[0118] Here, specific examples of valve metals constituting the valve metal layer include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Among these, an anodic oxide film of aluminum is preferred because it has good dimensional stability and is relatively inexpensive. Therefore, it is preferable to use a valve metal to form the anodic oxide film.

[0119] <Aluminum>

[0120] Aluminum is not particularly limited, and specific examples thereof include pure aluminum and aluminum alloys containing aluminum as a main component and containing trace amounts of foreign elements.

[0121] The aluminum purity is preferably 99.5% by mass or higher, more preferably 99.9% by mass or higher, and even more preferably 99.99% by mass or higher. When the aluminum purity is within the above range, the orderliness of the through-hole arrangement becomes sufficient.

[0122] Furthermore, in the valve metal layer composed of aluminum, it is preferable that the surface to be subjected to the anodizing treatment step is previously subjected to heat treatment, degreasing treatment, and mirror finishing treatment.

[0123] Here, regarding the heat treatment, degreasing treatment, and mirror finishing treatment, the same treatments as those described in paragraphs

[0044] to

[0054] of Japanese Patent Application Laid-Open No. 2008-270158 can be performed.

[0124] [Anodic oxide film formation process]

[0125] The anodic oxide film forming step is a step of performing an anodic oxidation treatment on the valve metal layer using the conductive layer as an electrode.

[0126] A conventionally known method can be used for the anodic oxidation treatment. However, from the viewpoint of improving the orderliness of the through-hole arrangement and ensuring the anisotropic conductivity of the conductive member 19 , a self-ordering method or a constant voltage treatment is preferably used.

[0127] Here, regarding the self-ordering method and constant pressure treatment of the anodic oxidation treatment, the same method as in paragraphs

[0056] to

[0108] and [ Figure 3 ] are the same as the processes described in .

[0128] <Anodizing treatment>

[0129] The average flow rate of the electrolyte during the anodizing treatment is preferably 0.5 to 20.0 m / min, more preferably 1.0 to 15.0 m / min, and even more preferably 2.0 to 10.0 m / min.

[0130] Furthermore, the method for causing the electrolyte to flow under the above conditions is not particularly limited, and for example, a method using a conventional stirring device such as a stirrer can be utilized. In particular, the use of a stirrer that can control the stirring speed via a digital display is preferred because the average flow rate can be controlled. Examples of such stirring devices include the "Magnetic Stirrer HS-50D (manufactured by AS ONE Corporation)".

[0131] The anodic oxidation treatment can utilize, for example, a method of passing electricity in a solution having an acid concentration of 1 to 10% by mass, with the conductive layer serving as a cathode and the valve metal layer serving as an anode, as described above.

[0132] As the solution used for the anodizing treatment, an acid aqueous solution is preferably used, and more preferably sulfuric acid, phosphoric acid, chromic acid, oxalic acid, benzenesulfonic acid, aminosulfonic acid, glycolic acid, tartaric acid, malic acid, citric acid, etc. Among them, sulfuric acid, phosphoric acid, and oxalic acid are particularly preferred. These acids can be used alone or in combination of two or more.

[0133] The conditions for anodizing treatment vary depending on the electrolyte used and therefore cannot be determined uniformly, but are generally preferably an electrolyte concentration of 0.1 to 20 mass %, a liquid temperature of -10 to 30°C, and a current density of 0.01 to 20 A / dm 2 , voltage 3 to 300 V, electrolysis time 0.5 to 30 hours, more preferably electrolyte concentration 0.5 to 15 mass %, liquid temperature -5 to 25 ° C, current density 0.05 to 15 A / dm 2 , voltage 5 to 250 V, electrolysis time 1 to 25 hours, more preferably the electrolyte concentration 1 to 10 mass%, liquid temperature 0 to 20 ° C, current density 0.1 to 10 A / dm 2 , voltage 10~200V, electrolysis time 2~20 hours.

[0134] The thickness of the anodized film formed by anodizing is preferably 30 μm or less, more preferably 5 to 20 μm. In addition, the thickness of the anodized film can be obtained by the following methods: cutting the anodized film in the thickness direction with a focused ion beam (FIB), taking a surface photograph of its cross section (50,000 times magnification) using a field emission scanning electron microscope (FE-SEM), measuring at 10 points, and calculating the average value.

[0135] 〔Maintaining process〕

[0136] The method for manufacturing a structure may include a holding step. The holding step is a step in which, after the anodizing step, the structure is held at a voltage of 1 V or higher and 95% to 105% of a holding voltage selected from a range of less than 30% of the voltage used in the anodizing step for a total of 5 minutes or more. In other words, the holding step is a step in which, after the anodizing step, electrolysis is performed at a voltage of 1 V or higher and 95% to 105% of a holding voltage selected from a range of less than 30% of the voltage used in the anodizing step for a total of 5 minutes or more.

[0137] Here, the “voltage during anodizing treatment” refers to the voltage applied between the valve metal layer and the conductive layer. For example, if the electrolysis time during anodizing treatment is 30 minutes, it refers to the average value of the voltage maintained during 30 minutes.

[0138] From the perspective of controlling the thickness of the barrier layer to an appropriate thickness relative to the side wall thickness of the anodized film, i.e., the depth of the through hole, the voltage in the holding step is preferably 5% to 25% of the voltage in the anodizing treatment, and more preferably 5% to 20%.

[0139] Furthermore, in order to further improve the in-plane uniformity, the total holding time in the holding step is preferably 5 minutes to 20 minutes, more preferably 5 minutes to 15 minutes, and even more preferably 5 minutes to 10 minutes.

[0140] Furthermore, the holding time in the holding step may be 5 minutes or more in total, but is preferably 5 minutes or more continuously.

[0141] In addition, the voltage in the holding process can also be set to be continuously or stepwise reduced from the voltage in the anodizing treatment process to the voltage in the holding process, but in order to further improve the in-plane uniformity, it is preferably set to a voltage of more than 95% and less than 105% of the above-mentioned holding voltage within 1 second after the end of the anodizing treatment process.

[0142] The holding step can be performed continuously with the anodic oxide film forming step, for example, by lowering the electrolytic potential at the end of the anodic oxidation treatment step.

[0143] In the holding step, the same electrolyte solution and treatment conditions as those in the above-mentioned conventionally known anodizing treatment can be employed with respect to conditions other than the electrolytic potential.

[0144] In particular, when the holding step and the anodic oxide film forming step are performed continuously, it is preferable to perform the treatment using the same electrolyte solution.

[0145] [Micropore Forming Process]

[0146] <Barrier layer removal process>

[0147] The barrier layer removal step is, for example, a step of removing the barrier layer of the anodized film using an alkaline aqueous solution containing ions of a metal M1 having a higher hydrogen overvoltage than aluminum.

[0148] The barrier layer is removed through the barrier layer removal process, and a metal layer composed of the metal M1 is formed at the bottom of the microhole.

[0149] Here, hydrogen overvoltage refers to the voltage required to generate hydrogen. For example, the hydrogen overvoltage of aluminum (Al) is -1.66 V (Journal of the Chemical Society of Japan, 1982, (8), pp. 1305-1313). The following also shows examples of metals M1 having a higher hydrogen overvoltage than aluminum and their hydrogen overvoltage values.

[0150] <Metal M1 and hydrogen (1N H2SO4) overvoltage>

[0151] Platinum (Pt): 0.00V

[0152] Gold (Au): 0.02V

[0153] Silver (Ag): 0.08V

[0154] Nickel (Ni): 0.21V

[0155] Copper (Cu): 0.23V

[0156] Tin (Sn): 0.53V

[0157] Zinc (Zn): 0.70V

[0158] The metal M1 used in the above-mentioned barrier layer removal process is preferably a metal with a higher ionization tendency than the metal M2 used in the filling process because it produces a substitution reaction with the metal M2 filled in the anodized film forming process and reduces the impact on the electrical properties of the metal filled inside the through hole.

[0159] Specifically, when copper (Cu) is used as the metal M2 in the filling process, examples of the metal M1 used in the barrier layer removal process include Zn, Fe, Ni, and Sn. Among them, Zn and Ni are preferably used, and Zn is more preferably used.

[0160] Furthermore, when Ni is used as the metal M2 in the filling step, examples of the metal M1 used in the barrier layer removal step include Zn and Fe, and among them, Zn is preferably used.

[0161] The method of removing the barrier layer using the alkaline aqueous solution containing ions of the metal M1 is not particularly limited, and examples thereof include methods similar to conventionally known chemical etching treatments.

[0162] Chemical etching

[0163] In the removal of the barrier layer based on chemical etching, for example, only the barrier layer can be selectively dissolved by the following method: the structure after the anodizing process is immersed in an alkaline aqueous solution, the alkaline aqueous solution is filled in the interior of the through-hole, and then the surface of the through-hole side of the anodized film is brought into contact with a pH (hydrogen ion index) buffer solution.

[0164] Here, the aqueous alkaline solution containing the metal M1 ions is preferably an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. The concentration of the aqueous alkaline solution is preferably 0.1 to 5% by mass. The temperature of the aqueous alkaline solution is preferably 10 to 60°C, more preferably 15 to 45°C, and even more preferably 20 to 35°C.

[0165] Specifically, for example, a 50 g / L, 40° C. aqueous phosphoric acid solution, a 0.5 g / L, 30° C. aqueous sodium hydroxide solution, a 0.5 g / L, 30° C. aqueous potassium hydroxide solution, or the like is preferably used.

[0166] As the pH buffer solution, a buffer solution corresponding to the above-mentioned aqueous alkali solution can be appropriately used.

[0167] The immersion time in the alkaline aqueous solution is preferably 5 to 120 minutes, more preferably 8 to 120 minutes, further preferably 8 to 90 minutes, particularly preferably 10 to 90 minutes, preferably 10 to 60 minutes, more preferably 15 to 60 minutes.

[0168] <Another Example of the Barrier Layer Removal Process>

[0169] In addition to the above, the barrier layer removal step may be a step of removing the barrier layer of the anodic oxide film to expose the conductive layer at the bottom of the through-hole.

[0170] In this case, the method for removing the barrier layer is not particularly limited. For example, there can be cited a method of electrochemically dissolving the barrier layer at a potential lower than the potential in the anodizing treatment of the anodized film forming process (hereinafter also referred to as "electrolytic removal treatment"), a method of removing the barrier layer by etching (hereinafter also referred to as "etching removal treatment"), and a method of combining these (especially a method of removing the remaining barrier layer by etching removal treatment after performing the electrolytic removal treatment).

[0171] <Electrolytic removal treatment>

[0172] The electrolytic removal treatment is not particularly limited as long as it is an electrolytic treatment performed at a potential lower than the potential (electrolytic potential) in the anodizing treatment in the anodized film forming step.

[0173] The electrolytic dissolution treatment can be performed continuously with the anodizing treatment by, for example, lowering the electrolytic potential at the end of the anodized film forming step.

[0174] In the electrolytic removal treatment, regarding conditions other than the electrolytic potential, the same electrolyte solution and treatment conditions as those of the above-mentioned conventionally known anodizing treatment can be employed.

[0175] In particular, as described above, when the electrolytic removal treatment and the anodizing treatment are performed continuously, it is preferable to perform the treatments using the same electrolyte.

[0176] (electrolysis potential)

[0177] The electrolytic potential in the electrolytic removal treatment is preferably lowered continuously or stepwise to a potential lower than the electrolytic potential in the anodic oxidation treatment.

[0178] Here, from the viewpoint of the withstand voltage of the barrier layer, the step width (Step Width) when the electrolytic potential is lowered stepwise is preferably 10 V or less, more preferably 5 V or less, and even more preferably 2 V or less.

[0179] Furthermore, from the viewpoint of productivity, the voltage drop rate when the electrolysis potential is lowered continuously or stepwise is preferably 1 V / s or less, more preferably 0.5 V / s or less, and even more preferably 0.2 V / s or less.

[0180] <Etching removal>

[0181] The etching removal process is not particularly limited, and may be a chemical etching process using an acid aqueous solution or an alkaline aqueous solution for dissolution, or may be a dry etching process.

[0182] (Chemical etching treatment)

[0183] The removal of the barrier layer based on chemical etching treatment is, for example, a method in which the structure after the anodizing treatment step is immersed in an acid aqueous solution or an alkaline aqueous solution, the acid aqueous solution or the alkaline aqueous solution is filled in the interior of the micropores, and then the surface of the opening side of the micropores of the anodized film is brought into contact with a pH (hydrogen ion index) buffer solution, etc., which can selectively dissolve only the barrier layer.

[0184] When using an aqueous acid solution, an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, or hydrochloric acid, or a mixture thereof, is preferably used. The concentration of the aqueous acid solution is preferably 1% to 10% by mass. The temperature of the aqueous acid solution is preferably 15°C to 80°C, more preferably 20°C to 60°C, and even more preferably 30°C to 50°C.

[0185] On the other hand, when using an aqueous alkali solution, it is preferably an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. The concentration of the aqueous alkali solution is preferably 0.1% to 5% by mass. The temperature of the aqueous alkali solution is preferably 10°C to 60°C, more preferably 15°C to 45°C, and even more preferably 20°C to 35°C. The aqueous alkali solution may contain zinc and other metals.

[0186] Specifically, for example, a 50 g / L, 40° C. aqueous phosphoric acid solution, a 0.5 g / L, 30° C. aqueous sodium hydroxide solution, a 0.5 g / L, 30° C. aqueous potassium hydroxide solution, or the like is preferably used.

[0187] In addition, as the pH buffer solution, a buffer solution corresponding to the above-mentioned acid aqueous solution or alkaline aqueous solution can be appropriately used.

[0188] The immersion time in the acid aqueous solution or the alkaline aqueous solution is preferably 8 to 120 minutes, more preferably 10 to 90 minutes, and even more preferably 15 to 60 minutes.

[0189] (Dry etching process)

[0190] In the dry etching process, it is preferable to use a gas type such as Cl 2 / Ar mixed gas.

[0191] 〔Filling process〕

[0192] The filling step is a step in which, after the barrier layer removal step, a conductive material, such as metal M2, is filled into the plurality of micropores of the anodic oxide film by electrolytic plating to form a conductive path.

[0193] <Metal M2>

[0194] The metal M2 preferably has a resistivity of 10 3 Specific examples of materials with a resistance of Ω·cm or less include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), and zinc (Zn).

[0195] Among them, from the viewpoint of electrical conductivity, Cu, Au, Al, and Ni are preferred, Cu and Au are more preferred, and Cu is further preferred.

[0196] In addition, the filling process has been described as filling with metal, but the conductive path is not limited to metal and may be made of conductive oxides, etc. Therefore, instead of metal, indium-doped tin oxide (ITO) or the like may be filled.

[0197] However, compared to oxide conductors, metals have superior ductility and are easily deformed, and are also easily deformed by compression during bonding. Therefore, the conductive path is preferably composed of metal. Among metals, Cu and Au are more preferred because, in addition to the aforementioned conductivity, they also have the property of being easily deformed by compression. Considering cost, Cu is even more preferred.

[0198] <Filling method>

[0199] As a plating method for filling the inside of the micropores with the metal M2, for example, an electrolytic plating method or an electroless plating method can be used.

[0200] Here, in the conventional electrolytic plating method for coloring, it is difficult to selectively precipitate (grow) metal in the hole with a high aspect ratio. This is because the precipitated metal is consumed in the hole, and even if electrolysis is performed for more than a certain period of time, the plating will not grow.

[0201] Therefore, when metal is filled by electrolytic plating, a pause time must be set during pulse electrolysis or constant potential electrolysis. The pause time must be at least 10 seconds, preferably 30 to 60 seconds.

[0202] Furthermore, in order to promote stirring of the electrolyte solution, it is also preferable to apply ultrasonic waves.

[0203] In addition, electrolysis voltage is generally below 20V, is preferably below 10V, but preferably measures the deposition potential of the target metal in the electrolytic solution to be used in advance, and carries out constant potential electrolysis in this current potential+1V.In addition, when carrying out constant potential electrolysis, preferably can and use the device of cyclic voltammetry, can use the constant potentiostat device of Solartron company, BAS company, HOKUTO DENKOCORPORATION, IVIUM company etc.

[0204] As the plating solution, a conventionally known plating solution can be used.

[0205] Specifically, when copper is precipitated, a copper sulfate aqueous solution is generally used, and the concentration of copper sulfate is preferably 1 to 300 g / L, more preferably 100 to 200 g / L. Furthermore, the addition of hydrochloric acid to the electrolyte can promote precipitation. In this case, the hydrochloric acid concentration is preferably 10 to 20 g / L.

[0206] Furthermore, when gold is deposited, it is preferable to perform electroplating by alternating current electrolysis using a sulfuric acid solution of tetrachlorogold.

[0207] Furthermore, in the electroless plating method, it takes a long time to completely fill the pores consisting of micropores with a high aspect ratio with metal. Therefore, in the production method of the present invention, it is preferable to fill the pores with metal by electrolytic plating.

[0208] In the present invention, the barrier layer is removed by the barrier layer removal step and a metal layer composed of the metal M1 is formed at the bottom of the micropore. Therefore, as described above, it is believed that the generation of hydrogen gas caused by the plating solution is suppressed, making metal filling by electroplating easy.

[0209] Hole expansion treatment

[0210] The pore expansion treatment is a treatment in which the aluminum member is immersed in an acid aqueous solution or an alkali aqueous solution to dissolve the anodic oxide film and expand the diameter of the micropores.

[0211] This makes it easier to control the orderliness of the micropore arrangement and the variation in pore size. Furthermore, by dissolving the barrier film at the bottom of the pores of the anodic oxide film, electrodeposition can be selectively performed inside the pores, increasing the pore size and significantly increasing the surface area of the electrode.

[0212] When an acid solution is used for the pore expansion treatment, an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture thereof is preferably used. The concentration of the acid solution is preferably 1 to 10% by mass. The temperature of the acid solution is preferably 25 to 40°C.

[0213] When an alkaline aqueous solution is used for the pore expansion treatment, it is preferably an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5% by mass. The temperature of the alkaline aqueous solution is preferably 20 to 35°C.

[0214] Specifically, for example, a 50 g / L, 40° C. aqueous phosphoric acid solution, a 0.5 g / L, 30° C. aqueous sodium hydroxide solution, or a 0.5 g / L, 30° C. aqueous potassium hydroxide solution is preferably used.

[0215] The immersion time in the acid aqueous solution or the alkaline aqueous solution is preferably 8 to 60 minutes, more preferably 10 to 50 minutes, and even more preferably 15 to 30 minutes.

[0216] [Valve metal layer removal process]

[0217] The valve metal layer removal step is a step for removing the valve metal layer. The method for removing the valve metal layer is not particularly limited; for example, removal by dissolution is preferred. In the valve metal layer removal step, a treatment solution that is less likely to dissolve the anodic oxide film but more likely to dissolve the valve metal layer is preferably used.

[0218] <Dissolution of aluminum>

[0219] As described above, when the valve metal layer is composed of aluminum, it is preferable to use a treatment liquid that does not readily dissolve the anodic oxide film but readily dissolves aluminum for dissolving the aluminum.

[0220] The dissolution rate of the aluminum by the treatment liquid is preferably 1 μm / minute or more, more preferably 3 μm / minute or more, and further preferably 5 μm / minute or more. Similarly, the dissolution rate of the anodized film is preferably 0.1 nm / minute or less, more preferably 0.05 nm / minute or less, and further preferably 0.01 nm / minute or less.

[0221] Specifically, the treatment liquid preferably contains at least one metal compound having a lower ionization tendency than aluminum and has a pH of 4 or less or 8 or more. The pH is more preferably 3 or less or 9 or more, and even more preferably 2 or less or 10 or more.

[0222] As a treatment liquid for dissolving aluminum, a treatment liquid having an acid or alkaline aqueous solution as a base and containing, for example, compounds of manganese, zinc, chromium, iron, cadmium, cobalt, nickel, tin, lead, antimony, bismuth, copper, mercury, silver, palladium, platinum, and gold (for example, chloroplatinic acid), their fluorides, their chlorides, etc. is preferred.

[0223] Among them, an acid aqueous solution matrix is preferred, and mixed chlorides are preferred.

[0224] In particular, from the viewpoint of treatment latitude, a treatment liquid in which mercuric chloride is mixed in a hydrochloric acid aqueous solution (hydrochloric acid / mercuric chloride) or a treatment liquid in which copper chloride is mixed in a hydrochloric acid aqueous solution (hydrochloric acid / copper chloride) is preferred.

[0225] The composition of the treatment liquid for dissolving aluminum is not particularly limited, and for example, a bromine / methanol mixture, a bromine / ethanol mixture, aqua regia, or the like can be used.

[0226] Furthermore, the concentration of the acid or alkali in the treatment solution for dissolving aluminum is preferably 0.01 to 10 mol / L, more preferably 0.05 to 5 mol / L.

[0227] The treatment temperature using the treatment liquid that dissolves aluminum is preferably -10°C to 80°C, more preferably 0°C to 60°C.

[0228] The aluminum is dissolved by contacting the aluminum substrate after the filling step with the treatment solution. The contact method is not particularly limited, and examples include immersion and spraying. Immersion is preferred. The contact time is preferably 10 seconds to 5 hours, more preferably 1 minute to 3 hours.

[0229] 〔Highlight process〕

[0230] The protrusion process is as follows: in order to set the protrusion, after the above-mentioned filling process, a part of the surface of the anodized film is removed in the thickness direction, so that multiple conductive paths composed of conductive materials such as the above-mentioned metal M2 protrude further than the surface of the above-mentioned anodized film.

[0231] The removal of a portion of the anodized film in the protrusion process can be performed, for example, by bringing the anodized film having through-holes filled with a conductive material into contact with an acidic or alkaline aqueous solution that does not dissolve the metal M1 and the metal M2 (particularly the metal M2) but dissolves the anodized film, such as aluminum oxide. The contact method is not particularly limited, and examples thereof include immersion and spraying. Among them, immersion is preferred.

[0232] When using an aqueous acid solution, an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, or hydrochloric acid, or a mixture thereof, is preferably used. For safety reasons, an aqueous solution that does not contain chromic acid is preferred. The concentration of the aqueous acid solution is preferably 1 to 10% by mass. The temperature of the aqueous acid solution is preferably 25 to 60°C.

[0233] When an alkaline aqueous solution is used, it is preferably an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5% by mass. The temperature of the alkaline aqueous solution is preferably 20 to 35°C.

[0234] Specifically, for example, a 50 g / L, 40° C. aqueous phosphoric acid solution, a 0.5 g / L, 30° C. aqueous sodium hydroxide solution, or a 0.5 g / L, 30° C. aqueous potassium hydroxide solution is preferably used.

[0235] The immersion time in the acidic or alkaline aqueous solution is preferably 8 to 120 minutes, more preferably 10 to 90 minutes, and even more preferably 15 to 60 minutes. When repeated short-term immersion treatments are performed, the immersion time refers to the total of each immersion time. Washing may be performed between each immersion treatment.

[0236] Structure

[0237] Figure 13 is a schematic plan view showing an example of a structure according to an embodiment of the present invention, Figure 14 This is a schematic cross-sectional view showing an example of a structure according to an embodiment of the present invention.

[0238] like Figure 13 and Figure 14 As shown, in the structure 18 , a plurality of conductive paths 16 are provided in the anodized film 14 at intervals.

[0239] like Figure 14 As shown, the structure 18 includes a conductive layer 12 and an anodized film 14 provided on the conductive layer 12. A plurality of conductive paths 16 penetrate the anodized film 14 in the thickness direction Dt. The anodized film 14 has electrical insulating properties, and therefore the plurality of conductive paths 16 are provided in the anodized film 14 in a state of being electrically insulated from each other.

[0240] The conductive member 19 is a member including the anodized film 14 and a plurality of conductive paths 16 provided in the anodized film 14 .

[0241] Here, “a state in which the conductors are electrically insulated from each other” means that the electrical conductivity between the conductors within the insulating base material is sufficiently low.

[0242] In the structure 18, the conductive member 19 is Figure 14 ) in the direction x perpendicular to the direction of the conductivity is sufficiently low, and in the thickness direction Dt (reference Figure 14 ) has conductivity. Thus, the conductive member 19 is a member in which the conductive paths 16 are electrically insulated from each other and exhibit anisotropic conductivity.

[0243] The structure 18 further includes a resin layer 17 provided on the surface 14a of the anodized film 14. The resin layer 17 has adhesive properties and also provides bonding. The length of the protrusion 16a is preferably 6 nm or more, more preferably 30 nm to 500 nm.

[0244] In addition, the conductive path 16 may also be a Figure 14 The structure of the protruding portion 16a.

[0245] Figure 14 The thickness h of the conductive member 19 shown is, for example, 30 μm or less. Furthermore, the TTV (Total Thickness Variation) of the conductive member 19 is preferably 10 μm or less.

[0246] Here, the thickness h of the conductive member 19 is obtained by observing the conductive member 19 at a magnification of 200,000 times using a field emission scanning electron microscope to obtain the contour shape of the conductive member 19 and measuring 10 points in a region corresponding to the thickness h.

[0247] The TTV (Total Thickness Variation) of the conductive member 19 is a value obtained by cutting the conductive member 19 by dicing and observing the cross-sectional shape of the conductive member 19 .

[0248] Furthermore, a protective layer (not shown) may be provided on the resin layer 17. The protective layer is used to protect the surface of the structure 18 from scratches, etc., and is preferably an easily removable tape. For example, a film with an adhesive layer can be used as the protective layer.

[0249] As the surface with an adhesive layer, commercially available products sold under the series name such as SUNYTECT [registered trademark] (manufactured by Sun A.Kaken Co., Ltd.) having an adhesive layer formed on the surface of a polyethylene resin film, E-MASK [registered trademark] (manufactured by Nitto Denko Corporation) having an adhesive layer formed on the surface of a polyethylene terephthalate resin, and MASTACK [registered trademark] (manufactured by FUJIMORI KOGYO CO., LTD.) having an adhesive layer formed on the surface of a polyethylene terephthalate resin can be used.

[0250] Furthermore, the method of attaching the film with the adhesive layer is not particularly limited, and the film can be attached using a conventionally known surface protection tape attaching device or laminator.

[0251] The distance between each conductive path in the anodic oxide film is preferably 5 nm to 800 nm, more preferably 10 nm to 200 nm, and even more preferably 50 nm to 140 nm. If the distance between each conductive path in the anodic oxide film is within this range, the anodic oxide film fully functions as an insulating barrier.

[0252] Here, the interval between each conductive path refers to the width w between adjacent conductive paths and is the average value of the widths between adjacent conductive paths measured at 10 points by observing a cross section of the structure at 200,000 magnification using a field emission scanning electron microscope.

[0253] <Conductive Path>

[0254] The plurality of conductive paths are formed of a conductive material.

[0255] <Conductive materials>

[0256] The conductive material constituting the conductive path has a resistivity of 10 3 The material with a resistance of Ω·cm or less is not particularly limited, and specific examples thereof include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), and indium-doped tin oxide (ITO).

[0257] Among them, copper, gold, aluminum, and nickel are preferred from the viewpoint of electrical conductivity, and copper and gold are more preferred.

[0258] <Protruding part>

[0259] In order to ensure sufficient insulation in the surface direction of the protrusion when it is flattened when the structure and the electrode are electrically connected or physically joined by crimping or other methods, the aspect ratio of the protrusion of the conductive path (height of the protrusion / diameter of the protrusion) is preferably greater than 0.5 and less than 50, more preferably 0.8 to 20, and even more preferably 1 to 10.

[0260] Furthermore, from the viewpoint of following the surface shape of the semiconductor component to be connected, as described above, the height of the protruding portion of the conductive path is preferably 20 nm or more, and more preferably 100 nm to 500 nm.

[0261] The height of the protruding portion of the conductive path is the average value of the heights of the protruding portion of the conductive path measured at 10 points by observing a cross section of the structure at a magnification of 20,000 times using a field emission scanning electron microscope.

[0262] The diameter of the protruding portion of the conductive path refers to the average value of the diameters of the protruding portion of the conductive path measured at 10 points on a cross section of the structure observed using a field emission scanning electron microscope.

[0263] <Other shapes>

[0264] The conductive path is columnar, and the diameter d of the conductive path is preferably greater than 5 nm and 10 μm or less, similarly to the diameter of the protruding portion, more preferably 20 nm to 1000 nm, and even more preferably 100 nm or less.

[0265] Furthermore, the conductive paths are electrically insulated from each other by the anodic oxide film, and the density is preferably 20,000 / mm 2 More than 2 million / mm 2 More than 10 million pieces / mm 2 More than 50 million / mm 2 More than 100 million / mm is most preferred 2 above.

[0266] In addition, the distance p between the centers of adjacent conductive paths (refer to Figure 13 ) is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and further preferably 50 nm to 140 nm.

[0267] <Resin layer>

[0268] The resin layer buries the conductive path. That is, the resin layer covers the surface of the anodic oxide film and the protruding portion of the conductive path.

[0269] The resin layer imparts temporary adhesiveness to the connection object. For example, the resin layer preferably exhibits fluidity in a temperature range of 50°C to 200°C and cures at 200°C or higher.

[0270] The composition of the resin agent is described below. The resin layer contains an antioxidant material and a polymer material.

[0271] <Anti-oxidation materials>

[0272] Specific examples of the antioxidant material contained in the resin layer include 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole, 5-methyl-1,2,3,4-tetrazole, 1H-tetrazole-5-acetic acid, 1H-tetrazole-5-succinic acid, 1,2,3-triazole, 4-amino-1,2,3-triazole, 4,5-diamino-1,2,3-triazole, 4-carboxyl-1H-1,2,3-triazole, 4,5-dicarboxyl-1H-1,2,3-triazole, 1H-1,2,3-triazole-4-acetic acid, 4-carboxyl-5-carboxyl Methyl-1H-1,2,3-triazole, 1,2,4-triazole, 3-amino-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-carboxy-1,2,4-triazole, 3,5-dicarboxy-1,2,4-triazole, 1,2,4-triazole-3-acetic acid, 1H-benzotriazole, 1H-benzotriazole-5-carboxylic acid, benzofurazan, 2,1,3-benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzimidazole, 2-mercaptobenzoxazole, melamine and derivatives thereof.

[0273] Among these, benzotriazole and its derivatives are preferred.

[0274] Examples of benzotriazole derivatives include substituted benzotriazoles having a hydroxyl group, an alkoxy group (e.g., methoxy, ethoxy, etc.), an amino group, a nitro group, an alkyl group (e.g., methyl, ethyl, butyl, etc.), a halogen atom (e.g., fluorine, chlorine, bromine, iodine, etc.) on the benzene ring of the benzotriazole. Examples include naphthalenetriazole, naphthalenebistriazole, and similarly substituted naphthalenetriazoles and substituted naphthalenebistriazoles.

[0275] Furthermore, other examples of the antioxidant material contained in the resin layer include common antioxidants such as higher fatty acids, higher fatty acid copper, phenol compounds, alkanolamines, hydroquinones, copper chelating agents, organic amines, and organic ammonium salts.

[0276] The content of the antioxidant material in the resin layer is not particularly limited, but from the perspective of corrosion protection, it is preferably 0.0001% by mass or greater, more preferably 0.001% by mass or greater, relative to the total mass of the resin layer. Furthermore, to achieve appropriate resistance during the actual bonding process, it is preferably 5.0% by mass or less, more preferably 2.5% by mass or less.

[0277] <Polymer Materials>

[0278] The polymer material contained in the resin layer is not particularly limited, but is preferably a thermosetting resin because it can efficiently fill the gap between the bonding object such as the semiconductor chip or semiconductor wafer and the structure and further improve the adhesion between the structure and the semiconductor chip or semiconductor wafer.

[0279] Specific examples of the thermosetting resin include epoxy resins, phenolic resins, polyimide resins, polyester resins, polyurethane resins, bismaleimide resins, melamine resins, and isocyanate resins.

[0280] Among them, polyimide resin and / or epoxy resin are preferably used because they can further improve insulation reliability and have excellent chemical resistance.

[0281] <Migration prevention materials>

[0282] The resin layer preferably contains a migration preventing material in order to further improve insulation reliability by capturing metal ions and halogen ions that may be contained in the resin layer, as well as metal ions originating from the semiconductor chip and the semiconductor wafer.

[0283] As the migration preventing material, for example, an ion exchanger can be used. Specifically, a mixture of a cation exchanger and an anion exchanger or only a cation exchanger can be used.

[0284] Here, the cation exchanger and the anion exchanger can be appropriately selected from, for example, inorganic ion exchangers and organic ion exchangers described below, respectively.

[0285] (Inorganic ion exchanger)

[0286] Examples of the inorganic ion exchanger include hydrous oxides of metals such as hydrous zirconium oxide.

[0287] As the types of metals, for example, iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, bismuth, and the like are known in addition to zirconium.

[0288] Among these, zirconium is the most active cationic Cu 2+ 、Al 3+ It has exchange capacity. And, iron has strong + 、Cu2+ Similarly, tin, titanium, and antimony are cation exchangers.

[0289] On the other hand, bismuth anions Cl - Has exchange capability.

[0290] Furthermore, zirconium exhibits anion exchange capacity depending on the production conditions, and the same is true for aluminum and tin.

[0291] As inorganic ion exchangers other than these, there are known synthetic compounds such as acidic salts of polyvalent metals represented by zirconium phosphate, heteropolyacid salts represented by ammonium phosphomolybdate, and insoluble ferrocyanide.

[0292] Some of these inorganic ion exchangers are commercially available, and for example, various grades are known under the trade name "IXE" from TOAGOSE Co., Ltd.

[0293] In addition to synthetic products, powders of inorganic ion exchangers such as natural zeolite and montmorillonite can also be used.

[0294] (Organic ion exchanger)

[0295] Among organic ion exchangers, examples of cation exchangers include cross-linked polystyrene having a sulfonic acid group, and further examples include cross-linked polystyrene having a carboxylic acid group, a phosphonic acid group, or a phosphinic acid group.

[0296] Furthermore, examples of the anion exchanger include cross-linked polystyrene having a quaternary ammonium group, a quaternary phosphonium group, or a tertiary sulfonium group.

[0297] These inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the type of cations and anions to be captured and their exchange capacity for the ions. Of course, inorganic ion exchangers and organic ion exchangers may also be used in combination.

[0298] Since the manufacturing process of electronic components includes a heating step, an inorganic ion exchanger is preferred.

[0299] Furthermore, regarding the mixing ratio of the ion exchanger to the polymer material, for example, from the perspective of mechanical strength, the ion exchanger is preferably 10% by mass or less, more preferably 5% by mass or less, and even more preferably 2.5% by mass or less. Furthermore, from the perspective of suppressing migration during bonding of a semiconductor chip or semiconductor wafer to a structure, the ion exchanger is preferably 0.01% by mass or more.

[0300] <Inorganic fillers>

[0301] The resin layer preferably contains an inorganic filler.

[0302] The inorganic filler is not particularly limited and can be appropriately selected from known inorganic fillers. Examples thereof include kaolin, barium sulfate, barium titanate, silica powder, finely powdered silica, fumed silica, amorphous silica, crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconium oxide, yttrium oxide, silicon carbide, and silicon nitride.

[0303] In order to prevent the inorganic filler from entering between the conductive paths and further improve the conduction reliability, the average particle size of the inorganic filler is preferably larger than the interval between the conductive paths.

[0304] The average particle size of the inorganic filler is preferably 30 nm to 10 μm, more preferably 80 nm to 1 μm.

[0305] Here, the average particle size is defined as the primary particle size measured using a laser diffraction and scattering particle size analyzer (MICROTRAC MT3300 manufactured by Nikkiso Co., Ltd.).

[0306] Curing agent

[0307] The resin layer may contain a curing agent.

[0308] When a curing agent is contained, it is more preferable to contain a curing agent that is liquid at room temperature rather than a solid curing agent at room temperature from the viewpoint of suppressing poor bonding to the surface shape of the semiconductor chip or semiconductor wafer to be connected.

[0309] Here, "solid at room temperature" means solid at 25°C, and for example, refers to a substance having a melting point higher than 25°C.

[0310] Specific examples of the curing agent include aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone, aliphatic amines, imidazole derivatives such as 4-methylimidazole, dicyandiamide, tetramethylguanidine, thiourea-added amines, carboxylic anhydrides such as methylhexahydrophthalic anhydride, carboxylic acid hydrazides, carboxylic acid amides, polyphenol compounds, novolac resins, and polythiol. From these curing agents, a curing agent that is liquid at 25° C. can be appropriately selected and used. The curing agents may be used alone or in combination of two or more.

[0311] The resin layer may contain various additives such as a dispersant, a buffer, and a viscosity modifier, which are widely and generally added to the resin insulating film of a semiconductor package, within a range that does not impair its characteristics.

[0312] <Shape>

[0313] In order to protect the conductive path of the structure, the thickness of the resin layer is larger than the height of the protruding portion of the conductive path, and is preferably 1 μm to 5 μm.

[0314] [Joining of structures]

[0315] Next, the joining of the structure 18 produced as described above will be described.

[0316] Figure 15 This is a schematic cross-sectional view showing an example of the structure of a structured body according to an embodiment of the present invention. Figure 16 and Figure 17 This is a schematic cross-sectional view showing an example of a method for joining a structure according to an embodiment of the present invention in order of steps. Figure 16 and Figure 17 The bonding method shown is related to chip on chip, and a semiconductor element 30 is bonded to a semiconductor element 32 as a structure 18. In this way, a bonded body 39 is obtained.

[0317] Figure 15 The semiconductor elements 30 and 32 shown include a semiconductor layer 33, a redistribution layer 34, and a passivation layer 36. The redistribution layer 34 and the passivation layer 36 are electrically insulating layers. A component region (not shown) containing circuits and other components that perform specific functions is provided on the surface 33a of the semiconductor layer 33. The component region will be described later. The surface 33a of the semiconductor layer 33 corresponds to the surface of the semiconductor where the terminals are provided.

[0318] A redistribution layer 34 is provided on the surface 33a of the semiconductor layer 33. The redistribution layer 34 includes wiring 37 electrically connected to the device region of the semiconductor layer 33. Pads 38 are provided on the wiring 37, and the wiring 37 and the pads 38 are electrically connected. The wiring 37 and the pads 38 enable signals to be transferred to and from the device region, and voltage, etc., can be supplied to the device region.

[0319] A passivation layer 36 is provided on the surface 34a of the redistribution layer 34. In the passivation layer 36, a conductive layer 12 functioning as an extraction electrode is provided on the pad 38 provided on the wiring 37. The conductive layer 12 is electrically connected to the semiconductor layer 33.

[0320] Furthermore, the redistribution layer 34 has no wiring 37 but only pads 38. The conductive layer 12 functioning as an electrode is provided on the pads 38 not provided on the wiring 37. The conductive layer 12 is not electrically connected to the semiconductor layer 33.

[0321] The end surface 12c of the conductive layer 12 is aligned with the surface 36a of the passivation layer 36 and is in the same horizontal plane. The conductive layer 12 does not protrude from the surface 36a of the passivation layer 36. Figure 15 The conductive layer 12 shown is polished to the same level as the surface 36a of the passivation layer 36, for example. The end surface 12c of the conductive layer 12 of the semiconductor element 30 corresponds to the surface 12a of the conductive layer 12. Conductive members 19 are formed on the end surface 12c of the conductive layer 12, forming a structure 18. Furthermore, when joining two semiconductor elements 30 and 32, either one can be used as the structure 18 to form the conductive member 19. Alternatively, both semiconductor elements 30 and 32 can be joined as the structure 18. In other words, the conductive members 19 can be joined to each other.

[0322] like Figure 16 As shown, the semiconductor element 30 and the semiconductor element 32 are arranged so that the conductive layer 12 faces each other.

[0323] The semiconductor element 30 and the semiconductor element 32 are aligned by, for example, using alignment marks (not shown) to align the conductive layer 12 of the semiconductor element 30 with the conductive layer 12 of the semiconductor element 32. The alignment is also referred to as alignment.

[0324] exist Figure 16 In the embodiment, the conductive member 19 is formed in the semiconductor element 30 located below.

[0325] In a state where the semiconductor element 30 and the semiconductor element 32 are aligned, as shown in FIG. Figure 17 As shown, semiconductor element 30 and semiconductor element 32 are brought close together so that conductive member 19 of semiconductor element 30 contacts conductive layer 12 of semiconductor element 32, thereby temporarily bonding semiconductor element 30 and semiconductor element 32. This temporary bonding will be described later, but it is a state of maintaining alignment, not a permanent fixation.

[0326] Then, if Figure 17 As shown, semiconductor element 30 and semiconductor element 32 are bonded. Consequently, corresponding conductive layers 12 are directly connected to each other via conductive member 19. Thus, semiconductor element 30 and semiconductor element 32 are electrically connected to each other through conductive member 19 and conductive layer 12, and are physically connected, rather than being electrically connected through conductive member 19 and conductive layer 12.

[0327] The step of bonding at least two components such as the semiconductor element 30 and the semiconductor element 32 is referred to as a bonding step. In the bonding step, for example, at least two components are bonded under predetermined bonding conditions.

[0328] In addition, joining refers to joining objects together to ensure mutual electrical conduction. In the case of joining, the objects remain joined permanently. The joining process is also called formal joining.

[0329] In the joining process, for example, joining can be performed under pre-determined conditions in a temporary joining state, but the temporary joining can also be omitted. In addition, the temporary joining process is referred to as the temporary joining process, and the joining process other than the temporary joining is also referred to as the formal joining.

[0330] The semiconductor layer 33 is not particularly limited as long as it is a semiconductor. Although it is made of silicon or the like, it is not limited thereto and may be silicon carbide, germanium, gallium arsenide, gallium nitride, or the like.

[0331] The redistribution layer 34 is made of an electrically insulating material, such as polyimide.

[0332] Furthermore, the passivation layer 36 is also made of an electrically insulating material, such as silicon nitride (SiN) or polyimide.

[0333] The wiring 37 and the pad 38 are made of a conductive material, such as copper, a copper alloy, aluminum, or an aluminum alloy.

[0334] Conductive layer 12 and conductive layer 12 are made of a material having the same conductivity as wiring 37 and pad 38, for example, a metal or alloy. Specifically, conductive layer 12 and conductive layer 12 are made of, for example, copper, a copper alloy, aluminum, or an aluminum alloy. As described above, conductive layer 12 and the conductive substance filled in structure 18 are preferably made of the same material.

[0335] The conductive layer 12 and the conductive layer 12 are not limited to being made of metal or alloy as long as they have conductivity, and materials used for terminals or components called electrode pads in the field of semiconductor devices can be appropriately used.

[0336] [Stacked Devices]

[0337] Next, a stacked device will be described as an example using the structure 18 .

[0338] Figure 18 1 is a schematic diagram showing a first example of a stacked device using a structure according to an embodiment of the present invention. Figure 19 1 is a schematic diagram showing a second example of a stacked device using the structure according to the embodiment of the present invention. Figure 20 1 is a schematic diagram showing a third example of a stacked device using the structure according to the embodiment of the present invention. Figure 21 This is a schematic diagram showing a fourth example of a stacked device using the structure according to the embodiment of the present invention.

[0339] exist Figure 18 In the stacked device 40 shown, either semiconductor element 42 or semiconductor element 44 is used as structure 18. Stacked device 40 is formed by bonding semiconductor element 42 and semiconductor element 44 via conductive member 19 (not shown) in stacking direction Ds to electrically connect semiconductor element 42 and semiconductor element 44.

[0340] The conductive member 19 of the structure 18 has a conductive path 16 (see FIG. Figure 14 ), and play the role of TSV (Through Silicon Via).

[0341] Apart from Figure 18 In addition to the structure shown, for example Figure 19 As in the stacked device 40 shown, a structure in which the semiconductor element 42 , the semiconductor element 44 , and the semiconductor element 46 are stacked in the stacking direction Ds and bonded and electrically connected may be employed.

[0342] Furthermore, based on the structure 18, as Figure 20 As in the stacked device 40 shown, a structure in which the semiconductor element 42 , the semiconductor element 44 , and the semiconductor element 46 are stacked in the stacking direction Ds using an interposer 45 , and are bonded and electrically connected can be adopted.

[0343] Interposer 45 is responsible for the electrical connection between semiconductor elements and also for the electrical connection between semiconductor elements and a wiring substrate, etc. Using interposer 45 can reduce wiring length and width, parasitic capacitance, and variations in wiring length.

[0344] The structure of the interposer 45 is not particularly limited as long as it can achieve the above-mentioned functions, and any known structure can be appropriately used. The interposer 45 can be made of, for example, organic materials such as polyimide, glass, ceramics, metal, silicon, and polysilicon.

[0345] And, as Figure 21 The stacked device 40 shown in FIG. 1 can function as an optical sensor. Figure 21 In the stacked device 40 shown, a semiconductor element 42 and a sensor chip 47 are stacked in a stacking direction Ds. In the stacked device 40, the semiconductor element 42 and the sensor chip 47 are bonded together using a structure 18. Furthermore, a lens 48 is provided on the sensor chip 47.

[0346] The semiconductor element 42 forms a logic circuit, and its structure is not particularly limited as long as it can process the signal obtained from the sensor chip 47 .

[0347] The sensor chip 47 includes a light sensor that detects light. The light sensor is not particularly limited as long as it can detect light, and for example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor can be used.

[0348] The structure of the lens 48 is not particularly limited as long as it can collect light on the sensor chip 47 , and for example, a member called a microlens can be used.

[0349] Furthermore, the semiconductor elements 42, 44, and 46 have element regions (not shown). The element regions are as described above. As described above, the element regions have element-constituting circuits formed therein, and, for example, a redistribution layer (not shown) is provided in the semiconductor elements.

[0350] In a stacked device, for example, a semiconductor element having a logic circuit and a semiconductor element having a memory circuit can be combined. Furthermore, all semiconductor elements can be elements having a memory circuit, and all semiconductor elements can be elements having a logic circuit. Furthermore, the combination of semiconductor elements in the stacked device 40 can include a combination of sensors, actuators, antennas, etc., with memory circuits and logic circuits, and can be appropriately determined based on the application of the stacked device 40.

[0351] Semiconductor components

[0352] In addition to the above-mentioned elements, the semiconductor elements 42, 44 and 46 may include, for example, logic LSI (Large Scale Integration) (for example, ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), ASSP (Application Specific Standard Product), etc.), microprocessors (for example, CPU (Central Processing Unit), GPU (Graphics Processing Unit), etc.), memories (for example, DRAM (Dynamic Random Access Memory), HMC (Hybrid Memory Cube), MRAM (Magnetic RAM) and PCM (Phase-Change Memory), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM), flash memories (NAND (Not AND) flash memories), etc.), LEDs (Light Emitting Diodes). Diode (for example, micro-flash for mobile terminals, automotive applications, projector light sources, LCD backlights, general lighting, etc.), power devices, analog IC (Integrated Circuit) (for example, DC (Direct Current)-DC (Direct Current) converters, insulated gate bipolar transistors (IGBTs), etc.), MEMS (Micro Electro Mechanical Systems) (for example, acceleration sensors, pressure sensors, vibrators, gyroscope sensors, etc.), wireless (for example,GPS (Global Positioning System), FM (Frequency Modulation), NFC (Nearfield Communication), RFEM (RF Expansion Module), MMIC (Monolithic Microwave Integrated Circuit), WLAN (Wireless Local Area Network), discrete components, BSI (Back Side Illumination), CIS (Contact Image Sensor), camera modules, CMOS (Complementary Metal Oxide Semiconductor), passive devices, SAW (Surface Acoustic Wave) filters, RF (Radio Frequency) filters, RFIPDs (Radio Frequency Integrated Passive Devices), BB (Broadband), etc.

[0353] A semiconductor element is, for example, a completely constructed element, and a specific function such as a circuit or a sensor is achieved by the semiconductor element alone.

[0354] Furthermore, the stacked device is not limited to a one-to-many system in which a plurality of semiconductor elements are bonded to one semiconductor element, but may also be a many-to-many system in which a plurality of semiconductor elements are bonded to a plurality of semiconductor elements.

[0355] [First Example of Method for Manufacturing a Laminated Device]

[0356] Next, a first example of a method for manufacturing a stacked device using the structure will be described.

[0357] The first example of a method for manufacturing a stacked device using a structure is related to a chip on wafer. Figure 18 The manufacturing method of the stacked device 40 is shown.

[0358] Figures 22 to 24 This is a schematic diagram showing a first example of a method for manufacturing a stacked device using a structure according to an embodiment of the present invention in order of steps.

[0359] In the first example of the method for manufacturing a stacked device using a structure, a structure 18 is manufactured on a first semiconductor wafer 50. A plurality of device regions (not shown) exist on a surface 50a of the first semiconductor wafer 50, and a conductive member 19 is provided in each device region.

[0360] Next, the semiconductor element 44 is placed facing the conductive member 19 of the first semiconductor wafer 50. Next, the semiconductor element 44 is positioned on the first semiconductor wafer 50 using the alignment mark of the semiconductor element 44 and the alignment mark of the first semiconductor wafer 50.

[0361] In addition, regarding alignment, as long as digital image data can be obtained regarding the image or reflection image of the alignment mark of the first semiconductor chip 50 and the image or reflection image of the alignment mark of the semiconductor element 44, its structure is not particularly limited and a known camera device can be appropriately used.

[0362] Next, the semiconductor element 44 is placed on the conductive member 19 provided in the element region of the first semiconductor wafer 50, and a predetermined pressure is applied, for example, and heated to a predetermined temperature and maintained for a predetermined time, for example, using the resin layer 17 (refer to Figure 14 ) for temporary bonding. The above process is performed on all semiconductor elements 44, such as Figure 23 As shown, all semiconductor elements 44 are temporarily bonded to the element region of the first semiconductor wafer 50 .

[0363] Using the resin layer 17 for temporary bonding is one method, and the following methods may also be used. For example, a sealing resin or the like may be supplied onto the conductive member 19 of the first semiconductor wafer 50 using a dispenser or the like, and the semiconductor element 44 may be temporarily bonded to the element region of the first semiconductor wafer 50. Alternatively, a pre-supplied insulating resin film (NCF (Non-conductive Film)) may be used on the first semiconductor wafer 50 to temporarily bond the semiconductor element 44 to the element region.

[0364] Next, while all semiconductor elements 44 are temporarily bonded to the element region of the first semiconductor wafer 50, a predetermined pressure is applied to the semiconductor elements 44, and the temperature is heated to a predetermined temperature and maintained for a predetermined time. This allows all of the semiconductor elements 44 to be collectively bonded to the element region of the first semiconductor wafer 50 via the conductive member 19. This bonding is called final bonding. Thus, the terminals (not shown) of the semiconductor elements 44 are bonded to the conductive member 19 of the first semiconductor wafer 50.

[0365] Then, if Figure 24As shown, the first semiconductor wafer 50 to which the semiconductor element 44 is bonded is singulated for each element region by dicing or laser scribing, etc. Thus, the stacked device 40 in which the semiconductor element 42 and the semiconductor element 44 are bonded can be obtained.

[0366] Furthermore, if the temporary joining strength is weak during temporary joining, positional deviation may occur during the conveying process and the process before joining, so the temporary joining strength becomes important.

[0367] Furthermore, the temperature conditions and pressurizing conditions in the provisional bonding step are not particularly limited, and examples thereof include the temperature conditions and pressurizing conditions described later.

[0368] The temperature conditions and pressurizing conditions in the main bonding step are not particularly limited, and examples thereof include the temperature conditions and pressurizing conditions described below.

[0369] By performing the final bonding under appropriate conditions, the resin layer flows between the electrodes of the semiconductor element 44 and is less likely to remain at the bonded portion. As described above, by collectively bonding multiple semiconductor elements 44 during the final bonding, the takt time can be reduced, thereby improving productivity.

[0370] [Second Example of Method for Manufacturing a Laminated Device]

[0371] A second example of the method for manufacturing a stacked device using the structure will be described.

[0372] Figure 25 This is a schematic diagram showing one step of a second example of a method for manufacturing a stacked device using the structure according to the embodiment of the present invention.

[0373] Compared to the first example of the method for manufacturing a stacked device using a structure, the second example of the method for manufacturing a stacked device using a structure is the same as the first example of the method for manufacturing a stacked device using a structure, except that the three semiconductor elements 42, 44, and 46 are stacked and bonded. Therefore, a detailed description of the manufacturing method common to the second example of the method for manufacturing a stacked device will be omitted.

[0374] Semiconductor element 44 has alignment marks (not shown) and terminals (not shown) on its back surface 44b. Furthermore, semiconductor element 46 includes structure 18 and conductive member 19 on its surface 46a. Similar to first semiconductor wafer 50, semiconductor element 46 is formed by fabricating structure 18 in an element region (not shown) and singulating the resulting wafers. Therefore, semiconductor element 46 includes conductive member 19.

[0375] like Figure 25As shown, in a state where all semiconductor elements 44 are temporarily bonded to the element region of the first semiconductor wafer 50 via the conductive member 19 , the semiconductor elements 44 and 46 are aligned using the alignment mark on the back surface 44 b of the semiconductor element 44 and the alignment mark of the semiconductor element 46 .

[0376] Next, semiconductor element 46 is provisionally bonded to back surface 44b of semiconductor element 44 via conductive member 19. Then, with all semiconductor elements 44 provisionally bonded to the element region of first semiconductor wafer 50 via conductive member 19, and semiconductor element 46 provisionally bonded to all semiconductor elements 44 via conductive member 19, final bonding is performed under predetermined conditions. Thus, semiconductor elements 44 and 46 are bonded, and semiconductor element 44 and first semiconductor wafer 50 are bonded.

[0377] Next, in a state where the semiconductor element 44 and the semiconductor element 46 are bonded to the first semiconductor wafer 50, they are singulated for each element region by, for example, dicing or laser scribing. Thus, a stacked device 40 (see FIG. 1 ) in which the semiconductor element 42, the semiconductor element 44, and the semiconductor element 46 are bonded can be obtained. Figure 19 ).

[0378] [Third Example of Method for Manufacturing a Laminated Device]

[0379] A third example of the method for manufacturing a stacked device using the structure will be described.

[0380] The third example of the method for manufacturing a stacked device using a structure is related to wafer on wafer. Figure 18 The method for manufacturing the stacked device 40 is shown.

[0381] Figure 26 and Figure 27 This is a schematic diagram showing a third example of a method for manufacturing a stacked device using the structure according to the embodiment of the present invention in order of steps.

[0382] Compared to the first example of the method for manufacturing a stacked device, the third example of the method for manufacturing a stacked device using a structure is identical to the first example of the method for manufacturing a stacked device, except that the structure 18 is used to bond the first semiconductor wafer 50 and the second semiconductor wafer 52. Therefore, a detailed description of the manufacturing method common to the first example of the method for manufacturing a stacked device will be omitted. Furthermore, since the structure 18 is as described above, a detailed description thereof will be omitted.

[0383] First, a first semiconductor wafer 50 and a second semiconductor wafer 52 are prepared. Either the first semiconductor wafer 50 or the second semiconductor wafer 52 is used as the structure 18 .

[0384] Next, the surface 50a of the first semiconductor wafer 50 is placed opposite the surface 52a of the second semiconductor wafer 52. Then, the first semiconductor wafer 50 is aligned with the second semiconductor wafer 52 using the alignment marks of the first semiconductor wafer 50 and the alignment marks of the second semiconductor wafer 52.

[0385] Next, the surface 50a of the first semiconductor wafer 50 and the surface 52a of the second semiconductor wafer 52 are placed opposite to each other. Figure 26 As shown, the first semiconductor wafer 50 and the second semiconductor wafer 52 are bonded together by the above-described method via the conductive member 19. In this case, the final bonding may be performed after the provisional bonding, or only the final bonding may be performed.

[0386] Then, if Figure 27 As shown, with the first semiconductor wafer 50 and the second semiconductor wafer 52 bonded via the conductive member 19, they are singulated for each device region, for example, by dicing or laser scribing. This yields a stacked device 40 in which the semiconductor elements 42 and 44 are bonded. In this manner, a stacked device 40 can be obtained even using a wafer-on-wafer method.

[0387] In addition, as for the singulation, as described above, detailed description is omitted.

[0388] And, as Figure 27 As shown, in a state where the first semiconductor wafer 50 and the second semiconductor wafer 52 are bonded, if one of the first semiconductor wafer 50 and the second semiconductor wafer 52 needs to be thinned, the thinning can be performed by chemical mechanical polishing (CMP) or the like.

[0389] In the third example of the method for manufacturing a stacked device using a structure, a two-layer structure of stacked semiconductor elements 42 and 44 is described as an example, but the present invention is not limited to this. As mentioned above, three or more layers are also possible. In this case, similar to the second example of the method for manufacturing the stacked device 40, alignment marks (not shown) and terminals (not shown) are provided on the back surface 52b of the second semiconductor wafer 52, thereby obtaining a stacked device 40 having three or more layers.

[0390] As described above, by utilizing structure 18 in stacked device 40, even if irregularities exist within the semiconductor element, these irregularities can be absorbed by protruding portion 16a, which functions as a buffer layer. Because protruding portion 16a functions as a buffer layer, high surface quality requirements are no longer required for the surface of the semiconductor element where the device region is located. This eliminates the need for smoothing processes such as polishing, reducing production costs and shortening production time.

[0391] Furthermore, since the stacked device 40 can be manufactured using a chip-on-wafer, the yield can be maintained and manufacturing losses can be reduced by bonding only good semiconductor chips to good parts within the semiconductor wafer.

[0392] Furthermore, as described above, the resin layer 17 has adhesive properties and can be used as a temporary adhesive during temporary bonding, thereby enabling full bonding to be performed in a lump sum.

[0393] The semiconductor element 44 can be formed using a semiconductor wafer having a plurality of element regions (not shown). As described above, alignment marks (not shown) and terminals (not shown) for alignment are provided in the element regions.

[0394] The bonding of stacked devices has been described using a method in which a semiconductor element is bonded to another semiconductor element. However, the bonding is not limited to this method and may be a one-to-many method in which a plurality of semiconductor elements are bonded to one semiconductor element. Alternatively, a many-to-many method in which a plurality of semiconductor elements are bonded to a plurality of semiconductor elements may be bonded.

[0395] Hereinafter, a method for manufacturing a stacked device will be described in more detail.

[0396] Temporary joining process

[0397] Temporary bonding in the temporary bonding process involves securing the semiconductor element to the object while it is aligned with the object. Temporary bonding maintains alignment but does not permanently secure the semiconductor element. Temporary bonding secures the semiconductor element to the object while it is aligned with the object.

[0398] The temporary joining step is performed by bringing at least two components into contact with each other. In this case, the pressurizing conditions are not particularly limited, but are preferably 10 MPa or less, more preferably 5 MPa or less, and particularly preferably 1 MPa or less.

[0399] Likewise, the temperature conditions in the temporary bonding step are not particularly limited, but are preferably 0°C to 300°C, more preferably 10°C to 200°C, and particularly preferably room temperature (23°C) to 100°C.

[0400] In the provisional joining process, devices from various companies such as TORAY ENGINEERING Co., Ltd., SHIBUYA CORPORATION, SHINKAWA LTD., and Yamaha Motor Co., Ltd. can be used.

[0401] 〔Joining process〕

[0402] As mentioned above, the bonding process is also called formal bonding. As mentioned above, once bonded, the objects remain permanently bonded. During formal bonding, factors such as the atmosphere, heating temperature, pressure (load), and processing time can be controlled, allowing conditions to be selected that are appropriate for the device being used, such as the semiconductor element.

[0403] The temperature conditions during the final bonding are not particularly limited, but are preferably a temperature higher than the temperature during the temporary bonding. Specifically, 150°C to 350°C is more preferred, and 200°C to 300°C is particularly preferred.

[0404] The pressurization conditions during the final joining are not particularly limited, but are preferably 30 MPa or less, more preferably 0.1 MPa to 20 MPa. The maximum load under the pressurization conditions is preferably 1 MN or less, and more preferably 0.1 MN or less.

[0405] The time for the main joining is not particularly limited, but is preferably 1 second to 60 minutes, more preferably 5 seconds to 10 minutes.

[0406] Furthermore, as devices for the above-mentioned formal bonding, for example, chip bonding devices from companies such as Mitsubishi Heavy Industries Machine Tool Co., Ltd., bondtech, PMT Corporation, Ayumi Industry Co., Ltd., Tokyo Electron Limited (TEL), EVG, Suss Microtec KK (SUSS), and MUSASHINO ENGINEERING CO., LTD. can be used.

[0407] The atmosphere during the final bonding process can be any of the following: an inert gas such as nitrogen or argon, a reducing gas such as hydrogen or carboxylic acid, or a mixture of these inert and reducing gases, starting with atmospheric air. Furthermore, a reduced pressure atmosphere, including a vacuum atmosphere, can also be used during the final bonding process. Any of these atmospheres can be achieved using known methods.

[0408] The heating temperature is not particularly limited to the above-mentioned temperatures and can be selected from a range of temperatures between 100°C and 400°C. The heating rate can also be selected from a range of 10°C / minute to 10°C / second depending on the performance of the heating stage or the heating method. The same applies to cooling. Furthermore, heating can be performed in steps, or the heating temperature can be increased in stages to achieve bonding.

[0409] The pressure (load) is not particularly limited to the above-mentioned pressures, and rapid pressure application or step-wise pressure application can be selected according to the physical properties such as the strength of the objects to be joined.

[0410] The holding time and change time of the atmosphere, heating, and pressurization during formal bonding can be set appropriately. Furthermore, the order of these can be changed as appropriate. For example, the following steps can be adopted: after achieving a vacuum state, the first stage of pressurization is performed, followed by heating and then the temperature is raised, followed by the second stage of pressurization and holding for a period of time, followed by cooling while the load is released, and returning to atmospheric pressure when the temperature reaches below a certain level.

[0411] This step can be varied in various ways. After pressurizing under the atmosphere, it can be set to a vacuum state and then heated. Alternatively, vacuumization, pressurization, and heating can be performed at once. Examples of their combination are shown in FIG. Figures 28 to 34 .

[0412] Furthermore, if a mechanism is used to individually control the pressure distribution and the heat distribution within the surface during bonding, the bonding yield can be improved.

[0413] Temporary bonding can also be modified in the same manner. For example, by performing the bonding in an inert atmosphere, oxidation of the electrode surface of the semiconductor element can be suppressed. Alternatively, bonding can be performed while applying ultrasonic waves.

[0414] Figures 28 to 34 It is a graph showing first to seventh examples of the actual bonding conditions of a stacked device using the structure according to the embodiment of the present invention. Figures 28 to 34 The following table shows the atmosphere, heating temperature, pressure (load) and processing time during bonding. Symbol V represents the degree of vacuum, symbol L represents the load, and symbol T represents the temperature. Figures 28 to 34 In the case of a high vacuum, the pressure decreases. Figures 28 to 34 The lower the vacuum degree, the closer it is to atmospheric pressure.

[0415] The atmosphere, heating temperature and load during bonding can be determined, for example, as follows: Figures 28 to 30 As shown in FIG, after applying a load in a state of reduced pressure, the temperature is raised. Figure 31 、 Figure 33 and Figure 34 As shown in the figure, the time of applying the load is aligned with the time of increasing the temperature. Figure 32 As shown in FIG, after raising the temperature, the load is applied. Figure 31 and Figure 32 As shown, the timing of pressure reduction is aligned with the timing of temperature increase.

[0416] The temperature rise can also be Figure 28 、 Figure 29and Figure 33 As shown, it can be increased in steps, or as Figure 34 The heating is carried out in two stages as shown in FIG. The load can also be Figure 30 and Figure 33 As shown, apply in steps.

[0417] Furthermore, the pressure reduction moment can be as follows Figure 28 、 Figure 30 、 Figure 32 、 Figure 33 and Figure 34 As shown, the load can be applied after decompression, or as Figure 29 and Figure 31 As shown, the timing of decompression is aligned with the timing of load application. In this case, decompression and bonding are performed simultaneously.

[0418] [Other joining processes]

[0419] The bonding method is not limited to the above method. For example, the semiconductor element 42 and the semiconductor element 44 are stacked via an electrode material containing at least tin as a heat-melting material. In this case, the electrode material is arranged at Figure 14 On the protruding portion 16a shown.

[0420] Next, the heated molten material containing tin is heated at a pressure of 1×10 4 Pa or more and in an atmosphere containing carboxylic acid vapor such as formic acid vapor, the heating process is performed to a temperature above the melting point of the heated molten material to melt it. Thus, the electrode material is formed into an electrode on the protruding portion 16a. Next, the semiconductor element 42 and the semiconductor element 44 are brought close together, and after the heated molten material solidifies, the carboxylic acid vapor is discharged and the 1×10 4 Pa above the pressure to 1×10 2 Pa or less. When the temperature of the electrode material is above 100 ° C and below the melting point, the carboxylic acid vapor is discharged. After decompression, it is replaced with an inert gas atmosphere that does not contain carboxylic acid. Figure 18 As shown, semiconductor element 42 and semiconductor element 44 are bonded together to obtain a stacked device 40. Furthermore, the carboxylic acid acts as a reducing agent, enabling bonding at a lower temperature. Furthermore, the electrode material containing tin is, for example, a solder material containing tin.

[0421] Furthermore, for example, the semiconductor element 42 and the semiconductor element 44 are stacked via a composition layer. In this case, the composition layer is arranged on Figure 14 Then, the protrusion 16a is heated at a temperature of 120 to 250°C in an atmosphere of any one of an inert gas, a reducing gas or a mixed gas thereof, and a load is applied. Figure 18As shown, semiconductor element 42 and semiconductor element 44 are bonded together to obtain a stacked device 40 .

[0422] In addition, the gas atmosphere is a gas atmosphere containing hydrogen gas or formic acid gas.

[0423] The conductor-forming composition comprises copper-containing particles, an organic acid, and a dispersion medium. The copper-containing particles have a core particle containing copper and an organic substance coating at least a portion of the surface of the core particle. The organic substance comprises an alkylamine having a hydrocarbon group having 7 or fewer carbon atoms.

[0424] Copper-containing particles are, for example, copper-containing particles disclosed in Japanese Patent Application Laid-Open No. 2016-037627. Copper-containing particles contain at least copper and may contain, as substances other than copper, metals such as gold, silver, platinum, tin, and nickel, or compounds containing these metal elements, reducing compounds, or organic substances.

[0425] The organic acid is, for example, an organic carboxylic acid used as a flux component for soldering, etc. The dispersion medium is an organic solvent generally used in the production of conductive inks, conductive pastes, and the like.

[0426] Regarding the bonding atmosphere, a known method can be used, such as introducing not only a vacuum atmosphere but also an atmosphere of any one of inert gases such as nitrogen and argon, or reducing gases such as hydrogen and carboxylic acid, or a mixture of these inert gases and reducing gases. It is particularly preferred to use a gas containing a reducing gas. Regarding the technology using these gases, technologies related to the fusion bonding of solder or bonding technologies using fine metal particles can be applied, and a reducing atmosphere gas containing carboxylic acids headed by formic acid or a reducing atmosphere gas containing hydrogen can be introduced into the chamber and heated and pressurized for bonding. The concentration of carboxylic acid in the atmosphere gas is preferably below the explosion limit and above 0.002%. In the case of a gas containing hydrogen, it is also preferably below the explosion limit and above 1%. By bonding under a reducing atmosphere, the detachment of organic matter on the surface of the copper pillar protruding on the surface of the anisotropic conductive component manufactured in the present invention and the removal of the oxide film become easy, and the bonding of the copper pillar to the copper electrode to be bonded is promoted.

[0427] Specifically, after the bonding object is introduced into the chamber, the chamber is temporarily evacuated and the reducing atmosphere gas is introduced into the chamber to maintain a certain pressure. At this time, the gas introduced into the chamber is a mixed gas of carboxylic acid vapor and a carrier gas (nitrogen, etc.). By introducing the gas, the pressure in the chamber becomes 1×10 4pa or above. The heated objects to be joined are joined together while the pressure in the chamber is constant. The objects to be joined can be heated during vacuum exhaust or after the introduction of a reducing gas. The pressure in the chamber during the heating process is not particularly limited. By setting it to a reduced pressure condition, there is a tendency to further promote conductor formation at low temperatures. It can also be a "flowing" state in which gas is introduced and exhausted simultaneously. By setting it to a "flowing" state, exhaust of the separation gas and the like is performed simultaneously, thereby reducing contamination of the chamber.

[0428] Hereinafter, a semiconductor package will be described using a structural body.

[0429] [Semiconductor Package]

[0430] Figure 35 1 is a schematic cross-sectional view showing a first example of a semiconductor package. Figure 35 In relation to the above Figure 13 and Figure 14 The same components of the structure 18 shown are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0431] Figure 35 The semiconductor package 60 shown has a structure 18 including a semiconductor element 62. The semiconductor element 62 is covered with a mold resin 64. The conductive member 19 of the semiconductor element 62 is electrically connected to a wiring board 70.

[0432] The wiring board 70 is provided with a wiring layer 74 on an insulating base material 72 having electrical insulation. One of the wiring layers 74 is connected to the conductive path 16 of the conductive member 19 (refer to FIG. Figure 13 ) and the other is electrically connected to the solder ball 75. Thus, a signal or the like can be output from the semiconductor element 62 to the outside of the semiconductor package 60. In addition, a signal, voltage, current, etc. can be supplied to the semiconductor element 62 from the outside of the semiconductor package 60.

[0433] In addition, the present invention is not limited to the above-mentioned embodiments. Examples of installation methods include SoC (System on a chip), SiP (System in Package), PoP (Package on Package), PiP (Package in Package), CSP (Chip Scale Package), and TSV (Through Silicon Via).

[0434] [Semiconductor device mounting process]

[0435] When the structure is mounted on a semiconductor element, mounting is performed by heating. However, in mounting by thermocompression bonding including solder reflow and mounting by flip chip, the maximum temperature is preferably 220 to 350°C, more preferably 240 to 320°C, and particularly preferably 260 to 300°C from the perspective of achieving uniform and reliable mounting.

[0436] From the same viewpoint, the time for maintaining the highest temperature is preferably 2 seconds to 10 minutes, more preferably 5 seconds to 5 minutes, and particularly preferably 10 seconds to 3 minutes.

[0437] Furthermore, from the perspective of suppressing cracks in the anodic oxide film caused by the difference in thermal expansion coefficient between the anodic oxide film of the joining object and the structure, a method can be adopted in which a heat treatment is performed at a desired constant temperature for 5 seconds to 10 minutes, more preferably 10 seconds to 5 minutes, and particularly preferably 20 seconds to 3 minutes, before reaching the above-mentioned maximum temperature. The desired constant temperature is preferably 80 to 200°C, more preferably 100 to 180°C, and particularly preferably 120 to 160°C.

[0438] Furthermore, from the perspective of reliable mounting, the temperature during wire bonding is preferably 80 to 300° C., more preferably 90 to 250° C., and particularly preferably 100 to 200° C. The heating time is preferably 2 seconds to 10 minutes, more preferably 5 seconds to 5 minutes, and particularly preferably 10 seconds to 3 minutes.

[0439] [Coaxial structure]

[0440] In addition, regarding the above wiring, for example Figure 36 and Figure 37 As shown, it is also possible to arrange a plurality of linear conductors 90 connected to the ground wiring 93 at predetermined intervals around the plurality of linear conductors 90 through which the signal current flows. This structure is equivalent to a coaxial line structure, and therefore can exert a shielding (shielding) effect. Furthermore, the plurality of linear conductors 90 connected to the ground wiring 93 are arranged between the plurality of linear conductors 90 through which adjacently arranged and different signal currents flow. Therefore, the electrical coupling (capacitive coupling) generated between the plurality of linear conductors 90 through which adjacently arranged and different signal currents flow can be reduced, and the plurality of linear conductors 90 through which the signal current flows can be suppressed from becoming a noise source. Figure 36 In the embodiment, a plurality of linear conductors 90 through which signal current flows are formed on an insulating base material 91 and are electrically insulated from each other and electrically connected to a signal wiring 92. A wiring layer 95 electrically insulated by an insulating layer 94 is electrically connected to the signal wiring 92 and the ground wiring 93.

[0441] and, Figure 38 It is a schematic cross-sectional view showing a second example of a semiconductor package.

[0442] like Figure 38 As shown, the structure can also be used to electrically connect the semiconductor package 60 and the printed wiring substrate 80. The structure 18 is fabricated on the printed wiring substrate 80. The printed wiring substrate 80 includes, for example, an insulating base material 82 made of a resin and provided with a wiring layer 84. The wiring layer 84 is electrically connected to the conductive path 16 of the conductive member 19.

[0443] Furthermore, the structure of the present invention can also be used to connect two or more semiconductor packages to each other (PoP; Package on Package). In this case, for example, two semiconductor packages arranged on the upper and lower surfaces can be connected via predetermined wiring.

[0444] Furthermore, the structure can also be used for multi-chip packaging in which two or more semiconductor elements are stacked or laid flat on a substrate. In this case, for example, two semiconductor elements are stacked and connected via predetermined wiring.

[0445] [Electronic devices]

[0446] The electronic device is not limited to a one-to-many system in which a plurality of semiconductor elements are bonded to one semiconductor element, but may also be a many-to-many system in which a plurality of semiconductor elements are bonded to a plurality of semiconductor elements.

[0447] Figure 39 is a schematic diagram showing a first example of an electronic device using a structure according to an embodiment of the present invention, Figure 40 1 is a schematic diagram showing a second example of an electronic device using the structure according to the embodiment of the present invention. Figure 41 1 is a schematic diagram showing a third example of an electronic device using the structure according to an embodiment of the present invention. Figure 42 This is a schematic diagram showing a fourth example of an electronic device using the structure according to the embodiment of the present invention.

[0448] As a many-to-many approach, for example Figure 39 As shown, an electronic device 100a is exemplified in which a structure 18 is formed in one semiconductor element 104, and semiconductor elements 106 and 108 are bonded and electrically connected using a conductive member 19 of the structure 18. The semiconductor element 104 may function as an interposer.

[0449] Furthermore, for example, multiple devices such as logic chips and memory chips having logic circuits can be stacked on a device having an interposer function. In this case, bonding can be achieved even if the electrode sizes of the individual devices are different.

[0450] exist Figure 40 In the illustrated electronic device 100b, electrodes 118 are not uniform in size, but rather are mixed. A structure 18 is formed within one semiconductor element 104, and the semiconductor elements 106 and 108 are bonded and electrically connected using a conductive member 19 of the structure 18. Furthermore, structures 18 are also formed within the semiconductor elements 106 and 108, and the semiconductor element 116 is bonded and electrically connected to the semiconductor element 106 using a conductive member 19 of the structure 18. A semiconductor element 117 straddles the semiconductor elements 106 and 108 and is bonded and electrically connected using a conductive member 19 of the structure 18.

[0451] And, as Figure 41 As shown in the electronic device 100c, a structure 18 is formed in one semiconductor element 104, and semiconductor elements 106 and 108 are bonded and electrically connected using a conductive member 19 of the structure 18. Alternatively, a structure may be employed in which a structure 18 is formed in each of semiconductor elements 106 and 108, semiconductor elements 116 and 117 are bonded and electrically connected to semiconductor element 106 using a conductive member 19 of the structure 18, and semiconductor element 121 is bonded and electrically connected to semiconductor element 108 using a conductive member 19 of the structure 18.

[0452] In the case of the above-described structure, by stacking a light-emitting element such as a VCSEL (Vertical Cavity Surface Emitting Laser) and a light-receiving element such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor on the surface of a device including an optical waveguide, it is also possible to cope with the envisioned high-frequency silicon photonics.

[0453] For example, Figure 42 As shown in the electronic device 100d, a structure 18 is formed in one semiconductor element 104, and semiconductor elements 106 and 108 are bonded and electrically connected using a conductive member 19 of the structure 18. Furthermore, a structure 18 is formed in each of the semiconductor elements 106 and 108, and semiconductor elements 116 and 117 are bonded and electrically connected to the semiconductor element 106 using the conductive member 19 of the structure 18. Semiconductor element 121 is bonded and electrically connected to the semiconductor element 108 using the conductive member 19 of the structure 18.

[0454] Semiconductor element 104 is provided with an optical waveguide 123. Semiconductor element 108 is provided with a light-emitting element 125, and semiconductor element 106 is provided with a light-receiving element 126. Light Lo output from light-emitting element 125 of semiconductor element 108 passes through optical waveguide 123 of semiconductor element 104 and is emitted as outgoing light Ld to light-receiving element 126 of semiconductor element 106. This enables support for the aforementioned silicon photonics.

[0455] Furthermore, in the structure 18 of the semiconductor element 104 , a conductive member 19 is formed avoiding a region 122 corresponding to the optical path of the light Lo and the outgoing light Ld.

[0456] The present invention is basically configured as described above. Although the method for producing the structure of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

[0457] Explanation of symbols

[0458] 10-Insulating support, 10a, 12a, 14a-Surface, 10c-Element region, 11-Resist layer, 11a-Surface, 12-Conductive layer, 12c-End face, 13-Valve metal layer, 14-Anodic oxide film, 15-Through hole, 16-Conductive path, 16a-Protrusion, 17-Resin layer, 18-Structural body, 19-Conductive component, 30, 32-Semiconductor element, 33-Semiconductor layer, 33a, 34a, 36a, 46a-Surface, 34-Rewiring layer, 36-Passivation layer, 37-Wiring, 38-Pad, 39-Joint body, 40-Stacked device, 42, 44, 46, 62-Semiconductor element, 44b-Back face, 45-Interposer, 47-Sensor chip, 48-Lens, 50-First semiconductor wafer, 50a-Surface, 5 2-second semiconductor chip, 60-semiconductor package, 64-molded resin, 70-wiring substrate, 72-insulating base material, 74-wiring layer, 75-solder ball, 80-printed wiring substrate, 82-insulating base material, 84-wiring layer, 90-linear conductor, 91-insulating base material, 92-signal wiring, 93-ground wiring, 94-insulating layer, 95-wiring layer, 100a, 100b, 100c, 100d-electronic device, 104, 106, 108, 116, 117, 121-semiconductor element, 118-electrode, 122-region, 123-optical waveguide, 125-light-emitting element, 126-light-receiving element, Ds-stacking direction, Dt-thickness direction, Ld-outgoing light, Lo-light, h-thickness, p-center-to-center distance, x-direction.

Claims

1. A method for manufacturing a structure for bonding to an object, comprising: A conductive layer forming step of forming a conductive layer on a device region on a surface of an insulating support having at least one surface; a valve metal layer forming step of forming a valve metal layer covering at least a portion of the conductive layer; an anodic oxide film forming step of performing an anodic oxidation treatment with the conductive layer serving as a cathode electrode and the valve metal layer serving as an anode electrode, wherein the entire valve metal layer is not anodic oxidized but an anodic oxide film is formed on a region of the valve metal layer on the conductive layer; a micropore forming step of forming a plurality of micropores extending in the thickness direction in the anodized film; and A filling step of filling the micropores with a conductive material. A valve metal layer removing step of removing the valve metal layer remaining without being anodized after the anodic oxide film forming step is provided between the anodic oxide film forming step and the filling step.

2. The method for manufacturing a structure for bonding to an object according to claim 1, wherein: The valve metal layer removal step is performed between the anodic oxide film forming step and the micropore forming step or between the micropore forming step and the filling step.

3. The method for manufacturing a structure for bonding to an object according to claim 1 or 2, wherein: The micropore forming step includes a step of penetrating the plurality of micropores in the anodized film in a thickness direction to expose the conductive layer.

4. The method for manufacturing a structure for joining to an object according to claim 1 or 2, wherein: In the valve metal layer forming step, the valve metal layer is formed at a temperature of the insulating support body of 60° C. or less.

5. The method for manufacturing a structure for joining to an object according to claim 1 or 2, wherein: The method for manufacturing the structure includes a protruding step of causing a plurality of conductive paths formed of the filled conductive material to protrude from the anodized film.

6. The method for manufacturing a structure for bonding to an object according to claim 5, wherein: The plurality of conductive paths protruded in the protruding step each have a same height at a protruding portion protruding from the anodized film.

7. The method for manufacturing a structure for joining to an object according to claim 1 or 2, wherein: The conductive layer and the conductive substance include the same material.

8. The method for manufacturing a structure for joining to an object according to claim 1 or 2, wherein: The valve metal is aluminum.

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