Flip-chip solder bump structure and manufacturing method thereof

Abstract

The present invention relates to a manufacturing method of an inverted solder bump structure, comprising: evaporating a first seed layer on the surface of a first detector chip substrate; forming a columnar first electroplated gold layer in the middle of the first seed layer by means of photolithography and electroplating; forming an annular second electroplated gold layer on the first seed layer by means of photolithography and electroplating; the second electroplated gold layer being wrapped around the periphery of the first electroplated gold layer, and the height of the second electroplated gold layer being greater than the height of the first electroplated gold layer; removing the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer. In the present invention, by using thick film photolithography, the morphology, size and height of the recessed solder bumps can be controlled by adjusting the aperture size and depth of the photoresist film; the recessed solder bumps with positioning grooves are formed by two electroplated gold layers, and the cooperation between the recessed solder bumps and the columnar solder bumps is easier to integrate and install, and the displacement during the flip-chip soldering is reduced, improving the alignment accuracy and reliability.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a flip-chip solder bump structure and a manufacturing method thereof. Background Art

[0002] Due to the short leads of flip-chip solder chips, the bump joints are generally directly soldered to the PCB or other substrates. Therefore, the lead inductance is small, the crosstalk between signals is small, the signal transmission delay time is short, and the electrical performance is good. In addition, due to the solid heat conduction of a large number of metal solder joints under the chip, the thermal resistance of the device is small. Therefore, the flip-chip soldering process is usually adopted in the manufacturing process of high-speed detector chips.

[0003] Currently, the composition materials of the bump joints on the chip usually include lead-tin alloy, gold, pure indium, and polymers. Since the melting point of pure indium is low, only about 156 °C, it is not compatible with general SMT technology and is relatively easy to corrode. It is only used in infrared devices with low-temperature operation. Polymer solder joints are not yet mature. Currently, the commonly used PbSn alloy and Au bump joints.

[0004] Traditional Au bumps are generally hemispherical or cylindrical solder joints. During the flip-chip soldering process, solder joint misalignment is likely to occur, resulting in short circuit of P\N electrodes and damage to the detector. In addition, due to the small number of solder joints, the shear force after flip-chip soldering is also relatively small, and the chip reliability is not high. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a flip-chip solder bump structure and a manufacturing method thereof that can improve the reliability of flip-chip soldering.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] A manufacturing method of a flip-chip solder bump structure, comprising the following steps:

[0008] Take a semi-insulating substrate as the first detector chip substrate;

[0009] Evaporate a first seed layer on the surface of the first detector chip substrate;

[0010] Form a columnar first electroplated gold layer in the middle of the first seed layer by using thick film lithography and electroplating;

[0011] Form an annular second electroplated gold layer on the first seed layer by using thick film lithography and electroplating; the second electroplated gold layer wraps around the periphery of the first electroplated gold layer, and the height of the second electroplated gold layer is greater than the height of the first electroplated gold layer;

[0012] Remove the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer.

[0013] Further, evaporating a first seed layer on the surface of the first detector chip substrate includes the following steps:

[0014] Evaporating a chromium layer on the surface of the first detector chip substrate; the thickness of the chromium layer is 0.1 μm to 0.3 μm;

[0015] Evaporating a gold layer on the surface of the chromium layer, the thickness of the gold layer is 1.0 μm to 1.5 μm.

[0016] Further, forming a columnar first electroplated gold layer in the middle of the first seed layer by thick photoresist lithography and electroplating includes the following steps:

[0017] Spin-coating a photoresist on the surface of the first seed layer to form a first electroplating photoresist film;

[0018] Forming a columnar first electroplating photoresist film hole in the middle of the first electroplating photoresist film by exposure and development, exposing the surface of the first seed layer in the area of the first electroplating photoresist film hole;

[0019] Forming a columnar first electroplated gold layer by electroplating in the first electroplating photoresist film hole;

[0020] Removing the first electroplating photoresist film with a chemical cleaning agent.

[0021] Further, forming an annular second electroplated gold layer on the first seed layer by thick photoresist lithography and electroplating includes the following steps:

[0022] Spin-coating a photoresist on the surface of the first seed layer and the first electroplated gold layer to form a second electroplating photoresist film;

[0023] Forming an annular second electroplating photoresist film hole around the first electroplated gold layer in the middle of the second electroplating photoresist film by exposure and development, exposing the surface of the first seed layer in the area of the second electroplating photoresist film hole and the side wall of the first electroplated gold layer;

[0024] Forming an annular second electroplated gold layer by electroplating in the second electroplating photoresist film hole, the thickness of the second electroplated gold layer is 3 μm to 6 μm greater than the thickness of the first electroplated gold layer;

[0025] Removing the second electroplating photoresist film with a chemical cleaning agent.

[0026] Further, removing the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer includes the following steps:

[0027] Spin-coating a photoresist on the surface of the first electroplated gold layer and the second electroplated gold layer;

[0028] Removing the photoresist on the surface of the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer by lithography, exposure, and development, exposing the surface of the first seed layer;

[0029] Etch away the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer;

[0030] Remove the photoresist on the surfaces of the first electroplated gold layer and the second electroplated gold layer.

[0031] A method for fabricating a flip-chip solder bump structure includes the following steps:

[0032] Take a semi-insulating substrate as the second detector chip substrate;

[0033] Evaporate a second seed layer on the surface of the second detector chip substrate;

[0034] Spin-coat photoresist on the surface of the second seed layer to form a third electroplating resist film; then use the methods of exposure and development to form a columnar third electroplating resist film hole in the middle of the third electroplating resist film, exposing the surface of the second seed layer;

[0035] Form a columnar third electroplated gold layer by electroplating in the third electroplating resist film hole;

[0036] Remove the third electroplating resist film;

[0037] Spin-coat photoresist on the surface of the third electroplated gold layer; then use the methods of photolithography, exposure, and development to remove the photoresist on the surface of the second seed layer that does not cover the third electroplated gold layer, exposing the surface of the second seed layer in this area;

[0038] Etch away the second seed layer that does not cover the third electroplated gold layer;

[0039] Use a chemical cleaning agent to remove the photoresist on the surface of the third electroplated gold layer.

[0040] Further, evaporating a second seed layer on the surface of the second detector chip substrate includes the following steps:

[0041] Evaporate a chromium layer on the surface of the second detector chip substrate; the thickness of the chromium layer is 0.1 μm to 0.3 μm;

[0042] Evaporate a gold layer on the surface of the chromium layer, and the thickness of the gold layer is 1.0 μm to 1.5 μm.

[0043] A flip-chip solder bump structure includes a first detector chip substrate and a second detector chip substrate, and both the first detector chip substrate and the second detector chip substrate are semi-insulating substrates; a first seed layer is provided on the upper end surface of the first detector chip substrate, a first solder bump is provided on the first seed layer, a positioning groove is provided in the middle of the first solder bump, and the positioning groove is a cylindrical groove; a second seed layer is provided on the upper end surface of the second detector chip substrate, and a cylindrical second solder bump is provided on the second seed layer at a position corresponding to the first solder bump, and the shape of the second solder bump is adapted to the shape of the positioning groove.

[0044] Further, the first solder bump includes a first electroplated gold layer and a second electroplated gold layer, a cylindrical hole is provided in the middle of the second electroplated gold layer, and the first electroplated gold layer is provided at the bottom of the cylindrical hole; the height of the first electroplated gold layer is less than the height of the second electroplated gold layer, so as to form a positioning groove in the middle of the second electroplated gold layer.

[0045] Further, the first seed layer includes a first chromium layer provided on the first detector chip substrate and a first gold layer provided on the first chromium layer, the thickness of the first chromium layer is 0.1 μm to 0.3 μm, and the thickness of the first gold layer is 1.0 μm to 1.5 μm; the second seed layer includes a second chromium layer provided on the second detector chip substrate and a second gold layer provided on the second chromium layer, the thickness of the second chromium layer is 0.1 μm to 0.3 μm, and the thickness of the second gold layer is 1.0 μm to 1.5 μm.

[0046] In the present invention, by using two electroplated gold layers, a concave solder bump with a positioning groove can be formed, and by using thick photoresist lithography, concave solder bumps and solder bumps with a cylindrical structure with controllable morphology, size and height can be obtained by adjusting the aperture size and depth of the photoresist film. By using concave solder bumps and solder bumps with a cylindrical structure on the two substrates of the flip-chip solder, when performing flip-chip solder, the solder bumps with a cylindrical structure are poured into the positioning grooves of the concave solder bumps, which is easier to integrate and install, and reduces the displacement during the flip-chip solder, improving the alignment accuracy and reliability. Description of the Drawings

[0047] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in detail and preferably with reference to the accompanying drawings, where:

[0048] Figure 1 It is a flowchart of a preferred embodiment of the manufacturing method of the flip-chip solder bump structure of the present invention.

[0049] Figure 2 It is a schematic structural diagram after evaporating the first seed layer on the surface of the first detector chip substrate.

[0050] Figure 3 Schematic diagram of the structure after forming the first electroplating resist film holes by lithography of the first electroplating resist film.

[0051] Figure 4 Schematic diagram of the structure after forming the first electroplated gold layer.

[0052] Figure 5 Schematic diagram of the structure after forming the second electroplating resist film holes by lithography of the second electroplating resist film.

[0053] Figure 6 Schematic diagram of the structure after forming the second electroplated gold layer.

[0054] Figure 7 Cross-sectional schematic diagram of the structure after forming the second electroplated gold layer.

[0055] Figure 8 Flowchart of another preferred embodiment of the method for manufacturing the flip-chip solder bump structure of the present invention.

[0056] Figure 9 Schematic diagram of the structure after evaporating the second seed layer on the surface of the second detector chip substrate.

[0057] Figure 10 Schematic diagram of the structure after forming the third electroplating resist film holes by lithography of the third electroplating resist film.

[0058] Figure 11 Schematic diagram of the structure after forming the second solder bumps.

[0059] Figure 12 Schematic diagram when assembling the first solder bumps and the second solder bumps by flip-chip bonding.

[0060] In the figure: 1. First solder bump, 2. Second solder bump, 10. First detector chip substrate, 11. First seed layer, 12. First electroplating resist film, 13. First electroplating resist film holes, 14. First electroplated gold layer, 15. Second electroplating resist film, 16. Second electroplating resist film holes, 17. Second electroplated gold layer, 18. Positioning groove, 20. Second detector chip substrate, 21. Second seed layer, 22. Third electroplating resist film, 23. Third electroplating resist film holes. Detailed implementation manners

[0061] The following illustrates the implementation manners of the present invention through specific specific examples. The diagrams provided in the following examples only schematically illustrate the basic concept of the present invention. Without conflict, the following examples and the features in the examples can be combined with each other.

[0062] Example 1

[0063] As Figure 1As shown, a preferred embodiment of the method for manufacturing the flip-chip gold bump structure of the present invention includes the following steps:

[0064] S101. Take a semi-insulating substrate as the first detector chip substrate 10. The semi-insulating substrate is preferably an InP substrate with a cuboid structure.

[0065] S102. As Figure 2 shown, evaporate a first seed layer 11 on the surface of the first detector chip substrate 10. The first seed layer 11 is used for conducting electricity during electroplating. This step may specifically include the following sub-steps:

[0066] S1021. Evaporate a layer of chromium on the surface of the first detector chip substrate 10 as the first chromium layer; the thickness of the first chromium layer is 0.1 μm to 0.3 μm. Using chromium as the bottom layer of the first seed layer 11 can enhance the adhesion of the bottom surface and prevent the migration of gold to the material, avoiding affecting the device performance. The thickness of the chromium layer is relatively thin, preferably 0.1 μm.

[0067] S1022. Evaporate a layer of gold on the surface of the first chromium layer as the first gold layer, and the thickness of the first gold layer is 1.0 μm to 1.5 μm. The thickness of the gold layer is relatively thick, preferably 1 μm.

[0068] S103. Use the methods of thick film lithography and electroplating to form a columnar first electroplated gold layer 14 in the middle of the first seed layer 11. Specifically, it may include the following sub-steps:

[0069] S1031. As Figure 3 shown, spin-coat a photoresist on the surface of the first seed layer 11 to form a first electroplating photoresist film 12 covering the first seed layer 11; the thickness of the first electroplating photoresist film 12 is equal to the thickness of the to-be-electroplated first electroplated gold layer 14. The photoresist can use AZ4620 photoresist.

[0070] S1032. Use the methods of exposure and development to form a columnar first electroplating photoresist film hole 13 in the middle of the first electroplating photoresist film 12, and expose the surface of the first seed layer 11 in this area through the first electroplating photoresist film hole 13 to facilitate the formation of the first electroplated gold layer 14.

[0071] S1033. Use electroplating to form a columnar first electroplated gold layer 14 in the first electroplating photoresist film hole 13; the first electroplated gold layer 14 is preferably an Au layer.

[0072] By first lithographing the first electroplating photoresist film hole 13 and then forming the first electroplated gold layer 14 in the first electroplating photoresist film hole 13, the shape, size, and thickness of the first electroplated gold layer 14 can be conveniently controlled.

[0073] S1034. Remove the first electroplated film 12 using a chemical cleaning agent. The chemical cleaning agent includes a stripping solution and other de-gluing reagents. The schematic structural diagram after removing the first electroplated film 12 is as shown in Figure 4 shown.

[0074] S104. Use the method of thick film lithography and electroplating to form an annular second electroplated gold layer 17 on the first seed layer 11; the second electroplated gold layer 17 is wrapped around the periphery of the first electroplated gold layer 14, and the height of the second electroplated gold layer 17 is greater than the height of the first electroplated gold layer 14; thus, the first gold bump 1 with a positioning groove 18 is formed by combining the first electroplated gold layer 14 and the second electroplated gold layer 17. This step may specifically include the following sub-steps:

[0075] S1041. As shown in Figure 5 shown, spin-coat a photoresist on the surfaces of the first seed layer 11 and the first electroplated gold layer 14 to form a second electroplated film 15 covering the first seed layer 11 and the first electroplated gold layer 14; the thickness of the second electroplated film 15 is equal to the thickness of the second electroplated gold layer 17 to be electroplated. The photoresist can use AZ4620 photoresist.

[0076] S1042. Use the methods of exposure and development to form an annular second electroplated film hole 16 around the first electroplated gold layer 14 in the middle of the second electroplated film 15, and expose the surface of the first seed layer 11 and the side wall of the first electroplated gold layer 14 in this area through the second electroplated film hole 16.

[0077] S1043. Electroplate an annular second electroplated gold layer 17 in the second electroplated film hole 16. The second electroplated gold layer 17 is preferably an Au layer. The thickness of the second electroplated gold layer 17 is greater than the thickness of the first electroplated gold layer 14. Preferably, the second electroplated gold layer 17 is 3 μm - 6 μm thicker than the first electroplated gold layer 14. Thus, the first gold bump 1 with a positioning groove 18 is formed by the first electroplated gold layer 14 and the second electroplated gold layer 17, and the depth of the positioning groove 18 is 3 μm - 6 μm.

[0078] S1044. Remove the second electroplated film 15 using a chemical cleaning agent. The chemical cleaning agent includes a stripping solution and other de-gluing reagents.

[0079] By first lithographing the annular second electroplated film hole 16 and then forming the second electroplated gold layer 17 in the second electroplated film hole 16, it can ensure that the bottom of the second electroplated gold layer 17 tightly wraps the first electroplated gold layer 14 and forms a whole, thus facilitating the control of the shape of the first gold bump 1 and the depth of the concave structure.

[0080] S105. Remove the first seed layer 11 that does not cover the first electroplated gold layer 14 and the second electroplated gold layer 17 (i.e., the first seed layer 11 in the area outside the first gold bump 1). Specifically, it may include the following sub-steps:

[0081] S1051. Spin-coat photoresist on the surface of the first gold bump 1; cover the upper surface, inner sidewall, and outer sidewall of the first electroplated gold layer 14 and the second electroplated gold layer 17 with the photoresist; the photoresist can be AZ4620 photoresist.

[0082] S1052. Remove the photoresist on the surface of the first seed layer 11 that does not cover the first electroplated gold layer 14 and the second electroplated gold layer 17 through photolithography, exposure, and development methods to expose the surface of the first seed layer 11. Since the photoresist will also be coated on the surface of the first seed layer 11 when spin-coating the photoresist in step S1051, it is necessary to first remove the photoresist on the surface of the first seed layer 11.

[0083] S1053. Etch the first seed layer 11 that does not cover the first electroplated gold layer 14 and the second electroplated gold layer 17 with an etching solution; thereby remove the first seed layer 11 in the area outside the first gold bump 1.

[0084] S1054. Remove the photoresist on the surface of the first gold bump 1 (the surface of the first electroplated gold layer 14 and the second electroplated gold layer 17) with a chemical cleaning agent. The chemical cleaning agent contains a de-glue reagent such as a stripping solution. The schematic diagram of the structure after removing the photoresist is as Figure 6 and Figure 7 shown.

[0085] In this embodiment, by using two electroplated gold layers, a recessed gold bump with a positioning groove 18 can be formed, and by using thick-film photolithography, a recessed gold bump with controllable morphology, size, and height can be obtained by adjusting the pore size and depth of the photoresist film. By using a recessed gold bump on one substrate of the flip-chip bonding, during flip-chip bonding, the columnar gold bump can be poured into the positioning groove 18 of the recessed gold bump, which is easier to integrate and install, and reduces the displacement during the upside-down soldering, improving the alignment accuracy and reliability.

[0086] Embodiment 2

[0087] As Figure 8 shown, the present invention also relates to a manufacturing method of another flip-chip gold bump structure adapted to the flip-chip gold bump structure of Embodiment 1, and its preferred embodiment may include the following steps:

[0088] S201. Take a semi-insulating substrate as the second detector chip substrate 20; the semi-insulating substrate is preferably an InP substrate with a cuboid structure.

[0089] S202. As Figure 9 shown, evaporate a second seed layer 21 on the surface of the second detector chip substrate 20; specifically, it may include the following sub-steps:

[0090] S2021. Evaporate a layer of chromium on the surface of the second detector chip substrate 20 as the second chromium layer; the thickness of the chromium layer is relatively thin, and the thickness of the second chromium layer is 0.1 μm to 0.3 μm, preferably 0.1 μm.

[0091] S2022. Evaporate a layer of gold on the surface of the second chromium layer as the second gold layer. The thickness of the gold layer is relatively thick, and the thickness of the second gold layer is 1.0 μm to 1.5 μm, preferably 1 μm.

[0092] S203. As Figure 10 shown, spin-coat photoresist on the surface of the second seed layer 21 to form a third electroplating resist film 22; then use the methods of exposure and development to form a columnar third electroplating resist film hole 23 in the middle of the third electroplating resist film 22, exposing the surface of the second seed layer 21 in this area. The thickness of the third electroplating resist film 22 is equal to the thickness of the third electroplating gold layer to be electroplated; the photoresist can use AZ4620 photoresist.

[0093] S204. Form a columnar third electroplating gold layer in the third electroplating resist film hole 23 by electroplating; the third electroplating gold layer is preferably an Au layer, and the shape of the third electroplating gold layer is adapted to the shape of the positioning groove 18 of the first gold bump 1 in Example 1. The second gold bump 2 with a columnar structure can be formed through the third electroplating gold layer.

[0094] S205. Remove the third electroplating resist film 22 with a chemical cleaning agent. The chemical cleaning agent includes stripping solution and other degluing reagents.

[0095] S206. Spin-coat photoresist on the surface of the second gold bump 2 (i.e., the third electroplating gold layer); then remove the photoresist on the surface of the second seed layer 21 that does not cover the third electroplating gold layer through photolithography, exposure, and development methods, exposing the surface of the second seed layer 21 in the area outside the second gold bump 2.

[0096] S207. Etch and remove the second seed layer 21 that does not cover the third electroplating gold layer (i.e., the second seed layer 21 in the area outside the second gold bump 2).

[0097] S208. Remove the photoresist on the surface of the second gold bump 2 with a chemical cleaning agent. The chemical cleaning agent includes stripping solution and other degluing reagents. The schematic diagram of the structure after removing the photoresist is as Figure 11 shown.

[0098] In this embodiment, by using thick-film lithography, cylindrical gold bumps with controllable morphology, size, and height can be obtained by adjusting the pore size and depth of the photoresist film, so that the shape of the cylindrical gold bumps is adapted to the shape of the concave gold bumps in Embodiment 1. During flip-chip soldering, the cylindrical gold bumps can be poured into the positioning grooves 18 of the concave gold bumps, which is easier to integrate and install, reduces the displacement during reflow soldering, and improves the alignment accuracy and reliability.

[0099] Embodiment 3

[0100] As Figure 6 、 Figure 7 and Figure 11 shown, the present invention also discloses a flip-chip soldering gold bump structure. A preferred embodiment of the flip-chip soldering gold bump structure of the present invention includes a first detector chip substrate 10 and a second detector chip substrate 20. Both the first detector chip substrate 10 and the second detector chip substrate 20 are semi-insulating substrates, preferably an InP substrate with a cuboid structure. A first seed layer 11 is provided on the upper end surface of the first detector chip substrate 10. The first seed layer 11 includes a first chromium layer provided on the first detector chip substrate 10 and a first gold layer provided on the first chromium layer. The thickness of the first chromium layer is 0.1 μm to 0.3 μm, and the thickness of the first gold layer is 1.0 μm to 1.5 μm. A first gold bump 1 is provided on the first seed layer 11. The first gold bump 1 includes a first electroplated gold layer 14 and a second electroplated gold layer 17. A cylindrical hole is provided in the middle of the second electroplated gold layer 17, and the first electroplated gold layer 14 is provided at the bottom of the cylindrical hole. The height of the first electroplated gold layer 14 is less than the height of the second electroplated gold layer 17, so as to form a positioning groove 18 in the middle of the second electroplated gold layer 17. The positioning groove 18 is a cylindrical groove. The depth of the positioning groove 18 is 3 μm to 6 μm.

[0101] A second seed layer 21 is provided on the upper end surface of the second detector chip substrate 20. The second seed layer 21 includes a second chromium layer provided on the second detector chip substrate 20 and a second gold layer provided on the second chromium layer. The thickness of the second chromium layer is 0.1 μm to 0.3 μm, preferably 0.1 μm. The thickness of the second gold layer is 1.0 μm to 1.5 μm, preferably 1 μm. A second gold bump 2 with a cylindrical structure is provided on the second seed layer 21 at a position corresponding to the first gold bump 1. The shape of the second gold bump 2 is adapted to the shape of the positioning groove 18.

[0102] As Figure 12As shown, when using the flip-chip solder bump structure in this embodiment, during flip-chip soldering, first align the second solder bumps 2 on the second detector chip substrate 20 with the positioning grooves 18 of the first solder bumps 1 at corresponding positions on the first detector chip substrate 10, so that the second solder bumps 2 extend into the positioning grooves 18 of the first solder bumps 1, thereby enabling the accurate positioning of the first solder bumps 1 and the second solder bumps 2.

[0103] In this embodiment, by using a concave solder bump and a columnar solder bump on the two substrates for flip-chip soldering respectively, during flip-chip soldering, pour the columnar solder bumps into the positioning grooves 18 of the concave solder bumps, which is easier for integration and installation, and reduces the displacement during flip-chip soldering, improving the alignment accuracy and reliability; it can effectively avoid the situation of short circuit of P\N electrodes and damage to the detector caused by solder joint misalignment.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A manufacturing method of an inverted solder bump structure, characterized in that, it includes the following steps: Take a semi-insulating substrate as the first detector chip substrate; Evaporate a first seed layer on the surface of the first detector chip substrate; Use thick photoresist lithography and electroplating methods to form a columnar first electroplated gold layer in the middle of the first seed layer; Use thick photoresist lithography and electroplating methods to form an annular second electroplated gold layer on the first seed layer; the second electroplated gold layer wraps around the periphery of the first electroplated gold layer, and the second electroplated gold layer is 3μm - 6μm thicker than the first electroplated gold layer; Remove the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer; Evaporating a layer of the first seed layer on the surface of the first detector chip substrate includes the following steps: Evaporate a chromium layer on the surface of the first detector chip substrate; the thickness of the chromium layer is 0.1μm - 0.3μm; Evaporate a gold layer on the surface of the chromium layer, and the thickness of the gold layer is 1.0μm - 1.5μm.

2. The manufacturing method of the inverted solder bump structure according to claim 1, characterized in that, Using thick photoresist lithography and electroplating methods to form a columnar first electroplated gold layer in the middle of the first seed layer includes the following steps: Spin-coat photoresist on the surface of the first seed layer to form a first electroplated photoresist film; Use exposure and development methods to form a columnar first electroplated photoresist film hole in the middle of the first electroplated photoresist film, exposing the surface of the first seed layer in the area of the first electroplated photoresist film hole; Form a columnar first electroplated gold layer by electroplating in the first electroplated photoresist film hole; Remove the first electroplated photoresist film using a chemical cleaning agent.

3. The manufacturing method of the inverted solder bump structure according to claim 1, characterized in that, Using thick photoresist lithography and electroplating methods to form an annular second electroplated gold layer on the first seed layer includes the following steps: Spin-coat photoresist on the surface of the first seed layer and the first electroplated gold layer to form a second electroplated photoresist film; Use exposure and development methods to form an annular second electroplated photoresist film hole around the first electroplated gold layer in the middle of the second electroplated photoresist film, exposing the surface of the first seed layer in the area of the second electroplated photoresist film hole and the side wall of the first electroplated gold layer; Form an annular second electroplated gold layer by electroplating in the second electroplated photoresist film hole; Remove the second electroplated photoresist film using a chemical cleaning agent.

4. The manufacturing method of the inverted solder bump structure according to claim 1, characterized in that, Removing the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer includes the following steps: Spin-coat photoresist on the surface of the first electroplated gold layer and the second electroplated gold layer; Through lithography, exposure, and development methods, remove the photoresist on the surface of the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer, exposing the surface of the first seed layer; Etch and remove the first seed layer that does not cover the first electroplated gold layer and the second electroplated gold layer; Remove the photoresist on the surface of the first electroplated gold layer and the second electroplated gold layer.

5. An inverted solder bump structure, characterized in that, It includes a first detector chip substrate and a second detector chip substrate, both the first detector chip substrate and the second detector chip substrate are semi-insulating substrates; a first seed layer is provided on the upper end surface of the first detector chip substrate, a first gold bump is provided on the first seed layer, a positioning groove is provided in the middle of the first gold bump, and the positioning groove is a cylindrical groove; a second seed layer is provided on the upper end surface of the second detector chip substrate, and a cylindrical second gold bump is provided at a position corresponding to the first gold bump on the second seed layer, and the shape of the second gold bump is adapted to the shape of the positioning groove; The first gold bump includes a first electroplated gold layer and a second electroplated gold layer, a cylindrical hole is provided in the middle of the second electroplated gold layer, and the first electroplated gold layer is provided at the bottom of the cylindrical hole; the second electroplated gold layer is 3μm - 6μm thicker than the first electroplated gold layer, so as to form a positioning groove in the middle of the second electroplated gold layer; The first seed layer includes a first chromium layer provided on the first detector chip substrate and a first gold layer provided on the first chromium layer, the thickness of the first chromium layer is 0.1μm - 0.3μm, and the thickness of the first gold layer is 1.0μm - 1.5μm; the second seed layer includes a second chromium layer provided on the second detector chip substrate and a second gold layer provided on the second chromium layer, the thickness of the second chromium layer is 0.1μm - 0.3μm, and the thickness of the second gold layer is 1.0μm - 1.5μm.

Images